1/* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27#ifndef RV770_H 28#define RV770_H 29 30#define R7XX_MAX_SH_GPRS 256 31#define R7XX_MAX_TEMP_GPRS 16 32#define R7XX_MAX_SH_THREADS 256 33#define R7XX_MAX_SH_STACK_ENTRIES 4096 34#define R7XX_MAX_BACKENDS 8 35#define R7XX_MAX_BACKENDS_MASK 0xff 36#define R7XX_MAX_SIMDS 16 37#define R7XX_MAX_SIMDS_MASK 0xffff 38#define R7XX_MAX_PIPES 8 39#define R7XX_MAX_PIPES_MASK 0xff 40 41/* Registers */ 42#define CB_COLOR0_BASE 0x28040 43#define CB_COLOR1_BASE 0x28044 44#define CB_COLOR2_BASE 0x28048 45#define CB_COLOR3_BASE 0x2804C 46#define CB_COLOR4_BASE 0x28050 47#define CB_COLOR5_BASE 0x28054 48#define CB_COLOR6_BASE 0x28058 49#define CB_COLOR7_BASE 0x2805C 50#define CB_COLOR7_FRAG 0x280FC 51 52#define CC_GC_SHADER_PIPE_CONFIG 0x8950 53#define CC_RB_BACKEND_DISABLE 0x98F4 54#define BACKEND_DISABLE(x) ((x) << 16) 55#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 56 57#define CGTS_SYS_TCC_DISABLE 0x3F90 58#define CGTS_TCC_DISABLE 0x9148 59#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 60#define CGTS_USER_TCC_DISABLE 0x914C 61 62#define CONFIG_MEMSIZE 0x5428 63 64#define CP_ME_CNTL 0x86D8 65#define CP_ME_HALT (1<<28) 66#define CP_PFP_HALT (1<<26) 67#define CP_ME_RAM_DATA 0xC160 68#define CP_ME_RAM_RADDR 0xC158 69#define CP_ME_RAM_WADDR 0xC15C 70#define CP_MEQ_THRESHOLDS 0x8764 71#define STQ_SPLIT(x) ((x) << 0) 72#define CP_PERFMON_CNTL 0x87FC 73#define CP_PFP_UCODE_ADDR 0xC150 74#define CP_PFP_UCODE_DATA 0xC154 75#define CP_QUEUE_THRESHOLDS 0x8760 76#define ROQ_IB1_START(x) ((x) << 0) 77#define ROQ_IB2_START(x) ((x) << 8) 78#define CP_RB_CNTL 0xC104 79#define RB_BUFSZ(x) ((x)<<0) 80#define RB_BLKSZ(x) ((x)<<8) 81#define RB_NO_UPDATE (1<<27) 82#define RB_RPTR_WR_ENA (1<<31) 83#define BUF_SWAP_32BIT (2 << 16) 84#define CP_RB_RPTR 0x8700 85#define CP_RB_RPTR_ADDR 0xC10C 86#define CP_RB_RPTR_ADDR_HI 0xC110 87#define CP_RB_RPTR_WR 0xC108 88#define CP_RB_WPTR 0xC114 89#define CP_RB_WPTR_ADDR 0xC118 90#define CP_RB_WPTR_ADDR_HI 0xC11C 91#define CP_RB_WPTR_DELAY 0x8704 92#define CP_SEM_WAIT_TIMER 0x85BC 93 94#define DB_DEBUG3 0x98B0 95#define DB_CLK_OFF_DELAY(x) ((x) << 11) 96#define DB_DEBUG4 0x9B8C 97#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 98 99#define DCP_TILING_CONFIG 0x6CA0 100#define PIPE_TILING(x) ((x) << 1) 101#define BANK_TILING(x) ((x) << 4) 102#define GROUP_SIZE(x) ((x) << 6) 103#define ROW_TILING(x) ((x) << 8) 104#define BANK_SWAPS(x) ((x) << 11) 105#define SAMPLE_SPLIT(x) ((x) << 14) 106#define BACKEND_MAP(x) ((x) << 16) 107 108#define GB_TILING_CONFIG 0x98F0 109 110#define GC_USER_SHADER_PIPE_CONFIG 0x8954 111#define INACTIVE_QD_PIPES(x) ((x) << 8) 112#define INACTIVE_QD_PIPES_MASK 0x0000FF00 113#define INACTIVE_SIMDS(x) ((x) << 16) 114#define INACTIVE_SIMDS_MASK 0x00FF0000 115 116#define GRBM_CNTL 0x8000 117#define GRBM_READ_TIMEOUT(x) ((x) << 0) 118#define GRBM_SOFT_RESET 0x8020 119#define SOFT_RESET_CP (1<<0) 120#define GRBM_STATUS 0x8010 121#define CMDFIFO_AVAIL_MASK 0x0000000F 122#define GUI_ACTIVE (1<<31) 123#define GRBM_STATUS2 0x8014 124 125#define HDP_HOST_PATH_CNTL 0x2C00 126#define HDP_NONSURFACE_BASE 0x2C04 127#define HDP_NONSURFACE_INFO 0x2C08 128#define HDP_NONSURFACE_SIZE 0x2C0C 129#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 130#define HDP_TILING_CONFIG 0x2F3C 131 132#define MC_SHARED_CHMAP 0x2004 133#define NOOFCHAN_SHIFT 12 134#define NOOFCHAN_MASK 0x00003000 135 136#define MC_ARB_RAMCFG 0x2760 137#define NOOFBANK_SHIFT 0 138#define NOOFBANK_MASK 0x00000003 139#define NOOFRANK_SHIFT 2 140#define NOOFRANK_MASK 0x00000004 141#define NOOFROWS_SHIFT 3 142#define NOOFROWS_MASK 0x00000038 143#define NOOFCOLS_SHIFT 6 144#define NOOFCOLS_MASK 0x000000C0 145#define CHANSIZE_SHIFT 8 146#define CHANSIZE_MASK 0x00000100 147#define BURSTLENGTH_SHIFT 9 148#define BURSTLENGTH_MASK 0x00000200 149#define CHANSIZE_OVERRIDE (1 << 11) 150#define MC_VM_AGP_TOP 0x2028 151#define MC_VM_AGP_BOT 0x202C 152#define MC_VM_AGP_BASE 0x2030 153#define MC_VM_FB_LOCATION 0x2024 154#define MC_VM_MB_L1_TLB0_CNTL 0x2234 155#define MC_VM_MB_L1_TLB1_CNTL 0x2238 156#define MC_VM_MB_L1_TLB2_CNTL 0x223C 157#define MC_VM_MB_L1_TLB3_CNTL 0x2240 158#define ENABLE_L1_TLB (1 << 0) 159#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 160#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 161#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 162#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 163#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 164#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 165#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 166#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 167#define MC_VM_MD_L1_TLB0_CNTL 0x2654 168#define MC_VM_MD_L1_TLB1_CNTL 0x2658 169#define MC_VM_MD_L1_TLB2_CNTL 0x265C 170#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 171#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 172#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 173 174#define PA_CL_ENHANCE 0x8A14 175#define CLIP_VTX_REORDER_ENA (1 << 0) 176#define NUM_CLIP_SEQ(x) ((x) << 1) 177#define PA_SC_AA_CONFIG 0x28C04 178#define PA_SC_CLIPRECT_RULE 0x2820C 179#define PA_SC_EDGERULE 0x28230 180#define PA_SC_FIFO_SIZE 0x8BCC 181#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 182#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 183#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 184#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 185#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 186#define PA_SC_LINE_STIPPLE 0x28A0C 187#define PA_SC_LINE_STIPPLE_STATE 0x8B10 188#define PA_SC_MODE_CNTL 0x28A4C 189#define PA_SC_MULTI_CHIP_CNTL 0x8B20 190#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 191 192#define SCRATCH_REG0 0x8500 193#define SCRATCH_REG1 0x8504 194#define SCRATCH_REG2 0x8508 195#define SCRATCH_REG3 0x850C 196#define SCRATCH_REG4 0x8510 197#define SCRATCH_REG5 0x8514 198#define SCRATCH_REG6 0x8518 199#define SCRATCH_REG7 0x851C 200#define SCRATCH_UMSK 0x8540 201#define SCRATCH_ADDR 0x8544 202 203#define SMX_DC_CTL0 0xA020 204#define USE_HASH_FUNCTION (1 << 0) 205#define CACHE_DEPTH(x) ((x) << 1) 206#define FLUSH_ALL_ON_EVENT (1 << 10) 207#define STALL_ON_EVENT (1 << 11) 208#define SMX_EVENT_CTL 0xA02C 209#define ES_FLUSH_CTL(x) ((x) << 0) 210#define GS_FLUSH_CTL(x) ((x) << 3) 211#define ACK_FLUSH_CTL(x) ((x) << 6) 212#define SYNC_FLUSH_CTL (1 << 8) 213 214#define SPI_CONFIG_CNTL 0x9100 215#define GPR_WRITE_PRIORITY(x) ((x) << 0) 216#define DISABLE_INTERP_1 (1 << 5) 217#define SPI_CONFIG_CNTL_1 0x913C 218#define VTX_DONE_DELAY(x) ((x) << 0) 219#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 220#define SPI_INPUT_Z 0x286D8 221#define SPI_PS_IN_CONTROL_0 0x286CC 222#define NUM_INTERP(x) ((x)<<0) 223#define POSITION_ENA (1<<8) 224#define POSITION_CENTROID (1<<9) 225#define POSITION_ADDR(x) ((x)<<10) 226#define PARAM_GEN(x) ((x)<<15) 227#define PARAM_GEN_ADDR(x) ((x)<<19) 228#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 229#define PERSP_GRADIENT_ENA (1<<28) 230#define LINEAR_GRADIENT_ENA (1<<29) 231#define POSITION_SAMPLE (1<<30) 232#define BARYC_AT_SAMPLE_ENA (1<<31) 233 234#define SQ_CONFIG 0x8C00 235#define VC_ENABLE (1 << 0) 236#define EXPORT_SRC_C (1 << 1) 237#define DX9_CONSTS (1 << 2) 238#define ALU_INST_PREFER_VECTOR (1 << 3) 239#define DX10_CLAMP (1 << 4) 240#define CLAUSE_SEQ_PRIO(x) ((x) << 8) 241#define PS_PRIO(x) ((x) << 24) 242#define VS_PRIO(x) ((x) << 26) 243#define GS_PRIO(x) ((x) << 28) 244#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 245#define SIMDA_RING0(x) ((x)<<0) 246#define SIMDA_RING1(x) ((x)<<8) 247#define SIMDB_RING0(x) ((x)<<16) 248#define SIMDB_RING1(x) ((x)<<24) 249#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 250#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 251#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC 252#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 253#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 254#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 255#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC 256#define ES_PRIO(x) ((x) << 30) 257#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 258#define NUM_PS_GPRS(x) ((x) << 0) 259#define NUM_VS_GPRS(x) ((x) << 16) 260#define DYN_GPR_ENABLE (1 << 27) 261#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 262#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 263#define NUM_GS_GPRS(x) ((x) << 0) 264#define NUM_ES_GPRS(x) ((x) << 16) 265#define SQ_MS_FIFO_SIZES 0x8CF0 266#define CACHE_FIFO_SIZE(x) ((x) << 0) 267#define FETCH_FIFO_HIWATER(x) ((x) << 8) 268#define DONE_FIFO_HIWATER(x) ((x) << 16) 269#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 270#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 271#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 272#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 273#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 274#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 275#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 276#define SQ_THREAD_RESOURCE_MGMT 0x8C0C 277#define NUM_PS_THREADS(x) ((x) << 0) 278#define NUM_VS_THREADS(x) ((x) << 8) 279#define NUM_GS_THREADS(x) ((x) << 16) 280#define NUM_ES_THREADS(x) ((x) << 24) 281 282#define SX_DEBUG_1 0x9058 283#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 284#define SX_EXPORT_BUFFER_SIZES 0x900C 285#define COLOR_BUFFER_SIZE(x) ((x) << 0) 286#define POSITION_BUFFER_SIZE(x) ((x) << 8) 287#define SMX_BUFFER_SIZE(x) ((x) << 16) 288#define SX_MISC 0x28350 289 290#define TA_CNTL_AUX 0x9508 291#define DISABLE_CUBE_WRAP (1 << 0) 292#define DISABLE_CUBE_ANISO (1 << 1) 293#define SYNC_GRADIENT (1 << 24) 294#define SYNC_WALKER (1 << 25) 295#define SYNC_ALIGNER (1 << 26) 296#define BILINEAR_PRECISION_6_BIT (0 << 31) 297#define BILINEAR_PRECISION_8_BIT (1 << 31) 298 299#define TCP_CNTL 0x9610 300 301#define VGT_CACHE_INVALIDATION 0x88C4 302#define CACHE_INVALIDATION(x) ((x)<<0) 303#define VC_ONLY 0 304#define TC_ONLY 1 305#define VC_AND_TC 2 306#define AUTO_INVLD_EN(x) ((x) << 6) 307#define NO_AUTO 0 308#define ES_AUTO 1 309#define GS_AUTO 2 310#define ES_AND_GS_AUTO 3 311#define VGT_ES_PER_GS 0x88CC 312#define VGT_GS_PER_ES 0x88C8 313#define VGT_GS_PER_VS 0x88E8 314#define VGT_GS_VERTEX_REUSE 0x88D4 315#define VGT_NUM_INSTANCES 0x8974 316#define VGT_OUT_DEALLOC_CNTL 0x28C5C 317#define DEALLOC_DIST_MASK 0x0000007F 318#define VGT_STRMOUT_EN 0x28AB0 319#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 320#define VTX_REUSE_DEPTH_MASK 0x000000FF 321 322#define VM_CONTEXT0_CNTL 0x1410 323#define ENABLE_CONTEXT (1 << 0) 324#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 325#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 326#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 327#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 328#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 329#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 330#define VM_L2_CNTL 0x1400 331#define ENABLE_L2_CACHE (1 << 0) 332#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 333#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 334#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 335#define VM_L2_CNTL2 0x1404 336#define INVALIDATE_ALL_L1_TLBS (1 << 0) 337#define INVALIDATE_L2_CACHE (1 << 1) 338#define VM_L2_CNTL3 0x1408 339#define BANK_SELECT(x) ((x) << 0) 340#define CACHE_UPDATE_MODE(x) ((x) << 6) 341#define VM_L2_STATUS 0x140C 342#define L2_BUSY (1 << 0) 343 344#define WAIT_UNTIL 0x8040 345 346#endif 347