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85#include <linux/kernel.h>
86#include <linux/list.h>
87#include <linux/slab.h>
88#include <linux/interrupt.h>
89#include <linux/wait.h>
90#include <linux/errno.h>
91#include <linux/module.h>
92#include <linux/moduleparam.h>
93#include <linux/pci.h>
94#include <linux/fs.h>
95#include <linux/poll.h>
96#include <asm/byteorder.h>
97#include <asm/atomic.h>
98#include <asm/uaccess.h>
99#include <linux/delay.h>
100#include <linux/spinlock.h>
101
102#include <asm/pgtable.h>
103#include <asm/page.h>
104#include <asm/irq.h>
105#include <linux/types.h>
106#include <linux/vmalloc.h>
107#include <linux/init.h>
108
109#ifdef CONFIG_PPC_PMAC
110#include <asm/machdep.h>
111#include <asm/pmac_feature.h>
112#include <asm/prom.h>
113#include <asm/pci-bridge.h>
114#endif
115
116#include "csr1212.h"
117#include "ieee1394.h"
118#include "ieee1394_types.h"
119#include "hosts.h"
120#include "dma.h"
121#include "iso.h"
122#include "ieee1394_core.h"
123#include "highlevel.h"
124#include "ohci1394.h"
125
126#ifdef CONFIG_IEEE1394_VERBOSEDEBUG
127#define OHCI1394_DEBUG
128#endif
129
130#ifdef DBGMSG
131#undef DBGMSG
132#endif
133
134#ifdef OHCI1394_DEBUG
135#define DBGMSG(fmt, args...) \
136printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
137#else
138#define DBGMSG(fmt, args...) do {} while (0)
139#endif
140
141
142#define PRINT_G(level, fmt, args...) \
143printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args)
144
145
146#define PRINT(level, fmt, args...) \
147printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
148
149
150static int phys_dma = 1;
151module_param(phys_dma, int, 0444);
152MODULE_PARM_DESC(phys_dma, "Enable physical DMA (default = 1).");
153
154static void dma_trm_tasklet(unsigned long data);
155static void dma_trm_reset(struct dma_trm_ctx *d);
156
157static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
158 enum context_type type, int ctx, int num_desc,
159 int buf_size, int split_buf_size, int context_base);
160static void free_dma_rcv_ctx(struct dma_rcv_ctx *d);
161
162static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
163 enum context_type type, int ctx, int num_desc,
164 int context_base);
165
166static void ohci1394_pci_remove(struct pci_dev *pdev);
167
168#ifndef __LITTLE_ENDIAN
169static const size_t hdr_sizes[] = {
170 3,
171 4,
172 3,
173 0,
174 3,
175 4,
176 3,
177 4,
178 1,
179 4,
180 2,
181 4,
182
183};
184
185static inline void header_le32_to_cpu(quadlet_t *data, unsigned char tcode)
186{
187 size_t size;
188
189 if (unlikely(tcode >= ARRAY_SIZE(hdr_sizes)))
190 return;
191
192 size = hdr_sizes[tcode];
193 while (size--)
194 data[size] = le32_to_cpu(data[size]);
195}
196#else
197#define header_le32_to_cpu(w,x) do {} while (0)
198#endif
199
200
201
202
203
204static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr)
205{
206 int i;
207 unsigned long flags;
208 quadlet_t r;
209
210 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
211
212 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
213
214 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
215 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
216 break;
217
218 mdelay(1);
219 }
220
221 r = reg_read(ohci, OHCI1394_PhyControl);
222
223 if (i >= OHCI_LOOP_COUNT)
224 PRINT (KERN_ERR, "Get PHY Reg timeout [0x%08x/0x%08x/%d]",
225 r, r & 0x80000000, i);
226
227 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
228
229 return (r & 0x00ff0000) >> 16;
230}
231
232static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
233{
234 int i;
235 unsigned long flags;
236 u32 r = 0;
237
238 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
239
240 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
241
242 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
243 r = reg_read(ohci, OHCI1394_PhyControl);
244 if (!(r & 0x00004000))
245 break;
246
247 mdelay(1);
248 }
249
250 if (i == OHCI_LOOP_COUNT)
251 PRINT (KERN_ERR, "Set PHY Reg timeout [0x%08x/0x%08x/%d]",
252 r, r & 0x00004000, i);
253
254 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
255
256 return;
257}
258
259
260static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
261{
262 u8 old;
263
264 old = get_phy_reg (ohci, addr);
265 old |= data;
266 set_phy_reg (ohci, addr, old);
267
268 return;
269}
270
271static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
272 int phyid, int isroot)
273{
274 quadlet_t *q = ohci->selfid_buf_cpu;
275 quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
276 size_t size;
277 quadlet_t q0, q1;
278
279
280
281 if (ohci->selfid_swap)
282 q0 = le32_to_cpu(q[0]);
283 else
284 q0 = q[0];
285
286 if ((self_id_count & 0x80000000) ||
287 ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) {
288 PRINT(KERN_ERR,
289 "Error in reception of SelfID packets [0x%08x/0x%08x] (count: %d)",
290 self_id_count, q0, ohci->self_id_errors);
291
292
293
294 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
295 set_phy_reg_mask (ohci, 1, 0x40);
296 ohci->self_id_errors++;
297 } else {
298 PRINT(KERN_ERR,
299 "Too many errors on SelfID error reception, giving up!");
300 }
301 return;
302 }
303
304
305 ohci->self_id_errors = 0;
306
307 size = ((self_id_count & 0x00001FFC) >> 2) - 1;
308 q++;
309
310 while (size > 0) {
311 if (ohci->selfid_swap) {
312 q0 = le32_to_cpu(q[0]);
313 q1 = le32_to_cpu(q[1]);
314 } else {
315 q0 = q[0];
316 q1 = q[1];
317 }
318
319 if (q0 == ~q1) {
320 DBGMSG ("SelfID packet 0x%x received", q0);
321 hpsb_selfid_received(host, cpu_to_be32(q0));
322 if (((q0 & 0x3f000000) >> 24) == phyid)
323 DBGMSG ("SelfID for this node is 0x%08x", q0);
324 } else {
325 PRINT(KERN_ERR,
326 "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1);
327 }
328 q += 2;
329 size -= 2;
330 }
331
332 DBGMSG("SelfID complete");
333
334 return;
335}
336
337static void ohci_soft_reset(struct ti_ohci *ohci) {
338 int i;
339
340 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
341
342 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
343 if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset))
344 break;
345 mdelay(1);
346 }
347 DBGMSG ("Soft reset finished");
348}
349
350
351
352static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d, int generate_irq)
353{
354 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
355 int i;
356
357 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
358
359 for (i=0; i<d->num_desc; i++) {
360 u32 c;
361
362 c = DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | DMA_CTL_BRANCH;
363 if (generate_irq)
364 c |= DMA_CTL_IRQ;
365
366 d->prg_cpu[i]->control = cpu_to_le32(c | d->buf_size);
367
368
369 if (i + 1 < d->num_desc) {
370 d->prg_cpu[i]->branchAddress =
371 cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1);
372 } else {
373 d->prg_cpu[i]->branchAddress =
374 cpu_to_le32((d->prg_bus[0] & 0xfffffff0));
375 }
376
377 d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]);
378 d->prg_cpu[i]->status = cpu_to_le32(d->buf_size);
379 }
380
381 d->buf_ind = 0;
382 d->buf_offset = 0;
383
384 if (d->type == DMA_CTX_ISO) {
385
386 reg_write(ohci, d->ctrlClear, 0xffffffff);
387
388
389 reg_write(ohci, d->ctrlSet, 0xd0000000);
390
391
392 reg_write(ohci, d->ctxtMatch, 0xf0000000);
393
394
395 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
396 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
397
398
399 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx);
400 }
401
402
403 reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
404
405
406 reg_write(ohci, d->ctrlSet, 0x00008000);
407
408 DBGMSG("Receive DMA ctx=%d initialized", d->ctx);
409}
410
411
412static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
413{
414 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
415
416
417 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
418
419 d->prg_ind = 0;
420 d->sent_ind = 0;
421 d->free_prgs = d->num_desc;
422 d->branchAddrPtr = NULL;
423 INIT_LIST_HEAD(&d->fifo_list);
424 INIT_LIST_HEAD(&d->pending_list);
425
426 if (d->type == DMA_CTX_ISO) {
427
428 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx);
429 }
430
431 DBGMSG("Transmit DMA ctx=%d initialized", d->ctx);
432}
433
434
435static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
436{
437 int i,ctx=0;
438 u32 tmp;
439
440 reg_write(ohci, reg, 0xffffffff);
441 tmp = reg_read(ohci, reg);
442
443 DBGMSG("Iso contexts reg: %08x implemented: %08x", reg, tmp);
444
445
446 for (i=0; i<32; i++) {
447 if (tmp & 1) ctx++;
448 tmp >>= 1;
449 }
450 return ctx;
451}
452
453
454static void ohci_initialize(struct ti_ohci *ohci)
455{
456 quadlet_t buf;
457 int num_ports, i;
458
459 spin_lock_init(&ohci->phy_reg_lock);
460
461
462 buf = reg_read(ohci, OHCI1394_BusOptions);
463 buf |= 0x60000000;
464 if (hpsb_disable_irm)
465 buf &= ~0x80000000;
466 else
467 buf |= 0x80000000;
468 buf &= ~0x00ff0000;
469 buf &= ~0x18000000;
470 reg_write(ohci, OHCI1394_BusOptions, buf);
471
472
473 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
474
475
476 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);
477
478
479 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
480
481
482
483 reg_write(ohci, OHCI1394_LinkControlSet,
484 OHCI1394_LinkControl_CycleTimerEnable |
485 OHCI1394_LinkControl_CycleMaster);
486 i = get_phy_reg(ohci, 4) | PHY_04_LCTRL;
487 if (hpsb_disable_irm)
488 i &= ~PHY_04_CONTENDER;
489 else
490 i |= PHY_04_CONTENDER;
491 set_phy_reg(ohci, 4, i);
492
493
494 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
495
496
497 reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID);
498
499
500 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
501
502
503 ohci->max_packet_size =
504 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
505
506
507 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
508 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
509
510
511 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
512 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
513
514
515 initialize_dma_rcv_ctx(&ohci->ar_req_context, 0);
516 initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0);
517
518
519 initialize_dma_trm_ctx(&ohci->at_req_context);
520 initialize_dma_trm_ctx(&ohci->at_resp_context);
521
522
523 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
524
525
526
527
528
529
530
531 reg_write(ohci, OHCI1394_PhyUpperBound,
532 OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED >> 16);
533
534 DBGMSG("physUpperBoundOffset=%08x",
535 reg_read(ohci, OHCI1394_PhyUpperBound));
536
537
538 reg_write(ohci, OHCI1394_ATRetries,
539 OHCI1394_MAX_AT_REQ_RETRIES |
540 (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
541 (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
542
543
544 reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
545
546
547 reg_write(ohci, OHCI1394_IntMaskSet,
548 OHCI1394_unrecoverableError |
549 OHCI1394_masterIntEnable |
550 OHCI1394_busReset |
551 OHCI1394_selfIDComplete |
552 OHCI1394_RSPkt |
553 OHCI1394_RQPkt |
554 OHCI1394_respTxComplete |
555 OHCI1394_reqTxComplete |
556 OHCI1394_isochRx |
557 OHCI1394_isochTx |
558 OHCI1394_postedWriteErr |
559 OHCI1394_cycleTooLong |
560 OHCI1394_cycleInconsistent);
561
562
563 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
564
565 buf = reg_read(ohci, OHCI1394_Version);
566 PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%d] "
567 "MMIO=[%llx-%llx] Max Packet=[%d] IR/IT contexts=[%d/%d]",
568 ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
569 ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), ohci->dev->irq,
570 (unsigned long long)pci_resource_start(ohci->dev, 0),
571 (unsigned long long)pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
572 ohci->max_packet_size,
573 ohci->nb_iso_rcv_ctx, ohci->nb_iso_xmit_ctx);
574
575
576
577 num_ports = get_phy_reg(ohci, 2) & 0xf;
578 for (i = 0; i < num_ports; i++) {
579 unsigned int status;
580
581 set_phy_reg(ohci, 7, i);
582 status = get_phy_reg(ohci, 8);
583
584 if (status & 0x20)
585 set_phy_reg(ohci, 8, status & ~1);
586 }
587
588
589 if ((ohci->max_packet_size < 512) ||
590 (ohci->max_packet_size > 4096)) {
591
592
593
594#ifdef CONFIG_IEEE1394_VERBOSEDEBUG
595 int i;
596#endif
597
598 PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, "
599 "attempting to set max_packet_size to 512 bytes");
600 reg_write(ohci, OHCI1394_BusOptions,
601 (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002);
602 ohci->max_packet_size = 512;
603#ifdef CONFIG_IEEE1394_VERBOSEDEBUG
604 PRINT(KERN_DEBUG, " EEPROM Present: %d",
605 (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1);
606 reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);
607
608 for (i = 0;
609 ((i < 1000) &&
610 (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++)
611 udelay(10);
612
613 for (i = 0; i < 0x20; i++) {
614 reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);
615 PRINT(KERN_DEBUG, " EEPROM %02x: %02x", i,
616 (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff);
617 }
618#endif
619 }
620}
621
622
623
624
625
626
627
628
629static void insert_packet(struct ti_ohci *ohci,
630 struct dma_trm_ctx *d, struct hpsb_packet *packet)
631{
632 u32 cycleTimer;
633 int idx = d->prg_ind;
634
635 DBGMSG("Inserting packet for node " NODE_BUS_FMT
636 ", tlabel=%d, tcode=0x%x, speed=%d",
637 NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel,
638 packet->tcode, packet->speed_code);
639
640 d->prg_cpu[idx]->begin.address = 0;
641 d->prg_cpu[idx]->begin.branchAddress = 0;
642
643 if (d->type == DMA_CTX_ASYNC_RESP) {
644
645
646
647
648 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
649 d->prg_cpu[idx]->begin.status = cpu_to_le32(
650 (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
651 ((cycleTimer&0x01fff000)>>12));
652
653 DBGMSG("cycleTimer: %08x timeStamp: %08x",
654 cycleTimer, d->prg_cpu[idx]->begin.status);
655 } else
656 d->prg_cpu[idx]->begin.status = 0;
657
658 if ( (packet->type == hpsb_async) || (packet->type == hpsb_raw) ) {
659
660 if (packet->type == hpsb_raw) {
661 d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4);
662 d->prg_cpu[idx]->data[1] = cpu_to_le32(packet->header[0]);
663 d->prg_cpu[idx]->data[2] = cpu_to_le32(packet->header[1]);
664 } else {
665 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
666 (packet->header[0] & 0xFFFF);
667
668 if (packet->tcode == TCODE_ISO_DATA) {
669
670 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
671 } else {
672
673 d->prg_cpu[idx]->data[1] =
674 (packet->header[1] & 0xFFFF) |
675 (packet->header[0] & 0xFFFF0000);
676 d->prg_cpu[idx]->data[2] = packet->header[2];
677 d->prg_cpu[idx]->data[3] = packet->header[3];
678 }
679 header_le32_to_cpu(d->prg_cpu[idx]->data, packet->tcode);
680 }
681
682 if (packet->data_size) {
683 if (packet->tcode == TCODE_STREAM_DATA){
684 d->prg_cpu[idx]->begin.control =
685 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
686 DMA_CTL_IMMEDIATE | 0x8);
687 } else {
688 d->prg_cpu[idx]->begin.control =
689 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
690 DMA_CTL_IMMEDIATE | 0x10);
691 }
692 d->prg_cpu[idx]->end.control =
693 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
694 DMA_CTL_IRQ |
695 DMA_CTL_BRANCH |
696 packet->data_size);
697
698
699
700
701
702
703
704
705#if 0
706 if (cross_bound((unsigned long)packet->data,
707 packet->data_size)>0) {
708
709 PRINT(KERN_ERR,
710 "%s: packet data addr: %p size %Zd bytes "
711 "cross page boundary", __func__,
712 packet->data, packet->data_size);
713 }
714#endif
715 d->prg_cpu[idx]->end.address = cpu_to_le32(
716 pci_map_single(ohci->dev, packet->data,
717 packet->data_size,
718 PCI_DMA_TODEVICE));
719
720 d->prg_cpu[idx]->end.branchAddress = 0;
721 d->prg_cpu[idx]->end.status = 0;
722 if (d->branchAddrPtr)
723 *(d->branchAddrPtr) =
724 cpu_to_le32(d->prg_bus[idx] | 0x3);
725 d->branchAddrPtr =
726 &(d->prg_cpu[idx]->end.branchAddress);
727 } else {
728 if (packet->type == hpsb_raw)
729 d->prg_cpu[idx]->begin.control =
730 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
731 DMA_CTL_IMMEDIATE |
732 DMA_CTL_IRQ |
733 DMA_CTL_BRANCH |
734 (packet->header_size + 4));
735 else
736 d->prg_cpu[idx]->begin.control =
737 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
738 DMA_CTL_IMMEDIATE |
739 DMA_CTL_IRQ |
740 DMA_CTL_BRANCH |
741 packet->header_size);
742
743 if (d->branchAddrPtr)
744 *(d->branchAddrPtr) =
745 cpu_to_le32(d->prg_bus[idx] | 0x2);
746 d->branchAddrPtr =
747 &(d->prg_cpu[idx]->begin.branchAddress);
748 }
749
750 } else {
751 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
752 (packet->header[0] & 0xFFFF);
753 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
754 header_le32_to_cpu(d->prg_cpu[idx]->data, packet->tcode);
755
756 d->prg_cpu[idx]->begin.control =
757 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
758 DMA_CTL_IMMEDIATE | 0x8);
759 d->prg_cpu[idx]->end.control =
760 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
761 DMA_CTL_UPDATE |
762 DMA_CTL_IRQ |
763 DMA_CTL_BRANCH |
764 packet->data_size);
765 d->prg_cpu[idx]->end.address = cpu_to_le32(
766 pci_map_single(ohci->dev, packet->data,
767 packet->data_size, PCI_DMA_TODEVICE));
768
769 d->prg_cpu[idx]->end.branchAddress = 0;
770 d->prg_cpu[idx]->end.status = 0;
771 DBGMSG("Iso xmit context info: header[%08x %08x]\n"
772 " begin=%08x %08x %08x %08x\n"
773 " %08x %08x %08x %08x\n"
774 " end =%08x %08x %08x %08x",
775 d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1],
776 d->prg_cpu[idx]->begin.control,
777 d->prg_cpu[idx]->begin.address,
778 d->prg_cpu[idx]->begin.branchAddress,
779 d->prg_cpu[idx]->begin.status,
780 d->prg_cpu[idx]->data[0],
781 d->prg_cpu[idx]->data[1],
782 d->prg_cpu[idx]->data[2],
783 d->prg_cpu[idx]->data[3],
784 d->prg_cpu[idx]->end.control,
785 d->prg_cpu[idx]->end.address,
786 d->prg_cpu[idx]->end.branchAddress,
787 d->prg_cpu[idx]->end.status);
788 if (d->branchAddrPtr)
789 *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3);
790 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
791 }
792 d->free_prgs--;
793
794
795 list_add_tail(&packet->driver_list, &d->fifo_list);
796 d->prg_ind = (d->prg_ind + 1) % d->num_desc;
797}
798
799
800
801
802
803
804
805static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
806{
807 struct hpsb_packet *packet, *ptmp;
808 int idx = d->prg_ind;
809 int z = 0;
810
811
812 list_for_each_entry_safe(packet, ptmp, &d->pending_list, driver_list) {
813 if (!d->free_prgs)
814 break;
815
816
817 if (!z)
818 z = (packet->data_size) ? 3 : 2;
819
820
821 list_del_init(&packet->driver_list);
822 insert_packet(ohci, d, packet);
823 }
824
825
826 if (z == 0)
827 return;
828
829
830
831 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
832 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
833
834 DBGMSG("Starting transmit DMA ctx=%d",d->ctx);
835 reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z);
836
837
838 if (!(nodeId & 0x80000000) || (nodeId & 0x3f) == 63)
839 PRINT(KERN_ERR, "Running dma failed because Node ID is not valid");
840 else
841 reg_write(ohci, d->ctrlSet, 0x8000);
842 } else {
843
844 if (!(reg_read(ohci, d->ctrlSet) & 0x400))
845 DBGMSG("Waking transmit DMA ctx=%d",d->ctx);
846
847
848 reg_write(ohci, d->ctrlSet, 0x1000);
849 }
850
851 return;
852}
853
854
855static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
856{
857 struct ti_ohci *ohci = host->hostdata;
858 struct dma_trm_ctx *d;
859 unsigned long flags;
860
861 if (packet->data_size > ohci->max_packet_size) {
862 PRINT(KERN_ERR,
863 "Transmit packet size %Zd is too big",
864 packet->data_size);
865 return -EOVERFLOW;
866 }
867
868 if (packet->type == hpsb_raw)
869 d = &ohci->at_req_context;
870 else if ((packet->tcode & 0x02) && (packet->tcode != TCODE_ISO_DATA))
871 d = &ohci->at_resp_context;
872 else
873 d = &ohci->at_req_context;
874
875 spin_lock_irqsave(&d->lock,flags);
876
877 list_add_tail(&packet->driver_list, &d->pending_list);
878
879 dma_trm_flush(ohci, d);
880
881 spin_unlock_irqrestore(&d->lock,flags);
882
883 return 0;
884}
885
886static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
887{
888 struct ti_ohci *ohci = host->hostdata;
889 int retval = 0, phy_reg;
890
891 switch (cmd) {
892 case RESET_BUS:
893 switch (arg) {
894 case SHORT_RESET:
895 phy_reg = get_phy_reg(ohci, 5);
896 phy_reg |= 0x40;
897 set_phy_reg(ohci, 5, phy_reg);
898 break;
899 case LONG_RESET:
900 phy_reg = get_phy_reg(ohci, 1);
901 phy_reg |= 0x40;
902 set_phy_reg(ohci, 1, phy_reg);
903 break;
904 case SHORT_RESET_NO_FORCE_ROOT:
905 phy_reg = get_phy_reg(ohci, 1);
906 if (phy_reg & 0x80) {
907 phy_reg &= ~0x80;
908 set_phy_reg(ohci, 1, phy_reg);
909 }
910
911 phy_reg = get_phy_reg(ohci, 5);
912 phy_reg |= 0x40;
913 set_phy_reg(ohci, 5, phy_reg);
914 break;
915 case LONG_RESET_NO_FORCE_ROOT:
916 phy_reg = get_phy_reg(ohci, 1);
917 phy_reg &= ~0x80;
918 phy_reg |= 0x40;
919 set_phy_reg(ohci, 1, phy_reg);
920 break;
921 case SHORT_RESET_FORCE_ROOT:
922 phy_reg = get_phy_reg(ohci, 1);
923 if (!(phy_reg & 0x80)) {
924 phy_reg |= 0x80;
925 set_phy_reg(ohci, 1, phy_reg);
926 }
927
928 phy_reg = get_phy_reg(ohci, 5);
929 phy_reg |= 0x40;
930 set_phy_reg(ohci, 5, phy_reg);
931 break;
932 case LONG_RESET_FORCE_ROOT:
933 phy_reg = get_phy_reg(ohci, 1);
934 phy_reg |= 0xc0;
935 set_phy_reg(ohci, 1, phy_reg);
936 break;
937 default:
938 retval = -1;
939 }
940 break;
941
942 case GET_CYCLE_COUNTER:
943 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
944 break;
945
946 case SET_CYCLE_COUNTER:
947 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
948 break;
949
950 case SET_BUS_ID:
951 PRINT(KERN_ERR, "devctl command SET_BUS_ID err");
952 break;
953
954 case ACT_CYCLE_MASTER:
955 if (arg) {
956
957 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
958 if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
959
960
961
962 DBGMSG("Cycle master enabled");
963 reg_write(ohci, OHCI1394_LinkControlSet,
964 OHCI1394_LinkControl_CycleTimerEnable |
965 OHCI1394_LinkControl_CycleMaster);
966 }
967 } else {
968
969 reg_write(ohci, OHCI1394_LinkControlClear,
970 OHCI1394_LinkControl_CycleTimerEnable |
971 OHCI1394_LinkControl_CycleMaster |
972 OHCI1394_LinkControl_CycleSource);
973 }
974 break;
975
976 case CANCEL_REQUESTS:
977 DBGMSG("Cancel request received");
978 dma_trm_reset(&ohci->at_req_context);
979 dma_trm_reset(&ohci->at_resp_context);
980 break;
981
982 default:
983 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
984 cmd);
985 break;
986 }
987 return retval;
988}
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007struct ohci_iso_recv {
1008 struct ti_ohci *ohci;
1009
1010 struct ohci1394_iso_tasklet task;
1011 int task_active;
1012
1013 enum { BUFFER_FILL_MODE = 0,
1014 PACKET_PER_BUFFER_MODE = 1 } dma_mode;
1015
1016
1017 struct dma_prog_region prog;
1018 struct dma_cmd *block;
1019
1020
1021 unsigned int nblocks;
1022
1023
1024 unsigned int buf_stride;
1025
1026
1027 int block_irq_interval;
1028
1029
1030 int block_dma;
1031
1032
1033 int block_reader;
1034
1035
1036
1037 int released_bytes;
1038
1039
1040 int dma_offset;
1041
1042
1043 u32 ContextControlSet;
1044 u32 ContextControlClear;
1045 u32 CommandPtr;
1046 u32 ContextMatch;
1047};
1048
1049static void ohci_iso_recv_task(unsigned long data);
1050static void ohci_iso_recv_stop(struct hpsb_iso *iso);
1051static void ohci_iso_recv_shutdown(struct hpsb_iso *iso);
1052static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync);
1053static void ohci_iso_recv_program(struct hpsb_iso *iso);
1054
1055static int ohci_iso_recv_init(struct hpsb_iso *iso)
1056{
1057 struct ti_ohci *ohci = iso->host->hostdata;
1058 struct ohci_iso_recv *recv;
1059 int ctx;
1060 int ret = -ENOMEM;
1061
1062 recv = kmalloc(sizeof(*recv), GFP_KERNEL);
1063 if (!recv)
1064 return -ENOMEM;
1065
1066 iso->hostdata = recv;
1067 recv->ohci = ohci;
1068 recv->task_active = 0;
1069 dma_prog_region_init(&recv->prog);
1070 recv->block = NULL;
1071
1072
1073
1074
1075 if (((iso->irq_interval == 1 && iso->dma_mode == HPSB_ISO_DMA_OLD_ABI) ||
1076 iso->dma_mode == HPSB_ISO_DMA_PACKET_PER_BUFFER) && iso->channel != -1) {
1077 recv->dma_mode = PACKET_PER_BUFFER_MODE;
1078 } else {
1079 recv->dma_mode = BUFFER_FILL_MODE;
1080 }
1081
1082
1083
1084 if (recv->dma_mode == BUFFER_FILL_MODE) {
1085 recv->buf_stride = PAGE_SIZE;
1086
1087
1088 recv->nblocks = iso->buf_size/PAGE_SIZE - 1;
1089 if (recv->nblocks < 3) {
1090 DBGMSG("ohci_iso_recv_init: DMA buffer too small");
1091 goto err;
1092 }
1093
1094
1095 if (iso->irq_interval == 1)
1096 recv->block_irq_interval = 1;
1097 else
1098 recv->block_irq_interval = iso->irq_interval *
1099 ((recv->nblocks+1)/iso->buf_packets);
1100 if (recv->block_irq_interval*4 > recv->nblocks)
1101 recv->block_irq_interval = recv->nblocks/4;
1102 if (recv->block_irq_interval < 1)
1103 recv->block_irq_interval = 1;
1104
1105 } else {
1106 int max_packet_size;
1107
1108 recv->nblocks = iso->buf_packets;
1109 recv->block_irq_interval = iso->irq_interval;
1110 if (recv->block_irq_interval * 4 > iso->buf_packets)
1111 recv->block_irq_interval = iso->buf_packets / 4;
1112 if (recv->block_irq_interval < 1)
1113 recv->block_irq_interval = 1;
1114
1115
1116
1117
1118 max_packet_size = iso->buf_size / iso->buf_packets;
1119
1120 for (recv->buf_stride = 8; recv->buf_stride < max_packet_size;
1121 recv->buf_stride *= 2);
1122
1123 if (recv->buf_stride*iso->buf_packets > iso->buf_size ||
1124 recv->buf_stride > PAGE_SIZE) {
1125
1126 DBGMSG("ohci_iso_recv_init: problem choosing a buffer stride");
1127 goto err;
1128 }
1129 }
1130
1131 recv->block_reader = 0;
1132 recv->released_bytes = 0;
1133 recv->block_dma = 0;
1134 recv->dma_offset = 0;
1135
1136
1137 if (dma_prog_region_alloc(&recv->prog,
1138 sizeof(struct dma_cmd) * recv->nblocks,
1139 recv->ohci->dev))
1140 goto err;
1141
1142 recv->block = (struct dma_cmd*) recv->prog.kvirt;
1143
1144 ohci1394_init_iso_tasklet(&recv->task,
1145 iso->channel == -1 ? OHCI_ISO_MULTICHANNEL_RECEIVE :
1146 OHCI_ISO_RECEIVE,
1147 ohci_iso_recv_task, (unsigned long) iso);
1148
1149 if (ohci1394_register_iso_tasklet(recv->ohci, &recv->task) < 0) {
1150 ret = -EBUSY;
1151 goto err;
1152 }
1153
1154 recv->task_active = 1;
1155
1156
1157 ctx = recv->task.context;
1158 recv->ContextControlSet = OHCI1394_IsoRcvContextControlSet + 32 * ctx;
1159 recv->ContextControlClear = OHCI1394_IsoRcvContextControlClear + 32 * ctx;
1160 recv->CommandPtr = OHCI1394_IsoRcvCommandPtr + 32 * ctx;
1161 recv->ContextMatch = OHCI1394_IsoRcvContextMatch + 32 * ctx;
1162
1163 if (iso->channel == -1) {
1164
1165 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF);
1166 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF);
1167 }
1168
1169
1170 ohci_iso_recv_program(iso);
1171
1172 DBGMSG("ohci_iso_recv_init: %s mode, DMA buffer is %lu pages"
1173 " (%u bytes), using %u blocks, buf_stride %u, block_irq_interval %d",
1174 recv->dma_mode == BUFFER_FILL_MODE ?
1175 "buffer-fill" : "packet-per-buffer",
1176 iso->buf_size/PAGE_SIZE, iso->buf_size,
1177 recv->nblocks, recv->buf_stride, recv->block_irq_interval);
1178
1179 return 0;
1180
1181err:
1182 ohci_iso_recv_shutdown(iso);
1183 return ret;
1184}
1185
1186static void ohci_iso_recv_stop(struct hpsb_iso *iso)
1187{
1188 struct ohci_iso_recv *recv = iso->hostdata;
1189
1190
1191 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context);
1192
1193
1194 ohci1394_stop_context(recv->ohci, recv->ContextControlClear, NULL);
1195}
1196
1197static void ohci_iso_recv_shutdown(struct hpsb_iso *iso)
1198{
1199 struct ohci_iso_recv *recv = iso->hostdata;
1200
1201 if (recv->task_active) {
1202 ohci_iso_recv_stop(iso);
1203 ohci1394_unregister_iso_tasklet(recv->ohci, &recv->task);
1204 recv->task_active = 0;
1205 }
1206
1207 dma_prog_region_free(&recv->prog);
1208 kfree(recv);
1209 iso->hostdata = NULL;
1210}
1211
1212
1213static void ohci_iso_recv_program(struct hpsb_iso *iso)
1214{
1215 struct ohci_iso_recv *recv = iso->hostdata;
1216 int blk;
1217
1218
1219 u32 *prev_branch = NULL;
1220
1221 for (blk = 0; blk < recv->nblocks; blk++) {
1222 u32 control;
1223
1224
1225 struct dma_cmd *cmd = &recv->block[blk];
1226
1227
1228 unsigned long prog_offset = blk * sizeof(struct dma_cmd);
1229
1230
1231 unsigned long buf_offset = blk * recv->buf_stride;
1232
1233 if (recv->dma_mode == BUFFER_FILL_MODE) {
1234 control = 2 << 28;
1235 } else {
1236 control = 3 << 28;
1237 }
1238
1239 control |= 8 << 24;
1240
1241
1242 if (blk == recv->nblocks-1 || (blk % recv->block_irq_interval) == 0) {
1243 control |= 3 << 20;
1244 }
1245
1246 control |= 3 << 18;
1247 control |= recv->buf_stride;
1248
1249 cmd->control = cpu_to_le32(control);
1250 cmd->address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, buf_offset));
1251 cmd->branchAddress = 0;
1252 cmd->status = cpu_to_le32(recv->buf_stride);
1253
1254
1255 if (prev_branch) {
1256 *prev_branch = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, prog_offset) | 1);
1257 }
1258
1259 prev_branch = &cmd->branchAddress;
1260 }
1261
1262
1263}
1264
1265
1266static void ohci_iso_recv_change_channel(struct hpsb_iso *iso, unsigned char channel, int listen)
1267{
1268 struct ohci_iso_recv *recv = iso->hostdata;
1269 int reg, i;
1270
1271 if (channel < 32) {
1272 reg = listen ? OHCI1394_IRMultiChanMaskLoSet : OHCI1394_IRMultiChanMaskLoClear;
1273 i = channel;
1274 } else {
1275 reg = listen ? OHCI1394_IRMultiChanMaskHiSet : OHCI1394_IRMultiChanMaskHiClear;
1276 i = channel - 32;
1277 }
1278
1279 reg_write(recv->ohci, reg, (1 << i));
1280
1281
1282 mb();
1283 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1284}
1285
1286static void ohci_iso_recv_set_channel_mask(struct hpsb_iso *iso, u64 mask)
1287{
1288 struct ohci_iso_recv *recv = iso->hostdata;
1289 int i;
1290
1291 for (i = 0; i < 64; i++) {
1292 if (mask & (1ULL << i)) {
1293 if (i < 32)
1294 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i));
1295 else
1296 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32)));
1297 } else {
1298 if (i < 32)
1299 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i));
1300 else
1301 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32)));
1302 }
1303 }
1304
1305
1306 mb();
1307 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1308}
1309
1310static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync)
1311{
1312 struct ohci_iso_recv *recv = iso->hostdata;
1313 struct ti_ohci *ohci = recv->ohci;
1314 u32 command, contextMatch;
1315
1316 reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF);
1317 wmb();
1318
1319
1320 command = (1 << 30);
1321
1322 if (recv->dma_mode == BUFFER_FILL_MODE)
1323 command |= (1 << 31);
1324
1325 reg_write(recv->ohci, recv->ContextControlSet, command);
1326
1327
1328 contextMatch = tag_mask << 28;
1329
1330 if (iso->channel == -1) {
1331
1332 reg_write(recv->ohci, recv->ContextControlSet, (1 << 28));
1333 } else {
1334
1335 contextMatch |= iso->channel;
1336 }
1337
1338 if (cycle != -1) {
1339 u32 seconds;
1340
1341
1342 reg_write(recv->ohci, recv->ContextControlSet, (1 << 29));
1343
1344
1345 cycle &= 0x1FFF;
1346
1347
1348
1349 seconds = reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
1350
1351
1352 seconds += 1;
1353
1354 cycle |= (seconds & 3) << 13;
1355
1356 contextMatch |= cycle << 12;
1357 }
1358
1359 if (sync != -1) {
1360
1361 struct dma_cmd *cmd = &recv->block[recv->block_dma];
1362 cmd->control |= cpu_to_le32(DMA_CTL_WAIT);
1363
1364
1365 contextMatch |= (sync&0xf)<<8;
1366 }
1367
1368 reg_write(recv->ohci, recv->ContextMatch, contextMatch);
1369
1370
1371 command = dma_prog_region_offset_to_bus(&recv->prog,
1372 recv->block_dma * sizeof(struct dma_cmd));
1373 command |= 1;
1374
1375 reg_write(recv->ohci, recv->CommandPtr, command);
1376
1377
1378 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context);
1379
1380 wmb();
1381
1382
1383 reg_write(recv->ohci, recv->ContextControlSet, 0x8000);
1384
1385
1386
1387 mb();
1388 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1389
1390
1391 if (!(reg_read(recv->ohci, recv->ContextControlSet) & 0x8000)) {
1392 PRINT(KERN_ERR,
1393 "Error starting IR DMA (ContextControl 0x%08x)\n",
1394 reg_read(recv->ohci, recv->ContextControlSet));
1395 return -1;
1396 }
1397
1398 return 0;
1399}
1400
1401static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block)
1402{
1403
1404
1405
1406 int next_i = block;
1407 int prev_i = (next_i == 0) ? (recv->nblocks - 1) : (next_i - 1);
1408
1409 struct dma_cmd *next = &recv->block[next_i];
1410 struct dma_cmd *prev = &recv->block[prev_i];
1411
1412
1413 if ((block < 0) || (block > recv->nblocks))
1414 return;
1415
1416
1417
1418 next->branchAddress = 0;
1419 next->control |= cpu_to_le32(3 << 20);
1420 next->status = cpu_to_le32(recv->buf_stride);
1421
1422
1423 prev->branchAddress = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog,
1424 sizeof(struct dma_cmd) * next_i)
1425 | 1);
1426
1427
1428 if ((prev_i % recv->block_irq_interval) == 0) {
1429 prev->control |= cpu_to_le32(3 << 20);
1430 } else {
1431 prev->control &= cpu_to_le32(~(3<<20));
1432 }
1433 wmb();
1434
1435
1436 reg_write(recv->ohci, recv->ContextControlSet, (1 << 12));
1437}
1438
1439static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv,
1440 struct hpsb_iso_packet_info *info)
1441{
1442
1443 recv->released_bytes += info->total_len;
1444
1445
1446 while (recv->released_bytes > recv->buf_stride) {
1447 ohci_iso_recv_release_block(recv, recv->block_reader);
1448 recv->block_reader = (recv->block_reader + 1) % recv->nblocks;
1449 recv->released_bytes -= recv->buf_stride;
1450 }
1451}
1452
1453static inline void ohci_iso_recv_release(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
1454{
1455 struct ohci_iso_recv *recv = iso->hostdata;
1456 if (recv->dma_mode == BUFFER_FILL_MODE) {
1457 ohci_iso_recv_bufferfill_release(recv, info);
1458 } else {
1459 ohci_iso_recv_release_block(recv, info - iso->infos);
1460 }
1461}
1462
1463
1464static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1465{
1466 int wake = 0;
1467 int runaway = 0;
1468 struct ti_ohci *ohci = recv->ohci;
1469
1470 while (1) {
1471
1472
1473
1474 unsigned int offset;
1475 unsigned short len, cycle, total_len;
1476 unsigned char channel, tag, sy;
1477
1478 unsigned char *p = iso->data_buf.kvirt;
1479
1480 unsigned int this_block = recv->dma_offset/recv->buf_stride;
1481
1482
1483 if (runaway++ > 100000) {
1484 atomic_inc(&iso->overflows);
1485 PRINT(KERN_ERR,
1486 "IR DMA error - Runaway during buffer parsing!\n");
1487 break;
1488 }
1489
1490
1491 if (this_block == recv->block_dma)
1492 break;
1493
1494 wake = 1;
1495
1496
1497
1498
1499
1500
1501 len = p[recv->dma_offset+2] | (p[recv->dma_offset+3] << 8);
1502
1503 if (len > 4096) {
1504 PRINT(KERN_ERR,
1505 "IR DMA error - bogus 'len' value %u\n", len);
1506 }
1507
1508 channel = p[recv->dma_offset+1] & 0x3F;
1509 tag = p[recv->dma_offset+1] >> 6;
1510 sy = p[recv->dma_offset+0] & 0xF;
1511
1512
1513 recv->dma_offset += 4;
1514
1515
1516 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1517 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1518 }
1519
1520
1521 offset = recv->dma_offset;
1522
1523
1524 recv->dma_offset += len;
1525
1526 total_len = len + 8;
1527
1528 if (len % 4) {
1529 recv->dma_offset += 4 - (len%4);
1530 total_len += 4 - (len%4);
1531 }
1532
1533
1534 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1535
1536
1537
1538
1539
1540 int guard_off = recv->buf_stride*recv->nblocks;
1541 int tail_len = len - (guard_off - offset);
1542
1543 if (tail_len > 0 && tail_len < recv->buf_stride) {
1544 memcpy(iso->data_buf.kvirt + guard_off,
1545 iso->data_buf.kvirt,
1546 tail_len);
1547 }
1548
1549 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1550 }
1551
1552
1553 cycle = p[recv->dma_offset+0] | (p[recv->dma_offset+1]<<8);
1554 cycle &= 0x1FFF;
1555
1556
1557 recv->dma_offset += 4;
1558
1559
1560 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1561 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1562 }
1563
1564 hpsb_iso_packet_received(iso, offset, len, total_len, cycle, channel, tag, sy);
1565 }
1566
1567 if (wake)
1568 hpsb_iso_wake(iso);
1569}
1570
1571static void ohci_iso_recv_bufferfill_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1572{
1573 int loop;
1574 struct ti_ohci *ohci = recv->ohci;
1575
1576
1577 for (loop = 0; loop < recv->nblocks; loop++) {
1578
1579
1580 struct dma_cmd *im = &recv->block[recv->block_dma];
1581
1582
1583 u16 xferstatus = le32_to_cpu(im->status) >> 16;
1584
1585
1586 u16 rescount = le32_to_cpu(im->status) & 0xFFFF;
1587
1588 unsigned char event = xferstatus & 0x1F;
1589
1590 if (!event) {
1591
1592 break;
1593 }
1594
1595 if (event != 0x11) {
1596 atomic_inc(&iso->overflows);
1597 PRINT(KERN_ERR,
1598 "IR DMA error - OHCI error code 0x%02x\n", event);
1599 }
1600
1601 if (rescount != 0) {
1602
1603
1604 break;
1605 }
1606
1607
1608
1609
1610 dma_region_sync_for_cpu(&iso->data_buf, recv->block_dma*recv->buf_stride, recv->buf_stride);
1611
1612
1613 im->status = recv->buf_stride;
1614
1615
1616 recv->block_dma = (recv->block_dma + 1) % recv->nblocks;
1617
1618 if ((recv->block_dma+1) % recv->nblocks == recv->block_reader) {
1619 atomic_inc(&iso->overflows);
1620 DBGMSG("ISO reception overflow - "
1621 "ran out of DMA blocks");
1622 }
1623 }
1624
1625
1626 ohci_iso_recv_bufferfill_parse(iso, recv);
1627}
1628
1629static void ohci_iso_recv_packetperbuf_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1630{
1631 int count;
1632 int wake = 0;
1633 struct ti_ohci *ohci = recv->ohci;
1634
1635
1636 for (count = 0; count < recv->nblocks; count++) {
1637 u32 packet_len = 0;
1638
1639
1640 struct dma_cmd *il = ((struct dma_cmd*) recv->prog.kvirt) + iso->pkt_dma;
1641
1642
1643 u16 xferstatus = le32_to_cpu(il->status) >> 16;
1644 u16 rescount = le32_to_cpu(il->status) & 0xFFFF;
1645
1646 unsigned char event = xferstatus & 0x1F;
1647
1648 if (!event) {
1649
1650 goto out;
1651 }
1652
1653 if (event == 0x11) {
1654
1655
1656
1657
1658 packet_len = recv->buf_stride - rescount;
1659
1660 } else if (event == 0x02) {
1661 PRINT(KERN_ERR, "IR DMA error - packet too long for buffer\n");
1662 } else if (event) {
1663 PRINT(KERN_ERR, "IR DMA error - OHCI error code 0x%02x\n", event);
1664 }
1665
1666
1667 dma_region_sync_for_cpu(&iso->data_buf, iso->pkt_dma * recv->buf_stride, recv->buf_stride);
1668
1669
1670 {
1671
1672 unsigned char *hdr;
1673
1674 unsigned int offset;
1675 unsigned short cycle;
1676 unsigned char channel, tag, sy;
1677
1678 offset = iso->pkt_dma * recv->buf_stride;
1679 hdr = iso->data_buf.kvirt + offset;
1680
1681
1682 offset += 8;
1683 packet_len -= 8;
1684
1685 cycle = (hdr[0] | (hdr[1] << 8)) & 0x1FFF;
1686 channel = hdr[5] & 0x3F;
1687 tag = hdr[5] >> 6;
1688 sy = hdr[4] & 0xF;
1689
1690 hpsb_iso_packet_received(iso, offset, packet_len,
1691 recv->buf_stride, cycle, channel, tag, sy);
1692 }
1693
1694
1695 il->status = recv->buf_stride;
1696
1697 wake = 1;
1698 recv->block_dma = iso->pkt_dma;
1699 }
1700
1701out:
1702 if (wake)
1703 hpsb_iso_wake(iso);
1704}
1705
1706static void ohci_iso_recv_task(unsigned long data)
1707{
1708 struct hpsb_iso *iso = (struct hpsb_iso*) data;
1709 struct ohci_iso_recv *recv = iso->hostdata;
1710
1711 if (recv->dma_mode == BUFFER_FILL_MODE)
1712 ohci_iso_recv_bufferfill_task(iso, recv);
1713 else
1714 ohci_iso_recv_packetperbuf_task(iso, recv);
1715}
1716
1717
1718
1719
1720
1721struct ohci_iso_xmit {
1722 struct ti_ohci *ohci;
1723 struct dma_prog_region prog;
1724 struct ohci1394_iso_tasklet task;
1725 int task_active;
1726 int last_cycle;
1727 atomic_t skips;
1728
1729 u32 ContextControlSet;
1730 u32 ContextControlClear;
1731 u32 CommandPtr;
1732};
1733
1734
1735
1736
1737
1738struct iso_xmit_cmd {
1739 struct dma_cmd output_more_immediate;
1740 u8 iso_hdr[8];
1741 u32 unused[2];
1742 struct dma_cmd output_last;
1743};
1744
1745static int ohci_iso_xmit_init(struct hpsb_iso *iso);
1746static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle);
1747static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso);
1748static void ohci_iso_xmit_task(unsigned long data);
1749
1750static int ohci_iso_xmit_init(struct hpsb_iso *iso)
1751{
1752 struct ohci_iso_xmit *xmit;
1753 unsigned int prog_size;
1754 int ctx;
1755 int ret = -ENOMEM;
1756
1757 xmit = kmalloc(sizeof(*xmit), GFP_KERNEL);
1758 if (!xmit)
1759 return -ENOMEM;
1760
1761 iso->hostdata = xmit;
1762 xmit->ohci = iso->host->hostdata;
1763 xmit->task_active = 0;
1764 xmit->last_cycle = -1;
1765 atomic_set(&iso->skips, 0);
1766
1767 dma_prog_region_init(&xmit->prog);
1768
1769 prog_size = sizeof(struct iso_xmit_cmd) * iso->buf_packets;
1770
1771 if (dma_prog_region_alloc(&xmit->prog, prog_size, xmit->ohci->dev))
1772 goto err;
1773
1774 ohci1394_init_iso_tasklet(&xmit->task, OHCI_ISO_TRANSMIT,
1775 ohci_iso_xmit_task, (unsigned long) iso);
1776
1777 if (ohci1394_register_iso_tasklet(xmit->ohci, &xmit->task) < 0) {
1778 ret = -EBUSY;
1779 goto err;
1780 }
1781
1782 xmit->task_active = 1;
1783
1784
1785 ctx = xmit->task.context;
1786 xmit->ContextControlSet = OHCI1394_IsoXmitContextControlSet + 16 * ctx;
1787 xmit->ContextControlClear = OHCI1394_IsoXmitContextControlClear + 16 * ctx;
1788 xmit->CommandPtr = OHCI1394_IsoXmitCommandPtr + 16 * ctx;
1789
1790 return 0;
1791
1792err:
1793 ohci_iso_xmit_shutdown(iso);
1794 return ret;
1795}
1796
1797static void ohci_iso_xmit_stop(struct hpsb_iso *iso)
1798{
1799 struct ohci_iso_xmit *xmit = iso->hostdata;
1800 struct ti_ohci *ohci = xmit->ohci;
1801
1802
1803 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context);
1804
1805
1806 if (ohci1394_stop_context(xmit->ohci, xmit->ContextControlClear, NULL)) {
1807
1808 PRINT(KERN_ERR,
1809 "you probably exceeded the OHCI card's bandwidth limit - "
1810 "reload the module and reduce xmit bandwidth");
1811 }
1812}
1813
1814static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso)
1815{
1816 struct ohci_iso_xmit *xmit = iso->hostdata;
1817
1818 if (xmit->task_active) {
1819 ohci_iso_xmit_stop(iso);
1820 ohci1394_unregister_iso_tasklet(xmit->ohci, &xmit->task);
1821 xmit->task_active = 0;
1822 }
1823
1824 dma_prog_region_free(&xmit->prog);
1825 kfree(xmit);
1826 iso->hostdata = NULL;
1827}
1828
1829static void ohci_iso_xmit_task(unsigned long data)
1830{
1831 struct hpsb_iso *iso = (struct hpsb_iso*) data;
1832 struct ohci_iso_xmit *xmit = iso->hostdata;
1833 struct ti_ohci *ohci = xmit->ohci;
1834 int wake = 0;
1835 int count;
1836
1837
1838 for (count = 0; count < iso->buf_packets; count++) {
1839 int cycle;
1840
1841
1842 struct iso_xmit_cmd *cmd = dma_region_i(&xmit->prog, struct iso_xmit_cmd, iso->pkt_dma);
1843
1844
1845 u16 xferstatus = le32_to_cpu(cmd->output_last.status) >> 16;
1846 u8 event = xferstatus & 0x1F;
1847
1848 if (!event) {
1849
1850 break;
1851 }
1852
1853 if (event != 0x11)
1854 PRINT(KERN_ERR,
1855 "IT DMA error - OHCI error code 0x%02x\n", event);
1856
1857
1858 wake = 1;
1859
1860
1861 cycle = le32_to_cpu(cmd->output_last.status) & 0x1FFF;
1862
1863 if (xmit->last_cycle > -1) {
1864 int cycle_diff = cycle - xmit->last_cycle;
1865 int skip;
1866
1867
1868 if (cycle_diff < 0) {
1869 cycle_diff += 8000;
1870 if (cycle_diff < 0)
1871 PRINT(KERN_ERR, "bogus cycle diff %d\n",
1872 cycle_diff);
1873 }
1874
1875 skip = cycle_diff - 1;
1876 if (skip > 0) {
1877 DBGMSG("skipped %d cycles without packet loss", skip);
1878 atomic_add(skip, &iso->skips);
1879 }
1880 }
1881 xmit->last_cycle = cycle;
1882
1883
1884 hpsb_iso_packet_sent(iso, cycle, event != 0x11);
1885
1886
1887 cmd->output_last.status = 0;
1888 }
1889
1890 if (wake)
1891 hpsb_iso_wake(iso);
1892}
1893
1894static int ohci_iso_xmit_queue(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
1895{
1896 struct ohci_iso_xmit *xmit = iso->hostdata;
1897 struct ti_ohci *ohci = xmit->ohci;
1898
1899 int next_i, prev_i;
1900 struct iso_xmit_cmd *next, *prev;
1901
1902 unsigned int offset;
1903 unsigned short len;
1904 unsigned char tag, sy;
1905
1906
1907
1908 if (cross_bound(info->offset, info->len)) {
1909 PRINT(KERN_ERR,
1910 "rawiso xmit: packet %u crosses a page boundary",
1911 iso->first_packet);
1912 return -EINVAL;
1913 }
1914
1915 offset = info->offset;
1916 len = info->len;
1917 tag = info->tag;
1918 sy = info->sy;
1919
1920
1921 dma_region_sync_for_device(&iso->data_buf, offset, len);
1922
1923
1924
1925
1926
1927 next_i = iso->first_packet;
1928 prev_i = (next_i == 0) ? (iso->buf_packets - 1) : (next_i - 1);
1929
1930 next = dma_region_i(&xmit->prog, struct iso_xmit_cmd, next_i);
1931 prev = dma_region_i(&xmit->prog, struct iso_xmit_cmd, prev_i);
1932
1933
1934 memset(next, 0, sizeof(struct iso_xmit_cmd));
1935 next->output_more_immediate.control = cpu_to_le32(0x02000008);
1936
1937
1938
1939
1940 next->iso_hdr[0] = 0xA0 | (sy & 0xF);
1941
1942
1943 next->iso_hdr[1] = (tag << 6) | (iso->channel & 0x3F);
1944
1945
1946 next->iso_hdr[2] = iso->speed & 0x7;
1947
1948
1949 next->iso_hdr[6] = len & 0xFF;
1950 next->iso_hdr[7] = len >> 8;
1951
1952
1953 next->output_last.control = cpu_to_le32(1 << 28);
1954 next->output_last.control |= cpu_to_le32(1 << 27);
1955 next->output_last.control |= cpu_to_le32(3 << 20);
1956 next->output_last.control |= cpu_to_le32(3 << 18);
1957 next->output_last.control |= cpu_to_le32(len);
1958
1959
1960 next->output_last.address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, offset));
1961
1962
1963
1964
1965
1966
1967 prev->output_last.branchAddress = cpu_to_le32(
1968 dma_prog_region_offset_to_bus(&xmit->prog, sizeof(struct iso_xmit_cmd) * next_i) | 3);
1969
1970
1971
1972
1973
1974
1975
1976
1977 next->output_more_immediate.branchAddress =
1978 prev->output_last.branchAddress;
1979
1980
1981 if (prev_i % iso->irq_interval) {
1982 prev->output_last.control &= cpu_to_le32(~(3 << 20));
1983 } else {
1984 prev->output_last.control |= cpu_to_le32(3 << 20);
1985 }
1986
1987 wmb();
1988
1989
1990 reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12);
1991
1992
1993
1994 mb();
1995 reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer);
1996
1997 return 0;
1998}
1999
2000static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle)
2001{
2002 struct ohci_iso_xmit *xmit = iso->hostdata;
2003 struct ti_ohci *ohci = xmit->ohci;
2004
2005
2006 reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF);
2007 wmb();
2008
2009
2010 reg_write(xmit->ohci, xmit->CommandPtr,
2011 dma_prog_region_offset_to_bus(&xmit->prog, iso->pkt_dma * sizeof(struct iso_xmit_cmd)) | 3);
2012
2013
2014 if (cycle != -1) {
2015 u32 start = cycle & 0x1FFF;
2016
2017
2018
2019 u32 seconds = reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
2020
2021
2022 seconds += 1;
2023
2024 start |= (seconds & 3) << 13;
2025
2026 reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16));
2027 }
2028
2029
2030 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context);
2031
2032
2033 reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000);
2034 mb();
2035
2036
2037 udelay(100);
2038
2039
2040 if (!(reg_read(xmit->ohci, xmit->ContextControlSet) & 0x8000)) {
2041 PRINT(KERN_ERR, "Error starting IT DMA (ContextControl 0x%08x)\n",
2042 reg_read(xmit->ohci, xmit->ContextControlSet));
2043 return -1;
2044 }
2045
2046 return 0;
2047}
2048
2049static int ohci_isoctl(struct hpsb_iso *iso, enum isoctl_cmd cmd, unsigned long arg)
2050{
2051
2052 switch(cmd) {
2053 case XMIT_INIT:
2054 return ohci_iso_xmit_init(iso);
2055 case XMIT_START:
2056 return ohci_iso_xmit_start(iso, arg);
2057 case XMIT_STOP:
2058 ohci_iso_xmit_stop(iso);
2059 return 0;
2060 case XMIT_QUEUE:
2061 return ohci_iso_xmit_queue(iso, (struct hpsb_iso_packet_info*) arg);
2062 case XMIT_SHUTDOWN:
2063 ohci_iso_xmit_shutdown(iso);
2064 return 0;
2065
2066 case RECV_INIT:
2067 return ohci_iso_recv_init(iso);
2068 case RECV_START: {
2069 int *args = (int*) arg;
2070 return ohci_iso_recv_start(iso, args[0], args[1], args[2]);
2071 }
2072 case RECV_STOP:
2073 ohci_iso_recv_stop(iso);
2074 return 0;
2075 case RECV_RELEASE:
2076 ohci_iso_recv_release(iso, (struct hpsb_iso_packet_info*) arg);
2077 return 0;
2078 case RECV_FLUSH:
2079 ohci_iso_recv_task((unsigned long) iso);
2080 return 0;
2081 case RECV_SHUTDOWN:
2082 ohci_iso_recv_shutdown(iso);
2083 return 0;
2084 case RECV_LISTEN_CHANNEL:
2085 ohci_iso_recv_change_channel(iso, arg, 1);
2086 return 0;
2087 case RECV_UNLISTEN_CHANNEL:
2088 ohci_iso_recv_change_channel(iso, arg, 0);
2089 return 0;
2090 case RECV_SET_CHANNEL_MASK:
2091 ohci_iso_recv_set_channel_mask(iso, *((u64*) arg));
2092 return 0;
2093
2094 default:
2095 PRINT_G(KERN_ERR, "ohci_isoctl cmd %d not implemented yet",
2096 cmd);
2097 break;
2098 }
2099 return -EINVAL;
2100}
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111static void dma_trm_reset(struct dma_trm_ctx *d)
2112{
2113 unsigned long flags;
2114 LIST_HEAD(packet_list);
2115 struct ti_ohci *ohci = d->ohci;
2116 struct hpsb_packet *packet, *ptmp;
2117
2118 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
2119
2120
2121
2122
2123
2124 spin_lock_irqsave(&d->lock, flags);
2125
2126 list_splice_init(&d->fifo_list, &packet_list);
2127 list_splice_init(&d->pending_list, &packet_list);
2128
2129 d->branchAddrPtr = NULL;
2130 d->sent_ind = d->prg_ind;
2131 d->free_prgs = d->num_desc;
2132
2133 spin_unlock_irqrestore(&d->lock, flags);
2134
2135 if (list_empty(&packet_list))
2136 return;
2137
2138 PRINT(KERN_INFO, "AT dma reset ctx=%d, aborting transmission", d->ctx);
2139
2140
2141
2142 list_for_each_entry_safe(packet, ptmp, &packet_list, driver_list) {
2143 list_del_init(&packet->driver_list);
2144 hpsb_packet_sent(ohci->host, packet, ACKX_ABORTED);
2145 }
2146}
2147
2148static void ohci_schedule_iso_tasklets(struct ti_ohci *ohci,
2149 quadlet_t rx_event,
2150 quadlet_t tx_event)
2151{
2152 struct ohci1394_iso_tasklet *t;
2153 unsigned long mask;
2154 unsigned long flags;
2155
2156 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
2157
2158 list_for_each_entry(t, &ohci->iso_tasklet_list, link) {
2159 mask = 1 << t->context;
2160
2161 if (t->type == OHCI_ISO_TRANSMIT) {
2162 if (tx_event & mask)
2163 tasklet_schedule(&t->tasklet);
2164 } else {
2165
2166 if (rx_event & mask)
2167 tasklet_schedule(&t->tasklet);
2168 }
2169 }
2170
2171 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
2172}
2173
2174static irqreturn_t ohci_irq_handler(int irq, void *dev_id)
2175{
2176 quadlet_t event, node_id;
2177 struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
2178 struct hpsb_host *host = ohci->host;
2179 int phyid = -1, isroot = 0;
2180 unsigned long flags;
2181
2182
2183
2184
2185 spin_lock_irqsave(&ohci->event_lock, flags);
2186 event = reg_read(ohci, OHCI1394_IntEventClear);
2187 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
2188 spin_unlock_irqrestore(&ohci->event_lock, flags);
2189
2190 if (!event)
2191 return IRQ_NONE;
2192
2193
2194
2195
2196 if (event == ~(u32) 0) {
2197 DBGMSG("Device removed.");
2198 return IRQ_NONE;
2199 }
2200
2201 DBGMSG("IntEvent: %08x", event);
2202
2203 if (event & OHCI1394_unrecoverableError) {
2204 int ctx;
2205 PRINT(KERN_ERR, "Unrecoverable error!");
2206
2207 if (reg_read(ohci, OHCI1394_AsReqTrContextControlSet) & 0x800)
2208 PRINT(KERN_ERR, "Async Req Tx Context died: "
2209 "ctrl[%08x] cmdptr[%08x]",
2210 reg_read(ohci, OHCI1394_AsReqTrContextControlSet),
2211 reg_read(ohci, OHCI1394_AsReqTrCommandPtr));
2212
2213 if (reg_read(ohci, OHCI1394_AsRspTrContextControlSet) & 0x800)
2214 PRINT(KERN_ERR, "Async Rsp Tx Context died: "
2215 "ctrl[%08x] cmdptr[%08x]",
2216 reg_read(ohci, OHCI1394_AsRspTrContextControlSet),
2217 reg_read(ohci, OHCI1394_AsRspTrCommandPtr));
2218
2219 if (reg_read(ohci, OHCI1394_AsReqRcvContextControlSet) & 0x800)
2220 PRINT(KERN_ERR, "Async Req Rcv Context died: "
2221 "ctrl[%08x] cmdptr[%08x]",
2222 reg_read(ohci, OHCI1394_AsReqRcvContextControlSet),
2223 reg_read(ohci, OHCI1394_AsReqRcvCommandPtr));
2224
2225 if (reg_read(ohci, OHCI1394_AsRspRcvContextControlSet) & 0x800)
2226 PRINT(KERN_ERR, "Async Rsp Rcv Context died: "
2227 "ctrl[%08x] cmdptr[%08x]",
2228 reg_read(ohci, OHCI1394_AsRspRcvContextControlSet),
2229 reg_read(ohci, OHCI1394_AsRspRcvCommandPtr));
2230
2231 for (ctx = 0; ctx < ohci->nb_iso_xmit_ctx; ctx++) {
2232 if (reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)) & 0x800)
2233 PRINT(KERN_ERR, "Iso Xmit %d Context died: "
2234 "ctrl[%08x] cmdptr[%08x]", ctx,
2235 reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)),
2236 reg_read(ohci, OHCI1394_IsoXmitCommandPtr + (16 * ctx)));
2237 }
2238
2239 for (ctx = 0; ctx < ohci->nb_iso_rcv_ctx; ctx++) {
2240 if (reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)) & 0x800)
2241 PRINT(KERN_ERR, "Iso Recv %d Context died: "
2242 "ctrl[%08x] cmdptr[%08x] match[%08x]", ctx,
2243 reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)),
2244 reg_read(ohci, OHCI1394_IsoRcvCommandPtr + (32 * ctx)),
2245 reg_read(ohci, OHCI1394_IsoRcvContextMatch + (32 * ctx)));
2246 }
2247
2248 event &= ~OHCI1394_unrecoverableError;
2249 }
2250 if (event & OHCI1394_postedWriteErr) {
2251 PRINT(KERN_ERR, "physical posted write error");
2252
2253 event &= ~OHCI1394_postedWriteErr;
2254 }
2255 if (event & OHCI1394_cycleTooLong) {
2256 if(printk_ratelimit())
2257 PRINT(KERN_WARNING, "isochronous cycle too long");
2258 else
2259 DBGMSG("OHCI1394_cycleTooLong");
2260 reg_write(ohci, OHCI1394_LinkControlSet,
2261 OHCI1394_LinkControl_CycleMaster);
2262 event &= ~OHCI1394_cycleTooLong;
2263 }
2264 if (event & OHCI1394_cycleInconsistent) {
2265
2266
2267
2268 DBGMSG("OHCI1394_cycleInconsistent");
2269 event &= ~OHCI1394_cycleInconsistent;
2270 }
2271 if (event & OHCI1394_busReset) {
2272
2273
2274
2275 spin_lock_irqsave(&ohci->event_lock, flags);
2276 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2277
2278 if (ohci->check_busreset) {
2279 int loop_count = 0;
2280
2281 udelay(10);
2282
2283 while (reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
2284 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2285
2286 spin_unlock_irqrestore(&ohci->event_lock, flags);
2287 udelay(10);
2288 spin_lock_irqsave(&ohci->event_lock, flags);
2289
2290
2291
2292
2293
2294
2295
2296 if (loop_count > 10000) {
2297 ohci_devctl(host, RESET_BUS, LONG_RESET);
2298 DBGMSG("Detected bus-reset loop. Forced a bus reset!");
2299 loop_count = 0;
2300 }
2301
2302 loop_count++;
2303 }
2304 }
2305 spin_unlock_irqrestore(&ohci->event_lock, flags);
2306 if (!host->in_bus_reset) {
2307 DBGMSG("irq_handler: Bus reset requested");
2308
2309
2310 hpsb_bus_reset(ohci->host);
2311 }
2312 event &= ~OHCI1394_busReset;
2313 }
2314 if (event & OHCI1394_reqTxComplete) {
2315 struct dma_trm_ctx *d = &ohci->at_req_context;
2316 DBGMSG("Got reqTxComplete interrupt "
2317 "status=0x%08X", reg_read(ohci, d->ctrlSet));
2318 if (reg_read(ohci, d->ctrlSet) & 0x800)
2319 ohci1394_stop_context(ohci, d->ctrlClear,
2320 "reqTxComplete");
2321 else
2322 dma_trm_tasklet((unsigned long)d);
2323
2324 event &= ~OHCI1394_reqTxComplete;
2325 }
2326 if (event & OHCI1394_respTxComplete) {
2327 struct dma_trm_ctx *d = &ohci->at_resp_context;
2328 DBGMSG("Got respTxComplete interrupt "
2329 "status=0x%08X", reg_read(ohci, d->ctrlSet));
2330 if (reg_read(ohci, d->ctrlSet) & 0x800)
2331 ohci1394_stop_context(ohci, d->ctrlClear,
2332 "respTxComplete");
2333 else
2334 tasklet_schedule(&d->task);
2335 event &= ~OHCI1394_respTxComplete;
2336 }
2337 if (event & OHCI1394_RQPkt) {
2338 struct dma_rcv_ctx *d = &ohci->ar_req_context;
2339 DBGMSG("Got RQPkt interrupt status=0x%08X",
2340 reg_read(ohci, d->ctrlSet));
2341 if (reg_read(ohci, d->ctrlSet) & 0x800)
2342 ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
2343 else
2344 tasklet_schedule(&d->task);
2345 event &= ~OHCI1394_RQPkt;
2346 }
2347 if (event & OHCI1394_RSPkt) {
2348 struct dma_rcv_ctx *d = &ohci->ar_resp_context;
2349 DBGMSG("Got RSPkt interrupt status=0x%08X",
2350 reg_read(ohci, d->ctrlSet));
2351 if (reg_read(ohci, d->ctrlSet) & 0x800)
2352 ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
2353 else
2354 tasklet_schedule(&d->task);
2355 event &= ~OHCI1394_RSPkt;
2356 }
2357 if (event & OHCI1394_isochRx) {
2358 quadlet_t rx_event;
2359
2360 rx_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
2361 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event);
2362 ohci_schedule_iso_tasklets(ohci, rx_event, 0);
2363 event &= ~OHCI1394_isochRx;
2364 }
2365 if (event & OHCI1394_isochTx) {
2366 quadlet_t tx_event;
2367
2368 tx_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
2369 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event);
2370 ohci_schedule_iso_tasklets(ohci, 0, tx_event);
2371 event &= ~OHCI1394_isochTx;
2372 }
2373 if (event & OHCI1394_selfIDComplete) {
2374 if (host->in_bus_reset) {
2375 node_id = reg_read(ohci, OHCI1394_NodeID);
2376
2377 if (!(node_id & 0x80000000)) {
2378 PRINT(KERN_ERR,
2379 "SelfID received, but NodeID invalid "
2380 "(probably new bus reset occurred): %08X",
2381 node_id);
2382 goto selfid_not_valid;
2383 }
2384
2385 phyid = node_id & 0x0000003f;
2386 isroot = (node_id & 0x40000000) != 0;
2387
2388 DBGMSG("SelfID interrupt received "
2389 "(phyid %d, %s)", phyid,
2390 (isroot ? "root" : "not root"));
2391
2392 handle_selfid(ohci, host, phyid, isroot);
2393
2394
2395
2396 spin_lock_irqsave(&ohci->event_lock, flags);
2397 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2398 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2399 spin_unlock_irqrestore(&ohci->event_lock, flags);
2400
2401
2402
2403
2404
2405 if (phys_dma) {
2406 reg_write(ohci, OHCI1394_PhyReqFilterHiSet,
2407 0xffffffff);
2408 reg_write(ohci, OHCI1394_PhyReqFilterLoSet,
2409 0xffffffff);
2410 }
2411
2412 DBGMSG("PhyReqFilter=%08x%08x",
2413 reg_read(ohci, OHCI1394_PhyReqFilterHiSet),
2414 reg_read(ohci, OHCI1394_PhyReqFilterLoSet));
2415
2416 hpsb_selfid_complete(host, phyid, isroot);
2417 } else
2418 PRINT(KERN_ERR,
2419 "SelfID received outside of bus reset sequence");
2420
2421selfid_not_valid:
2422 event &= ~OHCI1394_selfIDComplete;
2423 }
2424
2425
2426
2427 if (event)
2428 PRINT(KERN_ERR, "Unhandled interrupt(s) 0x%08x",
2429 event);
2430
2431 return IRQ_HANDLED;
2432}
2433
2434
2435static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
2436{
2437 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2438 DBGMSG("Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
2439
2440 d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size);
2441 d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0);
2442 idx = (idx + d->num_desc - 1 ) % d->num_desc;
2443 d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001);
2444
2445
2446
2447 wmb();
2448
2449
2450 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
2451 PRINT(KERN_INFO,
2452 "Waking dma ctx=%d ... processing is probably too slow",
2453 d->ctx);
2454 }
2455
2456
2457 reg_write(ohci, d->ctrlSet, 0x1000);
2458}
2459
2460#define cond_le32_to_cpu(data, noswap) \
2461 (noswap ? data : le32_to_cpu(data))
2462
2463static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0,
2464 -1, 0, -1, 0, -1, -1, 16, -1};
2465
2466
2467
2468
2469
2470static inline int packet_length(struct dma_rcv_ctx *d, int idx,
2471 quadlet_t *buf_ptr, int offset,
2472 unsigned char tcode, int noswap)
2473{
2474 int length = -1;
2475
2476 if (d->type == DMA_CTX_ASYNC_REQ || d->type == DMA_CTX_ASYNC_RESP) {
2477 length = TCODE_SIZE[tcode];
2478 if (length == 0) {
2479 if (offset + 12 >= d->buf_size) {
2480 length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc]
2481 [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16);
2482 } else {
2483 length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16);
2484 }
2485 length += 20;
2486 }
2487 } else if (d->type == DMA_CTX_ISO) {
2488
2489 length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8;
2490 }
2491
2492 if (length > 0 && length % 4)
2493 length += 4 - (length % 4);
2494
2495 return length;
2496}
2497
2498
2499static void dma_rcv_tasklet (unsigned long data)
2500{
2501 struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
2502 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2503 unsigned int split_left, idx, offset, rescount;
2504 unsigned char tcode;
2505 int length, bytes_left, ack;
2506 unsigned long flags;
2507 quadlet_t *buf_ptr;
2508 char *split_ptr;
2509 char msg[256];
2510
2511 spin_lock_irqsave(&d->lock, flags);
2512
2513 idx = d->buf_ind;
2514 offset = d->buf_offset;
2515 buf_ptr = d->buf_cpu[idx] + offset/4;
2516
2517 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2518 bytes_left = d->buf_size - rescount - offset;
2519
2520 while (bytes_left > 0) {
2521 tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming) >> 4) & 0xf;
2522
2523
2524 length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->no_swap_incoming);
2525
2526 if (length < 4) {
2527 sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d",
2528 tcode, cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming),
2529 d->ctx, length);
2530 ohci1394_stop_context(ohci, d->ctrlClear, msg);
2531 spin_unlock_irqrestore(&d->lock, flags);
2532 return;
2533 }
2534
2535
2536
2537
2538 if ((offset + length) > d->buf_size) {
2539 DBGMSG("Split packet rcv'd");
2540 if (length > d->split_buf_size) {
2541 ohci1394_stop_context(ohci, d->ctrlClear,
2542 "Split packet size exceeded");
2543 d->buf_ind = idx;
2544 d->buf_offset = offset;
2545 spin_unlock_irqrestore(&d->lock, flags);
2546 return;
2547 }
2548
2549 if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status)
2550 == d->buf_size) {
2551
2552
2553
2554 PRINT(KERN_INFO,
2555 "Got only half a packet!");
2556 d->buf_ind = idx;
2557 d->buf_offset = offset;
2558 spin_unlock_irqrestore(&d->lock, flags);
2559 return;
2560 }
2561
2562 split_left = length;
2563 split_ptr = (char *)d->spb;
2564 memcpy(split_ptr,buf_ptr,d->buf_size-offset);
2565 split_left -= d->buf_size-offset;
2566 split_ptr += d->buf_size-offset;
2567 insert_dma_buffer(d, idx);
2568 idx = (idx+1) % d->num_desc;
2569 buf_ptr = d->buf_cpu[idx];
2570 offset=0;
2571
2572 while (split_left >= d->buf_size) {
2573 memcpy(split_ptr,buf_ptr,d->buf_size);
2574 split_ptr += d->buf_size;
2575 split_left -= d->buf_size;
2576 insert_dma_buffer(d, idx);
2577 idx = (idx+1) % d->num_desc;
2578 buf_ptr = d->buf_cpu[idx];
2579 }
2580
2581 if (split_left > 0) {
2582 memcpy(split_ptr, buf_ptr, split_left);
2583 offset = split_left;
2584 buf_ptr += offset/4;
2585 }
2586 } else {
2587 DBGMSG("Single packet rcv'd");
2588 memcpy(d->spb, buf_ptr, length);
2589 offset += length;
2590 buf_ptr += length/4;
2591 if (offset==d->buf_size) {
2592 insert_dma_buffer(d, idx);
2593 idx = (idx+1) % d->num_desc;
2594 buf_ptr = d->buf_cpu[idx];
2595 offset=0;
2596 }
2597 }
2598
2599
2600
2601 if (tcode != OHCI1394_TCODE_PHY) {
2602 if (!ohci->no_swap_incoming)
2603 header_le32_to_cpu(d->spb, tcode);
2604 DBGMSG("Packet received from node"
2605 " %d ack=0x%02X spd=%d tcode=0x%X"
2606 " length=%d ctx=%d tlabel=%d",
2607 (d->spb[1]>>16)&0x3f,
2608 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f,
2609 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>21)&0x3,
2610 tcode, length, d->ctx,
2611 (d->spb[0]>>10)&0x3f);
2612
2613 ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f)
2614 == 0x11) ? 1 : 0;
2615
2616 hpsb_packet_received(ohci->host, d->spb,
2617 length-4, ack);
2618 }
2619#ifdef OHCI1394_DEBUG
2620 else
2621 PRINT (KERN_DEBUG, "Got phy packet ctx=%d ... discarded",
2622 d->ctx);
2623#endif
2624
2625 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2626
2627 bytes_left = d->buf_size - rescount - offset;
2628
2629 }
2630
2631 d->buf_ind = idx;
2632 d->buf_offset = offset;
2633
2634 spin_unlock_irqrestore(&d->lock, flags);
2635}
2636
2637
2638static void dma_trm_tasklet (unsigned long data)
2639{
2640 struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
2641 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2642 struct hpsb_packet *packet, *ptmp;
2643 unsigned long flags;
2644 u32 status, ack;
2645 size_t datasize;
2646
2647 spin_lock_irqsave(&d->lock, flags);
2648
2649 list_for_each_entry_safe(packet, ptmp, &d->fifo_list, driver_list) {
2650 datasize = packet->data_size;
2651 if (datasize && packet->type != hpsb_raw)
2652 status = le32_to_cpu(
2653 d->prg_cpu[d->sent_ind]->end.status) >> 16;
2654 else
2655 status = le32_to_cpu(
2656 d->prg_cpu[d->sent_ind]->begin.status) >> 16;
2657
2658 if (status == 0)
2659
2660 break;
2661
2662#ifdef OHCI1394_DEBUG
2663 if (datasize)
2664 if (((le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf) == 0xa)
2665 DBGMSG("Stream packet sent to channel %d tcode=0x%X "
2666 "ack=0x%X spd=%d dataLength=%d ctx=%d",
2667 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>8)&0x3f,
2668 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2669 status&0x1f, (status>>5)&0x3,
2670 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16,
2671 d->ctx);
2672 else
2673 DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2674 "%d ack=0x%X spd=%d dataLength=%d ctx=%d",
2675 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16)&0x3f,
2676 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2677 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>10)&0x3f,
2678 status&0x1f, (status>>5)&0x3,
2679 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])>>16,
2680 d->ctx);
2681 else
2682 DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2683 "%d ack=0x%X spd=%d data=0x%08X ctx=%d",
2684 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
2685 >>16)&0x3f,
2686 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2687 >>4)&0xf,
2688 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2689 >>10)&0x3f,
2690 status&0x1f, (status>>5)&0x3,
2691 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]),
2692 d->ctx);
2693#endif
2694
2695 if (status & 0x10) {
2696 ack = status & 0xf;
2697 } else {
2698 switch (status & 0x1f) {
2699 case EVT_NO_STATUS:
2700 case EVT_RESERVED_A:
2701 case EVT_LONG_PACKET:
2702 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2703 ack = ACKX_SEND_ERROR;
2704 break;
2705 case EVT_MISSING_ACK:
2706 ack = ACKX_TIMEOUT;
2707 break;
2708 case EVT_UNDERRUN:
2709 ack = ACKX_SEND_ERROR;
2710 break;
2711 case EVT_OVERRUN:
2712 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2713 ack = ACKX_SEND_ERROR;
2714 break;
2715 case EVT_DESCRIPTOR_READ:
2716 case EVT_DATA_READ:
2717 case EVT_DATA_WRITE:
2718 ack = ACKX_SEND_ERROR;
2719 break;
2720 case EVT_BUS_RESET:
2721 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2722 ack = ACKX_SEND_ERROR;
2723 break;
2724 case EVT_TIMEOUT:
2725 ack = ACKX_TIMEOUT;
2726 break;
2727 case EVT_TCODE_ERR:
2728 ack = ACKX_SEND_ERROR;
2729 break;
2730 case EVT_RESERVED_B:
2731 case EVT_RESERVED_C:
2732 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2733 ack = ACKX_SEND_ERROR;
2734 break;
2735 case EVT_UNKNOWN:
2736 case EVT_FLUSHED:
2737 ack = ACKX_SEND_ERROR;
2738 break;
2739 default:
2740 PRINT(KERN_ERR, "Unhandled OHCI evt_* error 0x%x", status & 0x1f);
2741 ack = ACKX_SEND_ERROR;
2742 BUG();
2743 }
2744 }
2745
2746 list_del_init(&packet->driver_list);
2747 hpsb_packet_sent(ohci->host, packet, ack);
2748
2749 if (datasize)
2750 pci_unmap_single(ohci->dev,
2751 cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address),
2752 datasize, PCI_DMA_TODEVICE);
2753
2754 d->sent_ind = (d->sent_ind+1)%d->num_desc;
2755 d->free_prgs++;
2756 }
2757
2758 dma_trm_flush(ohci, d);
2759
2760 spin_unlock_irqrestore(&d->lock, flags);
2761}
2762
2763static void free_dma_rcv_ctx(struct dma_rcv_ctx *d)
2764{
2765 int i;
2766 struct ti_ohci *ohci = d->ohci;
2767
2768 if (ohci == NULL)
2769 return;
2770
2771 DBGMSG("Freeing dma_rcv_ctx %d", d->ctx);
2772
2773 if (d->buf_cpu) {
2774 for (i=0; i<d->num_desc; i++)
2775 if (d->buf_cpu[i] && d->buf_bus[i])
2776 pci_free_consistent(
2777 ohci->dev, d->buf_size,
2778 d->buf_cpu[i], d->buf_bus[i]);
2779 kfree(d->buf_cpu);
2780 kfree(d->buf_bus);
2781 }
2782 if (d->prg_cpu) {
2783 for (i=0; i<d->num_desc; i++)
2784 if (d->prg_cpu[i] && d->prg_bus[i])
2785 pci_pool_free(d->prg_pool, d->prg_cpu[i],
2786 d->prg_bus[i]);
2787 pci_pool_destroy(d->prg_pool);
2788 kfree(d->prg_cpu);
2789 kfree(d->prg_bus);
2790 }
2791 kfree(d->spb);
2792
2793
2794 d->ohci = NULL;
2795}
2796
2797static int
2798alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
2799 enum context_type type, int ctx, int num_desc,
2800 int buf_size, int split_buf_size, int context_base)
2801{
2802 int i, len;
2803 static int num_allocs;
2804 static char pool_name[20];
2805
2806 d->ohci = ohci;
2807 d->type = type;
2808 d->ctx = ctx;
2809
2810 d->num_desc = num_desc;
2811 d->buf_size = buf_size;
2812 d->split_buf_size = split_buf_size;
2813
2814 d->ctrlSet = 0;
2815 d->ctrlClear = 0;
2816 d->cmdPtr = 0;
2817
2818 d->buf_cpu = kzalloc(d->num_desc * sizeof(*d->buf_cpu), GFP_ATOMIC);
2819 d->buf_bus = kzalloc(d->num_desc * sizeof(*d->buf_bus), GFP_ATOMIC);
2820
2821 if (d->buf_cpu == NULL || d->buf_bus == NULL) {
2822 PRINT(KERN_ERR, "Failed to allocate %s", "DMA buffer");
2823 free_dma_rcv_ctx(d);
2824 return -ENOMEM;
2825 }
2826
2827 d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_ATOMIC);
2828 d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_ATOMIC);
2829
2830 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
2831 PRINT(KERN_ERR, "Failed to allocate %s", "DMA prg");
2832 free_dma_rcv_ctx(d);
2833 return -ENOMEM;
2834 }
2835
2836 d->spb = kmalloc(d->split_buf_size, GFP_ATOMIC);
2837
2838 if (d->spb == NULL) {
2839 PRINT(KERN_ERR, "Failed to allocate %s", "split buffer");
2840 free_dma_rcv_ctx(d);
2841 return -ENOMEM;
2842 }
2843
2844 len = sprintf(pool_name, "ohci1394_rcv_prg");
2845 sprintf(pool_name+len, "%d", num_allocs);
2846 d->prg_pool = pci_pool_create(pool_name, ohci->dev,
2847 sizeof(struct dma_cmd), 4, 0);
2848 if(d->prg_pool == NULL)
2849 {
2850 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
2851 free_dma_rcv_ctx(d);
2852 return -ENOMEM;
2853 }
2854 num_allocs++;
2855
2856 for (i=0; i<d->num_desc; i++) {
2857 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
2858 d->buf_size,
2859 d->buf_bus+i);
2860
2861 if (d->buf_cpu[i] != NULL) {
2862 memset(d->buf_cpu[i], 0, d->buf_size);
2863 } else {
2864 PRINT(KERN_ERR,
2865 "Failed to allocate %s", "DMA buffer");
2866 free_dma_rcv_ctx(d);
2867 return -ENOMEM;
2868 }
2869
2870 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, GFP_KERNEL, d->prg_bus+i);
2871
2872 if (d->prg_cpu[i] != NULL) {
2873 memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
2874 } else {
2875 PRINT(KERN_ERR,
2876 "Failed to allocate %s", "DMA prg");
2877 free_dma_rcv_ctx(d);
2878 return -ENOMEM;
2879 }
2880 }
2881
2882 spin_lock_init(&d->lock);
2883
2884 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
2885 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
2886 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
2887
2888 tasklet_init(&d->task, dma_rcv_tasklet, (unsigned long) d);
2889 return 0;
2890}
2891
2892static void free_dma_trm_ctx(struct dma_trm_ctx *d)
2893{
2894 int i;
2895 struct ti_ohci *ohci = d->ohci;
2896
2897 if (ohci == NULL)
2898 return;
2899
2900 DBGMSG("Freeing dma_trm_ctx %d", d->ctx);
2901
2902 if (d->prg_cpu) {
2903 for (i=0; i<d->num_desc; i++)
2904 if (d->prg_cpu[i] && d->prg_bus[i])
2905 pci_pool_free(d->prg_pool, d->prg_cpu[i],
2906 d->prg_bus[i]);
2907 pci_pool_destroy(d->prg_pool);
2908 kfree(d->prg_cpu);
2909 kfree(d->prg_bus);
2910 }
2911
2912
2913 d->ohci = NULL;
2914}
2915
2916static int
2917alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
2918 enum context_type type, int ctx, int num_desc,
2919 int context_base)
2920{
2921 int i, len;
2922 static char pool_name[20];
2923 static int num_allocs=0;
2924
2925 d->ohci = ohci;
2926 d->type = type;
2927 d->ctx = ctx;
2928 d->num_desc = num_desc;
2929 d->ctrlSet = 0;
2930 d->ctrlClear = 0;
2931 d->cmdPtr = 0;
2932
2933 d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_KERNEL);
2934 d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_KERNEL);
2935
2936 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
2937 PRINT(KERN_ERR, "Failed to allocate %s", "AT DMA prg");
2938 free_dma_trm_ctx(d);
2939 return -ENOMEM;
2940 }
2941
2942 len = sprintf(pool_name, "ohci1394_trm_prg");
2943 sprintf(pool_name+len, "%d", num_allocs);
2944 d->prg_pool = pci_pool_create(pool_name, ohci->dev,
2945 sizeof(struct at_dma_prg), 4, 0);
2946 if (d->prg_pool == NULL) {
2947 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
2948 free_dma_trm_ctx(d);
2949 return -ENOMEM;
2950 }
2951 num_allocs++;
2952
2953 for (i = 0; i < d->num_desc; i++) {
2954 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, GFP_KERNEL, d->prg_bus+i);
2955
2956 if (d->prg_cpu[i] != NULL) {
2957 memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
2958 } else {
2959 PRINT(KERN_ERR,
2960 "Failed to allocate %s", "AT DMA prg");
2961 free_dma_trm_ctx(d);
2962 return -ENOMEM;
2963 }
2964 }
2965
2966 spin_lock_init(&d->lock);
2967
2968
2969 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
2970 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
2971 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
2972 tasklet_init(&d->task, dma_trm_tasklet, (unsigned long)d);
2973 return 0;
2974}
2975
2976static void ohci_set_hw_config_rom(struct hpsb_host *host, __be32 *config_rom)
2977{
2978 struct ti_ohci *ohci = host->hostdata;
2979
2980 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0]));
2981 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2]));
2982
2983 memcpy(ohci->csr_config_rom_cpu, config_rom, OHCI_CONFIG_ROM_LEN);
2984}
2985
2986
2987static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg,
2988 quadlet_t data, quadlet_t compare)
2989{
2990 struct ti_ohci *ohci = host->hostdata;
2991 int i;
2992
2993 reg_write(ohci, OHCI1394_CSRData, data);
2994 reg_write(ohci, OHCI1394_CSRCompareData, compare);
2995 reg_write(ohci, OHCI1394_CSRControl, reg & 0x3);
2996
2997 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
2998 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
2999 break;
3000
3001 mdelay(1);
3002 }
3003
3004 return reg_read(ohci, OHCI1394_CSRData);
3005}
3006
3007static struct hpsb_host_driver ohci1394_driver = {
3008 .owner = THIS_MODULE,
3009 .name = OHCI1394_DRIVER_NAME,
3010 .set_hw_config_rom = ohci_set_hw_config_rom,
3011 .transmit_packet = ohci_transmit,
3012 .devctl = ohci_devctl,
3013 .isoctl = ohci_isoctl,
3014 .hw_csr_reg = ohci_hw_csr_reg,
3015};
3016
3017
3018
3019
3020
3021#ifdef CONFIG_PPC_PMAC
3022static void ohci1394_pmac_on(struct pci_dev *dev)
3023{
3024 if (machine_is(powermac)) {
3025 struct device_node *ofn = pci_device_to_OF_node(dev);
3026
3027 if (ofn) {
3028 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3029 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3030 }
3031 }
3032}
3033
3034static void ohci1394_pmac_off(struct pci_dev *dev)
3035{
3036 if (machine_is(powermac)) {
3037 struct device_node *ofn = pci_device_to_OF_node(dev);
3038
3039 if (ofn) {
3040 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3041 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3042 }
3043 }
3044}
3045#else
3046#define ohci1394_pmac_on(dev)
3047#define ohci1394_pmac_off(dev)
3048#endif
3049
3050static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
3051 const struct pci_device_id *ent)
3052{
3053 struct hpsb_host *host;
3054 struct ti_ohci *ohci;
3055 resource_size_t ohci_base;
3056 int err = -ENOMEM;
3057
3058 ohci1394_pmac_on(dev);
3059 if (pci_enable_device(dev)) {
3060 PRINT_G(KERN_ERR, "Failed to enable OHCI hardware");
3061 err = -ENXIO;
3062 goto err;
3063 }
3064 pci_set_master(dev);
3065
3066 host = hpsb_alloc_host(&ohci1394_driver, sizeof(struct ti_ohci), &dev->dev);
3067 if (!host) {
3068 PRINT_G(KERN_ERR, "Failed to allocate %s", "host structure");
3069 goto err;
3070 }
3071 ohci = host->hostdata;
3072 ohci->dev = dev;
3073 ohci->host = host;
3074 ohci->init_state = OHCI_INIT_ALLOC_HOST;
3075 host->pdev = dev;
3076 pci_set_drvdata(dev, ohci);
3077
3078
3079 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3080
3081
3082
3083#ifndef __LITTLE_ENDIAN
3084
3085
3086
3087
3088
3089 if (dev->vendor == PCI_VENDOR_ID_APPLE &&
3090 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) {
3091 ohci->no_swap_incoming = 1;
3092 ohci->selfid_swap = 0;
3093 } else
3094 ohci->selfid_swap = 1;
3095#endif
3096
3097
3098#ifndef PCI_DEVICE_ID_NVIDIA_NFORCE2_FW
3099#define PCI_DEVICE_ID_NVIDIA_NFORCE2_FW 0x006e
3100#endif
3101
3102
3103
3104 if ((dev->vendor == PCI_VENDOR_ID_APPLE &&
3105 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) ||
3106 (dev->vendor == PCI_VENDOR_ID_NVIDIA &&
3107 dev->device == PCI_DEVICE_ID_NVIDIA_NFORCE2_FW))
3108 ohci->check_busreset = 1;
3109
3110
3111
3112
3113 ohci_base = pci_resource_start(dev, 0);
3114 if (pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE)
3115 PRINT(KERN_WARNING, "PCI resource length of 0x%llx too small!",
3116 (unsigned long long)pci_resource_len(dev, 0));
3117
3118 if (!request_mem_region(ohci_base, OHCI1394_REGISTER_SIZE,
3119 OHCI1394_DRIVER_NAME)) {
3120 PRINT_G(KERN_ERR, "MMIO resource (0x%llx - 0x%llx) unavailable",
3121 (unsigned long long)ohci_base,
3122 (unsigned long long)ohci_base + OHCI1394_REGISTER_SIZE);
3123 goto err;
3124 }
3125 ohci->init_state = OHCI_INIT_HAVE_MEM_REGION;
3126
3127 ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE);
3128 if (ohci->registers == NULL) {
3129 PRINT_G(KERN_ERR, "Failed to remap registers");
3130 err = -ENXIO;
3131 goto err;
3132 }
3133 ohci->init_state = OHCI_INIT_HAVE_IOMAPPING;
3134 DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers);
3135
3136
3137 ohci->csr_config_rom_cpu =
3138 pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3139 &ohci->csr_config_rom_bus);
3140 if (ohci->csr_config_rom_cpu == NULL) {
3141 PRINT_G(KERN_ERR, "Failed to allocate %s", "buffer config rom");
3142 goto err;
3143 }
3144 ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER;
3145
3146
3147 ohci->selfid_buf_cpu =
3148 pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3149 &ohci->selfid_buf_bus);
3150 if (ohci->selfid_buf_cpu == NULL) {
3151 PRINT_G(KERN_ERR, "Failed to allocate %s", "self-ID buffer");
3152 goto err;
3153 }
3154 ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER;
3155
3156 if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
3157 PRINT(KERN_INFO, "SelfID buffer %p is not aligned on "
3158 "8Kb boundary... may cause problems on some CXD3222 chip",
3159 ohci->selfid_buf_cpu);
3160
3161
3162 ohci->self_id_errors = 0;
3163
3164 ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE;
3165
3166 if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context,
3167 DMA_CTX_ASYNC_REQ, 0, AR_REQ_NUM_DESC,
3168 AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
3169 OHCI1394_AsReqRcvContextBase) < 0) {
3170 PRINT_G(KERN_ERR, "Failed to allocate %s", "AR Req context");
3171 goto err;
3172 }
3173
3174 if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context,
3175 DMA_CTX_ASYNC_RESP, 0, AR_RESP_NUM_DESC,
3176 AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
3177 OHCI1394_AsRspRcvContextBase) < 0) {
3178 PRINT_G(KERN_ERR, "Failed to allocate %s", "AR Resp context");
3179 goto err;
3180 }
3181
3182 if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context,
3183 DMA_CTX_ASYNC_REQ, 0, AT_REQ_NUM_DESC,
3184 OHCI1394_AsReqTrContextBase) < 0) {
3185 PRINT_G(KERN_ERR, "Failed to allocate %s", "AT Req context");
3186 goto err;
3187 }
3188
3189 if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context,
3190 DMA_CTX_ASYNC_RESP, 1, AT_RESP_NUM_DESC,
3191 OHCI1394_AsRspTrContextBase) < 0) {
3192 PRINT_G(KERN_ERR, "Failed to allocate %s", "AT Resp context");
3193 goto err;
3194 }
3195
3196
3197 ohci_soft_reset(ohci);
3198
3199
3200
3201
3202
3203 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3204
3205
3206 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3207 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3208
3209
3210 reg_read(ohci, OHCI1394_Version);
3211 msleep(50);
3212
3213
3214 ohci->nb_iso_rcv_ctx =
3215 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
3216 ohci->nb_iso_xmit_ctx =
3217 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
3218
3219
3220
3221 ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx;
3222 ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx;
3223
3224 INIT_LIST_HEAD(&ohci->iso_tasklet_list);
3225 spin_lock_init(&ohci->iso_tasklet_list_lock);
3226 ohci->ISO_channel_usage = 0;
3227 spin_lock_init(&ohci->IR_channel_lock);
3228
3229 spin_lock_init(&ohci->event_lock);
3230
3231
3232
3233
3234
3235
3236
3237 err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
3238 OHCI1394_DRIVER_NAME, ohci);
3239 if (err) {
3240 PRINT_G(KERN_ERR, "Failed to allocate interrupt %d", dev->irq);
3241 goto err;
3242 }
3243 ohci->init_state = OHCI_INIT_HAVE_IRQ;
3244 ohci_initialize(ohci);
3245
3246
3247 host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi);
3248 host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo);
3249 host->csr.cyc_clk_acc = 100;
3250 host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf;
3251 host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7;
3252
3253 if (phys_dma) {
3254 host->low_addr_space =
3255 (u64) reg_read(ohci, OHCI1394_PhyUpperBound) << 16;
3256 if (!host->low_addr_space)
3257 host->low_addr_space = OHCI1394_PHYS_UPPER_BOUND_FIXED;
3258 }
3259 host->middle_addr_space = OHCI1394_MIDDLE_ADDRESS_SPACE;
3260
3261
3262 if (hpsb_add_host(host)) {
3263 PRINT_G(KERN_ERR, "Failed to register host with highlevel");
3264 goto err;
3265 }
3266 ohci->init_state = OHCI_INIT_DONE;
3267
3268 return 0;
3269err:
3270 ohci1394_pci_remove(dev);
3271 return err;
3272}
3273
3274static void ohci1394_pci_remove(struct pci_dev *dev)
3275{
3276 struct ti_ohci *ohci;
3277 struct device *device;
3278
3279 ohci = pci_get_drvdata(dev);
3280 if (!ohci)
3281 goto out;
3282
3283 device = get_device(&ohci->host->device);
3284
3285 switch (ohci->init_state) {
3286 case OHCI_INIT_DONE:
3287 hpsb_remove_host(ohci->host);
3288
3289
3290 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3291 reg_write(ohci, OHCI1394_BusOptions,
3292 (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3293 0x00ff0000);
3294 memset(ohci->csr_config_rom_cpu, 0, OHCI_CONFIG_ROM_LEN);
3295
3296 case OHCI_INIT_HAVE_IRQ:
3297
3298 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3299 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3300 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3301 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3302 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3303 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3304
3305
3306 set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3307
3308
3309 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3310
3311
3312 ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3313
3314
3315
3316 ohci_soft_reset(ohci);
3317 free_irq(dev->irq, ohci);
3318
3319 case OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE:
3320
3321
3322 free_dma_rcv_ctx(&ohci->ar_req_context);
3323 free_dma_rcv_ctx(&ohci->ar_resp_context);
3324 free_dma_trm_ctx(&ohci->at_req_context);
3325 free_dma_trm_ctx(&ohci->at_resp_context);
3326
3327 case OHCI_INIT_HAVE_SELFID_BUFFER:
3328 pci_free_consistent(dev, OHCI1394_SI_DMA_BUF_SIZE,
3329 ohci->selfid_buf_cpu,
3330 ohci->selfid_buf_bus);
3331
3332 case OHCI_INIT_HAVE_CONFIG_ROM_BUFFER:
3333 pci_free_consistent(dev, OHCI_CONFIG_ROM_LEN,
3334 ohci->csr_config_rom_cpu,
3335 ohci->csr_config_rom_bus);
3336
3337 case OHCI_INIT_HAVE_IOMAPPING:
3338 iounmap(ohci->registers);
3339
3340 case OHCI_INIT_HAVE_MEM_REGION:
3341 release_mem_region(pci_resource_start(dev, 0),
3342 OHCI1394_REGISTER_SIZE);
3343
3344 case OHCI_INIT_ALLOC_HOST:
3345 pci_set_drvdata(dev, NULL);
3346 }
3347
3348 if (device)
3349 put_device(device);
3350out:
3351 ohci1394_pmac_off(dev);
3352}
3353
3354#ifdef CONFIG_PM
3355static int ohci1394_pci_suspend(struct pci_dev *dev, pm_message_t state)
3356{
3357 int err;
3358 struct ti_ohci *ohci = pci_get_drvdata(dev);
3359
3360 if (!ohci) {
3361 printk(KERN_ERR "%s: tried to suspend nonexisting host\n",
3362 OHCI1394_DRIVER_NAME);
3363 return -ENXIO;
3364 }
3365 DBGMSG("suspend called");
3366
3367
3368 hpsb_bus_reset(ohci->host);
3369
3370
3371 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3372 reg_write(ohci, OHCI1394_BusOptions,
3373 (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3374 0x00ff0000);
3375 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3376 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3377 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3378 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3379 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3380 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3381 set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3382 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3383 ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3384 ohci_soft_reset(ohci);
3385
3386 free_irq(dev->irq, ohci);
3387 err = pci_save_state(dev);
3388 if (err) {
3389 PRINT(KERN_ERR, "pci_save_state failed with %d", err);
3390 return err;
3391 }
3392 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3393 if (err)
3394 DBGMSG("pci_set_power_state failed with %d", err);
3395 ohci1394_pmac_off(dev);
3396
3397 return 0;
3398}
3399
3400static int ohci1394_pci_resume(struct pci_dev *dev)
3401{
3402 int err;
3403 struct ti_ohci *ohci = pci_get_drvdata(dev);
3404
3405 if (!ohci) {
3406 printk(KERN_ERR "%s: tried to resume nonexisting host\n",
3407 OHCI1394_DRIVER_NAME);
3408 return -ENXIO;
3409 }
3410 DBGMSG("resume called");
3411
3412 ohci1394_pmac_on(dev);
3413 pci_set_power_state(dev, PCI_D0);
3414 pci_restore_state(dev);
3415 err = pci_enable_device(dev);
3416 if (err) {
3417 PRINT(KERN_ERR, "pci_enable_device failed with %d", err);
3418 return err;
3419 }
3420
3421
3422 ohci_soft_reset(ohci);
3423 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3424 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3425 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3426 reg_read(ohci, OHCI1394_Version);
3427 msleep(50);
3428
3429 err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
3430 OHCI1394_DRIVER_NAME, ohci);
3431 if (err) {
3432 PRINT_G(KERN_ERR, "Failed to allocate interrupt %d", dev->irq);
3433 return err;
3434 }
3435
3436 ohci_initialize(ohci);
3437
3438 hpsb_resume_host(ohci->host);
3439 return 0;
3440}
3441#endif
3442
3443static struct pci_device_id ohci1394_pci_tbl[] = {
3444 {
3445 .class = PCI_CLASS_SERIAL_FIREWIRE_OHCI,
3446 .class_mask = PCI_ANY_ID,
3447 .vendor = PCI_ANY_ID,
3448 .device = PCI_ANY_ID,
3449 .subvendor = PCI_ANY_ID,
3450 .subdevice = PCI_ANY_ID,
3451 },
3452 { 0, },
3453};
3454
3455MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl);
3456
3457static struct pci_driver ohci1394_pci_driver = {
3458 .name = OHCI1394_DRIVER_NAME,
3459 .id_table = ohci1394_pci_tbl,
3460 .probe = ohci1394_pci_probe,
3461 .remove = ohci1394_pci_remove,
3462#ifdef CONFIG_PM
3463 .resume = ohci1394_pci_resume,
3464 .suspend = ohci1394_pci_suspend,
3465#endif
3466};
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
3477{
3478 int i=0;
3479
3480
3481 reg_write(ohci, reg, 0x8000);
3482
3483
3484 while (reg_read(ohci, reg) & 0x400) {
3485 i++;
3486 if (i>5000) {
3487 PRINT(KERN_ERR,
3488 "Runaway loop while stopping context: %s...", msg ? msg : "");
3489 return 1;
3490 }
3491
3492 mb();
3493 udelay(10);
3494 }
3495 if (msg) PRINT(KERN_ERR, "%s: dma prg stopped", msg);
3496 return 0;
3497}
3498
3499void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, int type,
3500 void (*func)(unsigned long), unsigned long data)
3501{
3502 tasklet_init(&tasklet->tasklet, func, data);
3503 tasklet->type = type;
3504
3505
3506 INIT_LIST_HEAD(&tasklet->link);
3507}
3508
3509int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
3510 struct ohci1394_iso_tasklet *tasklet)
3511{
3512 unsigned long flags, *usage;
3513 int n, i, r = -EBUSY;
3514
3515 if (tasklet->type == OHCI_ISO_TRANSMIT) {
3516 n = ohci->nb_iso_xmit_ctx;
3517 usage = &ohci->it_ctx_usage;
3518 }
3519 else {
3520 n = ohci->nb_iso_rcv_ctx;
3521 usage = &ohci->ir_ctx_usage;
3522
3523
3524 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3525 if (test_and_set_bit(0, &ohci->ir_multichannel_used)) {
3526 return r;
3527 }
3528 }
3529 }
3530
3531 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3532
3533 for (i = 0; i < n; i++)
3534 if (!test_and_set_bit(i, usage)) {
3535 tasklet->context = i;
3536 list_add_tail(&tasklet->link, &ohci->iso_tasklet_list);
3537 r = 0;
3538 break;
3539 }
3540
3541 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3542
3543 return r;
3544}
3545
3546void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
3547 struct ohci1394_iso_tasklet *tasklet)
3548{
3549 unsigned long flags;
3550
3551 tasklet_kill(&tasklet->tasklet);
3552
3553 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3554
3555 if (tasklet->type == OHCI_ISO_TRANSMIT)
3556 clear_bit(tasklet->context, &ohci->it_ctx_usage);
3557 else {
3558 clear_bit(tasklet->context, &ohci->ir_ctx_usage);
3559
3560 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3561 clear_bit(0, &ohci->ir_multichannel_used);
3562 }
3563 }
3564
3565 list_del(&tasklet->link);
3566
3567 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3568}
3569
3570EXPORT_SYMBOL(ohci1394_stop_context);
3571EXPORT_SYMBOL(ohci1394_init_iso_tasklet);
3572EXPORT_SYMBOL(ohci1394_register_iso_tasklet);
3573EXPORT_SYMBOL(ohci1394_unregister_iso_tasklet);
3574
3575
3576
3577
3578
3579MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
3580MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers");
3581MODULE_LICENSE("GPL");
3582
3583static void __exit ohci1394_cleanup (void)
3584{
3585 pci_unregister_driver(&ohci1394_pci_driver);
3586}
3587
3588static int __init ohci1394_init(void)
3589{
3590 return pci_register_driver(&ohci1394_pci_driver);
3591}
3592
3593module_init(ohci1394_init);
3594module_exit(ohci1394_cleanup);
3595