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38#include <linux/pci.h>
39#include <linux/delay.h>
40
41#include "ipath_kernel.h"
42#include "ipath_registers.h"
43#include "ipath_7220.h"
44
45
46
47
48
49
50#define KR_IBSerDesMappTable (0x94000 / (sizeof(uint64_t)))
51
52
53
54
55
56#define PCIE_SERDES0 0
57#define PCIE_SERDES1 1
58
59
60
61
62
63#define EPB_ADDR_SHF 8
64#define EPB_LOC(chn, elt, reg) \
65 (((elt & 0xf) | ((chn & 7) << 4) | ((reg & 0x3f) << 9)) << \
66 EPB_ADDR_SHF)
67#define EPB_IB_QUAD0_CS_SHF (25)
68#define EPB_IB_QUAD0_CS (1U << EPB_IB_QUAD0_CS_SHF)
69#define EPB_IB_UC_CS_SHF (26)
70#define EPB_PCIE_UC_CS_SHF (27)
71#define EPB_GLOBAL_WR (1U << (EPB_ADDR_SHF + 8))
72
73
74static int ipath_sd7220_reg_mod(struct ipath_devdata *dd, int sdnum, u32 loc,
75 u32 data, u32 mask);
76static int ibsd_mod_allchnls(struct ipath_devdata *dd, int loc, int val,
77 int mask);
78static int ipath_sd_trimdone_poll(struct ipath_devdata *dd);
79static void ipath_sd_trimdone_monitor(struct ipath_devdata *dd,
80 const char *where);
81static int ipath_sd_setvals(struct ipath_devdata *dd);
82static int ipath_sd_early(struct ipath_devdata *dd);
83static int ipath_sd_dactrim(struct ipath_devdata *dd);
84
85int ipath_sd7220_presets(struct ipath_devdata *dd);
86static int ipath_internal_presets(struct ipath_devdata *dd);
87
88static int ipath_sd_trimself(struct ipath_devdata *dd, int val);
89static int epb_access(struct ipath_devdata *dd, int sdnum, int claim);
90
91void ipath_set_relock_poll(struct ipath_devdata *dd, int ibup);
92
93
94
95
96
97
98
99
100
101static int ipath_ibsd_ucode_loaded(struct ipath_devdata *dd)
102{
103 if (!dd->serdes_first_init_done && (ipath_sd7220_ib_vfy(dd) > 0))
104 dd->serdes_first_init_done = 1;
105 return dd->serdes_first_init_done;
106}
107
108
109#define INFINIPATH_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
110#define IB_MPREG5 (EPB_LOC(6, 0, 0xE) | (1L << EPB_IB_UC_CS_SHF))
111#define IB_MPREG6 (EPB_LOC(6, 0, 0xF) | (1U << EPB_IB_UC_CS_SHF))
112#define UC_PAR_CLR_D 8
113#define UC_PAR_CLR_M 0xC
114#define IB_CTRL2(chn) (EPB_LOC(chn, 7, 3) | EPB_IB_QUAD0_CS)
115#define START_EQ1(chan) EPB_LOC(chan, 7, 0x27)
116
117void ipath_sd7220_clr_ibpar(struct ipath_devdata *dd)
118{
119 int ret;
120
121
122 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6,
123 UC_PAR_CLR_D, UC_PAR_CLR_M);
124 if (ret < 0) {
125 ipath_dev_err(dd, "Failed clearing IBSerDes Parity err\n");
126 goto bail;
127 }
128 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0,
129 UC_PAR_CLR_M);
130
131 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
132 udelay(4);
133 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
134 INFINIPATH_HWE_IB_UC_MEMORYPARITYERR);
135 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
136bail:
137 return;
138}
139
140
141
142
143
144
145#define IBSD_RESYNC_TRIES 3
146#define IB_PGUDP(chn) (EPB_LOC((chn), 2, 1) | EPB_IB_QUAD0_CS)
147#define IB_CMUDONE(chn) (EPB_LOC((chn), 7, 0xF) | EPB_IB_QUAD0_CS)
148
149static int ipath_resync_ibepb(struct ipath_devdata *dd)
150{
151 int ret, pat, tries, chn;
152 u32 loc;
153
154 ret = -1;
155 chn = 0;
156 for (tries = 0; tries < (4 * IBSD_RESYNC_TRIES); ++tries) {
157 loc = IB_PGUDP(chn);
158 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
159 if (ret < 0) {
160 ipath_dev_err(dd, "Failed read in resync\n");
161 continue;
162 }
163 if (ret != 0xF0 && ret != 0x55 && tries == 0)
164 ipath_dev_err(dd, "unexpected pattern in resync\n");
165 pat = ret ^ 0xA5;
166 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, pat, 0xFF);
167 if (ret < 0) {
168 ipath_dev_err(dd, "Failed write in resync\n");
169 continue;
170 }
171 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
172 if (ret < 0) {
173 ipath_dev_err(dd, "Failed re-read in resync\n");
174 continue;
175 }
176 if (ret != pat) {
177 ipath_dev_err(dd, "Failed compare1 in resync\n");
178 continue;
179 }
180 loc = IB_CMUDONE(chn);
181 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
182 if (ret < 0) {
183 ipath_dev_err(dd, "Failed CMUDONE rd in resync\n");
184 continue;
185 }
186 if ((ret & 0x70) != ((chn << 4) | 0x40)) {
187 ipath_dev_err(dd, "Bad CMUDONE value %02X, chn %d\n",
188 ret, chn);
189 continue;
190 }
191 if (++chn == 4)
192 break;
193 }
194 ipath_cdbg(VERBOSE, "Resync in %d tries\n", tries);
195 return (ret > 0) ? 0 : ret;
196}
197
198
199
200
201
202static int ipath_ibsd_reset(struct ipath_devdata *dd, int assert_rst)
203{
204 u64 rst_val;
205 int ret = 0;
206 unsigned long flags;
207
208 rst_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibserdesctrl);
209 if (assert_rst) {
210
211
212
213
214 spin_lock_irqsave(&dd->ipath_sdepb_lock, flags);
215 epb_access(dd, IB_7220_SERDES, 1);
216 rst_val |= 1ULL;
217
218 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
219 dd->ipath_hwerrmask &
220 ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR);
221 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibserdesctrl, rst_val);
222
223 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
224 udelay(2);
225
226 epb_access(dd, IB_7220_SERDES, -1);
227 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
228 } else {
229
230
231
232
233
234
235
236 u64 val;
237 rst_val &= ~(1ULL);
238 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
239 dd->ipath_hwerrmask &
240 ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR);
241
242 ret = ipath_resync_ibepb(dd);
243 if (ret < 0)
244 ipath_dev_err(dd, "unable to re-sync IB EPB\n");
245
246
247 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG5, 1, 1);
248 if (ret < 0)
249 goto bail;
250
251 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80,
252 0x80);
253 if (ret < 0) {
254 ipath_dev_err(dd, "Failed to set WDOG disable\n");
255 goto bail;
256 }
257 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibserdesctrl, rst_val);
258
259 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
260 udelay(1);
261
262 ipath_sd7220_clr_ibpar(dd);
263 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
264 if (val & INFINIPATH_HWE_IB_UC_MEMORYPARITYERR) {
265 ipath_dev_err(dd, "IBUC Parity still set after RST\n");
266 dd->ipath_hwerrmask &=
267 ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR;
268 }
269 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
270 dd->ipath_hwerrmask);
271 }
272
273bail:
274 return ret;
275}
276
277static void ipath_sd_trimdone_monitor(struct ipath_devdata *dd,
278 const char *where)
279{
280 int ret, chn, baduns;
281 u64 val;
282
283 if (!where)
284 where = "?";
285
286
287 udelay(2);
288
289 ret = ipath_resync_ibepb(dd);
290 if (ret < 0)
291 ipath_dev_err(dd, "not able to re-sync IB EPB (%s)\n", where);
292
293
294 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_CTRL2(0), 0, 0);
295 if (ret < 0)
296 ipath_dev_err(dd, "Failed TRIMDONE 1st read, (%s)\n", where);
297
298
299 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
300 if (val & (1ULL << 11))
301 ipath_cdbg(VERBOSE, "IBCS TRIMDONE set (%s)\n", where);
302 else
303 ipath_dev_err(dd, "IBCS TRIMDONE clear (%s)\n", where);
304
305 udelay(2);
306
307 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, 0x80);
308 if (ret < 0)
309 ipath_dev_err(dd, "Failed Dummy RMW, (%s)\n", where);
310 udelay(10);
311
312 baduns = 0;
313
314 for (chn = 3; chn >= 0; --chn) {
315
316 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
317 IB_CTRL2(chn), 0, 0);
318 if (ret < 0)
319 ipath_dev_err(dd, "Failed checking TRIMDONE, chn %d"
320 " (%s)\n", chn, where);
321
322 if (!(ret & 0x10)) {
323 int probe;
324 baduns |= (1 << chn);
325 ipath_dev_err(dd, "TRIMDONE cleared on chn %d (%02X)."
326 " (%s)\n", chn, ret, where);
327 probe = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
328 IB_PGUDP(0), 0, 0);
329 ipath_dev_err(dd, "probe is %d (%02X)\n",
330 probe, probe);
331 probe = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
332 IB_CTRL2(chn), 0, 0);
333 ipath_dev_err(dd, "re-read: %d (%02X)\n",
334 probe, probe);
335 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
336 IB_CTRL2(chn), 0x10, 0x10);
337 if (ret < 0)
338 ipath_dev_err(dd,
339 "Err on TRIMDONE rewrite1\n");
340 }
341 }
342 for (chn = 3; chn >= 0; --chn) {
343
344 if (baduns & (1 << chn)) {
345 ipath_dev_err(dd,
346 "Reseting TRIMDONE on chn %d (%s)\n",
347 chn, where);
348 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
349 IB_CTRL2(chn), 0x10, 0x10);
350 if (ret < 0)
351 ipath_dev_err(dd, "Failed re-setting "
352 "TRIMDONE, chn %d (%s)\n",
353 chn, where);
354 }
355 }
356}
357
358
359
360
361
362
363
364int ipath_sd7220_init(struct ipath_devdata *dd, int was_reset)
365{
366 int ret = 1;
367 int first_reset;
368 int val_stat;
369
370 if (!was_reset) {
371
372 ipath_ibsd_reset(dd, 1);
373 ipath_sd_trimdone_monitor(dd, "Driver-reload");
374 }
375
376
377 ret = ipath_ibsd_ucode_loaded(dd);
378 if (ret < 0) {
379 ret = 1;
380 goto done;
381 }
382 first_reset = !ret;
383
384
385
386
387
388 ret = ipath_sd_early(dd);
389 if (ret < 0) {
390 ipath_dev_err(dd, "Failed to set IB SERDES early defaults\n");
391 ret = 1;
392 goto done;
393 }
394
395
396
397
398
399
400 if (first_reset) {
401 ret = ipath_sd_dactrim(dd);
402 if (ret < 0) {
403 ipath_dev_err(dd, "Failed IB SERDES DAC trim\n");
404 ret = 1;
405 goto done;
406 }
407 }
408
409
410
411
412
413
414
415 ret = ipath_internal_presets(dd);
416 if (ret < 0) {
417 ipath_dev_err(dd, "Failed to set IB SERDES presets\n");
418 ret = 1;
419 goto done;
420 }
421 ret = ipath_sd_trimself(dd, 0x80);
422 if (ret < 0) {
423 ipath_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n");
424 ret = 1;
425 goto done;
426 }
427
428
429 ret = 0;
430 if (first_reset) {
431 int vfy;
432 int trim_done;
433 ipath_dbg("SerDes uC was reset, reloading PRAM\n");
434 ret = ipath_sd7220_ib_load(dd);
435 if (ret < 0) {
436 ipath_dev_err(dd, "Failed to load IB SERDES image\n");
437 ret = 1;
438 goto done;
439 }
440
441
442 vfy = ipath_sd7220_ib_vfy(dd);
443 if (vfy != ret) {
444 ipath_dev_err(dd, "SERDES PRAM VFY failed\n");
445 ret = 1;
446 goto done;
447 }
448
449
450
451
452 ret = 0;
453
454
455
456
457
458
459
460
461
462 ret = ibsd_mod_allchnls(dd, START_EQ1(0), 0, 0x38);
463 if (ret < 0) {
464 ipath_dev_err(dd, "Failed clearing START_EQ1\n");
465 ret = 1;
466 goto done;
467 }
468
469 ipath_ibsd_reset(dd, 0);
470
471
472
473
474 trim_done = ipath_sd_trimdone_poll(dd);
475
476
477
478
479
480 ipath_ibsd_reset(dd, 1);
481
482 if (!trim_done) {
483 ipath_dev_err(dd, "No TRIMDONE seen\n");
484 ret = 1;
485 goto done;
486 }
487
488 ipath_sd_trimdone_monitor(dd, "First-reset");
489
490 dd->serdes_first_init_done = 1;
491 }
492
493
494
495
496
497 val_stat = ipath_sd_setvals(dd);
498 if (val_stat < 0)
499 ret = 1;
500done:
501
502 ipath_set_relock_poll(dd, -1);
503 return ret;
504}
505
506#define EPB_ACC_REQ 1
507#define EPB_ACC_GNT 0x100
508#define EPB_DATA_MASK 0xFF
509#define EPB_RD (1ULL << 24)
510#define EPB_TRANS_RDY (1ULL << 31)
511#define EPB_TRANS_ERR (1ULL << 30)
512#define EPB_TRANS_TRIES 5
513
514
515
516
517
518
519
520static int epb_access(struct ipath_devdata *dd, int sdnum, int claim)
521{
522 u16 acc;
523 u64 accval;
524 int owned = 0;
525 u64 oct_sel = 0;
526
527 switch (sdnum) {
528 case IB_7220_SERDES :
529
530
531
532
533 acc = dd->ipath_kregs->kr_ib_epbacc;
534 break;
535 case PCIE_SERDES0 :
536 case PCIE_SERDES1 :
537
538 acc = dd->ipath_kregs->kr_pcie_epbacc;
539 oct_sel = (2 << (sdnum - PCIE_SERDES0));
540 break;
541 default :
542 return 0;
543 }
544
545
546 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
547 udelay(15);
548
549 accval = ipath_read_kreg32(dd, acc);
550
551 owned = !!(accval & EPB_ACC_GNT);
552 if (claim < 0) {
553
554 u64 pollval;
555
556
557
558
559 u64 newval = 0;
560 ipath_write_kreg(dd, acc, newval);
561
562 pollval = ipath_read_kreg32(dd, acc);
563 udelay(5);
564 pollval = ipath_read_kreg32(dd, acc);
565 if (pollval & EPB_ACC_GNT)
566 owned = -1;
567 } else if (claim > 0) {
568
569 u64 pollval;
570 u64 newval = EPB_ACC_REQ | oct_sel;
571 ipath_write_kreg(dd, acc, newval);
572
573 pollval = ipath_read_kreg32(dd, acc);
574 udelay(5);
575 pollval = ipath_read_kreg32(dd, acc);
576 if (!(pollval & EPB_ACC_GNT))
577 owned = -1;
578 }
579 return owned;
580}
581
582
583
584
585static int epb_trans(struct ipath_devdata *dd, u16 reg, u64 i_val, u64 *o_vp)
586{
587 int tries;
588 u64 transval;
589
590
591 ipath_write_kreg(dd, reg, i_val);
592
593 transval = ipath_read_kreg64(dd, reg);
594
595 for (tries = EPB_TRANS_TRIES; tries; --tries) {
596 transval = ipath_read_kreg32(dd, reg);
597 if (transval & EPB_TRANS_RDY)
598 break;
599 udelay(5);
600 }
601 if (transval & EPB_TRANS_ERR)
602 return -1;
603 if (tries > 0 && o_vp)
604 *o_vp = transval;
605 return tries;
606}
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622static int ipath_sd7220_reg_mod(struct ipath_devdata *dd, int sdnum, u32 loc,
623 u32 wd, u32 mask)
624{
625 u16 trans;
626 u64 transval;
627 int owned;
628 int tries, ret;
629 unsigned long flags;
630
631 switch (sdnum) {
632 case IB_7220_SERDES :
633 trans = dd->ipath_kregs->kr_ib_epbtrans;
634 break;
635 case PCIE_SERDES0 :
636 case PCIE_SERDES1 :
637 trans = dd->ipath_kregs->kr_pcie_epbtrans;
638 break;
639 default :
640 return -1;
641 }
642
643
644
645
646
647 spin_lock_irqsave(&dd->ipath_sdepb_lock, flags);
648
649 owned = epb_access(dd, sdnum, 1);
650 if (owned < 0) {
651 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
652 return -1;
653 }
654 ret = 0;
655 for (tries = EPB_TRANS_TRIES; tries; --tries) {
656 transval = ipath_read_kreg32(dd, trans);
657 if (transval & EPB_TRANS_RDY)
658 break;
659 udelay(5);
660 }
661
662 if (tries > 0) {
663 tries = 1;
664 if (mask != 0xFF) {
665
666
667
668
669 transval = loc | EPB_RD;
670 tries = epb_trans(dd, trans, transval, &transval);
671 }
672 if (tries > 0 && mask != 0) {
673
674
675
676 wd = (wd & mask) | (transval & ~mask);
677 transval = loc | (wd & EPB_DATA_MASK);
678 tries = epb_trans(dd, trans, transval, &transval);
679 }
680 }
681
682
683
684
685
686 if (epb_access(dd, sdnum, -1) < 0)
687 ret = -1;
688 else
689 ret = transval & EPB_DATA_MASK;
690
691 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
692 if (tries <= 0)
693 ret = -1;
694 return ret;
695}
696
697#define EPB_ROM_R (2)
698#define EPB_ROM_W (1)
699
700
701
702
703#define EPB_UC_CTL EPB_LOC(6, 0, 0)
704#define EPB_MADDRL EPB_LOC(6, 0, 2)
705#define EPB_MADDRH EPB_LOC(6, 0, 3)
706#define EPB_ROMDATA EPB_LOC(6, 0, 4)
707#define EPB_RAMDATA EPB_LOC(6, 0, 5)
708
709
710static int ipath_sd7220_ram_xfer(struct ipath_devdata *dd, int sdnum, u32 loc,
711 u8 *buf, int cnt, int rd_notwr)
712{
713 u16 trans;
714 u64 transval;
715 u64 csbit;
716 int owned;
717 int tries;
718 int sofar;
719 int addr;
720 int ret;
721 unsigned long flags;
722 const char *op;
723
724
725 switch (sdnum) {
726 case IB_7220_SERDES :
727 csbit = 1ULL << EPB_IB_UC_CS_SHF;
728 trans = dd->ipath_kregs->kr_ib_epbtrans;
729 break;
730 case PCIE_SERDES0 :
731 case PCIE_SERDES1 :
732
733 csbit = 1ULL << EPB_PCIE_UC_CS_SHF;
734 trans = dd->ipath_kregs->kr_pcie_epbtrans;
735 break;
736 default :
737 return -1;
738 }
739
740 op = rd_notwr ? "Rd" : "Wr";
741 spin_lock_irqsave(&dd->ipath_sdepb_lock, flags);
742
743 owned = epb_access(dd, sdnum, 1);
744 if (owned < 0) {
745 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
746 ipath_dbg("Could not get %s access to %s EPB: %X, loc %X\n",
747 op, (sdnum == IB_7220_SERDES) ? "IB" : "PCIe",
748 owned, loc);
749 return -1;
750 }
751
752
753
754
755
756
757
758
759 addr = loc & 0x1FFF;
760 for (tries = EPB_TRANS_TRIES; tries; --tries) {
761 transval = ipath_read_kreg32(dd, trans);
762 if (transval & EPB_TRANS_RDY)
763 break;
764 udelay(5);
765 }
766
767 sofar = 0;
768 if (tries <= 0)
769 ipath_dbg("No initial RDY on EPB access request\n");
770 else {
771
772
773
774
775
776
777
778 transval = csbit | EPB_UC_CTL |
779 (rd_notwr ? EPB_ROM_R : EPB_ROM_W);
780 tries = epb_trans(dd, trans, transval, &transval);
781 if (tries <= 0)
782 ipath_dbg("No EPB response to uC %s cmd\n", op);
783 while (tries > 0 && sofar < cnt) {
784 if (!sofar) {
785
786 int addrbyte = (addr + sofar) >> 8;
787 transval = csbit | EPB_MADDRH | addrbyte;
788 tries = epb_trans(dd, trans, transval,
789 &transval);
790 if (tries <= 0) {
791 ipath_dbg("No EPB response ADDRH\n");
792 break;
793 }
794 addrbyte = (addr + sofar) & 0xFF;
795 transval = csbit | EPB_MADDRL | addrbyte;
796 tries = epb_trans(dd, trans, transval,
797 &transval);
798 if (tries <= 0) {
799 ipath_dbg("No EPB response ADDRL\n");
800 break;
801 }
802 }
803
804 if (rd_notwr)
805 transval = csbit | EPB_ROMDATA | EPB_RD;
806 else
807 transval = csbit | EPB_ROMDATA | buf[sofar];
808 tries = epb_trans(dd, trans, transval, &transval);
809 if (tries <= 0) {
810 ipath_dbg("No EPB response DATA\n");
811 break;
812 }
813 if (rd_notwr)
814 buf[sofar] = transval & EPB_DATA_MASK;
815 ++sofar;
816 }
817
818 transval = csbit | EPB_UC_CTL;
819 tries = epb_trans(dd, trans, transval, &transval);
820 if (tries <= 0)
821 ipath_dbg("No EPB response to drop of uC %s cmd\n", op);
822 }
823
824 ret = sofar;
825
826 if (epb_access(dd, sdnum, -1) < 0)
827 ret = -1;
828
829 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
830 if (tries <= 0) {
831 ipath_dbg("SERDES PRAM %s failed after %d bytes\n", op, sofar);
832 ret = -1;
833 }
834 return ret;
835}
836
837#define PROG_CHUNK 64
838
839int ipath_sd7220_prog_ld(struct ipath_devdata *dd, int sdnum,
840 u8 *img, int len, int offset)
841{
842 int cnt, sofar, req;
843
844 sofar = 0;
845 while (sofar < len) {
846 req = len - sofar;
847 if (req > PROG_CHUNK)
848 req = PROG_CHUNK;
849 cnt = ipath_sd7220_ram_xfer(dd, sdnum, offset + sofar,
850 img + sofar, req, 0);
851 if (cnt < req) {
852 sofar = -1;
853 break;
854 }
855 sofar += req;
856 }
857 return sofar;
858}
859
860#define VFY_CHUNK 64
861#define SD_PRAM_ERROR_LIMIT 42
862
863int ipath_sd7220_prog_vfy(struct ipath_devdata *dd, int sdnum,
864 const u8 *img, int len, int offset)
865{
866 int cnt, sofar, req, idx, errors;
867 unsigned char readback[VFY_CHUNK];
868
869 errors = 0;
870 sofar = 0;
871 while (sofar < len) {
872 req = len - sofar;
873 if (req > VFY_CHUNK)
874 req = VFY_CHUNK;
875 cnt = ipath_sd7220_ram_xfer(dd, sdnum, sofar + offset,
876 readback, req, 1);
877 if (cnt < req) {
878
879 sofar = -1;
880 break;
881 }
882 for (idx = 0; idx < cnt; ++idx) {
883 if (readback[idx] != img[idx+sofar])
884 ++errors;
885 }
886 sofar += cnt;
887 }
888 return errors ? -errors : sofar;
889}
890
891
892#define IB_SERDES_TRIM_DONE (1ULL << 11)
893#define TRIM_TMO (30)
894
895static int ipath_sd_trimdone_poll(struct ipath_devdata *dd)
896{
897 int trim_tmo, ret;
898 uint64_t val;
899
900
901
902
903
904 ret = 0;
905 for (trim_tmo = 0; trim_tmo < TRIM_TMO; ++trim_tmo) {
906 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
907 if (val & IB_SERDES_TRIM_DONE) {
908 ipath_cdbg(VERBOSE, "TRIMDONE after %d\n", trim_tmo);
909 ret = 1;
910 break;
911 }
912 msleep(10);
913 }
914 if (trim_tmo >= TRIM_TMO) {
915 ipath_dev_err(dd, "No TRIMDONE in %d tries\n", trim_tmo);
916 ret = 0;
917 }
918 return ret;
919}
920
921#define TX_FAST_ELT (9)
922
923
924
925
926
927
928
929
930#define NUM_DDS_REGS 6
931#define DDS_REG_MAP 0x76A910
932
933#define DDS_VAL(amp_d, main_d, ipst_d, ipre_d, amp_s, main_s, ipst_s, ipre_s) \
934 { { ((amp_d & 0x1F) << 1) | 1, ((amp_s & 0x1F) << 1) | 1, \
935 (main_d << 3) | 4 | (ipre_d >> 2), \
936 (main_s << 3) | 4 | (ipre_s >> 2), \
937 ((ipst_d & 0xF) << 1) | ((ipre_d & 3) << 6) | 0x21, \
938 ((ipst_s & 0xF) << 1) | ((ipre_s & 3) << 6) | 0x21 } }
939
940static struct dds_init {
941 uint8_t reg_vals[NUM_DDS_REGS];
942} dds_init_vals[] = {
943
944
945#define DDS_3M 0
946 DDS_VAL(31, 19, 12, 0, 29, 22, 9, 0),
947 DDS_VAL(31, 12, 15, 4, 31, 15, 15, 1),
948 DDS_VAL(31, 13, 15, 3, 31, 16, 15, 0),
949 DDS_VAL(31, 14, 15, 2, 31, 17, 14, 0),
950 DDS_VAL(31, 15, 15, 1, 31, 18, 13, 0),
951 DDS_VAL(31, 16, 15, 0, 31, 19, 12, 0),
952 DDS_VAL(31, 17, 14, 0, 31, 20, 11, 0),
953 DDS_VAL(31, 18, 13, 0, 30, 21, 10, 0),
954 DDS_VAL(31, 20, 11, 0, 28, 23, 8, 0),
955 DDS_VAL(31, 21, 10, 0, 27, 24, 7, 0),
956 DDS_VAL(31, 22, 9, 0, 26, 25, 6, 0),
957 DDS_VAL(30, 23, 8, 0, 25, 26, 5, 0),
958 DDS_VAL(29, 24, 7, 0, 23, 27, 4, 0),
959
960#define DDS_1M 13
961 DDS_VAL(28, 25, 6, 0, 21, 28, 3, 0),
962 DDS_VAL(27, 26, 5, 0, 19, 29, 2, 0),
963 DDS_VAL(25, 27, 4, 0, 17, 30, 1, 0)
964};
965
966
967
968
969
970
971#define RXEQ_INIT_RDESC(elt, addr) (((elt) & 0xF) | ((addr) << 4))
972#define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \
973 {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} }
974
975#define RXEQ_VAL_ALL(elt, adr, val) \
976 {RXEQ_INIT_RDESC((elt), (adr)), {(val), (val), (val), (val)} }
977
978#define RXEQ_SDR_DFELTH 0
979#define RXEQ_SDR_TLTH 0
980#define RXEQ_SDR_G1CNT_Z1CNT 0x11
981#define RXEQ_SDR_ZCNT 23
982
983static struct rxeq_init {
984 u16 rdesc;
985 u8 rdata[4];
986} rxeq_init_vals[] = {
987
988 RXEQ_VAL_ALL(7, 0x27, 0x10),
989
990 RXEQ_VAL(7, 8, 0, 0, 0, 0),
991 RXEQ_VAL(7, 0x21, 0, 0, 0, 0),
992
993 RXEQ_VAL(7, 9, 2, 2, 2, 2),
994 RXEQ_VAL(7, 0x23, 2, 2, 2, 2),
995
996 RXEQ_VAL(7, 0x1B, 12, 12, 12, 12),
997 RXEQ_VAL(7, 0x1C, 12, 12, 12, 12),
998
999 RXEQ_VAL(7, 0x1E, 0x10, 0x10, 0x10, 0x10),
1000 RXEQ_VAL(7, 0x1F, 0x10, 0x10, 0x10, 0x10),
1001
1002 RXEQ_VAL_ALL(6, 6, 0x20),
1003 RXEQ_VAL_ALL(6, 6, 0),
1004};
1005
1006
1007#define DDS_ROWS (16)
1008#define RXEQ_ROWS ARRAY_SIZE(rxeq_init_vals)
1009
1010static int ipath_sd_setvals(struct ipath_devdata *dd)
1011{
1012 int idx, midx;
1013 int min_idx;
1014 uint32_t dds_reg_map;
1015 u64 __iomem *taddr, *iaddr;
1016 uint64_t data;
1017 uint64_t sdctl;
1018
1019 taddr = dd->ipath_kregbase + KR_IBSerDesMappTable;
1020 iaddr = dd->ipath_kregbase + dd->ipath_kregs->kr_ib_ddsrxeq;
1021
1022
1023
1024
1025
1026
1027 sdctl = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibserdesctrl);
1028 sdctl = (sdctl & ~(0x1f << 8)) | (NUM_DDS_REGS << 8);
1029 sdctl = (sdctl & ~(0x1f << 13)) | (RXEQ_ROWS << 13);
1030 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibserdesctrl, sdctl);
1031
1032
1033
1034
1035 dds_reg_map = DDS_REG_MAP;
1036 for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1037 data = ((dds_reg_map & 0xF) << 4) | TX_FAST_ELT;
1038 writeq(data, iaddr + idx);
1039 mmiowb();
1040 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1041 dds_reg_map >>= 4;
1042 for (midx = 0; midx < DDS_ROWS; ++midx) {
1043 u64 __iomem *daddr = taddr + ((midx << 4) + idx);
1044 data = dds_init_vals[midx].reg_vals[idx];
1045 writeq(data, daddr);
1046 mmiowb();
1047 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1048 }
1049 }
1050
1051
1052
1053
1054
1055
1056
1057 min_idx = idx;
1058 taddr += 0x100;
1059
1060 for (idx = 0; idx < RXEQ_ROWS; ++idx) {
1061 int didx;
1062 int vidx;
1063
1064
1065 didx = idx + min_idx;
1066
1067 writeq(rxeq_init_vals[idx].rdesc, iaddr + didx);
1068 mmiowb();
1069 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1070
1071 for (vidx = 0; vidx < 4; vidx++) {
1072 data = rxeq_init_vals[idx].rdata[vidx];
1073 writeq(data, taddr + (vidx << 6) + idx);
1074 mmiowb();
1075 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1076 }
1077 }
1078 return 0;
1079}
1080
1081#define CMUCTRL5 EPB_LOC(7, 0, 0x15)
1082#define RXHSCTRL0(chan) EPB_LOC(chan, 6, 0)
1083#define VCDL_DAC2(chan) EPB_LOC(chan, 6, 5)
1084#define VCDL_CTRL0(chan) EPB_LOC(chan, 6, 6)
1085#define VCDL_CTRL2(chan) EPB_LOC(chan, 6, 8)
1086#define START_EQ2(chan) EPB_LOC(chan, 7, 0x28)
1087
1088static int ibsd_sto_noisy(struct ipath_devdata *dd, int loc, int val, int mask)
1089{
1090 int ret = -1;
1091 int sloc;
1092
1093 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1094 sloc = loc >> EPB_ADDR_SHF;
1095
1096 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, mask);
1097 if (ret < 0)
1098 ipath_dev_err(dd, "Write failed: elt %d,"
1099 " addr 0x%X, chnl %d, val 0x%02X, mask 0x%02X\n",
1100 (sloc & 0xF), (sloc >> 9) & 0x3f, (sloc >> 4) & 7,
1101 val & 0xFF, mask & 0xFF);
1102 return ret;
1103}
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113static int ibsd_mod_allchnls(struct ipath_devdata *dd, int loc, int val,
1114 int mask)
1115{
1116 int ret = -1;
1117 int chnl;
1118
1119 if (loc & EPB_GLOBAL_WR) {
1120
1121
1122
1123
1124
1125
1126 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1127 chnl = (loc >> (4 + EPB_ADDR_SHF)) & 7;
1128 if (mask != 0xFF) {
1129 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
1130 loc & ~EPB_GLOBAL_WR, 0, 0);
1131 if (ret < 0) {
1132 int sloc = loc >> EPB_ADDR_SHF;
1133 ipath_dev_err(dd, "pre-read failed: elt %d,"
1134 " addr 0x%X, chnl %d\n", (sloc & 0xF),
1135 (sloc >> 9) & 0x3f, chnl);
1136 return ret;
1137 }
1138 val = (ret & ~mask) | (val & mask);
1139 }
1140 loc &= ~(7 << (4+EPB_ADDR_SHF));
1141 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF);
1142 if (ret < 0) {
1143 int sloc = loc >> EPB_ADDR_SHF;
1144 ipath_dev_err(dd, "Global WR failed: elt %d,"
1145 " addr 0x%X, val %02X\n",
1146 (sloc & 0xF), (sloc >> 9) & 0x3f, val);
1147 }
1148 return ret;
1149 }
1150
1151 loc &= ~(7 << (4+EPB_ADDR_SHF));
1152 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1153 for (chnl = 0; chnl < 4; ++chnl) {
1154 int cloc;
1155 cloc = loc | (chnl << (4+EPB_ADDR_SHF));
1156 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask);
1157 if (ret < 0) {
1158 int sloc = loc >> EPB_ADDR_SHF;
1159 ipath_dev_err(dd, "Write failed: elt %d,"
1160 " addr 0x%X, chnl %d, val 0x%02X,"
1161 " mask 0x%02X\n",
1162 (sloc & 0xF), (sloc >> 9) & 0x3f, chnl,
1163 val & 0xFF, mask & 0xFF);
1164 break;
1165 }
1166 }
1167 return ret;
1168}
1169
1170
1171
1172
1173
1174static int set_dds_vals(struct ipath_devdata *dd, struct dds_init *ddi)
1175{
1176 int ret;
1177 int idx, reg, data;
1178 uint32_t regmap;
1179
1180 regmap = DDS_REG_MAP;
1181 for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1182 reg = (regmap & 0xF);
1183 regmap >>= 4;
1184 data = ddi->reg_vals[idx];
1185
1186 ret = ibsd_mod_allchnls(dd, EPB_LOC(0, 9, reg), data, 0xFF);
1187 if (ret < 0)
1188 break;
1189 }
1190 return ret;
1191}
1192
1193
1194
1195
1196
1197static int set_rxeq_vals(struct ipath_devdata *dd, int vsel)
1198{
1199 int ret;
1200 int ridx;
1201 int cnt = ARRAY_SIZE(rxeq_init_vals);
1202
1203 for (ridx = 0; ridx < cnt; ++ridx) {
1204 int elt, reg, val, loc;
1205 elt = rxeq_init_vals[ridx].rdesc & 0xF;
1206 reg = rxeq_init_vals[ridx].rdesc >> 4;
1207 loc = EPB_LOC(0, elt, reg);
1208 val = rxeq_init_vals[ridx].rdata[vsel];
1209
1210 ret = ibsd_mod_allchnls(dd, loc, val, 0xFF);
1211 if (ret < 0)
1212 break;
1213 }
1214 return ret;
1215}
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225static unsigned ipath_rxeq_set = 2;
1226module_param_named(rxeq_default_set, ipath_rxeq_set, uint,
1227 S_IWUSR | S_IRUGO);
1228MODULE_PARM_DESC(rxeq_default_set,
1229 "Which set [0..3] of Rx Equalization values is default");
1230
1231static int ipath_internal_presets(struct ipath_devdata *dd)
1232{
1233 int ret = 0;
1234
1235 ret = set_dds_vals(dd, dds_init_vals + DDS_3M);
1236
1237 if (ret < 0)
1238 ipath_dev_err(dd, "Failed to set default DDS values\n");
1239 ret = set_rxeq_vals(dd, ipath_rxeq_set & 3);
1240 if (ret < 0)
1241 ipath_dev_err(dd, "Failed to set default RXEQ values\n");
1242 return ret;
1243}
1244
1245int ipath_sd7220_presets(struct ipath_devdata *dd)
1246{
1247 int ret = 0;
1248
1249 if (!dd->ipath_presets_needed)
1250 return ret;
1251 dd->ipath_presets_needed = 0;
1252
1253 ipath_ibsd_reset(dd, 1);
1254 udelay(2);
1255 ipath_sd_trimdone_monitor(dd, "link-down");
1256
1257 ret = ipath_internal_presets(dd);
1258return ret;
1259}
1260
1261static int ipath_sd_trimself(struct ipath_devdata *dd, int val)
1262{
1263 return ibsd_sto_noisy(dd, CMUCTRL5, val, 0xFF);
1264}
1265
1266static int ipath_sd_early(struct ipath_devdata *dd)
1267{
1268 int ret = -1;
1269 int chnl;
1270
1271 for (chnl = 0; chnl < 4; ++chnl) {
1272 ret = ibsd_sto_noisy(dd, RXHSCTRL0(chnl), 0xD4, 0xFF);
1273 if (ret < 0)
1274 goto bail;
1275 }
1276 for (chnl = 0; chnl < 4; ++chnl) {
1277 ret = ibsd_sto_noisy(dd, VCDL_DAC2(chnl), 0x2D, 0xFF);
1278 if (ret < 0)
1279 goto bail;
1280 }
1281
1282 for (chnl = 0; chnl < 4; ++chnl) {
1283 ret = ibsd_sto_noisy(dd, VCDL_CTRL2(chnl), 3, 0xF);
1284 if (ret < 0)
1285 goto bail;
1286 }
1287 for (chnl = 0; chnl < 4; ++chnl) {
1288 ret = ibsd_sto_noisy(dd, START_EQ1(chnl), 0x10, 0xFF);
1289 if (ret < 0)
1290 goto bail;
1291 }
1292 for (chnl = 0; chnl < 4; ++chnl) {
1293 ret = ibsd_sto_noisy(dd, START_EQ2(chnl), 0x30, 0xFF);
1294 if (ret < 0)
1295 goto bail;
1296 }
1297bail:
1298 return ret;
1299}
1300
1301#define BACTRL(chnl) EPB_LOC(chnl, 6, 0x0E)
1302#define LDOUTCTRL1(chnl) EPB_LOC(chnl, 7, 6)
1303#define RXHSSTATUS(chnl) EPB_LOC(chnl, 6, 0xF)
1304
1305static int ipath_sd_dactrim(struct ipath_devdata *dd)
1306{
1307 int ret = -1;
1308 int chnl;
1309
1310 for (chnl = 0; chnl < 4; ++chnl) {
1311 ret = ibsd_sto_noisy(dd, BACTRL(chnl), 0x40, 0xFF);
1312 if (ret < 0)
1313 goto bail;
1314 }
1315 for (chnl = 0; chnl < 4; ++chnl) {
1316 ret = ibsd_sto_noisy(dd, LDOUTCTRL1(chnl), 0x04, 0xFF);
1317 if (ret < 0)
1318 goto bail;
1319 }
1320 for (chnl = 0; chnl < 4; ++chnl) {
1321 ret = ibsd_sto_noisy(dd, RXHSSTATUS(chnl), 0x04, 0xFF);
1322 if (ret < 0)
1323 goto bail;
1324 }
1325
1326
1327
1328
1329 udelay(415);
1330 for (chnl = 0; chnl < 4; ++chnl) {
1331 ret = ibsd_sto_noisy(dd, LDOUTCTRL1(chnl), 0x00, 0xFF);
1332 if (ret < 0)
1333 goto bail;
1334 }
1335bail:
1336 return ret;
1337}
1338
1339#define RELOCK_FIRST_MS 3
1340#define RXLSPPM(chan) EPB_LOC(chan, 0, 2)
1341void ipath_toggle_rclkrls(struct ipath_devdata *dd)
1342{
1343 int loc = RXLSPPM(0) | EPB_GLOBAL_WR;
1344 int ret;
1345
1346 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1347 if (ret < 0)
1348 ipath_dev_err(dd, "RCLKRLS failed to clear D7\n");
1349 else {
1350 udelay(1);
1351 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1352 }
1353
1354 udelay(1);
1355 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1356 if (ret < 0)
1357 ipath_dev_err(dd, "RCLKRLS failed to clear D7\n");
1358 else {
1359 udelay(1);
1360 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1361 }
1362
1363 dd->ipath_f_xgxs_reset(dd);
1364}
1365
1366
1367
1368
1369
1370
1371
1372void ipath_shutdown_relock_poll(struct ipath_devdata *dd)
1373{
1374 struct ipath_relock *irp = &dd->ipath_relock_singleton;
1375 if (atomic_read(&irp->ipath_relock_timer_active)) {
1376 del_timer_sync(&irp->ipath_relock_timer);
1377 atomic_set(&irp->ipath_relock_timer_active, 0);
1378 }
1379}
1380
1381static unsigned ipath_relock_by_timer = 1;
1382module_param_named(relock_by_timer, ipath_relock_by_timer, uint,
1383 S_IWUSR | S_IRUGO);
1384MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up");
1385
1386static void ipath_run_relock(unsigned long opaque)
1387{
1388 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
1389 struct ipath_relock *irp = &dd->ipath_relock_singleton;
1390 u64 val, ltstate;
1391
1392 if (!(dd->ipath_flags & IPATH_INITTED)) {
1393
1394 irp->ipath_relock_interval = HZ;
1395 mod_timer(&irp->ipath_relock_timer, jiffies + HZ);
1396 return;
1397 }
1398
1399
1400
1401
1402
1403
1404
1405 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
1406 ltstate = ipath_ib_linktrstate(dd, val);
1407
1408 if (ltstate <= INFINIPATH_IBCS_LT_STATE_CFGWAITRMT
1409 && ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
1410 int timeoff;
1411
1412 if (ipath_relock_by_timer) {
1413 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)
1414 ipath_cdbg(VERBOSE, "Skip RELOCK in AUTONEG\n");
1415 else if (!(dd->ipath_flags & IPATH_IB_LINK_DISABLED)) {
1416 ipath_cdbg(VERBOSE, "RELOCK\n");
1417 ipath_toggle_rclkrls(dd);
1418 }
1419 }
1420
1421 timeoff = irp->ipath_relock_interval << 1;
1422 if (timeoff > HZ)
1423 timeoff = HZ;
1424 irp->ipath_relock_interval = timeoff;
1425
1426 mod_timer(&irp->ipath_relock_timer, jiffies + timeoff);
1427 } else {
1428
1429 mod_timer(&irp->ipath_relock_timer, jiffies + HZ);
1430 }
1431}
1432
1433void ipath_set_relock_poll(struct ipath_devdata *dd, int ibup)
1434{
1435 struct ipath_relock *irp = &dd->ipath_relock_singleton;
1436
1437 if (ibup > 0) {
1438
1439 if (atomic_read(&irp->ipath_relock_timer_active))
1440 mod_timer(&irp->ipath_relock_timer, jiffies + HZ);
1441 } else {
1442
1443 int timeout;
1444 timeout = (HZ * ((ibup == -1) ? 1000 : RELOCK_FIRST_MS))/1000;
1445 if (timeout == 0)
1446 timeout = 1;
1447
1448 if (atomic_inc_return(&irp->ipath_relock_timer_active) == 1) {
1449 init_timer(&irp->ipath_relock_timer);
1450 irp->ipath_relock_timer.function = ipath_run_relock;
1451 irp->ipath_relock_timer.data = (unsigned long) dd;
1452 irp->ipath_relock_interval = timeout;
1453 irp->ipath_relock_timer.expires = jiffies + timeout;
1454 add_timer(&irp->ipath_relock_timer);
1455 } else {
1456 irp->ipath_relock_interval = timeout;
1457 mod_timer(&irp->ipath_relock_timer, jiffies + timeout);
1458 atomic_dec(&irp->ipath_relock_timer_active);
1459 }
1460 }
1461}
1462
1463