1/* $Id: hfc_sx.h,v 1.2.6.1 2001/09/23 22:24:48 kai Exp $ 2 * 3 * specific defines for CCD's HFC 2BDS0 S+,SP chips 4 * 5 * Author Werner Cornelius 6 * based on existing driver for CCD HFC PCI cards 7 * Copyright by Werner Cornelius <werner@isdn4linux.de> 8 * 9 * This software may be used and distributed according to the terms 10 * of the GNU General Public License, incorporated herein by reference. 11 * 12 */ 13 14/*********************************************/ 15/* thresholds for transparent B-channel mode */ 16/* change mask and threshold simultaneously */ 17/*********************************************/ 18#define HFCSX_BTRANS_THRESHOLD 128 19#define HFCSX_BTRANS_THRESMASK 0x00 20 21/* GCI/IOM bus monitor registers */ 22 23#define HFCSX_C_I 0x02 24#define HFCSX_TRxR 0x03 25#define HFCSX_MON1_D 0x0A 26#define HFCSX_MON2_D 0x0B 27 28 29/* GCI/IOM bus timeslot registers */ 30 31#define HFCSX_B1_SSL 0x20 32#define HFCSX_B2_SSL 0x21 33#define HFCSX_AUX1_SSL 0x22 34#define HFCSX_AUX2_SSL 0x23 35#define HFCSX_B1_RSL 0x24 36#define HFCSX_B2_RSL 0x25 37#define HFCSX_AUX1_RSL 0x26 38#define HFCSX_AUX2_RSL 0x27 39 40/* GCI/IOM bus data registers */ 41 42#define HFCSX_B1_D 0x28 43#define HFCSX_B2_D 0x29 44#define HFCSX_AUX1_D 0x2A 45#define HFCSX_AUX2_D 0x2B 46 47/* GCI/IOM bus configuration registers */ 48 49#define HFCSX_MST_EMOD 0x2D 50#define HFCSX_MST_MODE 0x2E 51#define HFCSX_CONNECT 0x2F 52 53 54/* Interrupt and status registers */ 55 56#define HFCSX_TRM 0x12 57#define HFCSX_B_MODE 0x13 58#define HFCSX_CHIP_ID 0x16 59#define HFCSX_CIRM 0x18 60#define HFCSX_CTMT 0x19 61#define HFCSX_INT_M1 0x1A 62#define HFCSX_INT_M2 0x1B 63#define HFCSX_INT_S1 0x1E 64#define HFCSX_INT_S2 0x1F 65#define HFCSX_STATUS 0x1C 66 67/* S/T section registers */ 68 69#define HFCSX_STATES 0x30 70#define HFCSX_SCTRL 0x31 71#define HFCSX_SCTRL_E 0x32 72#define HFCSX_SCTRL_R 0x33 73#define HFCSX_SQ 0x34 74#define HFCSX_CLKDEL 0x37 75#define HFCSX_B1_REC 0x3C 76#define HFCSX_B1_SEND 0x3C 77#define HFCSX_B2_REC 0x3D 78#define HFCSX_B2_SEND 0x3D 79#define HFCSX_D_REC 0x3E 80#define HFCSX_D_SEND 0x3E 81#define HFCSX_E_REC 0x3F 82 83/****************/ 84/* FIFO section */ 85/****************/ 86#define HFCSX_FIF_SEL 0x10 87#define HFCSX_FIF_Z1L 0x80 88#define HFCSX_FIF_Z1H 0x84 89#define HFCSX_FIF_Z2L 0x88 90#define HFCSX_FIF_Z2H 0x8C 91#define HFCSX_FIF_INCF1 0xA8 92#define HFCSX_FIF_DWR 0xAC 93#define HFCSX_FIF_F1 0xB0 94#define HFCSX_FIF_F2 0xB4 95#define HFCSX_FIF_INCF2 0xB8 96#define HFCSX_FIF_DRD 0xBC 97 98/* bits in status register (READ) */ 99#define HFCSX_SX_PROC 0x02 100#define HFCSX_NBUSY 0x04 101#define HFCSX_TIMER_ELAP 0x10 102#define HFCSX_STATINT 0x20 103#define HFCSX_FRAMEINT 0x40 104#define HFCSX_ANYINT 0x80 105 106/* bits in CTMT (Write) */ 107#define HFCSX_CLTIMER 0x80 108#define HFCSX_TIM3_125 0x04 109#define HFCSX_TIM25 0x10 110#define HFCSX_TIM50 0x14 111#define HFCSX_TIM400 0x18 112#define HFCSX_TIM800 0x1C 113#define HFCSX_AUTO_TIMER 0x20 114#define HFCSX_TRANSB2 0x02 115#define HFCSX_TRANSB1 0x01 116 117/* bits in CIRM (Write) */ 118#define HFCSX_IRQ_SELMSK 0x07 119#define HFCSX_IRQ_SELDIS 0x00 120#define HFCSX_RESET 0x08 121#define HFCSX_FIFO_RESET 0x80 122 123 124/* bits in INT_M1 and INT_S1 */ 125#define HFCSX_INTS_B1TRANS 0x01 126#define HFCSX_INTS_B2TRANS 0x02 127#define HFCSX_INTS_DTRANS 0x04 128#define HFCSX_INTS_B1REC 0x08 129#define HFCSX_INTS_B2REC 0x10 130#define HFCSX_INTS_DREC 0x20 131#define HFCSX_INTS_L1STATE 0x40 132#define HFCSX_INTS_TIMER 0x80 133 134/* bits in INT_M2 */ 135#define HFCSX_PROC_TRANS 0x01 136#define HFCSX_GCI_I_CHG 0x02 137#define HFCSX_GCI_MON_REC 0x04 138#define HFCSX_IRQ_ENABLE 0x08 139 140/* bits in STATES */ 141#define HFCSX_STATE_MSK 0x0F 142#define HFCSX_LOAD_STATE 0x10 143#define HFCSX_ACTIVATE 0x20 144#define HFCSX_DO_ACTION 0x40 145#define HFCSX_NT_G2_G3 0x80 146 147/* bits in HFCD_MST_MODE */ 148#define HFCSX_MASTER 0x01 149#define HFCSX_SLAVE 0x00 150/* remaining bits are for codecs control */ 151 152/* bits in HFCD_SCTRL */ 153#define SCTRL_B1_ENA 0x01 154#define SCTRL_B2_ENA 0x02 155#define SCTRL_MODE_TE 0x00 156#define SCTRL_MODE_NT 0x04 157#define SCTRL_LOW_PRIO 0x08 158#define SCTRL_SQ_ENA 0x10 159#define SCTRL_TEST 0x20 160#define SCTRL_NONE_CAP 0x40 161#define SCTRL_PWR_DOWN 0x80 162 163/* bits in SCTRL_E */ 164#define HFCSX_AUTO_AWAKE 0x01 165#define HFCSX_DBIT_1 0x04 166#define HFCSX_IGNORE_COL 0x08 167#define HFCSX_CHG_B1_B2 0x80 168 169/**********************************/ 170/* definitions for FIFO selection */ 171/**********************************/ 172#define HFCSX_SEL_D_RX 5 173#define HFCSX_SEL_D_TX 4 174#define HFCSX_SEL_B1_RX 1 175#define HFCSX_SEL_B1_TX 0 176#define HFCSX_SEL_B2_RX 3 177#define HFCSX_SEL_B2_TX 2 178 179#define MAX_D_FRAMES 15 180#define MAX_B_FRAMES 31 181#define B_SUB_VAL_32K 0x0200 182#define B_FIFO_SIZE_32K (0x2000 - B_SUB_VAL_32K) 183#define B_SUB_VAL_8K 0x1A00 184#define B_FIFO_SIZE_8K (0x2000 - B_SUB_VAL_8K) 185#define D_FIFO_SIZE 512 186#define D_FREG_MASK 0xF 187 188/************************************************************/ 189/* structure holding additional dynamic data -> send marker */ 190/************************************************************/ 191struct hfcsx_extra { 192 unsigned short marker[2*(MAX_B_FRAMES+1) + (MAX_D_FRAMES+1)]; 193}; 194 195extern void main_irq_hfcsx(struct BCState *bcs); 196extern void releasehfcsx(struct IsdnCardState *cs); 197