LXR linux/drivers/media/dvb/frontends/dib3000mb

   1/*
   2 * dib3000mb_priv.h
   3 *
   4 * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
   5 *
   6 *      This program is free software; you can redistribute it and/or
   7 *      modify it under the terms of the GNU General Public License as
   8 *      published by the Free Software Foundation, version 2.
   9 *
  10 * for more information see dib3000mb.c .
  11 */
  12
  13#ifndef __DIB3000MB_PRIV_H_INCLUDED__
  14#define __DIB3000MB_PRIV_H_INCLUDED__
  15
  16/* info and err, taken from usb.h, if there is anything available like by default. */
  17#define err(format, arg...)  printk(KERN_ERR     "dib3000: " format "\n" , ## arg)
  18#define info(format, arg...) printk(KERN_INFO    "dib3000: " format "\n" , ## arg)
  19#define warn(format, arg...) printk(KERN_WARNING "dib3000: " format "\n" , ## arg)
  20
  21/* handy shortcuts */
  22#define rd(reg) dib3000_read_reg(state,reg)
  23
  24#define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \
  25        { err("while sending 0x%04x to 0x%04x.",val,reg); return -EREMOTEIO; }
  26
  27#define wr_foreach(a,v) { int i; \
  28        if (sizeof(a) != sizeof(v)) \
  29                err("sizeof: %zu %zu is different",sizeof(a),sizeof(v));\
  30        for (i=0; i < sizeof(a)/sizeof(u16); i++) \
  31                wr(a[i],v[i]); \
  32        }
  33
  34#define set_or(reg,val) wr(reg,rd(reg) | val)
  35
  36#define set_and(reg,val) wr(reg,rd(reg) & val)
  37
  38/* debug */
  39
  40#ifdef CONFIG_DVB_DIBCOM_DEBUG
  41#define dprintk(level,args...) \
  42    do { if ((debug & level)) { printk(args); } } while (0)
  43#else
  44#define dprintk(args...) do { } while (0)
  45#endif
  46
  47/* mask for enabling a specific pid for the pid_filter */
  48#define DIB3000_ACTIVATE_PID_FILTERING  (0x2000)
  49
  50/* common values for tuning */
  51#define DIB3000_ALPHA_0                                 (     0)
  52#define DIB3000_ALPHA_1                                 (     1)
  53#define DIB3000_ALPHA_2                                 (     2)
  54#define DIB3000_ALPHA_4                                 (     4)
  55
  56#define DIB3000_CONSTELLATION_QPSK              (     0)
  57#define DIB3000_CONSTELLATION_16QAM             (     1)
  58#define DIB3000_CONSTELLATION_64QAM             (     2)
  59
  60#define DIB3000_GUARD_TIME_1_32                 (     0)
  61#define DIB3000_GUARD_TIME_1_16                 (     1)
  62#define DIB3000_GUARD_TIME_1_8                  (     2)
  63#define DIB3000_GUARD_TIME_1_4                  (     3)
  64
  65#define DIB3000_TRANSMISSION_MODE_2K    (     0)
  66#define DIB3000_TRANSMISSION_MODE_8K    (     1)
  67
  68#define DIB3000_SELECT_LP                               (     0)
  69#define DIB3000_SELECT_HP                               (     1)
  70
  71#define DIB3000_FEC_1_2                                 (     1)
  72#define DIB3000_FEC_2_3                                 (     2)
  73#define DIB3000_FEC_3_4                                 (     3)
  74#define DIB3000_FEC_5_6                                 (     5)
  75#define DIB3000_FEC_7_8                                 (     7)
  76
  77#define DIB3000_HRCH_OFF                                (     0)
  78#define DIB3000_HRCH_ON                                 (     1)
  79
  80#define DIB3000_DDS_INVERSION_OFF               (     0)
  81#define DIB3000_DDS_INVERSION_ON                (     1)
  82
  83#define DIB3000_TUNER_WRITE_ENABLE(a)   (0xffff & (a << 8))
  84#define DIB3000_TUNER_WRITE_DISABLE(a)  (0xffff & ((a << 8) | (1 << 7)))
  85
  86#define DIB3000_REG_MANUFACTOR_ID               (  1025)
  87#define DIB3000_I2C_ID_DIBCOM                   (0x01b3)
  88
  89#define DIB3000_REG_DEVICE_ID                   (  1026)
  90#define DIB3000MB_DEVICE_ID                             (0x3000)
  91#define DIB3000MC_DEVICE_ID                             (0x3001)
  92#define DIB3000P_DEVICE_ID                              (0x3002)
  93
  94/* frontend state */
  95struct dib3000_state {
  96        struct i2c_adapter* i2c;
  97
  98/* configuration settings */
  99        struct dib3000_config config;
 100
 101        struct dvb_frontend frontend;
 102        int timing_offset;
 103        int timing_offset_comp_done;
 104
 105        fe_bandwidth_t last_tuned_bw;
 106        u32 last_tuned_freq;
 107};
 108
 109/* register addresses and some of their default values */
 110
 111/* restart subsystems */
 112#define DIB3000MB_REG_RESTART                   (     0)
 113
 114#define DIB3000MB_RESTART_OFF                   (     0)
 115#define DIB3000MB_RESTART_AUTO_SEARCH           (1 << 1)
 116#define DIB3000MB_RESTART_CTRL                          (1 << 2)
 117#define DIB3000MB_RESTART_AGC                           (1 << 3)
 118
 119/* FFT size */
 120#define DIB3000MB_REG_FFT                               (     1)
 121
 122/* Guard time */
 123#define DIB3000MB_REG_GUARD_TIME                (     2)
 124
 125/* QAM */
 126#define DIB3000MB_REG_QAM                               (     3)
 127
 128/* Alpha coefficient high priority Viterbi algorithm */
 129#define DIB3000MB_REG_VIT_ALPHA                 (     4)
 130
 131/* spectrum inversion */
 132#define DIB3000MB_REG_DDS_INV                   (     5)
 133
 134/* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */
 135#define DIB3000MB_REG_DDS_FREQ_MSB              (     6)
 136#define DIB3000MB_REG_DDS_FREQ_LSB              (     7)
 137#define DIB3000MB_DDS_FREQ_MSB                          (   178)
 138#define DIB3000MB_DDS_FREQ_LSB                          (  8990)
 139
 140/* timing frequency (carrier spacing) */
 141static u16 dib3000mb_reg_timing_freq[] = { 8,9 };
 142static u16 dib3000mb_timing_freq[][2] = {
 143        { 126 , 48873 }, /* 6 MHz */
 144        { 147 , 57019 }, /* 7 MHz */
 145        { 168 , 65164 }, /* 8 MHz */
 146};
 147
 148/* impulse noise parameter */
 149/* 36 ??? */
 150
 151static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 };
 152
 153enum dib3000mb_impulse_noise_type {
 154        DIB3000MB_IMPNOISE_OFF,
 155        DIB3000MB_IMPNOISE_MOBILE,
 156        DIB3000MB_IMPNOISE_FIXED,
 157        DIB3000MB_IMPNOISE_DEFAULT
 158};
 159
 160static u16 dib3000mb_impulse_noise_values[][5] = {
 161        { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */
 162        { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */
 163        { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */
 164        { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */
 165};
 166
 167/*
 168 * Dual Automatic-Gain-Control
 169 * - gains RF in tuner (AGC1)
 170 * - gains IF after filtering (AGC2)
 171 */
 172
 173/* also from 16 to 18 */
 174static u16 dib3000mb_reg_agc_gain[] = {
 175        19,20,21,22,23,24,25,26,27,28,29,30,31,32
 176};
 177
 178static u16 dib3000mb_default_agc_gain[] =
 179        { 0x0001, 52429,   623, 128, 166, 195, 61,   /* RF ??? */
 180          0x0001, 53766, 38011,   0,  90,  33, 23 }; /* IF ??? */
 181
 182/* phase noise */
 183/* 36 is set when setting the impulse noise */
 184static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 };
 185
 186static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 };
 187
 188/* lock duration */
 189static u16 dib3000mb_reg_lock_duration[] = { 39,40 };
 190static u16 dib3000mb_default_lock_duration[] = { 135, 135 };
 191
 192/* AGC loop bandwidth */
 193static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 };
 194
 195static u16 dib3000mb_agc_bandwidth_low[]  =
 196        { 2088, 10, 2088, 10, 3448, 5, 3448, 5 };
 197static u16 dib3000mb_agc_bandwidth_high[] =
 198        { 2349,  5, 2349,  5, 2586, 2, 2586, 2 };
 199
 200/*
 201 * lock0 definition (coff_lock)
 202 */
 203#define DIB3000MB_REG_LOCK0_MASK                (    51)
 204#define DIB3000MB_LOCK0_DEFAULT                         (     4)
 205
 206/*
 207 * lock1 definition (cpil_lock)
 208 * for auto search
 209 * which values hide behind the lock masks
 210 */
 211#define DIB3000MB_REG_LOCK1_MASK                (    52)
 212#define DIB3000MB_LOCK1_SEARCH_4                        (0x0004)
 213#define DIB3000MB_LOCK1_SEARCH_2048                     (0x0800)
 214#define DIB3000MB_LOCK1_DEFAULT                         (0x0001)
 215
 216/*
 217 * lock2 definition (fec_lock) */
 218#define DIB3000MB_REG_LOCK2_MASK                (    53)
 219#define DIB3000MB_LOCK2_DEFAULT                         (0x0080)
 220
 221/*
 222 * SEQ ? what was that again ... :)
 223 * changes when, inversion, guard time and fft is
 224 * either automatically detected or not
 225 */
 226#define DIB3000MB_REG_SEQ                               (    54)
 227
 228/* bandwidth */
 229static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 };
 230static u16 dib3000mb_bandwidth_6mhz[] =
 231        { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 };
 232
 233static u16 dib3000mb_bandwidth_7mhz[] =
 234        { 0, 28, 64421,  96, 39973, 483,  3255, 0, 1000, 0, 1010, 1, 45264 };
 235
 236static u16 dib3000mb_bandwidth_8mhz[] =
 237        { 0, 25, 23600,  84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 };
 238
 239#define DIB3000MB_REG_UNK_68                            (    68)
 240#define DIB3000MB_UNK_68                                                (     0)
 241
 242#define DIB3000MB_REG_UNK_69                            (    69)
 243#define DIB3000MB_UNK_69                                                (     0)
 244
 245#define DIB3000MB_REG_UNK_71                            (    71)
 246#define DIB3000MB_UNK_71                                                (     0)
 247
 248#define DIB3000MB_REG_UNK_77                            (    77)
 249#define DIB3000MB_UNK_77                                                (     6)
 250
 251#define DIB3000MB_REG_UNK_78                            (    78)
 252#define DIB3000MB_UNK_78                                                (0x0080)
 253
 254/* isi */
 255#define DIB3000MB_REG_ISI                               (    79)
 256#define DIB3000MB_ISI_ACTIVATE                          (     0)
 257#define DIB3000MB_ISI_INHIBIT                           (     1)
 258
 259/* sync impovement */
 260#define DIB3000MB_REG_SYNC_IMPROVEMENT  (    84)
 261#define DIB3000MB_SYNC_IMPROVE_2K_1_8           (     3)
 262#define DIB3000MB_SYNC_IMPROVE_DEFAULT          (     0)
 263
 264/* phase noise compensation inhibition */
 265#define DIB3000MB_REG_PHASE_NOISE               (    87)
 266#define DIB3000MB_PHASE_NOISE_DEFAULT   (     0)
 267
 268#define DIB3000MB_REG_UNK_92                            (    92)
 269#define DIB3000MB_UNK_92                                                (0x0080)
 270
 271#define DIB3000MB_REG_UNK_96                            (    96)
 272#define DIB3000MB_UNK_96                                                (0x0010)
 273
 274#define DIB3000MB_REG_UNK_97                            (    97)
 275#define DIB3000MB_UNK_97                                                (0x0009)
 276
 277/* mobile mode ??? */
 278#define DIB3000MB_REG_MOBILE_MODE               (   101)
 279#define DIB3000MB_MOBILE_MODE_ON                        (     1)
 280#define DIB3000MB_MOBILE_MODE_OFF                       (     0)
 281
 282#define DIB3000MB_REG_UNK_106                   (   106)
 283#define DIB3000MB_UNK_106                                       (0x0080)
 284
 285#define DIB3000MB_REG_UNK_107                   (   107)
 286#define DIB3000MB_UNK_107                                       (0x0080)
 287
 288#define DIB3000MB_REG_UNK_108                   (   108)
 289#define DIB3000MB_UNK_108                                       (0x0080)
 290
 291/* fft */
 292#define DIB3000MB_REG_UNK_121                   (   121)
 293#define DIB3000MB_UNK_121_2K                            (     7)
 294#define DIB3000MB_UNK_121_DEFAULT                       (     5)
 295
 296#define DIB3000MB_REG_UNK_122                   (   122)
 297#define DIB3000MB_UNK_122                                       (  2867)
 298
 299/* QAM for mobile mode */
 300#define DIB3000MB_REG_MOBILE_MODE_QAM   (   126)
 301#define DIB3000MB_MOBILE_MODE_QAM_64            (     3)
 302#define DIB3000MB_MOBILE_MODE_QAM_QPSK_16       (     1)
 303#define DIB3000MB_MOBILE_MODE_QAM_OFF           (     0)
 304
 305/*
 306 * data diversity when having more than one chip on-board
 307 * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY
 308 */
 309#define DIB3000MB_REG_DATA_IN_DIVERSITY         (   127)
 310#define DIB3000MB_DATA_DIVERSITY_IN_OFF                 (     0)
 311#define DIB3000MB_DATA_DIVERSITY_IN_ON                  (     2)
 312
 313/* vit hrch */
 314#define DIB3000MB_REG_VIT_HRCH                  (   128)
 315
 316/* vit code rate */
 317#define DIB3000MB_REG_VIT_CODE_RATE             (   129)
 318
 319/* vit select hp */
 320#define DIB3000MB_REG_VIT_HP                    (   130)
 321
 322/* time frame for Bit-Error-Rate calculation */
 323#define DIB3000MB_REG_BERLEN                    (   135)
 324#define DIB3000MB_BERLEN_LONG                           (     0)
 325#define DIB3000MB_BERLEN_DEFAULT                        (     1)
 326#define DIB3000MB_BERLEN_MEDIUM                         (     2)
 327#define DIB3000MB_BERLEN_SHORT                          (     3)
 328
 329/* 142 - 152 FIFO parameters
 330 * which is what ?
 331 */
 332
 333#define DIB3000MB_REG_FIFO_142                  (   142)
 334#define DIB3000MB_FIFO_142                                      (     0)
 335
 336/* MPEG2 TS output mode */
 337#define DIB3000MB_REG_MPEG2_OUT_MODE    (   143)
 338#define DIB3000MB_MPEG2_OUT_MODE_204            (     0)
 339#define DIB3000MB_MPEG2_OUT_MODE_188            (     1)
 340
 341#define DIB3000MB_REG_PID_PARSE                 (   144)
 342#define DIB3000MB_PID_PARSE_INHIBIT             (     0)
 343#define DIB3000MB_PID_PARSE_ACTIVATE    (     1)
 344
 345#define DIB3000MB_REG_FIFO                              (   145)
 346#define DIB3000MB_FIFO_INHIBIT                          (     1)
 347#define DIB3000MB_FIFO_ACTIVATE                         (     0)
 348
 349#define DIB3000MB_REG_FIFO_146                  (   146)
 350#define DIB3000MB_FIFO_146                                      (     3)
 351
 352#define DIB3000MB_REG_FIFO_147                  (   147)
 353#define DIB3000MB_FIFO_147                                      (0x0100)
 354
 355/*
 356 * pidfilter
 357 * it is not a hardware pidfilter but a filter which drops all pids
 358 * except the ones set. Necessary because of the limited USB1.1 bandwidth.
 359 * regs 153-168
 360 */
 361
 362#define DIB3000MB_REG_FIRST_PID                 (   153)
 363#define DIB3000MB_NUM_PIDS                              (    16)
 364
 365/*
 366 * output mode
 367 * USB devices have to use 'slave'-mode
 368 * see also DIB3000MB_REG_ELECT_OUT_MODE
 369 */
 370#define DIB3000MB_REG_OUTPUT_MODE               (   169)
 371#define DIB3000MB_OUTPUT_MODE_GATED_CLK         (     0)
 372#define DIB3000MB_OUTPUT_MODE_CONT_CLK          (     1)
 373#define DIB3000MB_OUTPUT_MODE_SERIAL            (     2)
 374#define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY    (     5)
 375#define DIB3000MB_OUTPUT_MODE_SLAVE                     (     6)
 376
 377/* irq event mask */
 378#define DIB3000MB_REG_IRQ_EVENT_MASK            (   170)
 379#define DIB3000MB_IRQ_EVENT_MASK                                (     0)
 380
 381/* filter coefficients */
 382static u16 dib3000mb_reg_filter_coeffs[] = {
 383        171, 172, 173, 174, 175, 176, 177, 178,
 384        179, 180, 181, 182, 183, 184, 185, 186,
 385        188, 189, 190, 191, 192, 194
 386};
 387
 388static u16 dib3000mb_filter_coeffs[] = {
 389         226,  160,   29,
 390         979,  998,   19,
 391          22, 1019, 1006,
 392        1022,   12,    6,
 393        1017, 1017,    3,
 394           6,       1019,
 395        1021,    2,    3,
 396           1,          0,
 397};
 398
 399/*
 400 * mobile algorithm (when you are moving with your device)
 401 * but not faster than 90 km/h
 402 */
 403#define DIB3000MB_REG_MOBILE_ALGO               (   195)
 404#define DIB3000MB_MOBILE_ALGO_ON                        (     0)
 405#define DIB3000MB_MOBILE_ALGO_OFF                       (     1)
 406
 407/* multiple demodulators algorithm */
 408#define DIB3000MB_REG_MULTI_DEMOD_MSB   (   206)
 409#define DIB3000MB_REG_MULTI_DEMOD_LSB   (   207)
 410
 411/* terminator, no more demods */
 412#define DIB3000MB_MULTI_DEMOD_MSB                       ( 32767)
 413#define DIB3000MB_MULTI_DEMOD_LSB                       (  4095)
 414
 415/* bring the device into a known  */
 416#define DIB3000MB_REG_RESET_DEVICE              (  1024)
 417#define DIB3000MB_RESET_DEVICE                          (0x812c)
 418#define DIB3000MB_RESET_DEVICE_RST                      (     0)
 419
 420/* hardware clock configuration */
 421#define DIB3000MB_REG_CLOCK                             (  1027)
 422#define DIB3000MB_CLOCK_DEFAULT                         (0x9000)
 423#define DIB3000MB_CLOCK_DIVERSITY                       (0x92b0)
 424
 425/* power down config */
 426#define DIB3000MB_REG_POWER_CONTROL             (  1028)
 427#define DIB3000MB_POWER_DOWN                            (     1)
 428#define DIB3000MB_POWER_UP                                      (     0)
 429
 430/* electrical output mode */
 431#define DIB3000MB_REG_ELECT_OUT_MODE    (  1029)
 432#define DIB3000MB_ELECT_OUT_MODE_OFF            (     0)
 433#define DIB3000MB_ELECT_OUT_MODE_ON                     (     1)
 434
 435/* set the tuner i2c address */
 436#define DIB3000MB_REG_TUNER                             (  1089)
 437
 438/* monitoring registers (read only) */
 439
 440/* agc loop locked (size: 1) */
 441#define DIB3000MB_REG_AGC_LOCK                  (   324)
 442
 443/* agc power (size: 16) */
 444#define DIB3000MB_REG_AGC_POWER                 (   325)
 445
 446/* agc1 value (16) */
 447#define DIB3000MB_REG_AGC1_VALUE                (   326)
 448
 449/* agc2 value (16) */
 450#define DIB3000MB_REG_AGC2_VALUE                (   327)
 451
 452/* total RF power (16), can be used for signal strength */
 453#define DIB3000MB_REG_RF_POWER                  (   328)
 454
 455/* dds_frequency with offset (24) */
 456#define DIB3000MB_REG_DDS_VALUE_MSB             (   339)
 457#define DIB3000MB_REG_DDS_VALUE_LSB             (   340)
 458
 459/* timing offset signed (24) */
 460#define DIB3000MB_REG_TIMING_OFFSET_MSB (   341)
 461#define DIB3000MB_REG_TIMING_OFFSET_LSB (   342)
 462
 463/* fft start position (13) */
 464#define DIB3000MB_REG_FFT_WINDOW_POS    (   353)
 465
 466/* carriers locked (1) */
 467#define DIB3000MB_REG_CARRIER_LOCK              (   355)
 468
 469/* noise power (24) */
 470#define DIB3000MB_REG_NOISE_POWER_MSB   (   372)
 471#define DIB3000MB_REG_NOISE_POWER_LSB   (   373)
 472
 473#define DIB3000MB_REG_MOBILE_NOISE_MSB  (   374)
 474#define DIB3000MB_REG_MOBILE_NOISE_LSB  (   375)
 475
 476/*
 477 * signal power (16), this and the above can be
 478 * used to calculate the signal/noise - ratio
 479 */
 480#define DIB3000MB_REG_SIGNAL_POWER              (   380)
 481
 482/* mer (24) */
 483#define DIB3000MB_REG_MER_MSB                   (   381)
 484#define DIB3000MB_REG_MER_LSB                   (   382)
 485
 486/*
 487 * Transmission Parameter Signalling (TPS)
 488 * the following registers can be used to get TPS-information.
 489 * The values are according to the DVB-T standard.
 490 */
 491
 492/* TPS locked (1) */
 493#define DIB3000MB_REG_TPS_LOCK                  (   394)
 494
 495/* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */
 496#define DIB3000MB_REG_TPS_QAM                   (   398)
 497
 498/* hierarchy from TPS (1) */
 499#define DIB3000MB_REG_TPS_HRCH                  (   399)
 500
 501/* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */
 502#define DIB3000MB_REG_TPS_VIT_ALPHA             (   400)
 503
 504/* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */
 505#define DIB3000MB_REG_TPS_CODE_RATE_HP  (   401)
 506
 507/* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */
 508#define DIB3000MB_REG_TPS_CODE_RATE_LP  (   402)
 509
 510/* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */
 511#define DIB3000MB_REG_TPS_GUARD_TIME    (   403)
 512
 513/* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */
 514#define DIB3000MB_REG_TPS_FFT                   (   404)
 515
 516/* cell id from TPS (16) */
 517#define DIB3000MB_REG_TPS_CELL_ID               (   406)
 518
 519/* TPS (68) */
 520#define DIB3000MB_REG_TPS_1                             (   408)
 521#define DIB3000MB_REG_TPS_2                             (   409)
 522#define DIB3000MB_REG_TPS_3                             (   410)
 523#define DIB3000MB_REG_TPS_4                             (   411)
 524#define DIB3000MB_REG_TPS_5                             (   412)
 525
 526/* bit error rate (before RS correction) (21) */
 527#define DIB3000MB_REG_BER_MSB                   (   414)
 528#define DIB3000MB_REG_BER_LSB                   (   415)
 529
 530/* packet error rate (uncorrected TS packets) (16) */
 531#define DIB3000MB_REG_PACKET_ERROR_RATE (   417)
 532
 533/* uncorrected packet count (16) */
 534#define DIB3000MB_REG_UNC                               (   420)
 535
 536/* viterbi locked (1) */
 537#define DIB3000MB_REG_VIT_LCK                   (   421)
 538
 539/* viterbi inidcator (16) */
 540#define DIB3000MB_REG_VIT_INDICATOR             (   422)
 541
 542/* transport stream sync lock (1) */
 543#define DIB3000MB_REG_TS_SYNC_LOCK              (   423)
 544
 545/* transport stream RS lock (1) */
 546#define DIB3000MB_REG_TS_RS_LOCK                (   424)
 547
 548/* lock mask 0 value (1) */
 549#define DIB3000MB_REG_LOCK0_VALUE               (   425)
 550
 551/* lock mask 1 value (1) */
 552#define DIB3000MB_REG_LOCK1_VALUE               (   426)
 553
 554/* lock mask 2 value (1) */
 555#define DIB3000MB_REG_LOCK2_VALUE               (   427)
 556
 557/* interrupt pending for auto search */
 558#define DIB3000MB_REG_AS_IRQ_PENDING    (   434)
 559
 560#endif
 561