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33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/delay.h>
37#include <linux/string.h>
38#include <linux/slab.h>
39
40#include "dvb_frontend.h"
41#include "mt352_priv.h"
42#include "mt352.h"
43
44struct mt352_state {
45 struct i2c_adapter* i2c;
46 struct dvb_frontend frontend;
47
48
49 struct mt352_config config;
50};
51
52static int debug;
53#define dprintk(args...) \
54 do { \
55 if (debug) printk(KERN_DEBUG "mt352: " args); \
56 } while (0)
57
58static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
59{
60 struct mt352_state* state = fe->demodulator_priv;
61 u8 buf[2] = { reg, val };
62 struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
63 .buf = buf, .len = 2 };
64 int err = i2c_transfer(state->i2c, &msg, 1);
65 if (err != 1) {
66 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
67 return err;
68 }
69 return 0;
70}
71
72static int _mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
73{
74 int err,i;
75 for (i=0; i < ilen-1; i++)
76 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
77 return err;
78
79 return 0;
80}
81
82static int mt352_read_register(struct mt352_state* state, u8 reg)
83{
84 int ret;
85 u8 b0 [] = { reg };
86 u8 b1 [] = { 0 };
87 struct i2c_msg msg [] = { { .addr = state->config.demod_address,
88 .flags = 0,
89 .buf = b0, .len = 1 },
90 { .addr = state->config.demod_address,
91 .flags = I2C_M_RD,
92 .buf = b1, .len = 1 } };
93
94 ret = i2c_transfer(state->i2c, msg, 2);
95
96 if (ret != 2) {
97 printk("%s: readreg error (reg=%d, ret==%i)\n",
98 __func__, reg, ret);
99 return ret;
100 }
101
102 return b1[0];
103}
104
105static int mt352_sleep(struct dvb_frontend* fe)
106{
107 static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
108
109 _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
110 return 0;
111}
112
113static void mt352_calc_nominal_rate(struct mt352_state* state,
114 enum fe_bandwidth bandwidth,
115 unsigned char *buf)
116{
117 u32 adc_clock = 20480;
118 u32 bw,value;
119
120 switch (bandwidth) {
121 case BANDWIDTH_6_MHZ:
122 bw = 6;
123 break;
124 case BANDWIDTH_7_MHZ:
125 bw = 7;
126 break;
127 case BANDWIDTH_8_MHZ:
128 default:
129 bw = 8;
130 break;
131 }
132 if (state->config.adc_clock)
133 adc_clock = state->config.adc_clock;
134
135 value = 64 * bw * (1<<16) / (7 * 8);
136 value = value * 1000 / adc_clock;
137 dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
138 __func__, bw, adc_clock, value);
139 buf[0] = msb(value);
140 buf[1] = lsb(value);
141}
142
143static void mt352_calc_input_freq(struct mt352_state* state,
144 unsigned char *buf)
145{
146 int adc_clock = 20480;
147 int if2 = 36167;
148 int ife,value;
149
150 if (state->config.adc_clock)
151 adc_clock = state->config.adc_clock;
152 if (state->config.if2)
153 if2 = state->config.if2;
154
155 if (adc_clock >= if2 * 2)
156 ife = if2;
157 else {
158 ife = adc_clock - (if2 % adc_clock);
159 if (ife > adc_clock / 2)
160 ife = adc_clock - ife;
161 }
162 value = -16374 * ife / adc_clock;
163 dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
164 __func__, if2, ife, adc_clock, value, value & 0x3fff);
165 buf[0] = msb(value);
166 buf[1] = lsb(value);
167}
168
169static int mt352_set_parameters(struct dvb_frontend* fe,
170 struct dvb_frontend_parameters *param)
171{
172 struct mt352_state* state = fe->demodulator_priv;
173 unsigned char buf[13];
174 static unsigned char tuner_go[] = { 0x5d, 0x01 };
175 static unsigned char fsm_go[] = { 0x5e, 0x01 };
176 unsigned int tps = 0;
177 struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
178
179 switch (op->code_rate_HP) {
180 case FEC_2_3:
181 tps |= (1 << 7);
182 break;
183 case FEC_3_4:
184 tps |= (2 << 7);
185 break;
186 case FEC_5_6:
187 tps |= (3 << 7);
188 break;
189 case FEC_7_8:
190 tps |= (4 << 7);
191 break;
192 case FEC_1_2:
193 case FEC_AUTO:
194 break;
195 default:
196 return -EINVAL;
197 }
198
199 switch (op->code_rate_LP) {
200 case FEC_2_3:
201 tps |= (1 << 4);
202 break;
203 case FEC_3_4:
204 tps |= (2 << 4);
205 break;
206 case FEC_5_6:
207 tps |= (3 << 4);
208 break;
209 case FEC_7_8:
210 tps |= (4 << 4);
211 break;
212 case FEC_1_2:
213 case FEC_AUTO:
214 break;
215 case FEC_NONE:
216 if (op->hierarchy_information == HIERARCHY_AUTO ||
217 op->hierarchy_information == HIERARCHY_NONE)
218 break;
219 default:
220 return -EINVAL;
221 }
222
223 switch (op->constellation) {
224 case QPSK:
225 break;
226 case QAM_AUTO:
227 case QAM_16:
228 tps |= (1 << 13);
229 break;
230 case QAM_64:
231 tps |= (2 << 13);
232 break;
233 default:
234 return -EINVAL;
235 }
236
237 switch (op->transmission_mode) {
238 case TRANSMISSION_MODE_2K:
239 case TRANSMISSION_MODE_AUTO:
240 break;
241 case TRANSMISSION_MODE_8K:
242 tps |= (1 << 0);
243 break;
244 default:
245 return -EINVAL;
246 }
247
248 switch (op->guard_interval) {
249 case GUARD_INTERVAL_1_32:
250 case GUARD_INTERVAL_AUTO:
251 break;
252 case GUARD_INTERVAL_1_16:
253 tps |= (1 << 2);
254 break;
255 case GUARD_INTERVAL_1_8:
256 tps |= (2 << 2);
257 break;
258 case GUARD_INTERVAL_1_4:
259 tps |= (3 << 2);
260 break;
261 default:
262 return -EINVAL;
263 }
264
265 switch (op->hierarchy_information) {
266 case HIERARCHY_AUTO:
267 case HIERARCHY_NONE:
268 break;
269 case HIERARCHY_1:
270 tps |= (1 << 10);
271 break;
272 case HIERARCHY_2:
273 tps |= (2 << 10);
274 break;
275 case HIERARCHY_4:
276 tps |= (3 << 10);
277 break;
278 default:
279 return -EINVAL;
280 }
281
282
283 buf[0] = TPS_GIVEN_1;
284
285 buf[1] = msb(tps);
286 buf[2] = lsb(tps);
287
288 buf[3] = 0x50;
289
290
291 mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
292 mt352_calc_input_freq(state, buf+6);
293
294 if (state->config.no_tuner) {
295 if (fe->ops.tuner_ops.set_params) {
296 fe->ops.tuner_ops.set_params(fe, param);
297 if (fe->ops.i2c_gate_ctrl)
298 fe->ops.i2c_gate_ctrl(fe, 0);
299 }
300
301 _mt352_write(fe, buf, 8);
302 _mt352_write(fe, fsm_go, 2);
303 } else {
304 if (fe->ops.tuner_ops.calc_regs) {
305 fe->ops.tuner_ops.calc_regs(fe, param, buf+8, 5);
306 buf[8] <<= 1;
307 _mt352_write(fe, buf, sizeof(buf));
308 _mt352_write(fe, tuner_go, 2);
309 }
310 }
311
312 return 0;
313}
314
315static int mt352_get_parameters(struct dvb_frontend* fe,
316 struct dvb_frontend_parameters *param)
317{
318 struct mt352_state* state = fe->demodulator_priv;
319 u16 tps;
320 u16 div;
321 u8 trl;
322 struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
323 static const u8 tps_fec_to_api[8] =
324 {
325 FEC_1_2,
326 FEC_2_3,
327 FEC_3_4,
328 FEC_5_6,
329 FEC_7_8,
330 FEC_AUTO,
331 FEC_AUTO,
332 FEC_AUTO
333 };
334
335 if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
336 return -EINVAL;
337
338
339
340
341 tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
342 div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
343 trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
344
345 op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
346 op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
347
348 switch ( (tps >> 13) & 3)
349 {
350 case 0:
351 op->constellation = QPSK;
352 break;
353 case 1:
354 op->constellation = QAM_16;
355 break;
356 case 2:
357 op->constellation = QAM_64;
358 break;
359 default:
360 op->constellation = QAM_AUTO;
361 break;
362 }
363
364 op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
365
366 switch ( (tps >> 2) & 3)
367 {
368 case 0:
369 op->guard_interval = GUARD_INTERVAL_1_32;
370 break;
371 case 1:
372 op->guard_interval = GUARD_INTERVAL_1_16;
373 break;
374 case 2:
375 op->guard_interval = GUARD_INTERVAL_1_8;
376 break;
377 case 3:
378 op->guard_interval = GUARD_INTERVAL_1_4;
379 break;
380 default:
381 op->guard_interval = GUARD_INTERVAL_AUTO;
382 break;
383 }
384
385 switch ( (tps >> 10) & 7)
386 {
387 case 0:
388 op->hierarchy_information = HIERARCHY_NONE;
389 break;
390 case 1:
391 op->hierarchy_information = HIERARCHY_1;
392 break;
393 case 2:
394 op->hierarchy_information = HIERARCHY_2;
395 break;
396 case 3:
397 op->hierarchy_information = HIERARCHY_4;
398 break;
399 default:
400 op->hierarchy_information = HIERARCHY_AUTO;
401 break;
402 }
403
404 param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;
405
406 if (trl == 0x72)
407 op->bandwidth = BANDWIDTH_8_MHZ;
408 else if (trl == 0x64)
409 op->bandwidth = BANDWIDTH_7_MHZ;
410 else
411 op->bandwidth = BANDWIDTH_6_MHZ;
412
413
414 if (mt352_read_register(state, STATUS_2) & 0x02)
415 param->inversion = INVERSION_OFF;
416 else
417 param->inversion = INVERSION_ON;
418
419 return 0;
420}
421
422static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
423{
424 struct mt352_state* state = fe->demodulator_priv;
425 int s0, s1, s3;
426
427
428
429
430
431
432
433
434
435
436
437
438
439 if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
440 return -EREMOTEIO;
441 if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
442 return -EREMOTEIO;
443 if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
444 return -EREMOTEIO;
445
446 *status = 0;
447 if (s0 & (1 << 4))
448 *status |= FE_HAS_CARRIER;
449 if (s0 & (1 << 1))
450 *status |= FE_HAS_VITERBI;
451 if (s0 & (1 << 5))
452 *status |= FE_HAS_LOCK;
453 if (s1 & (1 << 1))
454 *status |= FE_HAS_SYNC;
455 if (s3 & (1 << 6))
456 *status |= FE_HAS_SIGNAL;
457
458 if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
459 (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
460 *status &= ~FE_HAS_LOCK;
461
462 return 0;
463}
464
465static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
466{
467 struct mt352_state* state = fe->demodulator_priv;
468
469 *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
470 (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
471 (mt352_read_register (state, RS_ERR_CNT_0));
472
473 return 0;
474}
475
476static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
477{
478 struct mt352_state* state = fe->demodulator_priv;
479
480
481 u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
482 (mt352_read_register(state, AGC_GAIN_0) << 4);
483
484
485 *strength = ~signal;
486 return 0;
487}
488
489static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
490{
491 struct mt352_state* state = fe->demodulator_priv;
492
493 u8 _snr = mt352_read_register (state, SNR);
494 *snr = (_snr << 8) | _snr;
495
496 return 0;
497}
498
499static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
500{
501 struct mt352_state* state = fe->demodulator_priv;
502
503 *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
504 (mt352_read_register (state, RS_UBC_0));
505
506 return 0;
507}
508
509static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
510{
511 fe_tune_settings->min_delay_ms = 800;
512 fe_tune_settings->step_size = 0;
513 fe_tune_settings->max_drift = 0;
514
515 return 0;
516}
517
518static int mt352_init(struct dvb_frontend* fe)
519{
520 struct mt352_state* state = fe->demodulator_priv;
521
522 static u8 mt352_reset_attach [] = { RESET, 0xC0 };
523
524 dprintk("%s: hello\n",__func__);
525
526 if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
527 (mt352_read_register(state, CONFIG) & 0x20) == 0) {
528
529
530 _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
531 return state->config.demod_init(fe);
532 }
533
534 return 0;
535}
536
537static void mt352_release(struct dvb_frontend* fe)
538{
539 struct mt352_state* state = fe->demodulator_priv;
540 kfree(state);
541}
542
543static struct dvb_frontend_ops mt352_ops;
544
545struct dvb_frontend* mt352_attach(const struct mt352_config* config,
546 struct i2c_adapter* i2c)
547{
548 struct mt352_state* state = NULL;
549
550
551 state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
552 if (state == NULL) goto error;
553
554
555 state->i2c = i2c;
556 memcpy(&state->config,config,sizeof(struct mt352_config));
557
558
559 if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
560
561
562 memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
563 state->frontend.demodulator_priv = state;
564 return &state->frontend;
565
566error:
567 kfree(state);
568 return NULL;
569}
570
571static struct dvb_frontend_ops mt352_ops = {
572
573 .info = {
574 .name = "Zarlink MT352 DVB-T",
575 .type = FE_OFDM,
576 .frequency_min = 174000000,
577 .frequency_max = 862000000,
578 .frequency_stepsize = 166667,
579 .frequency_tolerance = 0,
580 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
581 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
582 FE_CAN_FEC_AUTO |
583 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
584 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
585 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
586 FE_CAN_MUTE_TS
587 },
588
589 .release = mt352_release,
590
591 .init = mt352_init,
592 .sleep = mt352_sleep,
593 .write = _mt352_write,
594
595 .set_frontend = mt352_set_parameters,
596 .get_frontend = mt352_get_parameters,
597 .get_tune_settings = mt352_get_tune_settings,
598
599 .read_status = mt352_read_status,
600 .read_ber = mt352_read_ber,
601 .read_signal_strength = mt352_read_signal_strength,
602 .read_snr = mt352_read_snr,
603 .read_ucblocks = mt352_read_ucblocks,
604};
605
606module_param(debug, int, 0644);
607MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
608
609MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
610MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
611MODULE_LICENSE("GPL");
612
613EXPORT_SYMBOL(mt352_attach);
614
