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22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include "dvb_frontend.h"
29#include "s5h1409.h"
30
31struct s5h1409_state {
32
33 struct i2c_adapter *i2c;
34
35
36 const struct s5h1409_config *config;
37
38 struct dvb_frontend frontend;
39
40
41 fe_modulation_t current_modulation;
42
43 u32 current_frequency;
44 int if_freq;
45
46 u32 is_qam_locked;
47 u32 qam_state;
48};
49
50static int debug;
51module_param(debug, int, 0644);
52MODULE_PARM_DESC(debug, "Enable verbose debug messages");
53
54#define dprintk if (debug) printk
55
56
57static struct init_tab {
58 u8 reg;
59 u16 data;
60} init_tab[] = {
61 { 0x00, 0x0071, },
62 { 0x01, 0x3213, },
63 { 0x09, 0x0025, },
64 { 0x1c, 0x001d, },
65 { 0x1f, 0x002d, },
66 { 0x20, 0x001d, },
67 { 0x22, 0x0022, },
68 { 0x23, 0x0020, },
69 { 0x29, 0x110f, },
70 { 0x2a, 0x10b4, },
71 { 0x2b, 0x10ae, },
72 { 0x2c, 0x0031, },
73 { 0x31, 0x010d, },
74 { 0x32, 0x0100, },
75 { 0x44, 0x0510, },
76 { 0x54, 0x0104, },
77 { 0x58, 0x2222, },
78 { 0x59, 0x1162, },
79 { 0x5a, 0x3211, },
80 { 0x5d, 0x0370, },
81 { 0x5e, 0x0296, },
82 { 0x61, 0x0010, },
83 { 0x63, 0x4a00, },
84 { 0x65, 0x0800, },
85 { 0x71, 0x0003, },
86 { 0x72, 0x0470, },
87 { 0x81, 0x0002, },
88 { 0x82, 0x0600, },
89 { 0x86, 0x0002, },
90 { 0x8a, 0x2c38, },
91 { 0x8b, 0x2a37, },
92 { 0x92, 0x302f, },
93 { 0x93, 0x3332, },
94 { 0x96, 0x000c, },
95 { 0x99, 0x0101, },
96 { 0x9c, 0x2e37, },
97 { 0x9d, 0x2c37, },
98 { 0x9e, 0x2c37, },
99 { 0xab, 0x0100, },
100 { 0xac, 0x1003, },
101 { 0xad, 0x103f, },
102 { 0xe2, 0x0100, },
103 { 0xe3, 0x1000, },
104 { 0x28, 0x1010, },
105 { 0xb1, 0x000e, },
106};
107
108
109static struct vsb_snr_tab {
110 u16 val;
111 u16 data;
112} vsb_snr_tab[] = {
113 { 924, 300, },
114 { 923, 300, },
115 { 918, 295, },
116 { 915, 290, },
117 { 911, 285, },
118 { 906, 280, },
119 { 901, 275, },
120 { 896, 270, },
121 { 891, 265, },
122 { 885, 260, },
123 { 879, 255, },
124 { 873, 250, },
125 { 864, 245, },
126 { 858, 240, },
127 { 850, 235, },
128 { 841, 230, },
129 { 832, 225, },
130 { 823, 220, },
131 { 812, 215, },
132 { 802, 210, },
133 { 788, 205, },
134 { 778, 200, },
135 { 767, 195, },
136 { 753, 190, },
137 { 740, 185, },
138 { 725, 180, },
139 { 707, 175, },
140 { 689, 170, },
141 { 671, 165, },
142 { 656, 160, },
143 { 637, 155, },
144 { 616, 150, },
145 { 542, 145, },
146 { 519, 140, },
147 { 507, 135, },
148 { 497, 130, },
149 { 492, 125, },
150 { 474, 120, },
151 { 300, 111, },
152 { 0, 0, },
153};
154
155
156static struct qam64_snr_tab {
157 u16 val;
158 u16 data;
159} qam64_snr_tab[] = {
160 { 1, 0, },
161 { 12, 300, },
162 { 15, 290, },
163 { 18, 280, },
164 { 22, 270, },
165 { 23, 268, },
166 { 24, 266, },
167 { 25, 264, },
168 { 27, 262, },
169 { 28, 260, },
170 { 29, 258, },
171 { 30, 256, },
172 { 32, 254, },
173 { 33, 252, },
174 { 34, 250, },
175 { 35, 249, },
176 { 36, 248, },
177 { 37, 247, },
178 { 38, 246, },
179 { 39, 245, },
180 { 40, 244, },
181 { 41, 243, },
182 { 42, 241, },
183 { 43, 240, },
184 { 44, 239, },
185 { 45, 238, },
186 { 46, 237, },
187 { 47, 236, },
188 { 48, 235, },
189 { 49, 234, },
190 { 50, 233, },
191 { 51, 232, },
192 { 52, 231, },
193 { 53, 230, },
194 { 55, 229, },
195 { 56, 228, },
196 { 57, 227, },
197 { 58, 226, },
198 { 59, 225, },
199 { 60, 224, },
200 { 62, 223, },
201 { 63, 222, },
202 { 65, 221, },
203 { 66, 220, },
204 { 68, 219, },
205 { 69, 218, },
206 { 70, 217, },
207 { 72, 216, },
208 { 73, 215, },
209 { 75, 214, },
210 { 76, 213, },
211 { 78, 212, },
212 { 80, 211, },
213 { 81, 210, },
214 { 83, 209, },
215 { 84, 208, },
216 { 85, 207, },
217 { 87, 206, },
218 { 89, 205, },
219 { 91, 204, },
220 { 93, 203, },
221 { 95, 202, },
222 { 96, 201, },
223 { 104, 200, },
224 { 255, 0, },
225};
226
227
228static struct qam256_snr_tab {
229 u16 val;
230 u16 data;
231} qam256_snr_tab[] = {
232 { 1, 0, },
233 { 12, 400, },
234 { 13, 390, },
235 { 15, 380, },
236 { 17, 360, },
237 { 19, 350, },
238 { 22, 348, },
239 { 23, 346, },
240 { 24, 344, },
241 { 25, 342, },
242 { 26, 340, },
243 { 27, 336, },
244 { 28, 334, },
245 { 29, 332, },
246 { 30, 330, },
247 { 31, 328, },
248 { 32, 326, },
249 { 33, 325, },
250 { 34, 322, },
251 { 35, 320, },
252 { 37, 318, },
253 { 39, 316, },
254 { 40, 314, },
255 { 41, 312, },
256 { 42, 310, },
257 { 43, 308, },
258 { 46, 306, },
259 { 47, 304, },
260 { 49, 302, },
261 { 51, 300, },
262 { 53, 298, },
263 { 54, 297, },
264 { 55, 296, },
265 { 56, 295, },
266 { 57, 294, },
267 { 59, 293, },
268 { 60, 292, },
269 { 61, 291, },
270 { 63, 290, },
271 { 64, 289, },
272 { 65, 288, },
273 { 66, 287, },
274 { 68, 286, },
275 { 69, 285, },
276 { 71, 284, },
277 { 72, 283, },
278 { 74, 282, },
279 { 75, 281, },
280 { 76, 280, },
281 { 77, 279, },
282 { 78, 278, },
283 { 81, 277, },
284 { 83, 276, },
285 { 84, 275, },
286 { 86, 274, },
287 { 87, 273, },
288 { 89, 272, },
289 { 90, 271, },
290 { 92, 270, },
291 { 93, 269, },
292 { 95, 268, },
293 { 96, 267, },
294 { 98, 266, },
295 { 100, 265, },
296 { 102, 264, },
297 { 104, 263, },
298 { 105, 262, },
299 { 106, 261, },
300 { 110, 260, },
301 { 255, 0, },
302};
303
304
305static int s5h1409_writereg(struct s5h1409_state *state, u8 reg, u16 data)
306{
307 int ret;
308 u8 buf[] = { reg, data >> 8, data & 0xff };
309
310 struct i2c_msg msg = { .addr = state->config->demod_address,
311 .flags = 0, .buf = buf, .len = 3 };
312
313 ret = i2c_transfer(state->i2c, &msg, 1);
314
315 if (ret != 1)
316 printk(KERN_ERR "%s: error (reg == 0x%02x, val == 0x%04x, "
317 "ret == %i)\n", __func__, reg, data, ret);
318
319 return (ret != 1) ? -1 : 0;
320}
321
322static u16 s5h1409_readreg(struct s5h1409_state *state, u8 reg)
323{
324 int ret;
325 u8 b0[] = { reg };
326 u8 b1[] = { 0, 0 };
327
328 struct i2c_msg msg[] = {
329 { .addr = state->config->demod_address, .flags = 0,
330 .buf = b0, .len = 1 },
331 { .addr = state->config->demod_address, .flags = I2C_M_RD,
332 .buf = b1, .len = 2 } };
333
334 ret = i2c_transfer(state->i2c, msg, 2);
335
336 if (ret != 2)
337 printk("%s: readreg error (ret == %i)\n", __func__, ret);
338 return (b1[0] << 8) | b1[1];
339}
340
341static int s5h1409_softreset(struct dvb_frontend *fe)
342{
343 struct s5h1409_state *state = fe->demodulator_priv;
344
345 dprintk("%s()\n", __func__);
346
347 s5h1409_writereg(state, 0xf5, 0);
348 s5h1409_writereg(state, 0xf5, 1);
349 state->is_qam_locked = 0;
350 state->qam_state = 0;
351 return 0;
352}
353
354#define S5H1409_VSB_IF_FREQ 5380
355#define S5H1409_QAM_IF_FREQ (state->config->qam_if)
356
357static int s5h1409_set_if_freq(struct dvb_frontend *fe, int KHz)
358{
359 struct s5h1409_state *state = fe->demodulator_priv;
360
361 dprintk("%s(%d KHz)\n", __func__, KHz);
362
363 switch (KHz) {
364 case 4000:
365 s5h1409_writereg(state, 0x87, 0x014b);
366 s5h1409_writereg(state, 0x88, 0x0cb5);
367 s5h1409_writereg(state, 0x89, 0x03e2);
368 break;
369 case 5380:
370 case 44000:
371 default:
372 s5h1409_writereg(state, 0x87, 0x01be);
373 s5h1409_writereg(state, 0x88, 0x0436);
374 s5h1409_writereg(state, 0x89, 0x054d);
375 break;
376 }
377 state->if_freq = KHz;
378
379 return 0;
380}
381
382static int s5h1409_set_spectralinversion(struct dvb_frontend *fe, int inverted)
383{
384 struct s5h1409_state *state = fe->demodulator_priv;
385
386 dprintk("%s(%d)\n", __func__, inverted);
387
388 if (inverted == 1)
389 return s5h1409_writereg(state, 0x1b, 0x1101);
390 else
391 return s5h1409_writereg(state, 0x1b, 0x0110);
392}
393
394static int s5h1409_enable_modulation(struct dvb_frontend *fe,
395 fe_modulation_t m)
396{
397 struct s5h1409_state *state = fe->demodulator_priv;
398
399 dprintk("%s(0x%08x)\n", __func__, m);
400
401 switch (m) {
402 case VSB_8:
403 dprintk("%s() VSB_8\n", __func__);
404 if (state->if_freq != S5H1409_VSB_IF_FREQ)
405 s5h1409_set_if_freq(fe, S5H1409_VSB_IF_FREQ);
406 s5h1409_writereg(state, 0xf4, 0);
407 break;
408 case QAM_64:
409 case QAM_256:
410 case QAM_AUTO:
411 dprintk("%s() QAM_AUTO (64/256)\n", __func__);
412 if (state->if_freq != S5H1409_QAM_IF_FREQ)
413 s5h1409_set_if_freq(fe, S5H1409_QAM_IF_FREQ);
414 s5h1409_writereg(state, 0xf4, 1);
415 s5h1409_writereg(state, 0x85, 0x110);
416 break;
417 default:
418 dprintk("%s() Invalid modulation\n", __func__);
419 return -EINVAL;
420 }
421
422 state->current_modulation = m;
423 s5h1409_softreset(fe);
424
425 return 0;
426}
427
428static int s5h1409_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
429{
430 struct s5h1409_state *state = fe->demodulator_priv;
431
432 dprintk("%s(%d)\n", __func__, enable);
433
434 if (enable)
435 return s5h1409_writereg(state, 0xf3, 1);
436 else
437 return s5h1409_writereg(state, 0xf3, 0);
438}
439
440static int s5h1409_set_gpio(struct dvb_frontend *fe, int enable)
441{
442 struct s5h1409_state *state = fe->demodulator_priv;
443
444 dprintk("%s(%d)\n", __func__, enable);
445
446 if (enable)
447 return s5h1409_writereg(state, 0xe3,
448 s5h1409_readreg(state, 0xe3) | 0x1100);
449 else
450 return s5h1409_writereg(state, 0xe3,
451 s5h1409_readreg(state, 0xe3) & 0xfeff);
452}
453
454static int s5h1409_sleep(struct dvb_frontend *fe, int enable)
455{
456 struct s5h1409_state *state = fe->demodulator_priv;
457
458 dprintk("%s(%d)\n", __func__, enable);
459
460 return s5h1409_writereg(state, 0xf2, enable);
461}
462
463static int s5h1409_register_reset(struct dvb_frontend *fe)
464{
465 struct s5h1409_state *state = fe->demodulator_priv;
466
467 dprintk("%s()\n", __func__);
468
469 return s5h1409_writereg(state, 0xfa, 0);
470}
471
472static void s5h1409_set_qam_amhum_mode(struct dvb_frontend *fe)
473{
474 struct s5h1409_state *state = fe->demodulator_priv;
475 u16 reg;
476
477 if (state->is_qam_locked)
478 return;
479
480
481 reg = s5h1409_readreg(state, 0xf0);
482
483 if ((reg >> 13) & 0x1) {
484
485 state->is_qam_locked = 1;
486 reg &= 0xff;
487
488 s5h1409_writereg(state, 0x96, 0x00c);
489 if ((reg < 0x38) || (reg > 0x68)) {
490 s5h1409_writereg(state, 0x93, 0x3332);
491 s5h1409_writereg(state, 0x9e, 0x2c37);
492 } else {
493 s5h1409_writereg(state, 0x93, 0x3130);
494 s5h1409_writereg(state, 0x9e, 0x2836);
495 }
496
497 } else {
498 s5h1409_writereg(state, 0x96, 0x0008);
499 s5h1409_writereg(state, 0x93, 0x3332);
500 s5h1409_writereg(state, 0x9e, 0x2c37);
501 }
502}
503
504static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
505{
506 struct s5h1409_state *state = fe->demodulator_priv;
507 u16 reg, reg1, reg2;
508
509 reg = s5h1409_readreg(state, 0xf1);
510
511
512 if ((reg >> 15) & 0x1) {
513 if (state->qam_state != 2) {
514 state->qam_state = 2;
515 reg1 = s5h1409_readreg(state, 0xb2);
516 reg2 = s5h1409_readreg(state, 0xad);
517
518 s5h1409_writereg(state, 0x96, 0x20);
519 s5h1409_writereg(state, 0xad,
520 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
521 s5h1409_writereg(state, 0xab,
522 s5h1409_readreg(state, 0xab) & 0xeffe);
523 }
524 } else {
525 if (state->qam_state != 1) {
526 state->qam_state = 1;
527 s5h1409_writereg(state, 0x96, 0x08);
528 s5h1409_writereg(state, 0xab,
529 s5h1409_readreg(state, 0xab) | 0x1001);
530 }
531 }
532}
533
534
535static int s5h1409_set_frontend(struct dvb_frontend *fe,
536 struct dvb_frontend_parameters *p)
537{
538 struct s5h1409_state *state = fe->demodulator_priv;
539
540 dprintk("%s(frequency=%d)\n", __func__, p->frequency);
541
542 s5h1409_softreset(fe);
543
544 state->current_frequency = p->frequency;
545
546 s5h1409_enable_modulation(fe, p->u.vsb.modulation);
547
548 if (fe->ops.tuner_ops.set_params) {
549 if (fe->ops.i2c_gate_ctrl)
550 fe->ops.i2c_gate_ctrl(fe, 1);
551 fe->ops.tuner_ops.set_params(fe, p);
552 if (fe->ops.i2c_gate_ctrl)
553 fe->ops.i2c_gate_ctrl(fe, 0);
554 }
555
556
557 if (p->u.vsb.modulation != VSB_8) {
558 s5h1409_set_qam_amhum_mode(fe);
559 s5h1409_set_qam_interleave_mode(fe);
560 }
561
562
563
564 s5h1409_softreset(fe);
565
566 return 0;
567}
568
569static int s5h1409_set_mpeg_timing(struct dvb_frontend *fe, int mode)
570{
571 struct s5h1409_state *state = fe->demodulator_priv;
572 u16 val;
573
574 dprintk("%s(%d)\n", __func__, mode);
575
576 val = s5h1409_readreg(state, 0xac) & 0xcfff;
577 switch (mode) {
578 case S5H1409_MPEGTIMING_CONTINOUS_INVERTING_CLOCK:
579 val |= 0x0000;
580 break;
581 case S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK:
582 dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
583 val |= 0x1000;
584 break;
585 case S5H1409_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK:
586 val |= 0x2000;
587 break;
588 case S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK:
589 val |= 0x3000;
590 break;
591 default:
592 return -EINVAL;
593 }
594
595
596 return s5h1409_writereg(state, 0xac, val);
597}
598
599
600
601static int s5h1409_init(struct dvb_frontend *fe)
602{
603 int i;
604
605 struct s5h1409_state *state = fe->demodulator_priv;
606 dprintk("%s()\n", __func__);
607
608 s5h1409_sleep(fe, 0);
609 s5h1409_register_reset(fe);
610
611 for (i = 0; i < ARRAY_SIZE(init_tab); i++)
612 s5h1409_writereg(state, init_tab[i].reg, init_tab[i].data);
613
614
615 state->current_modulation = VSB_8;
616
617 if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
618 s5h1409_writereg(state, 0xab,
619 s5h1409_readreg(state, 0xab) | 0x100);
620 else
621 s5h1409_writereg(state, 0xab,
622 s5h1409_readreg(state, 0xab) & 0xfeff);
623
624 s5h1409_set_spectralinversion(fe, state->config->inversion);
625 s5h1409_set_if_freq(fe, state->if_freq);
626 s5h1409_set_gpio(fe, state->config->gpio);
627 s5h1409_set_mpeg_timing(fe, state->config->mpeg_timing);
628 s5h1409_softreset(fe);
629
630
631 s5h1409_i2c_gate_ctrl(fe, 0);
632
633 return 0;
634}
635
636static int s5h1409_read_status(struct dvb_frontend *fe, fe_status_t *status)
637{
638 struct s5h1409_state *state = fe->demodulator_priv;
639 u16 reg;
640 u32 tuner_status = 0;
641
642 *status = 0;
643
644
645 reg = s5h1409_readreg(state, 0xf1);
646 if (reg & 0x1000)
647 *status |= FE_HAS_VITERBI;
648 if (reg & 0x8000)
649 *status |= FE_HAS_LOCK | FE_HAS_SYNC;
650
651 switch (state->config->status_mode) {
652 case S5H1409_DEMODLOCKING:
653 if (*status & FE_HAS_VITERBI)
654 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
655 break;
656 case S5H1409_TUNERLOCKING:
657
658 if (fe->ops.tuner_ops.get_status) {
659 if (fe->ops.i2c_gate_ctrl)
660 fe->ops.i2c_gate_ctrl(fe, 1);
661
662 fe->ops.tuner_ops.get_status(fe, &tuner_status);
663
664 if (fe->ops.i2c_gate_ctrl)
665 fe->ops.i2c_gate_ctrl(fe, 0);
666 }
667 if (tuner_status)
668 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
669 break;
670 }
671
672 dprintk("%s() status 0x%08x\n", __func__, *status);
673
674 return 0;
675}
676
677static int s5h1409_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
678{
679 int i, ret = -EINVAL;
680 dprintk("%s()\n", __func__);
681
682 for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
683 if (v < qam256_snr_tab[i].val) {
684 *snr = qam256_snr_tab[i].data;
685 ret = 0;
686 break;
687 }
688 }
689 return ret;
690}
691
692static int s5h1409_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
693{
694 int i, ret = -EINVAL;
695 dprintk("%s()\n", __func__);
696
697 for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
698 if (v < qam64_snr_tab[i].val) {
699 *snr = qam64_snr_tab[i].data;
700 ret = 0;
701 break;
702 }
703 }
704 return ret;
705}
706
707static int s5h1409_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
708{
709 int i, ret = -EINVAL;
710 dprintk("%s()\n", __func__);
711
712 for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
713 if (v > vsb_snr_tab[i].val) {
714 *snr = vsb_snr_tab[i].data;
715 ret = 0;
716 break;
717 }
718 }
719 dprintk("%s() snr=%d\n", __func__, *snr);
720 return ret;
721}
722
723static int s5h1409_read_snr(struct dvb_frontend *fe, u16 *snr)
724{
725 struct s5h1409_state *state = fe->demodulator_priv;
726 u16 reg;
727 dprintk("%s()\n", __func__);
728
729 switch (state->current_modulation) {
730 case QAM_64:
731 reg = s5h1409_readreg(state, 0xf0) & 0xff;
732 return s5h1409_qam64_lookup_snr(fe, snr, reg);
733 case QAM_256:
734 reg = s5h1409_readreg(state, 0xf0) & 0xff;
735 return s5h1409_qam256_lookup_snr(fe, snr, reg);
736 case VSB_8:
737 reg = s5h1409_readreg(state, 0xf1) & 0x3ff;
738 return s5h1409_vsb_lookup_snr(fe, snr, reg);
739 default:
740 break;
741 }
742
743 return -EINVAL;
744}
745
746static int s5h1409_read_signal_strength(struct dvb_frontend *fe,
747 u16 *signal_strength)
748{
749 return s5h1409_read_snr(fe, signal_strength);
750}
751
752static int s5h1409_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
753{
754 struct s5h1409_state *state = fe->demodulator_priv;
755
756 *ucblocks = s5h1409_readreg(state, 0xb5);
757
758 return 0;
759}
760
761static int s5h1409_read_ber(struct dvb_frontend *fe, u32 *ber)
762{
763 return s5h1409_read_ucblocks(fe, ber);
764}
765
766static int s5h1409_get_frontend(struct dvb_frontend *fe,
767 struct dvb_frontend_parameters *p)
768{
769 struct s5h1409_state *state = fe->demodulator_priv;
770
771 p->frequency = state->current_frequency;
772 p->u.vsb.modulation = state->current_modulation;
773
774 return 0;
775}
776
777static int s5h1409_get_tune_settings(struct dvb_frontend *fe,
778 struct dvb_frontend_tune_settings *tune)
779{
780 tune->min_delay_ms = 1000;
781 return 0;
782}
783
784static void s5h1409_release(struct dvb_frontend *fe)
785{
786 struct s5h1409_state *state = fe->demodulator_priv;
787 kfree(state);
788}
789
790static struct dvb_frontend_ops s5h1409_ops;
791
792struct dvb_frontend *s5h1409_attach(const struct s5h1409_config *config,
793 struct i2c_adapter *i2c)
794{
795 struct s5h1409_state *state = NULL;
796 u16 reg;
797
798
799 state = kzalloc(sizeof(struct s5h1409_state), GFP_KERNEL);
800 if (state == NULL)
801 goto error;
802
803
804 state->config = config;
805 state->i2c = i2c;
806 state->current_modulation = 0;
807 state->if_freq = S5H1409_VSB_IF_FREQ;
808
809
810 reg = s5h1409_readreg(state, 0x04);
811 if ((reg != 0x0066) && (reg != 0x007f))
812 goto error;
813
814
815 memcpy(&state->frontend.ops, &s5h1409_ops,
816 sizeof(struct dvb_frontend_ops));
817 state->frontend.demodulator_priv = state;
818
819 if (s5h1409_init(&state->frontend) != 0) {
820 printk(KERN_ERR "%s: Failed to initialize correctly\n",
821 __func__);
822 goto error;
823 }
824
825
826 s5h1409_i2c_gate_ctrl(&state->frontend, 1);
827
828 return &state->frontend;
829
830error:
831 kfree(state);
832 return NULL;
833}
834EXPORT_SYMBOL(s5h1409_attach);
835
836static struct dvb_frontend_ops s5h1409_ops = {
837
838 .info = {
839 .name = "Samsung S5H1409 QAM/8VSB Frontend",
840 .type = FE_ATSC,
841 .frequency_min = 54000000,
842 .frequency_max = 858000000,
843 .frequency_stepsize = 62500,
844 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
845 },
846
847 .init = s5h1409_init,
848 .i2c_gate_ctrl = s5h1409_i2c_gate_ctrl,
849 .set_frontend = s5h1409_set_frontend,
850 .get_frontend = s5h1409_get_frontend,
851 .get_tune_settings = s5h1409_get_tune_settings,
852 .read_status = s5h1409_read_status,
853 .read_ber = s5h1409_read_ber,
854 .read_signal_strength = s5h1409_read_signal_strength,
855 .read_snr = s5h1409_read_snr,
856 .read_ucblocks = s5h1409_read_ucblocks,
857 .release = s5h1409_release,
858};
859
860MODULE_DESCRIPTION("Samsung S5H1409 QAM-B/ATSC Demodulator driver");
861MODULE_AUTHOR("Steven Toth");
862MODULE_LICENSE("GPL");
863
864
865
866
867
868
869
