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21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/timer.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/videodev2.h>
30#include <linux/i2c.h>
31#include <linux/init.h>
32#include <linux/kthread.h>
33#include <linux/freezer.h>
34
35#include <media/tvaudio.h>
36#include <media/v4l2-device.h>
37#include <media/v4l2-chip-ident.h>
38#include <media/v4l2-i2c-drv.h>
39
40#include <media/i2c-addr.h>
41
42
43
44
45static int debug;
46module_param(debug, int, 0644);
47
48MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
49MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
50MODULE_LICENSE("GPL");
51
52#define UNSET (-1U)
53
54
55
56
57#define MAXREGS 256
58
59struct CHIPSTATE;
60typedef int (*getvalue)(int);
61typedef int (*checkit)(struct CHIPSTATE*);
62typedef int (*initialize)(struct CHIPSTATE*);
63typedef int (*getmode)(struct CHIPSTATE*);
64typedef void (*setmode)(struct CHIPSTATE*, int mode);
65
66
67typedef struct AUDIOCMD {
68 int count;
69 unsigned char bytes[MAXREGS+1];
70} audiocmd;
71
72
73struct CHIPDESC {
74 char *name;
75 int addr_lo, addr_hi;
76 int registers;
77
78 int *insmodopt;
79 checkit checkit;
80 initialize initialize;
81 int flags;
82#define CHIP_HAS_VOLUME 1
83#define CHIP_HAS_BASSTREBLE 2
84#define CHIP_HAS_INPUTSEL 4
85#define CHIP_NEED_CHECKMODE 8
86
87
88 audiocmd init;
89
90
91 int leftreg,rightreg,treblereg,bassreg;
92
93
94 int leftinit,rightinit,trebleinit,bassinit;
95
96
97 getvalue volfunc,treblefunc,bassfunc;
98
99
100 getmode getmode;
101 setmode setmode;
102
103
104 int inputreg;
105 int inputmap[4];
106 int inputmute;
107 int inputmask;
108};
109
110
111struct CHIPSTATE {
112 struct v4l2_subdev sd;
113
114
115
116 struct CHIPDESC *desc;
117
118
119 audiocmd shadow;
120
121
122 __u16 left,right,treble,bass,muted,mode;
123 int prevmode;
124 int radio;
125 int input;
126
127
128 struct task_struct *thread;
129 struct timer_list wt;
130 int watch_stereo;
131 int audmode;
132};
133
134static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
135{
136 return container_of(sd, struct CHIPSTATE, sd);
137}
138
139
140
141
142
143static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
144{
145 struct v4l2_subdev *sd = &chip->sd;
146 struct i2c_client *c = v4l2_get_subdevdata(sd);
147 unsigned char buffer[2];
148
149 if (subaddr < 0) {
150 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
151 chip->shadow.bytes[1] = val;
152 buffer[0] = val;
153 if (1 != i2c_master_send(c, buffer, 1)) {
154 v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
155 return -1;
156 }
157 } else {
158 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
159 v4l2_info(sd,
160 "Tried to access a non-existent register: %d\n",
161 subaddr);
162 return -EINVAL;
163 }
164
165 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
166 subaddr, val);
167 chip->shadow.bytes[subaddr+1] = val;
168 buffer[0] = subaddr;
169 buffer[1] = val;
170 if (2 != i2c_master_send(c, buffer, 2)) {
171 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
172 subaddr, val);
173 return -1;
174 }
175 }
176 return 0;
177}
178
179static int chip_write_masked(struct CHIPSTATE *chip,
180 int subaddr, int val, int mask)
181{
182 struct v4l2_subdev *sd = &chip->sd;
183
184 if (mask != 0) {
185 if (subaddr < 0) {
186 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
187 } else {
188 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
189 v4l2_info(sd,
190 "Tried to access a non-existent register: %d\n",
191 subaddr);
192 return -EINVAL;
193 }
194
195 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
196 }
197 }
198 return chip_write(chip, subaddr, val);
199}
200
201static int chip_read(struct CHIPSTATE *chip)
202{
203 struct v4l2_subdev *sd = &chip->sd;
204 struct i2c_client *c = v4l2_get_subdevdata(sd);
205 unsigned char buffer;
206
207 if (1 != i2c_master_recv(c, &buffer, 1)) {
208 v4l2_warn(sd, "I/O error (read)\n");
209 return -1;
210 }
211 v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
212 return buffer;
213}
214
215static int chip_read2(struct CHIPSTATE *chip, int subaddr)
216{
217 struct v4l2_subdev *sd = &chip->sd;
218 struct i2c_client *c = v4l2_get_subdevdata(sd);
219 unsigned char write[1];
220 unsigned char read[1];
221 struct i2c_msg msgs[2] = {
222 { c->addr, 0, 1, write },
223 { c->addr, I2C_M_RD, 1, read }
224 };
225
226 write[0] = subaddr;
227
228 if (2 != i2c_transfer(c->adapter, msgs, 2)) {
229 v4l2_warn(sd, "I/O error (read2)\n");
230 return -1;
231 }
232 v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
233 subaddr, read[0]);
234 return read[0];
235}
236
237static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
238{
239 struct v4l2_subdev *sd = &chip->sd;
240 struct i2c_client *c = v4l2_get_subdevdata(sd);
241 int i;
242
243 if (0 == cmd->count)
244 return 0;
245
246 if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
247 v4l2_info(sd,
248 "Tried to access a non-existent register range: %d to %d\n",
249 cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
250 return -EINVAL;
251 }
252
253
254
255
256 v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
257 name, cmd->bytes[0]);
258 for (i = 1; i < cmd->count; i++) {
259 if (debug)
260 printk(KERN_CONT " 0x%x", cmd->bytes[i]);
261 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
262 }
263 if (debug)
264 printk(KERN_CONT "\n");
265
266
267 if (cmd->count != i2c_master_send(c, cmd->bytes, cmd->count)) {
268 v4l2_warn(sd, "I/O error (%s)\n", name);
269 return -1;
270 }
271 return 0;
272}
273
274
275
276
277
278
279
280
281static void chip_thread_wake(unsigned long data)
282{
283 struct CHIPSTATE *chip = (struct CHIPSTATE*)data;
284 wake_up_process(chip->thread);
285}
286
287static int chip_thread(void *data)
288{
289 struct CHIPSTATE *chip = data;
290 struct CHIPDESC *desc = chip->desc;
291 struct v4l2_subdev *sd = &chip->sd;
292 int mode;
293
294 v4l2_dbg(1, debug, sd, "thread started\n");
295 set_freezable();
296 for (;;) {
297 set_current_state(TASK_INTERRUPTIBLE);
298 if (!kthread_should_stop())
299 schedule();
300 set_current_state(TASK_RUNNING);
301 try_to_freeze();
302 if (kthread_should_stop())
303 break;
304 v4l2_dbg(1, debug, sd, "thread wakeup\n");
305
306
307 if (chip->radio || chip->mode != 0)
308 continue;
309
310
311 mode = desc->getmode(chip);
312 if (mode == chip->prevmode)
313 continue;
314
315
316 v4l2_dbg(1, debug, sd, "thread checkmode\n");
317
318 chip->prevmode = mode;
319
320 if (mode & V4L2_TUNER_MODE_STEREO)
321 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
322 if (mode & V4L2_TUNER_MODE_LANG1_LANG2)
323 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
324 else if (mode & V4L2_TUNER_MODE_LANG1)
325 desc->setmode(chip, V4L2_TUNER_MODE_LANG1);
326 else if (mode & V4L2_TUNER_MODE_LANG2)
327 desc->setmode(chip, V4L2_TUNER_MODE_LANG2);
328 else
329 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
330
331
332 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
333 }
334
335 v4l2_dbg(1, debug, sd, "thread exiting\n");
336 return 0;
337}
338
339
340
341
342#define TDA9840_SW 0x00
343#define TDA9840_LVADJ 0x02
344#define TDA9840_STADJ 0x03
345#define TDA9840_TEST 0x04
346
347#define TDA9840_MONO 0x10
348#define TDA9840_STEREO 0x2a
349#define TDA9840_DUALA 0x12
350#define TDA9840_DUALB 0x1e
351#define TDA9840_DUALAB 0x1a
352#define TDA9840_DUALBA 0x16
353#define TDA9840_EXTERNAL 0x7a
354
355#define TDA9840_DS_DUAL 0x20
356#define TDA9840_ST_STEREO 0x40
357#define TDA9840_PONRES 0x80
358
359#define TDA9840_TEST_INT1SN 0x1
360#define TDA9840_TEST_INTFU 0x02
361
362static int tda9840_getmode(struct CHIPSTATE *chip)
363{
364 struct v4l2_subdev *sd = &chip->sd;
365 int val, mode;
366
367 val = chip_read(chip);
368 mode = V4L2_TUNER_MODE_MONO;
369 if (val & TDA9840_DS_DUAL)
370 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
371 if (val & TDA9840_ST_STEREO)
372 mode |= V4L2_TUNER_MODE_STEREO;
373
374 v4l2_dbg(1, debug, sd, "tda9840_getmode(): raw chip read: %d, return: %d\n",
375 val, mode);
376 return mode;
377}
378
379static void tda9840_setmode(struct CHIPSTATE *chip, int mode)
380{
381 int update = 1;
382 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
383
384 switch (mode) {
385 case V4L2_TUNER_MODE_MONO:
386 t |= TDA9840_MONO;
387 break;
388 case V4L2_TUNER_MODE_STEREO:
389 t |= TDA9840_STEREO;
390 break;
391 case V4L2_TUNER_MODE_LANG1:
392 t |= TDA9840_DUALA;
393 break;
394 case V4L2_TUNER_MODE_LANG2:
395 t |= TDA9840_DUALB;
396 break;
397 default:
398 update = 0;
399 }
400
401 if (update)
402 chip_write(chip, TDA9840_SW, t);
403}
404
405static int tda9840_checkit(struct CHIPSTATE *chip)
406{
407 int rc;
408 rc = chip_read(chip);
409
410 return ((rc & 0x1f) == 0) ? 1 : 0;
411}
412
413
414
415
416
417#define TDA9855_VR 0x00
418#define TDA9855_VL 0x01
419#define TDA9855_BA 0x02
420#define TDA9855_TR 0x03
421#define TDA9855_SW 0x04
422
423
424#define TDA9850_C4 0x04
425
426
427#define TDA985x_C5 0x05
428#define TDA985x_C6 0x06
429#define TDA985x_C7 0x07
430#define TDA985x_A1 0x08
431#define TDA985x_A2 0x09
432#define TDA985x_A3 0x0a
433
434
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446
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448
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450
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460
461
462
463#define TDA9855_MUTE 1<<7
464#define TDA9855_AVL 1<<6
465#define TDA9855_LOUD 1<<5
466#define TDA9855_SUR 1<<3
467
468
469
470#define TDA9855_EXT 1<<2
471#define TDA9855_INT 0
472
473
474
475
476
477
478
479
480#define TDA985x_SAP 3<<6
481#define TDA985x_STEREO 1<<6
482#define TDA985x_MONO 0
483#define TDA985x_LMU 1<<3
484
485
486#define TDA9855_TZCM 1<<5
487#define TDA9855_VZCM 1<<4
488#define TDA9855_LINEAR 0
489#define TDA9855_PSEUDO 1
490#define TDA9855_SPAT_30 2
491#define TDA9855_SPAT_50 3
492#define TDA9855_E_MONO 7
493
494
495
496
497
498
499
500
501
502
503#define TDA985x_STP 1<<5
504#define TDA985x_SAPP 1<<6
505#define TDA985x_STS 1<<7
506
507
508
509
510
511#define TDA985x_ADJ 1<<7
512
513static int tda9855_volume(int val) { return val/0x2e8+0x27; }
514static int tda9855_bass(int val) { return val/0xccc+0x06; }
515static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
516
517static int tda985x_getmode(struct CHIPSTATE *chip)
518{
519 int mode;
520
521 mode = ((TDA985x_STP | TDA985x_SAPP) &
522 chip_read(chip)) >> 4;
523
524
525 return mode | V4L2_TUNER_MODE_MONO;
526}
527
528static void tda985x_setmode(struct CHIPSTATE *chip, int mode)
529{
530 int update = 1;
531 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
532
533 switch (mode) {
534 case V4L2_TUNER_MODE_MONO:
535 c6 |= TDA985x_MONO;
536 break;
537 case V4L2_TUNER_MODE_STEREO:
538 c6 |= TDA985x_STEREO;
539 break;
540 case V4L2_TUNER_MODE_LANG1:
541 c6 |= TDA985x_SAP;
542 break;
543 default:
544 update = 0;
545 }
546 if (update)
547 chip_write(chip,TDA985x_C6,c6);
548}
549
550
551
552
553
554
555
556#define TDA9873_SW 0x00
557#define TDA9873_AD 0x01
558#define TDA9873_PT 0x02
559
560
561
562
563
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565
566
567
568#define TDA9873_INP_MASK 3
569#define TDA9873_INTERNAL 0
570#define TDA9873_EXT_STEREO 2
571#define TDA9873_EXT_MONO 1
572
573
574
575
576
577
578
579
580
581
582
583
584#define TDA9873_TR_MASK (7 << 2)
585#define TDA9873_TR_MONO 4
586#define TDA9873_TR_STEREO 1 << 4
587#define TDA9873_TR_REVERSE (1 << 3) & (1 << 2)
588#define TDA9873_TR_DUALA 1 << 2
589#define TDA9873_TR_DUALB 1 << 3
590
591
592
593
594
595
596
597#define TDA9873_GAIN_NORMAL 1 << 5
598#define TDA9873_MUTE 1 << 6
599#define TDA9873_AUTOMUTE 1 << 7
600
601
602
603
604
605
606
607#define TDA9873_STEREO_ADJ 0x06
608
609
610
611
612
613
614
615
616
617
618#define TDA9873_BG 0
619#define TDA9873_M 1
620#define TDA9873_DK1 2
621#define TDA9873_DK2 3
622#define TDA9873_DK3 4
623#define TDA9873_I 5
624
625
626
627#define TDA9873_IDR_NORM 0
628#define TDA9873_IDR_FAST 1 << 7
629
630
631
632
633
634
635
636
637
638
639
640#define TDA9873_PORTS 3
641
642
643#define TDA9873_TST_PORT 1 << 2
644
645
646
647
648
649
650
651
652#define TDA9873_MOUT_MONO 0
653#define TDA9873_MOUT_FMONO 0
654#define TDA9873_MOUT_DUALA 0
655#define TDA9873_MOUT_DUALB 1 << 3
656#define TDA9873_MOUT_ST 1 << 4
657#define TDA9873_MOUT_EXTM (1 << 4 ) & (1 << 3)
658#define TDA9873_MOUT_EXTL 1 << 5
659#define TDA9873_MOUT_EXTR (1 << 5 ) & (1 << 3)
660#define TDA9873_MOUT_EXTLR (1 << 5 ) & (1 << 4)
661#define TDA9873_MOUT_MUTE (1 << 5 ) & (1 << 4) & (1 << 3)
662
663
664#define TDA9873_PONR 0
665#define TDA9873_STEREO 2
666#define TDA9873_DUAL 4
667
668static int tda9873_getmode(struct CHIPSTATE *chip)
669{
670 struct v4l2_subdev *sd = &chip->sd;
671 int val,mode;
672
673 val = chip_read(chip);
674 mode = V4L2_TUNER_MODE_MONO;
675 if (val & TDA9873_STEREO)
676 mode |= V4L2_TUNER_MODE_STEREO;
677 if (val & TDA9873_DUAL)
678 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
679 v4l2_dbg(1, debug, sd, "tda9873_getmode(): raw chip read: %d, return: %d\n",
680 val, mode);
681 return mode;
682}
683
684static void tda9873_setmode(struct CHIPSTATE *chip, int mode)
685{
686 struct v4l2_subdev *sd = &chip->sd;
687 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
688
689
690 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
691 v4l2_dbg(1, debug, sd, "tda9873_setmode(): external input\n");
692 return;
693 }
694
695 v4l2_dbg(1, debug, sd, "tda9873_setmode(): chip->shadow.bytes[%d] = %d\n", TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
696 v4l2_dbg(1, debug, sd, "tda9873_setmode(): sw_data = %d\n", sw_data);
697
698 switch (mode) {
699 case V4L2_TUNER_MODE_MONO:
700 sw_data |= TDA9873_TR_MONO;
701 break;
702 case V4L2_TUNER_MODE_STEREO:
703 sw_data |= TDA9873_TR_STEREO;
704 break;
705 case V4L2_TUNER_MODE_LANG1:
706 sw_data |= TDA9873_TR_DUALA;
707 break;
708 case V4L2_TUNER_MODE_LANG2:
709 sw_data |= TDA9873_TR_DUALB;
710 break;
711 default:
712 chip->mode = 0;
713 return;
714 }
715
716 chip_write(chip, TDA9873_SW, sw_data);
717 v4l2_dbg(1, debug, sd, "tda9873_setmode(): req. mode %d; chip_write: %d\n",
718 mode, sw_data);
719}
720
721static int tda9873_checkit(struct CHIPSTATE *chip)
722{
723 int rc;
724
725 if (-1 == (rc = chip_read2(chip,254)))
726 return 0;
727 return (rc & ~0x1f) == 0x80;
728}
729
730
731
732
733
734
735
736#define TDA9874A_AGCGR 0x00
737#define TDA9874A_GCONR 0x01
738#define TDA9874A_MSR 0x02
739#define TDA9874A_C1FRA 0x03
740#define TDA9874A_C1FRB 0x04
741#define TDA9874A_C1FRC 0x05
742#define TDA9874A_C2FRA 0x06
743#define TDA9874A_C2FRB 0x07
744#define TDA9874A_C2FRC 0x08
745#define TDA9874A_DCR 0x09
746#define TDA9874A_FMER 0x0a
747#define TDA9874A_FMMR 0x0b
748#define TDA9874A_C1OLAR 0x0c
749#define TDA9874A_C2OLAR 0x0d
750#define TDA9874A_NCONR 0x0e
751#define TDA9874A_NOLAR 0x0f
752#define TDA9874A_NLELR 0x10
753#define TDA9874A_NUELR 0x11
754#define TDA9874A_AMCONR 0x12
755#define TDA9874A_SDACOSR 0x13
756#define TDA9874A_AOSR 0x14
757#define TDA9874A_DAICONR 0x15
758#define TDA9874A_I2SOSR 0x16
759#define TDA9874A_I2SOLAR 0x17
760#define TDA9874A_MDACOSR 0x18
761#define TDA9874A_ESP 0xFF
762
763
764#define TDA9874A_DSR 0x00
765#define TDA9874A_NSR 0x01
766#define TDA9874A_NECR 0x02
767#define TDA9874A_DR1 0x03
768#define TDA9874A_DR2 0x04
769#define TDA9874A_LLRA 0x05
770#define TDA9874A_LLRB 0x06
771#define TDA9874A_SIFLR 0x07
772#define TDA9874A_TR2 252
773#define TDA9874A_TR1 253
774#define TDA9874A_DIC 254
775#define TDA9874A_SIC 255
776
777
778static int tda9874a_mode = 1;
779static int tda9874a_GCONR = 0xc0;
780static int tda9874a_NCONR = 0x01;
781static int tda9874a_ESP = 0x07;
782static int tda9874a_dic = -1;
783
784
785static unsigned int tda9874a_SIF = UNSET;
786static unsigned int tda9874a_AMSEL = UNSET;
787static unsigned int tda9874a_STD = UNSET;
788module_param(tda9874a_SIF, int, 0444);
789module_param(tda9874a_AMSEL, int, 0444);
790module_param(tda9874a_STD, int, 0444);
791
792
793
794
795
796
797
798
799
800static struct tda9874a_MODES {
801 char *name;
802 audiocmd cmd;
803} tda9874a_modelist[9] = {
804 { "A2, B/G",
805 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
806 { "A2, M (Korea)",
807 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
808 { "A2, D/K (1)",
809 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
810 { "A2, D/K (2)",
811 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
812 { "A2, D/K (3)",
813 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
814 { "NICAM, I",
815 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
816 { "NICAM, B/G",
817 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
818 { "NICAM, D/K",
819 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
820 { "NICAM, L",
821 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
822};
823
824static int tda9874a_setup(struct CHIPSTATE *chip)
825{
826 struct v4l2_subdev *sd = &chip->sd;
827
828 chip_write(chip, TDA9874A_AGCGR, 0x00);
829 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
830 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
831 if(tda9874a_dic == 0x11) {
832 chip_write(chip, TDA9874A_FMMR, 0x80);
833 } else {
834 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
835 chip_write(chip, TDA9874A_FMMR, 0x00);
836 }
837 chip_write(chip, TDA9874A_C1OLAR, 0x00);
838 chip_write(chip, TDA9874A_C2OLAR, 0x00);
839 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
840 chip_write(chip, TDA9874A_NOLAR, 0x00);
841
842
843
844 chip_write(chip, TDA9874A_NLELR, 0x14);
845 chip_write(chip, TDA9874A_NUELR, 0x50);
846
847 if(tda9874a_dic == 0x11) {
848 chip_write(chip, TDA9874A_AMCONR, 0xf9);
849 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
850 chip_write(chip, TDA9874A_AOSR, 0x80);
851 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
852 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
853 } else {
854 chip_write(chip, TDA9874A_AMCONR, 0xfb);
855 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
856 chip_write(chip, TDA9874A_AOSR, 0x00);
857 }
858 v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
859 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
860 return 1;
861}
862
863static int tda9874a_getmode(struct CHIPSTATE *chip)
864{
865 struct v4l2_subdev *sd = &chip->sd;
866 int dsr,nsr,mode;
867 int necr;
868
869 mode = V4L2_TUNER_MODE_MONO;
870
871 if(-1 == (dsr = chip_read2(chip,TDA9874A_DSR)))
872 return mode;
873 if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
874 return mode;
875 if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
876 return mode;
877
878
879 chip->shadow.bytes[MAXREGS-2] = dsr;
880 chip->shadow.bytes[MAXREGS-1] = nsr;
881
882 if(tda9874a_mode) {
883
884
885
886
887
888
889
890
891 if(nsr & 0x02)
892 mode |= V4L2_TUNER_MODE_STEREO;
893 if(nsr & 0x01)
894 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
895 } else {
896 if(dsr & 0x02)
897 mode |= V4L2_TUNER_MODE_STEREO;
898 if(dsr & 0x04)
899 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
900 }
901
902 v4l2_dbg(1, debug, sd, "tda9874a_getmode(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
903 dsr, nsr, necr, mode);
904 return mode;
905}
906
907static void tda9874a_setmode(struct CHIPSTATE *chip, int mode)
908{
909 struct v4l2_subdev *sd = &chip->sd;
910
911
912
913 if (tda9874a_mode) {
914 if(chip->shadow.bytes[MAXREGS-2] & 0x20)
915 tda9874a_NCONR &= 0xfe;
916 else
917 tda9874a_NCONR |= 0x01;
918 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
919 }
920
921
922
923
924
925
926
927 if(tda9874a_dic == 0x11) {
928 int aosr = 0x80;
929 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
930
931 switch(mode) {
932 case V4L2_TUNER_MODE_MONO:
933 case V4L2_TUNER_MODE_STEREO:
934 break;
935 case V4L2_TUNER_MODE_LANG1:
936 aosr = 0x80;
937 mdacosr = (tda9874a_mode) ? 0x82:0x80;
938 break;
939 case V4L2_TUNER_MODE_LANG2:
940 aosr = 0xa0;
941 mdacosr = (tda9874a_mode) ? 0x83:0x81;
942 break;
943 default:
944 chip->mode = 0;
945 return;
946 }
947 chip_write(chip, TDA9874A_AOSR, aosr);
948 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
949
950 v4l2_dbg(1, debug, sd, "tda9874a_setmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
951 mode, aosr, mdacosr);
952
953 } else {
954 int fmmr,aosr;
955
956 switch(mode) {
957 case V4L2_TUNER_MODE_MONO:
958 fmmr = 0x00;
959 aosr = 0x10;
960 break;
961 case V4L2_TUNER_MODE_STEREO:
962 if(tda9874a_mode) {
963 fmmr = 0x00;
964 aosr = 0x00;
965 } else {
966 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04;
967 aosr = 0x00;
968 }
969 break;
970 case V4L2_TUNER_MODE_LANG1:
971 fmmr = 0x02;
972 aosr = 0x10;
973 break;
974 case V4L2_TUNER_MODE_LANG2:
975 fmmr = 0x02;
976 aosr = 0x20;
977 break;
978 default:
979 chip->mode = 0;
980 return;
981 }
982 chip_write(chip, TDA9874A_FMMR, fmmr);
983 chip_write(chip, TDA9874A_AOSR, aosr);
984
985 v4l2_dbg(1, debug, sd, "tda9874a_setmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
986 mode, fmmr, aosr);
987 }
988}
989
990static int tda9874a_checkit(struct CHIPSTATE *chip)
991{
992 struct v4l2_subdev *sd = &chip->sd;
993 int dic,sic;
994
995 if(-1 == (dic = chip_read2(chip,TDA9874A_DIC)))
996 return 0;
997 if(-1 == (sic = chip_read2(chip,TDA9874A_SIC)))
998 return 0;
999
1000 v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1001
1002 if((dic == 0x11)||(dic == 0x07)) {
1003 v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
1004 tda9874a_dic = dic;
1005 return 1;
1006 }
1007 return 0;
1008}
1009
1010static int tda9874a_initialize(struct CHIPSTATE *chip)
1011{
1012 if (tda9874a_SIF > 2)
1013 tda9874a_SIF = 1;
1014 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1015 tda9874a_STD = 0;
1016 if(tda9874a_AMSEL > 1)
1017 tda9874a_AMSEL = 0;
1018
1019 if(tda9874a_SIF == 1)
1020 tda9874a_GCONR = 0xc0;
1021 else
1022 tda9874a_GCONR = 0xc1;
1023
1024 tda9874a_ESP = tda9874a_STD;
1025 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
1026
1027 if(tda9874a_AMSEL == 0)
1028 tda9874a_NCONR = 0x01;
1029 else
1030 tda9874a_NCONR = 0x05;
1031
1032 tda9874a_setup(chip);
1033 return 0;
1034}
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045#define TDA9875_MUT 0x12
1046#define TDA9875_CFG 0x01
1047#define TDA9875_DACOS 0x13
1048#define TDA9875_LOSR 0x16
1049
1050#define TDA9875_CH1V 0x0c
1051#define TDA9875_CH2V 0x0d
1052#define TDA9875_SC1 0x14
1053#define TDA9875_SC2 0x15
1054
1055#define TDA9875_ADCIS 0x17
1056#define TDA9875_AER 0x19
1057#define TDA9875_MCS 0x18
1058#define TDA9875_MVL 0x1a
1059#define TDA9875_MVR 0x1b
1060#define TDA9875_MBA 0x1d
1061#define TDA9875_MTR 0x1e
1062#define TDA9875_ACS 0x1f
1063#define TDA9875_AVL 0x20
1064#define TDA9875_AVR 0x21
1065#define TDA9875_ABA 0x22
1066#define TDA9875_ATR 0x23
1067
1068#define TDA9875_MSR 0x02
1069#define TDA9875_C1MSB 0x03
1070#define TDA9875_C1MIB 0x04
1071#define TDA9875_C1LSB 0x05
1072#define TDA9875_C2MSB 0x06
1073#define TDA9875_C2MIB 0x07
1074#define TDA9875_C2LSB 0x08
1075#define TDA9875_DCR 0x09
1076#define TDA9875_DEEM 0x0a
1077#define TDA9875_FMAT 0x0b
1078
1079
1080#define TDA9875_MUTE_ON 0xff
1081#define TDA9875_MUTE_OFF 0xcc
1082
1083static int tda9875_initialize(struct CHIPSTATE *chip)
1084{
1085 chip_write(chip, TDA9875_CFG, 0xd0);
1086 chip_write(chip, TDA9875_MSR, 0x03);
1087 chip_write(chip, TDA9875_C1MSB, 0x00);
1088 chip_write(chip, TDA9875_C1MIB, 0x00);
1089 chip_write(chip, TDA9875_C1LSB, 0x00);
1090 chip_write(chip, TDA9875_C2MSB, 0x00);
1091 chip_write(chip, TDA9875_C2MIB, 0x00);
1092 chip_write(chip, TDA9875_C2LSB, 0x00);
1093 chip_write(chip, TDA9875_DCR, 0x00);
1094 chip_write(chip, TDA9875_DEEM, 0x44);
1095 chip_write(chip, TDA9875_FMAT, 0x00);
1096 chip_write(chip, TDA9875_SC1, 0x00);
1097 chip_write(chip, TDA9875_SC2, 0x01);
1098
1099 chip_write(chip, TDA9875_CH1V, 0x10);
1100 chip_write(chip, TDA9875_CH2V, 0x10);
1101 chip_write(chip, TDA9875_DACOS, 0x02);
1102 chip_write(chip, TDA9875_ADCIS, 0x6f);
1103 chip_write(chip, TDA9875_LOSR, 0x00);
1104 chip_write(chip, TDA9875_AER, 0x00);
1105 chip_write(chip, TDA9875_MCS, 0x44);
1106 chip_write(chip, TDA9875_MVL, 0x03);
1107 chip_write(chip, TDA9875_MVR, 0x03);
1108 chip_write(chip, TDA9875_MBA, 0x00);
1109 chip_write(chip, TDA9875_MTR, 0x00);
1110 chip_write(chip, TDA9875_ACS, 0x44);
1111 chip_write(chip, TDA9875_AVL, 0x00);
1112 chip_write(chip, TDA9875_AVR, 0x00);
1113 chip_write(chip, TDA9875_ABA, 0x00);
1114 chip_write(chip, TDA9875_ATR, 0x00);
1115
1116 chip_write(chip, TDA9875_MUT, 0xcc);
1117 return 0;
1118}
1119
1120static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
1121static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
1122static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
1123
1124
1125
1126
1127
1128
1129
1130
1131static int tda9875_checkit(struct CHIPSTATE *chip)
1132{
1133 struct v4l2_subdev *sd = &chip->sd;
1134 int dic, rev;
1135
1136 dic = chip_read2(chip, 254);
1137 rev = chip_read2(chip, 255);
1138
1139 if (dic == 0 || dic == 2) {
1140 v4l2_info(sd, "found tda9875%s rev. %d.\n",
1141 dic == 0 ? "" : "A", rev);
1142 return 1;
1143 }
1144 return 0;
1145}
1146
1147
1148
1149
1150#define TEA6300_VL 0x00
1151#define TEA6300_VR 0x01
1152#define TEA6300_BA 0x02
1153#define TEA6300_TR 0x03
1154#define TEA6300_FA 0x04
1155#define TEA6300_S 0x05
1156
1157#define TEA6300_S_SA 0x01
1158#define TEA6300_S_SB 0x02
1159#define TEA6300_S_SC 0x04
1160#define TEA6300_S_GMU 0x80
1161
1162#define TEA6320_V 0x00
1163#define TEA6320_FFR 0x01
1164#define TEA6320_FFL 0x02
1165#define TEA6320_FRR 0x03
1166#define TEA6320_FRL 0x04
1167#define TEA6320_BA 0x05
1168#define TEA6320_TR 0x06
1169#define TEA6320_S 0x07
1170
1171#define TEA6320_S_SA 0x07
1172#define TEA6320_S_SB 0x06
1173#define TEA6320_S_SC 0x05
1174#define TEA6320_S_SD 0x04
1175#define TEA6320_S_GMU 0x80
1176
1177#define TEA6420_S_SA 0x00
1178#define TEA6420_S_SB 0x01
1179#define TEA6420_S_SC 0x02
1180#define TEA6420_S_SD 0x03
1181#define TEA6420_S_SE 0x04
1182#define TEA6420_S_GMU 0x05
1183
1184static int tea6300_shift10(int val) { return val >> 10; }
1185static int tea6300_shift12(int val) { return val >> 12; }
1186
1187
1188
1189static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1190static int tea6320_shift11(int val) { return val >> 11; }
1191static int tea6320_initialize(struct CHIPSTATE * chip)
1192{
1193 chip_write(chip, TEA6320_FFR, 0x3f);
1194 chip_write(chip, TEA6320_FFL, 0x3f);
1195 chip_write(chip, TEA6320_FRR, 0x3f);
1196 chip_write(chip, TEA6320_FRL, 0x3f);
1197
1198 return 0;
1199}
1200
1201
1202
1203
1204
1205#define TDA8425_VL 0x00
1206#define TDA8425_VR 0x01
1207#define TDA8425_BA 0x02
1208#define TDA8425_TR 0x03
1209#define TDA8425_S1 0x08
1210
1211#define TDA8425_S1_OFF 0xEE
1212#define TDA8425_S1_CH1 0xCE
1213#define TDA8425_S1_CH2 0xCF
1214#define TDA8425_S1_MU 0x20
1215#define TDA8425_S1_STEREO 0x18
1216#define TDA8425_S1_STEREO_SPATIAL 0x18
1217#define TDA8425_S1_STEREO_LINEAR 0x08
1218#define TDA8425_S1_STEREO_PSEUDO 0x10
1219#define TDA8425_S1_STEREO_MONO 0x00
1220#define TDA8425_S1_ML 0x06
1221#define TDA8425_S1_ML_SOUND_A 0x02
1222#define TDA8425_S1_ML_SOUND_B 0x04
1223#define TDA8425_S1_ML_STEREO 0x06
1224#define TDA8425_S1_IS 0x01
1225
1226
1227static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1228static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1229
1230static int tda8425_initialize(struct CHIPSTATE *chip)
1231{
1232 struct CHIPDESC *desc = chip->desc;
1233 struct i2c_client *c = v4l2_get_subdevdata(&chip->sd);
1234 int inputmap[4] = { TDA8425_S1_CH2, TDA8425_S1_CH1,
1235 TDA8425_S1_CH1, TDA8425_S1_OFF};
1236
1237 if (c->adapter->id == I2C_HW_B_RIVA)
1238 memcpy(desc->inputmap, inputmap, sizeof(inputmap));
1239 return 0;
1240}
1241
1242static void tda8425_setmode(struct CHIPSTATE *chip, int mode)
1243{
1244 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1245
1246 if (mode & V4L2_TUNER_MODE_LANG1) {
1247 s1 |= TDA8425_S1_ML_SOUND_A;
1248 s1 |= TDA8425_S1_STEREO_PSEUDO;
1249
1250 } else if (mode & V4L2_TUNER_MODE_LANG2) {
1251 s1 |= TDA8425_S1_ML_SOUND_B;
1252 s1 |= TDA8425_S1_STEREO_PSEUDO;
1253
1254 } else {
1255 s1 |= TDA8425_S1_ML_STEREO;
1256
1257 if (mode & V4L2_TUNER_MODE_MONO)
1258 s1 |= TDA8425_S1_STEREO_MONO;
1259 if (mode & V4L2_TUNER_MODE_STEREO)
1260 s1 |= TDA8425_S1_STEREO_SPATIAL;
1261 }
1262 chip_write(chip,TDA8425_S1,s1);
1263}
1264
1265
1266
1267
1268
1269
1270#define PIC16C54_REG_KEY_CODE 0x01
1271#define PIC16C54_REG_MISC 0x02
1272
1273
1274#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01
1275
1276#define PIC16C54_MISC_MTS_MAIN 0x02
1277#define PIC16C54_MISC_MTS_SAP 0x04
1278#define PIC16C54_MISC_MTS_BOTH 0x08
1279#define PIC16C54_MISC_SND_MUTE 0x10
1280#define PIC16C54_MISC_SND_NOTMUTE 0x20
1281#define PIC16C54_MISC_SWITCH_TUNER 0x40
1282#define PIC16C54_MISC_SWITCH_LINE 0x80
1283
1284
1285
1286
1287
1288#define TA8874Z_LED_STE 0x80
1289#define TA8874Z_LED_BIL 0x40
1290#define TA8874Z_LED_EXT 0x20
1291#define TA8874Z_MONO_SET 0x10
1292#define TA8874Z_MUTE 0x08
1293#define TA8874Z_F_MONO 0x04
1294#define TA8874Z_MODE_SUB 0x02
1295#define TA8874Z_MODE_MAIN 0x01
1296
1297
1298
1299#define TA8874Z_SEPARATION 0x3f
1300#define TA8874Z_SEPARATION_DEFAULT 0x10
1301
1302
1303#define TA8874Z_B1 0x80
1304#define TA8874Z_B0 0x40
1305#define TA8874Z_CHAG_FLAG 0x20
1306
1307
1308
1309
1310
1311
1312
1313static int ta8874z_getmode(struct CHIPSTATE *chip)
1314{
1315 int val, mode;
1316
1317 val = chip_read(chip);
1318 mode = V4L2_TUNER_MODE_MONO;
1319 if (val & TA8874Z_B1){
1320 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1321 }else if (!(val & TA8874Z_B0)){
1322 mode |= V4L2_TUNER_MODE_STEREO;
1323 }
1324
1325 return mode;
1326}
1327
1328static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1329static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1330static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1331static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1332
1333static void ta8874z_setmode(struct CHIPSTATE *chip, int mode)
1334{
1335 struct v4l2_subdev *sd = &chip->sd;
1336 int update = 1;
1337 audiocmd *t = NULL;
1338
1339 v4l2_dbg(1, debug, sd, "ta8874z_setmode(): mode: 0x%02x\n", mode);
1340
1341 switch(mode){
1342 case V4L2_TUNER_MODE_MONO:
1343 t = &ta8874z_mono;
1344 break;
1345 case V4L2_TUNER_MODE_STEREO:
1346 t = &ta8874z_stereo;
1347 break;
1348 case V4L2_TUNER_MODE_LANG1:
1349 t = &ta8874z_main;
1350 break;
1351 case V4L2_TUNER_MODE_LANG2:
1352 t = &ta8874z_sub;
1353 break;
1354 default:
1355 update = 0;
1356 }
1357
1358 if(update)
1359 chip_cmd(chip, "TA8874Z", t);
1360}
1361
1362static int ta8874z_checkit(struct CHIPSTATE *chip)
1363{
1364 int rc;
1365 rc = chip_read(chip);
1366 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1367}
1368
1369
1370
1371
1372
1373static int tda8425 = 1;
1374static int tda9840 = 1;
1375static int tda9850 = 1;
1376static int tda9855 = 1;
1377static int tda9873 = 1;
1378static int tda9874a = 1;
1379static int tda9875 = 1;
1380static int tea6300;
1381static int tea6320;
1382static int tea6420 = 1;
1383static int pic16c54 = 1;
1384static int ta8874z;
1385
1386module_param(tda8425, int, 0444);
1387module_param(tda9840, int, 0444);
1388module_param(tda9850, int, 0444);
1389module_param(tda9855, int, 0444);
1390module_param(tda9873, int, 0444);
1391module_param(tda9874a, int, 0444);
1392module_param(tda9875, int, 0444);
1393module_param(tea6300, int, 0444);
1394module_param(tea6320, int, 0444);
1395module_param(tea6420, int, 0444);
1396module_param(pic16c54, int, 0444);
1397module_param(ta8874z, int, 0444);
1398
1399static struct CHIPDESC chiplist[] = {
1400 {
1401 .name = "tda9840",
1402 .insmodopt = &tda9840,
1403 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1404 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1405 .registers = 5,
1406 .flags = CHIP_NEED_CHECKMODE,
1407
1408
1409 .checkit = tda9840_checkit,
1410 .getmode = tda9840_getmode,
1411 .setmode = tda9840_setmode,
1412
1413 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1414 } }
1415 },
1416 {
1417 .name = "tda9873h",
1418 .insmodopt = &tda9873,
1419 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1420 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1421 .registers = 3,
1422 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1423
1424
1425 .checkit = tda9873_checkit,
1426 .getmode = tda9873_getmode,
1427 .setmode = tda9873_setmode,
1428
1429 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1430 .inputreg = TDA9873_SW,
1431 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
1432 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1433 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1434
1435 },
1436 {
1437 .name = "tda9874h/a",
1438 .insmodopt = &tda9874a,
1439 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1440 .addr_hi = I2C_ADDR_TDA9874 >> 1,
1441 .flags = CHIP_NEED_CHECKMODE,
1442
1443
1444 .initialize = tda9874a_initialize,
1445 .checkit = tda9874a_checkit,
1446 .getmode = tda9874a_getmode,
1447 .setmode = tda9874a_setmode,
1448 },
1449 {
1450 .name = "tda9875",
1451 .insmodopt = &tda9875,
1452 .addr_lo = I2C_ADDR_TDA9875 >> 1,
1453 .addr_hi = I2C_ADDR_TDA9875 >> 1,
1454 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1455
1456
1457 .initialize = tda9875_initialize,
1458 .checkit = tda9875_checkit,
1459 .volfunc = tda9875_volume,
1460 .bassfunc = tda9875_bass,
1461 .treblefunc = tda9875_treble,
1462 .leftreg = TDA9875_MVL,
1463 .rightreg = TDA9875_MVR,
1464 .bassreg = TDA9875_MBA,
1465 .treblereg = TDA9875_MTR,
1466 .leftinit = 58880,
1467 .rightinit = 58880,
1468 },
1469 {
1470 .name = "tda9850",
1471 .insmodopt = &tda9850,
1472 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1473 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1474 .registers = 11,
1475
1476 .getmode = tda985x_getmode,
1477 .setmode = tda985x_setmode,
1478
1479 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1480 },
1481 {
1482 .name = "tda9855",
1483 .insmodopt = &tda9855,
1484 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1485 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1486 .registers = 11,
1487 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1488
1489 .leftreg = TDA9855_VL,
1490 .rightreg = TDA9855_VR,
1491 .bassreg = TDA9855_BA,
1492 .treblereg = TDA9855_TR,
1493
1494
1495 .volfunc = tda9855_volume,
1496 .bassfunc = tda9855_bass,
1497 .treblefunc = tda9855_treble,
1498 .getmode = tda985x_getmode,
1499 .setmode = tda985x_setmode,
1500
1501 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1502 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1503 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1504 0x07, 0x10, 0x10, 0x03 }}
1505 },
1506 {
1507 .name = "tea6300",
1508 .insmodopt = &tea6300,
1509 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1510 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1511 .registers = 6,
1512 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1513
1514 .leftreg = TEA6300_VR,
1515 .rightreg = TEA6300_VL,
1516 .bassreg = TEA6300_BA,
1517 .treblereg = TEA6300_TR,
1518
1519
1520 .volfunc = tea6300_shift10,
1521 .bassfunc = tea6300_shift12,
1522 .treblefunc = tea6300_shift12,
1523
1524 .inputreg = TEA6300_S,
1525 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1526 .inputmute = TEA6300_S_GMU,
1527 },
1528 {
1529 .name = "tea6320",
1530 .insmodopt = &tea6320,
1531 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1532 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1533 .registers = 8,
1534 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1535
1536 .leftreg = TEA6320_V,
1537 .rightreg = TEA6320_V,
1538 .bassreg = TEA6320_BA,
1539 .treblereg = TEA6320_TR,
1540
1541
1542 .initialize = tea6320_initialize,
1543 .volfunc = tea6320_volume,
1544 .bassfunc = tea6320_shift11,
1545 .treblefunc = tea6320_shift11,
1546
1547 .inputreg = TEA6320_S,
1548 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1549 .inputmute = TEA6300_S_GMU,
1550 },
1551 {
1552 .name = "tea6420",
1553 .insmodopt = &tea6420,
1554 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1555 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1556 .registers = 1,
1557 .flags = CHIP_HAS_INPUTSEL,
1558
1559 .inputreg = -1,
1560 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
1561 .inputmute = TEA6300_S_GMU,
1562 },
1563 {
1564 .name = "tda8425",
1565 .insmodopt = &tda8425,
1566 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1567 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1568 .registers = 9,
1569 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1570
1571 .leftreg = TDA8425_VL,
1572 .rightreg = TDA8425_VR,
1573 .bassreg = TDA8425_BA,
1574 .treblereg = TDA8425_TR,
1575
1576
1577 .initialize = tda8425_initialize,
1578 .volfunc = tda8425_shift10,
1579 .bassfunc = tda8425_shift12,
1580 .treblefunc = tda8425_shift12,
1581 .setmode = tda8425_setmode,
1582
1583 .inputreg = TDA8425_S1,
1584 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1585 .inputmute = TDA8425_S1_OFF,
1586
1587 },
1588 {
1589 .name = "pic16c54 (PV951)",
1590 .insmodopt = &pic16c54,
1591 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1592 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1593 .registers = 2,
1594 .flags = CHIP_HAS_INPUTSEL,
1595
1596 .inputreg = PIC16C54_REG_MISC,
1597 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1598 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1599 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1600 PIC16C54_MISC_SND_MUTE},
1601 .inputmute = PIC16C54_MISC_SND_MUTE,
1602 },
1603 {
1604 .name = "ta8874z",
1605 .checkit = ta8874z_checkit,
1606 .insmodopt = &ta8874z,
1607 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1608 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1609 .registers = 2,
1610 .flags = CHIP_NEED_CHECKMODE,
1611
1612
1613 .getmode = ta8874z_getmode,
1614 .setmode = ta8874z_setmode,
1615
1616 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1617 },
1618 { .name = NULL }
1619};
1620
1621
1622
1623
1624static int tvaudio_g_ctrl(struct v4l2_subdev *sd,
1625 struct v4l2_control *ctrl)
1626{
1627 struct CHIPSTATE *chip = to_state(sd);
1628 struct CHIPDESC *desc = chip->desc;
1629
1630 switch (ctrl->id) {
1631 case V4L2_CID_AUDIO_MUTE:
1632 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1633 break;
1634 ctrl->value=chip->muted;
1635 return 0;
1636 case V4L2_CID_AUDIO_VOLUME:
1637 if (!(desc->flags & CHIP_HAS_VOLUME))
1638 break;
1639 ctrl->value = max(chip->left,chip->right);
1640 return 0;
1641 case V4L2_CID_AUDIO_BALANCE:
1642 {
1643 int volume;
1644 if (!(desc->flags & CHIP_HAS_VOLUME))
1645 break;
1646 volume = max(chip->left,chip->right);
1647 if (volume)
1648 ctrl->value=(32768*min(chip->left,chip->right))/volume;
1649 else
1650 ctrl->value=32768;
1651 return 0;
1652 }
1653 case V4L2_CID_AUDIO_BASS:
1654 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1655 break;
1656 ctrl->value = chip->bass;
1657 return 0;
1658 case V4L2_CID_AUDIO_TREBLE:
1659 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1660 break;
1661 ctrl->value = chip->treble;
1662 return 0;
1663 }
1664 return -EINVAL;
1665}
1666
1667static int tvaudio_s_ctrl(struct v4l2_subdev *sd,
1668 struct v4l2_control *ctrl)
1669{
1670 struct CHIPSTATE *chip = to_state(sd);
1671 struct CHIPDESC *desc = chip->desc;
1672
1673 switch (ctrl->id) {
1674 case V4L2_CID_AUDIO_MUTE:
1675 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1676 break;
1677
1678 if (ctrl->value < 0 || ctrl->value >= 2)
1679 return -ERANGE;
1680 chip->muted = ctrl->value;
1681 if (chip->muted)
1682 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1683 else
1684 chip_write_masked(chip,desc->inputreg,
1685 desc->inputmap[chip->input],desc->inputmask);
1686 return 0;
1687 case V4L2_CID_AUDIO_VOLUME:
1688 {
1689 int volume,balance;
1690
1691 if (!(desc->flags & CHIP_HAS_VOLUME))
1692 break;
1693
1694 volume = max(chip->left,chip->right);
1695 if (volume)
1696 balance=(32768*min(chip->left,chip->right))/volume;
1697 else
1698 balance=32768;
1699
1700 volume=ctrl->value;
1701 chip->left = (min(65536 - balance,32768) * volume) / 32768;
1702 chip->right = (min(balance,volume *(__u16)32768)) / 32768;
1703
1704 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1705 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1706
1707 return 0;
1708 }
1709 case V4L2_CID_AUDIO_BALANCE:
1710 {
1711 int volume, balance;
1712 if (!(desc->flags & CHIP_HAS_VOLUME))
1713 break;
1714
1715 volume = max(chip->left,chip->right);
1716 balance = ctrl->value;
1717
1718 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1719 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1720
1721 return 0;
1722 }
1723 case V4L2_CID_AUDIO_BASS:
1724 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1725 break;
1726 chip->bass = ctrl->value;
1727 chip_write(chip,desc->bassreg,desc->bassfunc(chip->bass));
1728
1729 return 0;
1730 case V4L2_CID_AUDIO_TREBLE:
1731 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1732 break;
1733 chip->treble = ctrl->value;
1734 chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble));
1735
1736 return 0;
1737 }
1738 return -EINVAL;
1739}
1740
1741
1742
1743
1744
1745static int tvaudio_s_radio(struct v4l2_subdev *sd)
1746{
1747 struct CHIPSTATE *chip = to_state(sd);
1748
1749 chip->radio = 1;
1750 chip->watch_stereo = 0;
1751
1752 return 0;
1753}
1754
1755static int tvaudio_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
1756{
1757 struct CHIPSTATE *chip = to_state(sd);
1758 struct CHIPDESC *desc = chip->desc;
1759
1760 switch (qc->id) {
1761 case V4L2_CID_AUDIO_MUTE:
1762 if (desc->flags & CHIP_HAS_INPUTSEL)
1763 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1764 break;
1765 case V4L2_CID_AUDIO_VOLUME:
1766 if (desc->flags & CHIP_HAS_VOLUME)
1767 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 58880);
1768 break;
1769 case V4L2_CID_AUDIO_BALANCE:
1770 if (desc->flags & CHIP_HAS_VOLUME)
1771 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
1772 break;
1773 case V4L2_CID_AUDIO_BASS:
1774 case V4L2_CID_AUDIO_TREBLE:
1775 if (desc->flags & CHIP_HAS_BASSTREBLE)
1776 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
1777 break;
1778 default:
1779 break;
1780 }
1781 return -EINVAL;
1782}
1783
1784static int tvaudio_s_routing(struct v4l2_subdev *sd,
1785 u32 input, u32 output, u32 config)
1786{
1787 struct CHIPSTATE *chip = to_state(sd);
1788 struct CHIPDESC *desc = chip->desc;
1789
1790 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1791 return 0;
1792 if (input >= 4)
1793 return -EINVAL;
1794
1795 chip->input = input;
1796 if (chip->muted)
1797 return 0;
1798 chip_write_masked(chip, desc->inputreg,
1799 desc->inputmap[chip->input], desc->inputmask);
1800 return 0;
1801}
1802
1803static int tvaudio_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1804{
1805 struct CHIPSTATE *chip = to_state(sd);
1806 struct CHIPDESC *desc = chip->desc;
1807 int mode = 0;
1808
1809 if (!desc->setmode)
1810 return 0;
1811 if (chip->radio)
1812 return 0;
1813
1814 switch (vt->audmode) {
1815 case V4L2_TUNER_MODE_MONO:
1816 case V4L2_TUNER_MODE_STEREO:
1817 case V4L2_TUNER_MODE_LANG1:
1818 case V4L2_TUNER_MODE_LANG2:
1819 mode = vt->audmode;
1820 break;
1821 case V4L2_TUNER_MODE_LANG1_LANG2:
1822 mode = V4L2_TUNER_MODE_STEREO;
1823 break;
1824 default:
1825 return -EINVAL;
1826 }
1827 chip->audmode = vt->audmode;
1828
1829 if (mode) {
1830 chip->watch_stereo = 0;
1831
1832 chip->mode = mode;
1833 desc->setmode(chip, mode);
1834 }
1835 return 0;
1836}
1837
1838static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1839{
1840 struct CHIPSTATE *chip = to_state(sd);
1841 struct CHIPDESC *desc = chip->desc;
1842 int mode = V4L2_TUNER_MODE_MONO;
1843
1844 if (!desc->getmode)
1845 return 0;
1846 if (chip->radio)
1847 return 0;
1848
1849 vt->audmode = chip->audmode;
1850 vt->rxsubchans = 0;
1851 vt->capability = V4L2_TUNER_CAP_STEREO |
1852 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
1853
1854 mode = desc->getmode(chip);
1855
1856 if (mode & V4L2_TUNER_MODE_MONO)
1857 vt->rxsubchans |= V4L2_TUNER_SUB_MONO;
1858 if (mode & V4L2_TUNER_MODE_STEREO)
1859 vt->rxsubchans |= V4L2_TUNER_SUB_STEREO;
1860
1861
1862
1863 if (mode & V4L2_TUNER_MODE_LANG1)
1864 vt->rxsubchans = V4L2_TUNER_SUB_LANG1 |
1865 V4L2_TUNER_SUB_LANG2;
1866 return 0;
1867}
1868
1869static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1870{
1871 struct CHIPSTATE *chip = to_state(sd);
1872
1873 chip->radio = 0;
1874 return 0;
1875}
1876
1877static int tvaudio_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1878{
1879 struct CHIPSTATE *chip = to_state(sd);
1880 struct CHIPDESC *desc = chip->desc;
1881
1882 chip->mode = 0;
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892 if (chip->thread) {
1893 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
1894 if (chip->prevmode != V4L2_TUNER_MODE_MONO)
1895 chip->prevmode = -1;
1896 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1897 }
1898 return 0;
1899}
1900
1901static int tvaudio_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
1902{
1903 struct i2c_client *client = v4l2_get_subdevdata(sd);
1904
1905 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVAUDIO, 0);
1906}
1907
1908
1909
1910static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
1911 .g_chip_ident = tvaudio_g_chip_ident,
1912 .queryctrl = tvaudio_queryctrl,
1913 .g_ctrl = tvaudio_g_ctrl,
1914 .s_ctrl = tvaudio_s_ctrl,
1915 .s_std = tvaudio_s_std,
1916};
1917
1918static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
1919 .s_radio = tvaudio_s_radio,
1920 .s_frequency = tvaudio_s_frequency,
1921 .s_tuner = tvaudio_s_tuner,
1922 .s_tuner = tvaudio_g_tuner,
1923};
1924
1925static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
1926 .s_routing = tvaudio_s_routing,
1927};
1928
1929static const struct v4l2_subdev_ops tvaudio_ops = {
1930 .core = &tvaudio_core_ops,
1931 .tuner = &tvaudio_tuner_ops,
1932 .audio = &tvaudio_audio_ops,
1933};
1934
1935
1936
1937
1938
1939
1940static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
1941{
1942 struct CHIPSTATE *chip;
1943 struct CHIPDESC *desc;
1944 struct v4l2_subdev *sd;
1945
1946 if (debug) {
1947 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1948 printk(KERN_INFO "tvaudio: known chips: ");
1949 for (desc = chiplist; desc->name != NULL; desc++)
1950 printk("%s%s", (desc == chiplist) ? "" : ", ", desc->name);
1951 printk("\n");
1952 }
1953
1954 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1955 if (!chip)
1956 return -ENOMEM;
1957 sd = &chip->sd;
1958 v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
1959
1960
1961 v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
1962 for (desc = chiplist; desc->name != NULL; desc++) {
1963 if (0 == *(desc->insmodopt))
1964 continue;
1965 if (client->addr < desc->addr_lo ||
1966 client->addr > desc->addr_hi)
1967 continue;
1968 if (desc->checkit && !desc->checkit(chip))
1969 continue;
1970 break;
1971 }
1972 if (desc->name == NULL) {
1973 v4l2_dbg(1, debug, sd, "no matching chip description found\n");
1974 kfree(chip);
1975 return -EIO;
1976 }
1977 v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
1978 if (desc->flags) {
1979 v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
1980 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1981 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1982 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
1983 }
1984
1985
1986 if (!id)
1987 strlcpy(client->name, desc->name, I2C_NAME_SIZE);
1988 chip->desc = desc;
1989 chip->shadow.count = desc->registers+1;
1990 chip->prevmode = -1;
1991 chip->audmode = V4L2_TUNER_MODE_LANG1;
1992
1993
1994 if (desc->initialize != NULL)
1995 desc->initialize(chip);
1996 else
1997 chip_cmd(chip, "init", &desc->init);
1998
1999 if (desc->flags & CHIP_HAS_VOLUME) {
2000 if (!desc->volfunc) {
2001
2002
2003
2004 v4l2_info(sd, "volume callback undefined!\n");
2005 desc->flags &= ~CHIP_HAS_VOLUME;
2006 } else {
2007 chip->left = desc->leftinit ? desc->leftinit : 65535;
2008 chip->right = desc->rightinit ? desc->rightinit : 65535;
2009 chip_write(chip, desc->leftreg,
2010 desc->volfunc(chip->left));
2011 chip_write(chip, desc->rightreg,
2012 desc->volfunc(chip->right));
2013 }
2014 }
2015 if (desc->flags & CHIP_HAS_BASSTREBLE) {
2016 if (!desc->bassfunc || !desc->treblefunc) {
2017
2018
2019
2020 v4l2_info(sd, "bass/treble callbacks undefined!\n");
2021 desc->flags &= ~CHIP_HAS_BASSTREBLE;
2022 } else {
2023 chip->treble = desc->trebleinit ?
2024 desc->trebleinit : 32768;
2025 chip->bass = desc->bassinit ?
2026 desc->bassinit : 32768;
2027 chip_write(chip, desc->bassreg,
2028 desc->bassfunc(chip->bass));
2029 chip_write(chip, desc->treblereg,
2030 desc->treblefunc(chip->treble));
2031 }
2032 }
2033
2034 chip->thread = NULL;
2035 init_timer(&chip->wt);
2036 if (desc->flags & CHIP_NEED_CHECKMODE) {
2037 if (!desc->getmode || !desc->setmode) {
2038
2039
2040
2041 v4l2_info(sd, "set/get mode callbacks undefined!\n");
2042 return 0;
2043 }
2044
2045 chip->wt.function = chip_thread_wake;
2046 chip->wt.data = (unsigned long)chip;
2047 chip->thread = kthread_run(chip_thread, chip, client->name);
2048 if (IS_ERR(chip->thread)) {
2049 v4l2_warn(sd, "failed to create kthread\n");
2050 chip->thread = NULL;
2051 }
2052 }
2053 return 0;
2054}
2055
2056static int tvaudio_remove(struct i2c_client *client)
2057{
2058 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2059 struct CHIPSTATE *chip = to_state(sd);
2060
2061 del_timer_sync(&chip->wt);
2062 if (chip->thread) {
2063
2064 kthread_stop(chip->thread);
2065 chip->thread = NULL;
2066 }
2067
2068 v4l2_device_unregister_subdev(sd);
2069 kfree(chip);
2070 return 0;
2071}
2072
2073
2074
2075
2076static const struct i2c_device_id tvaudio_id[] = {
2077 { "tvaudio", 0 },
2078 { }
2079};
2080MODULE_DEVICE_TABLE(i2c, tvaudio_id);
2081
2082static struct v4l2_i2c_driver_data v4l2_i2c_data = {
2083 .name = "tvaudio",
2084 .probe = tvaudio_probe,
2085 .remove = tvaudio_remove,
2086 .id_table = tvaudio_id,
2087};
2088