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19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/gpio.h>
23#include <linux/io.h>
24#include <linux/spinlock.h>
25#include <linux/platform_device.h>
26
27#include <linux/mfd/asic3.h>
28#include <linux/mfd/core.h>
29#include <linux/mfd/ds1wm.h>
30#include <linux/mfd/tmio.h>
31
32enum {
33 ASIC3_CLOCK_SPI,
34 ASIC3_CLOCK_OWM,
35 ASIC3_CLOCK_PWM0,
36 ASIC3_CLOCK_PWM1,
37 ASIC3_CLOCK_LED0,
38 ASIC3_CLOCK_LED1,
39 ASIC3_CLOCK_LED2,
40 ASIC3_CLOCK_SD_HOST,
41 ASIC3_CLOCK_SD_BUS,
42 ASIC3_CLOCK_SMBUS,
43 ASIC3_CLOCK_EX0,
44 ASIC3_CLOCK_EX1,
45};
46
47struct asic3_clk {
48 int enabled;
49 unsigned int cdex;
50 unsigned long rate;
51};
52
53#define INIT_CDEX(_name, _rate) \
54 [ASIC3_CLOCK_##_name] = { \
55 .cdex = CLOCK_CDEX_##_name, \
56 .rate = _rate, \
57 }
58
59struct asic3_clk asic3_clk_init[] __initdata = {
60 INIT_CDEX(SPI, 0),
61 INIT_CDEX(OWM, 5000000),
62 INIT_CDEX(PWM0, 0),
63 INIT_CDEX(PWM1, 0),
64 INIT_CDEX(LED0, 0),
65 INIT_CDEX(LED1, 0),
66 INIT_CDEX(LED2, 0),
67 INIT_CDEX(SD_HOST, 24576000),
68 INIT_CDEX(SD_BUS, 12288000),
69 INIT_CDEX(SMBUS, 0),
70 INIT_CDEX(EX0, 32768),
71 INIT_CDEX(EX1, 24576000),
72};
73
74struct asic3 {
75 void __iomem *mapping;
76 unsigned int bus_shift;
77 unsigned int irq_nr;
78 unsigned int irq_base;
79 spinlock_t lock;
80 u16 irq_bothedge[4];
81 struct gpio_chip gpio;
82 struct device *dev;
83
84 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
85};
86
87static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
88
89static inline void asic3_write_register(struct asic3 *asic,
90 unsigned int reg, u32 value)
91{
92 iowrite16(value, asic->mapping +
93 (reg >> asic->bus_shift));
94}
95
96static inline u32 asic3_read_register(struct asic3 *asic,
97 unsigned int reg)
98{
99 return ioread16(asic->mapping +
100 (reg >> asic->bus_shift));
101}
102
103void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
104{
105 unsigned long flags;
106 u32 val;
107
108 spin_lock_irqsave(&asic->lock, flags);
109 val = asic3_read_register(asic, reg);
110 if (set)
111 val |= bits;
112 else
113 val &= ~bits;
114 asic3_write_register(asic, reg, val);
115 spin_unlock_irqrestore(&asic->lock, flags);
116}
117
118
119#define MAX_ASIC_ISR_LOOPS 20
120#define ASIC3_GPIO_BASE_INCR \
121 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
122
123static void asic3_irq_flip_edge(struct asic3 *asic,
124 u32 base, int bit)
125{
126 u16 edge;
127 unsigned long flags;
128
129 spin_lock_irqsave(&asic->lock, flags);
130 edge = asic3_read_register(asic,
131 base + ASIC3_GPIO_EDGE_TRIGGER);
132 edge ^= bit;
133 asic3_write_register(asic,
134 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
135 spin_unlock_irqrestore(&asic->lock, flags);
136}
137
138static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
139{
140 int iter, i;
141 unsigned long flags;
142 struct asic3 *asic;
143
144 desc->chip->ack(irq);
145
146 asic = desc->handler_data;
147
148 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
149 u32 status;
150 int bank;
151
152 spin_lock_irqsave(&asic->lock, flags);
153 status = asic3_read_register(asic,
154 ASIC3_OFFSET(INTR, P_INT_STAT));
155 spin_unlock_irqrestore(&asic->lock, flags);
156
157
158 if ((status & 0x3ff) == 0)
159 break;
160
161
162 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
163 if (status & (1 << bank)) {
164 unsigned long base, istat;
165
166 base = ASIC3_GPIO_A_BASE
167 + bank * ASIC3_GPIO_BASE_INCR;
168
169 spin_lock_irqsave(&asic->lock, flags);
170 istat = asic3_read_register(asic,
171 base +
172 ASIC3_GPIO_INT_STATUS);
173
174 asic3_write_register(asic,
175 base +
176 ASIC3_GPIO_INT_STATUS, 0);
177 spin_unlock_irqrestore(&asic->lock, flags);
178
179 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
180 int bit = (1 << i);
181 unsigned int irqnr;
182
183 if (!(istat & bit))
184 continue;
185
186 irqnr = asic->irq_base +
187 (ASIC3_GPIOS_PER_BANK * bank)
188 + i;
189 desc = irq_to_desc(irqnr);
190 desc->handle_irq(irqnr, desc);
191 if (asic->irq_bothedge[bank] & bit)
192 asic3_irq_flip_edge(asic, base,
193 bit);
194 }
195 }
196 }
197
198
199 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
200
201 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
202 desc = irq_to_desc(asic->irq_base + i);
203 desc->handle_irq(asic->irq_base + i,
204 desc);
205 }
206 }
207 }
208
209 if (iter >= MAX_ASIC_ISR_LOOPS)
210 dev_err(asic->dev, "interrupt processing overrun\n");
211}
212
213static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
214{
215 int n;
216
217 n = (irq - asic->irq_base) >> 4;
218
219 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
220}
221
222static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
223{
224 return (irq - asic->irq_base) & 0xf;
225}
226
227static void asic3_mask_gpio_irq(unsigned int irq)
228{
229 struct asic3 *asic = get_irq_chip_data(irq);
230 u32 val, bank, index;
231 unsigned long flags;
232
233 bank = asic3_irq_to_bank(asic, irq);
234 index = asic3_irq_to_index(asic, irq);
235
236 spin_lock_irqsave(&asic->lock, flags);
237 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
238 val |= 1 << index;
239 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
240 spin_unlock_irqrestore(&asic->lock, flags);
241}
242
243static void asic3_mask_irq(unsigned int irq)
244{
245 struct asic3 *asic = get_irq_chip_data(irq);
246 int regval;
247 unsigned long flags;
248
249 spin_lock_irqsave(&asic->lock, flags);
250 regval = asic3_read_register(asic,
251 ASIC3_INTR_BASE +
252 ASIC3_INTR_INT_MASK);
253
254 regval &= ~(ASIC3_INTMASK_MASK0 <<
255 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
256
257 asic3_write_register(asic,
258 ASIC3_INTR_BASE +
259 ASIC3_INTR_INT_MASK,
260 regval);
261 spin_unlock_irqrestore(&asic->lock, flags);
262}
263
264static void asic3_unmask_gpio_irq(unsigned int irq)
265{
266 struct asic3 *asic = get_irq_chip_data(irq);
267 u32 val, bank, index;
268 unsigned long flags;
269
270 bank = asic3_irq_to_bank(asic, irq);
271 index = asic3_irq_to_index(asic, irq);
272
273 spin_lock_irqsave(&asic->lock, flags);
274 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
275 val &= ~(1 << index);
276 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
277 spin_unlock_irqrestore(&asic->lock, flags);
278}
279
280static void asic3_unmask_irq(unsigned int irq)
281{
282 struct asic3 *asic = get_irq_chip_data(irq);
283 int regval;
284 unsigned long flags;
285
286 spin_lock_irqsave(&asic->lock, flags);
287 regval = asic3_read_register(asic,
288 ASIC3_INTR_BASE +
289 ASIC3_INTR_INT_MASK);
290
291 regval |= (ASIC3_INTMASK_MASK0 <<
292 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
293
294 asic3_write_register(asic,
295 ASIC3_INTR_BASE +
296 ASIC3_INTR_INT_MASK,
297 regval);
298 spin_unlock_irqrestore(&asic->lock, flags);
299}
300
301static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
302{
303 struct asic3 *asic = get_irq_chip_data(irq);
304 u32 bank, index;
305 u16 trigger, level, edge, bit;
306 unsigned long flags;
307
308 bank = asic3_irq_to_bank(asic, irq);
309 index = asic3_irq_to_index(asic, irq);
310 bit = 1<<index;
311
312 spin_lock_irqsave(&asic->lock, flags);
313 level = asic3_read_register(asic,
314 bank + ASIC3_GPIO_LEVEL_TRIGGER);
315 edge = asic3_read_register(asic,
316 bank + ASIC3_GPIO_EDGE_TRIGGER);
317 trigger = asic3_read_register(asic,
318 bank + ASIC3_GPIO_TRIGGER_TYPE);
319 asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
320
321 if (type == IRQ_TYPE_EDGE_RISING) {
322 trigger |= bit;
323 edge |= bit;
324 } else if (type == IRQ_TYPE_EDGE_FALLING) {
325 trigger |= bit;
326 edge &= ~bit;
327 } else if (type == IRQ_TYPE_EDGE_BOTH) {
328 trigger |= bit;
329 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
330 edge &= ~bit;
331 else
332 edge |= bit;
333 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
334 } else if (type == IRQ_TYPE_LEVEL_LOW) {
335 trigger &= ~bit;
336 level &= ~bit;
337 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
338 trigger &= ~bit;
339 level |= bit;
340 } else {
341
342
343
344
345
346 dev_notice(asic->dev, "irq type not changed\n");
347 }
348 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
349 level);
350 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
351 edge);
352 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
353 trigger);
354 spin_unlock_irqrestore(&asic->lock, flags);
355 return 0;
356}
357
358static struct irq_chip asic3_gpio_irq_chip = {
359 .name = "ASIC3-GPIO",
360 .ack = asic3_mask_gpio_irq,
361 .mask = asic3_mask_gpio_irq,
362 .unmask = asic3_unmask_gpio_irq,
363 .set_type = asic3_gpio_irq_type,
364};
365
366static struct irq_chip asic3_irq_chip = {
367 .name = "ASIC3",
368 .ack = asic3_mask_irq,
369 .mask = asic3_mask_irq,
370 .unmask = asic3_unmask_irq,
371};
372
373static int __init asic3_irq_probe(struct platform_device *pdev)
374{
375 struct asic3 *asic = platform_get_drvdata(pdev);
376 unsigned long clksel = 0;
377 unsigned int irq, irq_base;
378 int ret;
379
380 ret = platform_get_irq(pdev, 0);
381 if (ret < 0)
382 return ret;
383 asic->irq_nr = ret;
384
385
386 clksel |= CLOCK_SEL_CX;
387 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
388 clksel);
389
390 irq_base = asic->irq_base;
391
392 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
393 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
394 set_irq_chip(irq, &asic3_gpio_irq_chip);
395 else
396 set_irq_chip(irq, &asic3_irq_chip);
397
398 set_irq_chip_data(irq, asic);
399 set_irq_handler(irq, handle_level_irq);
400 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
401 }
402
403 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
404 ASIC3_INTMASK_GINTMASK);
405
406 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
407 set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
408 set_irq_data(asic->irq_nr, asic);
409
410 return 0;
411}
412
413static void asic3_irq_remove(struct platform_device *pdev)
414{
415 struct asic3 *asic = platform_get_drvdata(pdev);
416 unsigned int irq, irq_base;
417
418 irq_base = asic->irq_base;
419
420 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
421 set_irq_flags(irq, 0);
422 set_irq_handler(irq, NULL);
423 set_irq_chip(irq, NULL);
424 set_irq_chip_data(irq, NULL);
425 }
426 set_irq_chained_handler(asic->irq_nr, NULL);
427}
428
429
430static int asic3_gpio_direction(struct gpio_chip *chip,
431 unsigned offset, int out)
432{
433 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
434 unsigned int gpio_base;
435 unsigned long flags;
436 struct asic3 *asic;
437
438 asic = container_of(chip, struct asic3, gpio);
439 gpio_base = ASIC3_GPIO_TO_BASE(offset);
440
441 if (gpio_base > ASIC3_GPIO_D_BASE) {
442 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
443 gpio_base, offset);
444 return -EINVAL;
445 }
446
447 spin_lock_irqsave(&asic->lock, flags);
448
449 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
450
451
452 if (out)
453 out_reg |= mask;
454 else
455 out_reg &= ~mask;
456
457 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
458
459 spin_unlock_irqrestore(&asic->lock, flags);
460
461 return 0;
462
463}
464
465static int asic3_gpio_direction_input(struct gpio_chip *chip,
466 unsigned offset)
467{
468 return asic3_gpio_direction(chip, offset, 0);
469}
470
471static int asic3_gpio_direction_output(struct gpio_chip *chip,
472 unsigned offset, int value)
473{
474 return asic3_gpio_direction(chip, offset, 1);
475}
476
477static int asic3_gpio_get(struct gpio_chip *chip,
478 unsigned offset)
479{
480 unsigned int gpio_base;
481 u32 mask = ASIC3_GPIO_TO_MASK(offset);
482 struct asic3 *asic;
483
484 asic = container_of(chip, struct asic3, gpio);
485 gpio_base = ASIC3_GPIO_TO_BASE(offset);
486
487 if (gpio_base > ASIC3_GPIO_D_BASE) {
488 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
489 gpio_base, offset);
490 return -EINVAL;
491 }
492
493 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
494}
495
496static void asic3_gpio_set(struct gpio_chip *chip,
497 unsigned offset, int value)
498{
499 u32 mask, out_reg;
500 unsigned int gpio_base;
501 unsigned long flags;
502 struct asic3 *asic;
503
504 asic = container_of(chip, struct asic3, gpio);
505 gpio_base = ASIC3_GPIO_TO_BASE(offset);
506
507 if (gpio_base > ASIC3_GPIO_D_BASE) {
508 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
509 gpio_base, offset);
510 return;
511 }
512
513 mask = ASIC3_GPIO_TO_MASK(offset);
514
515 spin_lock_irqsave(&asic->lock, flags);
516
517 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
518
519 if (value)
520 out_reg |= mask;
521 else
522 out_reg &= ~mask;
523
524 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
525
526 spin_unlock_irqrestore(&asic->lock, flags);
527
528 return;
529}
530
531static __init int asic3_gpio_probe(struct platform_device *pdev,
532 u16 *gpio_config, int num)
533{
534 struct asic3 *asic = platform_get_drvdata(pdev);
535 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
536 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
537 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
538 int i;
539
540 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
541 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
542 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
543
544
545 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
546 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
547 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
548 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
549
550 for (i = 0; i < num; i++) {
551 u8 alt, pin, dir, init, bank_num, bit_num;
552 u16 config = gpio_config[i];
553
554 pin = ASIC3_CONFIG_GPIO_PIN(config);
555 alt = ASIC3_CONFIG_GPIO_ALT(config);
556 dir = ASIC3_CONFIG_GPIO_DIR(config);
557 init = ASIC3_CONFIG_GPIO_INIT(config);
558
559 bank_num = ASIC3_GPIO_TO_BANK(pin);
560 bit_num = ASIC3_GPIO_TO_BIT(pin);
561
562 alt_reg[bank_num] |= (alt << bit_num);
563 out_reg[bank_num] |= (init << bit_num);
564 dir_reg[bank_num] |= (dir << bit_num);
565 }
566
567 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
568 asic3_write_register(asic,
569 ASIC3_BANK_TO_BASE(i) +
570 ASIC3_GPIO_DIRECTION,
571 dir_reg[i]);
572 asic3_write_register(asic,
573 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
574 out_reg[i]);
575 asic3_write_register(asic,
576 ASIC3_BANK_TO_BASE(i) +
577 ASIC3_GPIO_ALT_FUNCTION,
578 alt_reg[i]);
579 }
580
581 return gpiochip_add(&asic->gpio);
582}
583
584static int asic3_gpio_remove(struct platform_device *pdev)
585{
586 struct asic3 *asic = platform_get_drvdata(pdev);
587
588 return gpiochip_remove(&asic->gpio);
589}
590
591static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
592{
593 unsigned long flags;
594 u32 cdex;
595
596 spin_lock_irqsave(&asic->lock, flags);
597 if (clk->enabled++ == 0) {
598 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
599 cdex |= clk->cdex;
600 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
601 }
602 spin_unlock_irqrestore(&asic->lock, flags);
603
604 return 0;
605}
606
607static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
608{
609 unsigned long flags;
610 u32 cdex;
611
612 WARN_ON(clk->enabled == 0);
613
614 spin_lock_irqsave(&asic->lock, flags);
615 if (--clk->enabled == 0) {
616 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
617 cdex &= ~clk->cdex;
618 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
619 }
620 spin_unlock_irqrestore(&asic->lock, flags);
621}
622
623
624static struct ds1wm_driver_data ds1wm_pdata = {
625 .active_high = 1,
626};
627
628static struct resource ds1wm_resources[] = {
629 {
630 .start = ASIC3_OWM_BASE,
631 .end = ASIC3_OWM_BASE + 0x13,
632 .flags = IORESOURCE_MEM,
633 },
634 {
635 .start = ASIC3_IRQ_OWM,
636 .start = ASIC3_IRQ_OWM,
637 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
638 },
639};
640
641static int ds1wm_enable(struct platform_device *pdev)
642{
643 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
644
645
646 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
647 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
648 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
649 msleep(1);
650
651
652 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
653 ASIC3_EXTCF_OWM_RESET, 1);
654 msleep(1);
655 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
656 ASIC3_EXTCF_OWM_RESET, 0);
657 msleep(1);
658 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
659 ASIC3_EXTCF_OWM_EN, 1);
660 msleep(1);
661
662 return 0;
663}
664
665static int ds1wm_disable(struct platform_device *pdev)
666{
667 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
668
669 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
670 ASIC3_EXTCF_OWM_EN, 0);
671
672 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
673 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
674 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
675
676 return 0;
677}
678
679static struct mfd_cell asic3_cell_ds1wm = {
680 .name = "ds1wm",
681 .enable = ds1wm_enable,
682 .disable = ds1wm_disable,
683 .driver_data = &ds1wm_pdata,
684 .num_resources = ARRAY_SIZE(ds1wm_resources),
685 .resources = ds1wm_resources,
686};
687
688static struct tmio_mmc_data asic3_mmc_data = {
689 .hclk = 24576000,
690};
691
692static struct resource asic3_mmc_resources[] = {
693 {
694 .start = ASIC3_SD_CTRL_BASE,
695 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
696 .flags = IORESOURCE_MEM,
697 },
698 {
699 .start = ASIC3_SD_CONFIG_BASE,
700 .end = ASIC3_SD_CONFIG_BASE + 0x1ff,
701 .flags = IORESOURCE_MEM,
702 },
703 {
704 .start = 0,
705 .end = 0,
706 .flags = IORESOURCE_IRQ,
707 },
708};
709
710static int asic3_mmc_enable(struct platform_device *pdev)
711{
712 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
713
714
715 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
716 ASIC3_SDHWCTRL_LEVCD, 1);
717 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
718 ASIC3_SDHWCTRL_LEVWP, 1);
719 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
720 ASIC3_SDHWCTRL_SUSPEND, 0);
721 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
722 ASIC3_SDHWCTRL_PCLR, 0);
723
724 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
725
726
727
728 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
729 msleep(1);
730
731
732 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
733 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
734
735 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
736 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
737 msleep(1);
738
739 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
740 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
741
742
743 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
744 ASIC3_SDHWCTRL_SDPWR, 1);
745
746 return 0;
747}
748
749static int asic3_mmc_disable(struct platform_device *pdev)
750{
751 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
752
753
754 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
755 ASIC3_SDHWCTRL_SUSPEND, 1);
756
757
758 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
759 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
760 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
761 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
762 return 0;
763}
764
765static struct mfd_cell asic3_cell_mmc = {
766 .name = "tmio-mmc",
767 .enable = asic3_mmc_enable,
768 .disable = asic3_mmc_disable,
769 .driver_data = &asic3_mmc_data,
770 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
771 .resources = asic3_mmc_resources,
772};
773
774static int __init asic3_mfd_probe(struct platform_device *pdev,
775 struct resource *mem)
776{
777 struct asic3 *asic = platform_get_drvdata(pdev);
778 struct resource *mem_sdio;
779 int irq, ret;
780
781 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
782 if (!mem_sdio)
783 dev_dbg(asic->dev, "no SDIO MEM resource\n");
784
785 irq = platform_get_irq(pdev, 1);
786 if (irq < 0)
787 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
788
789
790 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
791 ASIC3_EXTCF_OWM_SMB, 0);
792
793 ds1wm_resources[0].start >>= asic->bus_shift;
794 ds1wm_resources[0].end >>= asic->bus_shift;
795
796 asic3_cell_ds1wm.platform_data = &asic3_cell_ds1wm;
797 asic3_cell_ds1wm.data_size = sizeof(asic3_cell_ds1wm);
798
799
800 asic3_mmc_resources[0].start >>= asic->bus_shift;
801 asic3_mmc_resources[0].end >>= asic->bus_shift;
802 asic3_mmc_resources[1].start >>= asic->bus_shift;
803 asic3_mmc_resources[1].end >>= asic->bus_shift;
804
805 asic3_cell_mmc.platform_data = &asic3_cell_mmc;
806 asic3_cell_mmc.data_size = sizeof(asic3_cell_mmc);
807
808 ret = mfd_add_devices(&pdev->dev, pdev->id,
809 &asic3_cell_ds1wm, 1, mem, asic->irq_base);
810 if (ret < 0)
811 goto out;
812
813 if (mem_sdio && (irq >= 0))
814 ret = mfd_add_devices(&pdev->dev, pdev->id,
815 &asic3_cell_mmc, 1, mem_sdio, irq);
816
817 out:
818 return ret;
819}
820
821static void asic3_mfd_remove(struct platform_device *pdev)
822{
823 mfd_remove_devices(&pdev->dev);
824}
825
826
827static int __init asic3_probe(struct platform_device *pdev)
828{
829 struct asic3_platform_data *pdata = pdev->dev.platform_data;
830 struct asic3 *asic;
831 struct resource *mem;
832 unsigned long clksel;
833 int ret = 0;
834
835 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
836 if (asic == NULL) {
837 printk(KERN_ERR "kzalloc failed\n");
838 return -ENOMEM;
839 }
840
841 spin_lock_init(&asic->lock);
842 platform_set_drvdata(pdev, asic);
843 asic->dev = &pdev->dev;
844
845 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
846 if (!mem) {
847 ret = -ENOMEM;
848 dev_err(asic->dev, "no MEM resource\n");
849 goto out_free;
850 }
851
852 asic->mapping = ioremap(mem->start, resource_size(mem));
853 if (!asic->mapping) {
854 ret = -ENOMEM;
855 dev_err(asic->dev, "Couldn't ioremap\n");
856 goto out_free;
857 }
858
859 asic->irq_base = pdata->irq_base;
860
861
862 asic->bus_shift = 2 - (resource_size(mem) >> 12);
863
864 clksel = 0;
865 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
866
867 ret = asic3_irq_probe(pdev);
868 if (ret < 0) {
869 dev_err(asic->dev, "Couldn't probe IRQs\n");
870 goto out_unmap;
871 }
872
873 asic->gpio.base = pdata->gpio_base;
874 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
875 asic->gpio.get = asic3_gpio_get;
876 asic->gpio.set = asic3_gpio_set;
877 asic->gpio.direction_input = asic3_gpio_direction_input;
878 asic->gpio.direction_output = asic3_gpio_direction_output;
879
880 ret = asic3_gpio_probe(pdev,
881 pdata->gpio_config,
882 pdata->gpio_config_num);
883 if (ret < 0) {
884 dev_err(asic->dev, "GPIO probe failed\n");
885 goto out_irq;
886 }
887
888
889
890
891 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
892
893 asic3_mfd_probe(pdev, mem);
894
895 dev_info(asic->dev, "ASIC3 Core driver\n");
896
897 return 0;
898
899 out_irq:
900 asic3_irq_remove(pdev);
901
902 out_unmap:
903 iounmap(asic->mapping);
904
905 out_free:
906 kfree(asic);
907
908 return ret;
909}
910
911static int asic3_remove(struct platform_device *pdev)
912{
913 int ret;
914 struct asic3 *asic = platform_get_drvdata(pdev);
915
916 asic3_mfd_remove(pdev);
917
918 ret = asic3_gpio_remove(pdev);
919 if (ret < 0)
920 return ret;
921 asic3_irq_remove(pdev);
922
923 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
924
925 iounmap(asic->mapping);
926
927 kfree(asic);
928
929 return 0;
930}
931
932static void asic3_shutdown(struct platform_device *pdev)
933{
934}
935
936static struct platform_driver asic3_device_driver = {
937 .driver = {
938 .name = "asic3",
939 },
940 .remove = __devexit_p(asic3_remove),
941 .shutdown = asic3_shutdown,
942};
943
944static int __init asic3_init(void)
945{
946 int retval = 0;
947 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
948 return retval;
949}
950
951subsys_initcall(asic3_init);
952
