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27#include <linux/sched.h>
28#include <linux/delay.h>
29#include <linux/bio.h>
30#include <linux/dma-mapping.h>
31#include <linux/crc7.h>
32#include <linux/crc-itu-t.h>
33#include <linux/scatterlist.h>
34
35#include <linux/mmc/host.h>
36#include <linux/mmc/mmc.h>
37
38#include <linux/spi/spi.h>
39#include <linux/spi/mmc_spi.h>
40
41#include <asm/unaligned.h>
42
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76
77#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
78#define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
79#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
80#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
81
82
83
84
85#define SPI_TOKEN_SINGLE 0xfe
86#define SPI_TOKEN_MULTI_WRITE 0xfc
87#define SPI_TOKEN_STOP_TRAN 0xfd
88
89#define MMC_SPI_BLOCKSIZE 512
90
91
92
93
94
95
96
97
98#define r1b_timeout (HZ * 3)
99
100
101
102
103
104
105
106
107#define MMC_SPI_BLOCKSATONCE 128
108
109
110
111
112
113
114
115
116struct scratch {
117 u8 status[29];
118 u8 data_token;
119 __be16 crc_val;
120};
121
122struct mmc_spi_host {
123 struct mmc_host *mmc;
124 struct spi_device *spi;
125
126 unsigned char power_mode;
127 u16 powerup_msecs;
128
129 struct mmc_spi_platform_data *pdata;
130
131
132 struct spi_transfer token, t, crc, early_status;
133 struct spi_message m;
134
135
136 struct spi_transfer status;
137 struct spi_message readback;
138
139
140 struct device *dma_dev;
141
142
143 struct scratch *data;
144 dma_addr_t data_dma;
145
146
147
148
149
150 void *ones;
151 dma_addr_t ones_dma;
152};
153
154
155
156
157
158
159
160
161static inline int mmc_cs_off(struct mmc_spi_host *host)
162{
163
164 return spi_setup(host->spi);
165}
166
167static int
168mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)
169{
170 int status;
171
172 if (len > sizeof(*host->data)) {
173 WARN_ON(1);
174 return -EIO;
175 }
176
177 host->status.len = len;
178
179 if (host->dma_dev)
180 dma_sync_single_for_device(host->dma_dev,
181 host->data_dma, sizeof(*host->data),
182 DMA_FROM_DEVICE);
183
184 status = spi_sync(host->spi, &host->readback);
185
186 if (host->dma_dev)
187 dma_sync_single_for_cpu(host->dma_dev,
188 host->data_dma, sizeof(*host->data),
189 DMA_FROM_DEVICE);
190
191 return status;
192}
193
194static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,
195 unsigned n, u8 byte)
196{
197 u8 *cp = host->data->status;
198 unsigned long start = jiffies;
199
200 while (1) {
201 int status;
202 unsigned i;
203
204 status = mmc_spi_readbytes(host, n);
205 if (status < 0)
206 return status;
207
208 for (i = 0; i < n; i++) {
209 if (cp[i] != byte)
210 return cp[i];
211 }
212
213 if (time_is_before_jiffies(start + timeout))
214 break;
215
216
217
218
219
220 if (time_is_before_jiffies(start+1))
221 schedule();
222 }
223 return -ETIMEDOUT;
224}
225
226static inline int
227mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout)
228{
229 return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
230}
231
232static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout)
233{
234 return mmc_spi_skip(host, timeout, 1, 0xff);
235}
236
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238
239
240
241
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243
244
245
246
247static char *maptype(struct mmc_command *cmd)
248{
249 switch (mmc_spi_resp_type(cmd)) {
250 case MMC_RSP_SPI_R1: return "R1";
251 case MMC_RSP_SPI_R1B: return "R1B";
252 case MMC_RSP_SPI_R2: return "R2/R5";
253 case MMC_RSP_SPI_R3: return "R3/R4/R7";
254 default: return "?";
255 }
256}
257
258
259static int mmc_spi_response_get(struct mmc_spi_host *host,
260 struct mmc_command *cmd, int cs_on)
261{
262 u8 *cp = host->data->status;
263 u8 *end = cp + host->t.len;
264 int value = 0;
265 int bitshift;
266 u8 leftover = 0;
267 unsigned short rotator;
268 int i;
269 char tag[32];
270
271 snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s",
272 cmd->opcode, maptype(cmd));
273
274
275
276
277
278
279
280 cp += 8;
281 while (cp < end && *cp == 0xff)
282 cp++;
283
284
285 if (cp == end) {
286 cp = host->data->status;
287 end = cp+1;
288
289
290
291
292
293
294
295
296
297
298
299
300 for (i = 2; i < 16; i++) {
301 value = mmc_spi_readbytes(host, 1);
302 if (value < 0)
303 goto done;
304 if (*cp != 0xff)
305 goto checkstatus;
306 }
307 value = -ETIMEDOUT;
308 goto done;
309 }
310
311checkstatus:
312 bitshift = 0;
313 if (*cp & 0x80) {
314
315 rotator = *cp++ << 8;
316
317 if (cp == end) {
318 value = mmc_spi_readbytes(host, 1);
319 if (value < 0)
320 goto done;
321 cp = host->data->status;
322 end = cp+1;
323 }
324 rotator |= *cp++;
325 while (rotator & 0x8000) {
326 bitshift++;
327 rotator <<= 1;
328 }
329 cmd->resp[0] = rotator >> 8;
330 leftover = rotator;
331 } else {
332 cmd->resp[0] = *cp++;
333 }
334 cmd->error = 0;
335
336
337 if (cmd->resp[0] != 0) {
338 if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
339 & cmd->resp[0])
340 value = -EFAULT;
341 else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
342 value = -ENOSYS;
343 else if (R1_SPI_COM_CRC & cmd->resp[0])
344 value = -EILSEQ;
345 else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
346 & cmd->resp[0])
347 value = -EIO;
348
349 }
350
351 switch (mmc_spi_resp_type(cmd)) {
352
353
354
355
356 case MMC_RSP_SPI_R1B:
357
358 while (cp < end && *cp == 0)
359 cp++;
360 if (cp == end)
361 mmc_spi_wait_unbusy(host, r1b_timeout);
362 break;
363
364
365
366
367 case MMC_RSP_SPI_R2:
368
369 if (cp == end) {
370 value = mmc_spi_readbytes(host, 1);
371 if (value < 0)
372 goto done;
373 cp = host->data->status;
374 end = cp+1;
375 }
376 if (bitshift) {
377 rotator = leftover << 8;
378 rotator |= *cp << bitshift;
379 cmd->resp[0] |= (rotator & 0xFF00);
380 } else {
381 cmd->resp[0] |= *cp << 8;
382 }
383 break;
384
385
386 case MMC_RSP_SPI_R3:
387 rotator = leftover << 8;
388 cmd->resp[1] = 0;
389 for (i = 0; i < 4; i++) {
390 cmd->resp[1] <<= 8;
391
392 if (cp == end) {
393 value = mmc_spi_readbytes(host, 1);
394 if (value < 0)
395 goto done;
396 cp = host->data->status;
397 end = cp+1;
398 }
399 if (bitshift) {
400 rotator |= *cp++ << bitshift;
401 cmd->resp[1] |= (rotator >> 8);
402 rotator <<= 8;
403 } else {
404 cmd->resp[1] |= *cp++;
405 }
406 }
407 break;
408
409
410 case MMC_RSP_SPI_R1:
411 break;
412
413 default:
414 dev_dbg(&host->spi->dev, "bad response type %04x\n",
415 mmc_spi_resp_type(cmd));
416 if (value >= 0)
417 value = -EINVAL;
418 goto done;
419 }
420
421 if (value < 0)
422 dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n",
423 tag, cmd->resp[0], cmd->resp[1]);
424
425
426 if (value >= 0 && cs_on)
427 return value;
428done:
429 if (value < 0)
430 cmd->error = value;
431 mmc_cs_off(host);
432 return value;
433}
434
435
436
437
438
439
440
441static int
442mmc_spi_command_send(struct mmc_spi_host *host,
443 struct mmc_request *mrq,
444 struct mmc_command *cmd, int cs_on)
445{
446 struct scratch *data = host->data;
447 u8 *cp = data->status;
448 u32 arg = cmd->arg;
449 int status;
450 struct spi_transfer *t;
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465 memset(cp++, 0xff, sizeof(data->status));
466
467 *cp++ = 0x40 | cmd->opcode;
468 *cp++ = (u8)(arg >> 24);
469 *cp++ = (u8)(arg >> 16);
470 *cp++ = (u8)(arg >> 8);
471 *cp++ = (u8)arg;
472 *cp++ = (crc7(0, &data->status[1], 5) << 1) | 0x01;
473
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508
509 if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
510 cp += 2;
511
512 } else {
513 cp += 10;
514 if (cmd->flags & MMC_RSP_SPI_S2)
515 cp++;
516 else if (cmd->flags & MMC_RSP_SPI_B4)
517 cp += 4;
518 else if (cmd->flags & MMC_RSP_BUSY)
519 cp = data->status + sizeof(data->status);
520
521 }
522
523 dev_dbg(&host->spi->dev, " mmc_spi: CMD%d, resp %s\n",
524 cmd->opcode, maptype(cmd));
525
526
527 spi_message_init(&host->m);
528
529 t = &host->t;
530 memset(t, 0, sizeof(*t));
531 t->tx_buf = t->rx_buf = data->status;
532 t->tx_dma = t->rx_dma = host->data_dma;
533 t->len = cp - data->status;
534 t->cs_change = 1;
535 spi_message_add_tail(t, &host->m);
536
537 if (host->dma_dev) {
538 host->m.is_dma_mapped = 1;
539 dma_sync_single_for_device(host->dma_dev,
540 host->data_dma, sizeof(*host->data),
541 DMA_BIDIRECTIONAL);
542 }
543 status = spi_sync(host->spi, &host->m);
544
545 if (host->dma_dev)
546 dma_sync_single_for_cpu(host->dma_dev,
547 host->data_dma, sizeof(*host->data),
548 DMA_BIDIRECTIONAL);
549 if (status < 0) {
550 dev_dbg(&host->spi->dev, " ... write returned %d\n", status);
551 cmd->error = status;
552 return status;
553 }
554
555
556 return mmc_spi_response_get(host, cmd, cs_on);
557}
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569
570static void
571mmc_spi_setup_data_message(
572 struct mmc_spi_host *host,
573 int multiple,
574 enum dma_data_direction direction)
575{
576 struct spi_transfer *t;
577 struct scratch *scratch = host->data;
578 dma_addr_t dma = host->data_dma;
579
580 spi_message_init(&host->m);
581 if (dma)
582 host->m.is_dma_mapped = 1;
583
584
585
586
587 if (direction == DMA_TO_DEVICE) {
588 t = &host->token;
589 memset(t, 0, sizeof(*t));
590 t->len = 1;
591 if (multiple)
592 scratch->data_token = SPI_TOKEN_MULTI_WRITE;
593 else
594 scratch->data_token = SPI_TOKEN_SINGLE;
595 t->tx_buf = &scratch->data_token;
596 if (dma)
597 t->tx_dma = dma + offsetof(struct scratch, data_token);
598 spi_message_add_tail(t, &host->m);
599 }
600
601
602
603
604 t = &host->t;
605 memset(t, 0, sizeof(*t));
606 t->tx_buf = host->ones;
607 t->tx_dma = host->ones_dma;
608
609 spi_message_add_tail(t, &host->m);
610
611 t = &host->crc;
612 memset(t, 0, sizeof(*t));
613 t->len = 2;
614 if (direction == DMA_TO_DEVICE) {
615
616 t->tx_buf = &scratch->crc_val;
617 if (dma)
618 t->tx_dma = dma + offsetof(struct scratch, crc_val);
619 } else {
620 t->tx_buf = host->ones;
621 t->tx_dma = host->ones_dma;
622 t->rx_buf = &scratch->crc_val;
623 if (dma)
624 t->rx_dma = dma + offsetof(struct scratch, crc_val);
625 }
626 spi_message_add_tail(t, &host->m);
627
628
629
630
631
632
633
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635
636
637
638
639
640
641
642 if (multiple || direction == DMA_TO_DEVICE) {
643 t = &host->early_status;
644 memset(t, 0, sizeof(*t));
645 t->len = (direction == DMA_TO_DEVICE)
646 ? sizeof(scratch->status)
647 : 1;
648 t->tx_buf = host->ones;
649 t->tx_dma = host->ones_dma;
650 t->rx_buf = scratch->status;
651 if (dma)
652 t->rx_dma = dma + offsetof(struct scratch, status);
653 t->cs_change = 1;
654 spi_message_add_tail(t, &host->m);
655 }
656}
657
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664
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668
669
670static int
671mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,
672 unsigned long timeout)
673{
674 struct spi_device *spi = host->spi;
675 int status, i;
676 struct scratch *scratch = host->data;
677 u32 pattern;
678
679 if (host->mmc->use_spi_crc)
680 scratch->crc_val = cpu_to_be16(
681 crc_itu_t(0, t->tx_buf, t->len));
682 if (host->dma_dev)
683 dma_sync_single_for_device(host->dma_dev,
684 host->data_dma, sizeof(*scratch),
685 DMA_BIDIRECTIONAL);
686
687 status = spi_sync(spi, &host->m);
688
689 if (status != 0) {
690 dev_dbg(&spi->dev, "write error (%d)\n", status);
691 return status;
692 }
693
694 if (host->dma_dev)
695 dma_sync_single_for_cpu(host->dma_dev,
696 host->data_dma, sizeof(*scratch),
697 DMA_BIDIRECTIONAL);
698
699
700
701
702
703
704
705
706
707
708
709
710
711 pattern = scratch->status[0] << 24;
712 pattern |= scratch->status[1] << 16;
713 pattern |= scratch->status[2] << 8;
714 pattern |= scratch->status[3];
715
716
717 pattern |= 0xE0000000;
718
719
720 while (pattern & 0x80000000)
721 pattern <<= 1;
722
723 pattern >>= 27;
724
725 switch (pattern) {
726 case SPI_RESPONSE_ACCEPTED:
727 status = 0;
728 break;
729 case SPI_RESPONSE_CRC_ERR:
730
731 status = -EILSEQ;
732 break;
733 case SPI_RESPONSE_WRITE_ERR:
734
735
736
737 status = -EIO;
738 break;
739 default:
740 status = -EPROTO;
741 break;
742 }
743 if (status != 0) {
744 dev_dbg(&spi->dev, "write error %02x (%d)\n",
745 scratch->status[0], status);
746 return status;
747 }
748
749 t->tx_buf += t->len;
750 if (host->dma_dev)
751 t->tx_dma += t->len;
752
753
754
755
756 for (i = 4; i < sizeof(scratch->status); i++) {
757
758 if (scratch->status[i] & 0x01)
759 return 0;
760 }
761 return mmc_spi_wait_unbusy(host, timeout);
762}
763
764
765
766
767
768
769
770
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777
778
779
780static int
781mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,
782 unsigned long timeout)
783{
784 struct spi_device *spi = host->spi;
785 int status;
786 struct scratch *scratch = host->data;
787 unsigned int bitshift;
788 u8 leftover;
789
790
791
792
793 status = mmc_spi_readbytes(host, 1);
794 if (status < 0)
795 return status;
796 status = scratch->status[0];
797 if (status == 0xff || status == 0)
798 status = mmc_spi_readtoken(host, timeout);
799
800 if (status < 0) {
801 dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
802 return status;
803 }
804
805
806
807
808 bitshift = 7;
809 while (status & 0x80) {
810 status <<= 1;
811 bitshift--;
812 }
813 leftover = status << 1;
814
815 if (host->dma_dev) {
816 dma_sync_single_for_device(host->dma_dev,
817 host->data_dma, sizeof(*scratch),
818 DMA_BIDIRECTIONAL);
819 dma_sync_single_for_device(host->dma_dev,
820 t->rx_dma, t->len,
821 DMA_FROM_DEVICE);
822 }
823
824 status = spi_sync(spi, &host->m);
825
826 if (host->dma_dev) {
827 dma_sync_single_for_cpu(host->dma_dev,
828 host->data_dma, sizeof(*scratch),
829 DMA_BIDIRECTIONAL);
830 dma_sync_single_for_cpu(host->dma_dev,
831 t->rx_dma, t->len,
832 DMA_FROM_DEVICE);
833 }
834
835 if (bitshift) {
836
837
838
839 u8 *cp = t->rx_buf;
840 unsigned int len;
841 unsigned int bitright = 8 - bitshift;
842 u8 temp;
843 for (len = t->len; len; len--) {
844 temp = *cp;
845 *cp++ = leftover | (temp >> bitshift);
846 leftover = temp << bitright;
847 }
848 cp = (u8 *) &scratch->crc_val;
849 temp = *cp;
850 *cp++ = leftover | (temp >> bitshift);
851 leftover = temp << bitright;
852 temp = *cp;
853 *cp = leftover | (temp >> bitshift);
854 }
855
856 if (host->mmc->use_spi_crc) {
857 u16 crc = crc_itu_t(0, t->rx_buf, t->len);
858
859 be16_to_cpus(&scratch->crc_val);
860 if (scratch->crc_val != crc) {
861 dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, "
862 "computed=0x%04x len=%d\n",
863 scratch->crc_val, crc, t->len);
864 return -EILSEQ;
865 }
866 }
867
868 t->rx_buf += t->len;
869 if (host->dma_dev)
870 t->rx_dma += t->len;
871
872 return 0;
873}
874
875
876
877
878
879
880static void
881mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
882 struct mmc_data *data, u32 blk_size)
883{
884 struct spi_device *spi = host->spi;
885 struct device *dma_dev = host->dma_dev;
886 struct spi_transfer *t;
887 enum dma_data_direction direction;
888 struct scatterlist *sg;
889 unsigned n_sg;
890 int multiple = (data->blocks > 1);
891 u32 clock_rate;
892 unsigned long timeout;
893
894 if (data->flags & MMC_DATA_READ)
895 direction = DMA_FROM_DEVICE;
896 else
897 direction = DMA_TO_DEVICE;
898 mmc_spi_setup_data_message(host, multiple, direction);
899 t = &host->t;
900
901 if (t->speed_hz)
902 clock_rate = t->speed_hz;
903 else
904 clock_rate = spi->max_speed_hz;
905
906 timeout = data->timeout_ns +
907 data->timeout_clks * 1000000 / clock_rate;
908 timeout = usecs_to_jiffies((unsigned int)(timeout / 1000)) + 1;
909
910
911
912
913 for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) {
914 int status = 0;
915 dma_addr_t dma_addr = 0;
916 void *kmap_addr;
917 unsigned length = sg->length;
918 enum dma_data_direction dir = direction;
919
920
921
922
923 if (dma_dev) {
924
925 if ((sg->offset != 0 || length != PAGE_SIZE)
926 && dir == DMA_FROM_DEVICE)
927 dir = DMA_BIDIRECTIONAL;
928
929 dma_addr = dma_map_page(dma_dev, sg_page(sg), 0,
930 PAGE_SIZE, dir);
931 if (direction == DMA_TO_DEVICE)
932 t->tx_dma = dma_addr + sg->offset;
933 else
934 t->rx_dma = dma_addr + sg->offset;
935 }
936
937
938 kmap_addr = kmap(sg_page(sg));
939 if (direction == DMA_TO_DEVICE)
940 t->tx_buf = kmap_addr + sg->offset;
941 else
942 t->rx_buf = kmap_addr + sg->offset;
943
944
945 while (length) {
946 t->len = min(length, blk_size);
947
948 dev_dbg(&host->spi->dev,
949 " mmc_spi: %s block, %d bytes\n",
950 (direction == DMA_TO_DEVICE)
951 ? "write"
952 : "read",
953 t->len);
954
955 if (direction == DMA_TO_DEVICE)
956 status = mmc_spi_writeblock(host, t, timeout);
957 else
958 status = mmc_spi_readblock(host, t, timeout);
959 if (status < 0)
960 break;
961
962 data->bytes_xfered += t->len;
963 length -= t->len;
964
965 if (!multiple)
966 break;
967 }
968
969
970 if (direction == DMA_FROM_DEVICE)
971 flush_kernel_dcache_page(sg_page(sg));
972 kunmap(sg_page(sg));
973 if (dma_dev)
974 dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir);
975
976 if (status < 0) {
977 data->error = status;
978 dev_dbg(&spi->dev, "%s status %d\n",
979 (direction == DMA_TO_DEVICE)
980 ? "write" : "read",
981 status);
982 break;
983 }
984 }
985
986
987
988
989
990
991
992 if (direction == DMA_TO_DEVICE && multiple) {
993 struct scratch *scratch = host->data;
994 int tmp;
995 const unsigned statlen = sizeof(scratch->status);
996
997 dev_dbg(&spi->dev, " mmc_spi: STOP_TRAN\n");
998
999
1000
1001
1002
1003
1004 INIT_LIST_HEAD(&host->m.transfers);
1005 list_add(&host->early_status.transfer_list,
1006 &host->m.transfers);
1007
1008 memset(scratch->status, 0xff, statlen);
1009 scratch->status[0] = SPI_TOKEN_STOP_TRAN;
1010
1011 host->early_status.tx_buf = host->early_status.rx_buf;
1012 host->early_status.tx_dma = host->early_status.rx_dma;
1013 host->early_status.len = statlen;
1014
1015 if (host->dma_dev)
1016 dma_sync_single_for_device(host->dma_dev,
1017 host->data_dma, sizeof(*scratch),
1018 DMA_BIDIRECTIONAL);
1019
1020 tmp = spi_sync(spi, &host->m);
1021
1022 if (host->dma_dev)
1023 dma_sync_single_for_cpu(host->dma_dev,
1024 host->data_dma, sizeof(*scratch),
1025 DMA_BIDIRECTIONAL);
1026
1027 if (tmp < 0) {
1028 if (!data->error)
1029 data->error = tmp;
1030 return;
1031 }
1032
1033
1034
1035
1036
1037 for (tmp = 2; tmp < statlen; tmp++) {
1038 if (scratch->status[tmp] != 0)
1039 return;
1040 }
1041 tmp = mmc_spi_wait_unbusy(host, timeout);
1042 if (tmp < 0 && !data->error)
1043 data->error = tmp;
1044 }
1045}
1046
1047
1048
1049
1050
1051
1052
1053static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
1054{
1055 struct mmc_spi_host *host = mmc_priv(mmc);
1056 int status = -EINVAL;
1057
1058#ifdef DEBUG
1059
1060 {
1061 struct mmc_command *cmd;
1062 int invalid = 0;
1063
1064 cmd = mrq->cmd;
1065 if (!mmc_spi_resp_type(cmd)) {
1066 dev_dbg(&host->spi->dev, "bogus command\n");
1067 cmd->error = -EINVAL;
1068 invalid = 1;
1069 }
1070
1071 cmd = mrq->stop;
1072 if (cmd && !mmc_spi_resp_type(cmd)) {
1073 dev_dbg(&host->spi->dev, "bogus STOP command\n");
1074 cmd->error = -EINVAL;
1075 invalid = 1;
1076 }
1077
1078 if (invalid) {
1079 dump_stack();
1080 mmc_request_done(host->mmc, mrq);
1081 return;
1082 }
1083 }
1084#endif
1085
1086
1087 status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
1088 if (status == 0 && mrq->data) {
1089 mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
1090 if (mrq->stop)
1091 status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
1092 else
1093 mmc_cs_off(host);
1094 }
1095
1096 mmc_request_done(host->mmc, mrq);
1097}
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107static void mmc_spi_initsequence(struct mmc_spi_host *host)
1108{
1109
1110
1111
1112 mmc_spi_wait_unbusy(host, r1b_timeout);
1113 mmc_spi_readbytes(host, 10);
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129 host->spi->mode |= SPI_CS_HIGH;
1130 if (spi_setup(host->spi) != 0) {
1131
1132 dev_warn(&host->spi->dev,
1133 "can't change chip-select polarity\n");
1134 host->spi->mode &= ~SPI_CS_HIGH;
1135 } else {
1136 mmc_spi_readbytes(host, 18);
1137
1138 host->spi->mode &= ~SPI_CS_HIGH;
1139 if (spi_setup(host->spi) != 0) {
1140
1141 dev_err(&host->spi->dev,
1142 "can't restore chip-select polarity\n");
1143 }
1144 }
1145}
1146
1147static char *mmc_powerstring(u8 power_mode)
1148{
1149 switch (power_mode) {
1150 case MMC_POWER_OFF: return "off";
1151 case MMC_POWER_UP: return "up";
1152 case MMC_POWER_ON: return "on";
1153 }
1154 return "?";
1155}
1156
1157static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1158{
1159 struct mmc_spi_host *host = mmc_priv(mmc);
1160
1161 if (host->power_mode != ios->power_mode) {
1162 int canpower;
1163
1164 canpower = host->pdata && host->pdata->setpower;
1165
1166 dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n",
1167 mmc_powerstring(ios->power_mode),
1168 ios->vdd,
1169 canpower ? ", can switch" : "");
1170
1171
1172
1173
1174 if (canpower) {
1175 switch (ios->power_mode) {
1176 case MMC_POWER_OFF:
1177 case MMC_POWER_UP:
1178 host->pdata->setpower(&host->spi->dev,
1179 ios->vdd);
1180 if (ios->power_mode == MMC_POWER_UP)
1181 msleep(host->powerup_msecs);
1182 }
1183 }
1184
1185
1186 if (ios->power_mode == MMC_POWER_ON)
1187 mmc_spi_initsequence(host);
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198 if (canpower && ios->power_mode == MMC_POWER_OFF) {
1199 int mres;
1200 u8 nullbyte = 0;
1201
1202 host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
1203 mres = spi_setup(host->spi);
1204 if (mres < 0)
1205 dev_dbg(&host->spi->dev,
1206 "switch to SPI mode 0 failed\n");
1207
1208 if (spi_write(host->spi, &nullbyte, 1) < 0)
1209 dev_dbg(&host->spi->dev,
1210 "put spi signals to low failed\n");
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221 msleep(10);
1222 if (mres == 0) {
1223 host->spi->mode |= (SPI_CPOL|SPI_CPHA);
1224 mres = spi_setup(host->spi);
1225 if (mres < 0)
1226 dev_dbg(&host->spi->dev,
1227 "switch back to SPI mode 3"
1228 " failed\n");
1229 }
1230 }
1231
1232 host->power_mode = ios->power_mode;
1233 }
1234
1235 if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
1236 int status;
1237
1238 host->spi->max_speed_hz = ios->clock;
1239 status = spi_setup(host->spi);
1240 dev_dbg(&host->spi->dev,
1241 "mmc_spi: clock to %d Hz, %d\n",
1242 host->spi->max_speed_hz, status);
1243 }
1244}
1245
1246static int mmc_spi_get_ro(struct mmc_host *mmc)
1247{
1248 struct mmc_spi_host *host = mmc_priv(mmc);
1249
1250 if (host->pdata && host->pdata->get_ro)
1251 return !!host->pdata->get_ro(mmc->parent);
1252
1253
1254
1255
1256 return -ENOSYS;
1257}
1258
1259static int mmc_spi_get_cd(struct mmc_host *mmc)
1260{
1261 struct mmc_spi_host *host = mmc_priv(mmc);
1262
1263 if (host->pdata && host->pdata->get_cd)
1264 return !!host->pdata->get_cd(mmc->parent);
1265 return -ENOSYS;
1266}
1267
1268static const struct mmc_host_ops mmc_spi_ops = {
1269 .request = mmc_spi_request,
1270 .set_ios = mmc_spi_set_ios,
1271 .get_ro = mmc_spi_get_ro,
1272 .get_cd = mmc_spi_get_cd,
1273};
1274
1275
1276
1277
1278
1279
1280
1281
1282static irqreturn_t
1283mmc_spi_detect_irq(int irq, void *mmc)
1284{
1285 struct mmc_spi_host *host = mmc_priv(mmc);
1286 u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
1287
1288 mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
1289 return IRQ_HANDLED;
1290}
1291
1292struct count_children {
1293 unsigned n;
1294 struct bus_type *bus;
1295};
1296
1297static int maybe_count_child(struct device *dev, void *c)
1298{
1299 struct count_children *ccp = c;
1300
1301 if (dev->bus == ccp->bus) {
1302 if (ccp->n)
1303 return -EBUSY;
1304 ccp->n++;
1305 }
1306 return 0;
1307}
1308
1309static int mmc_spi_probe(struct spi_device *spi)
1310{
1311 void *ones;
1312 struct mmc_host *mmc;
1313 struct mmc_spi_host *host;
1314 int status;
1315
1316
1317
1318
1319 if (spi->master->flags & SPI_MASTER_HALF_DUPLEX)
1320 return -EINVAL;
1321
1322
1323
1324
1325
1326
1327
1328 if (spi->mode != SPI_MODE_3)
1329 spi->mode = SPI_MODE_0;
1330 spi->bits_per_word = 8;
1331
1332 status = spi_setup(spi);
1333 if (status < 0) {
1334 dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
1335 spi->mode, spi->max_speed_hz / 1000,
1336 status);
1337 return status;
1338 }
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351 if (spi->master->num_chipselect > 1) {
1352 struct count_children cc;
1353
1354 cc.n = 0;
1355 cc.bus = spi->dev.bus;
1356 status = device_for_each_child(spi->dev.parent, &cc,
1357 maybe_count_child);
1358 if (status < 0) {
1359 dev_err(&spi->dev, "can't share SPI bus\n");
1360 return status;
1361 }
1362
1363 dev_warn(&spi->dev, "ASSUMING SPI bus stays unshared!\n");
1364 }
1365
1366
1367
1368
1369
1370
1371
1372 status = -ENOMEM;
1373 ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
1374 if (!ones)
1375 goto nomem;
1376 memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
1377
1378 mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
1379 if (!mmc)
1380 goto nomem;
1381
1382 mmc->ops = &mmc_spi_ops;
1383 mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1384 mmc->max_hw_segs = MMC_SPI_BLOCKSATONCE;
1385 mmc->max_phys_segs = MMC_SPI_BLOCKSATONCE;
1386 mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
1387 mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
1388
1389 mmc->caps = MMC_CAP_SPI;
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399 mmc->f_min = 400000;
1400 mmc->f_max = spi->max_speed_hz;
1401
1402 host = mmc_priv(mmc);
1403 host->mmc = mmc;
1404 host->spi = spi;
1405
1406 host->ones = ones;
1407
1408
1409
1410
1411 host->pdata = mmc_spi_get_pdata(spi);
1412 if (host->pdata)
1413 mmc->ocr_avail = host->pdata->ocr_mask;
1414 if (!mmc->ocr_avail) {
1415 dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
1416 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1417 }
1418 if (host->pdata && host->pdata->setpower) {
1419 host->powerup_msecs = host->pdata->powerup_msecs;
1420 if (!host->powerup_msecs || host->powerup_msecs > 250)
1421 host->powerup_msecs = 250;
1422 }
1423
1424 dev_set_drvdata(&spi->dev, mmc);
1425
1426
1427 host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
1428 if (!host->data)
1429 goto fail_nobuf1;
1430
1431 if (spi->master->dev.parent->dma_mask) {
1432 struct device *dev = spi->master->dev.parent;
1433
1434 host->dma_dev = dev;
1435 host->ones_dma = dma_map_single(dev, ones,
1436 MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1437 host->data_dma = dma_map_single(dev, host->data,
1438 sizeof(*host->data), DMA_BIDIRECTIONAL);
1439
1440
1441
1442 dma_sync_single_for_cpu(host->dma_dev,
1443 host->data_dma, sizeof(*host->data),
1444 DMA_BIDIRECTIONAL);
1445 }
1446
1447
1448 spi_message_init(&host->readback);
1449 host->readback.is_dma_mapped = (host->dma_dev != NULL);
1450
1451 spi_message_add_tail(&host->status, &host->readback);
1452 host->status.tx_buf = host->ones;
1453 host->status.tx_dma = host->ones_dma;
1454 host->status.rx_buf = &host->data->status;
1455 host->status.rx_dma = host->data_dma + offsetof(struct scratch, status);
1456 host->status.cs_change = 1;
1457
1458
1459 if (host->pdata && host->pdata->init) {
1460 status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
1461 if (status != 0)
1462 goto fail_glue_init;
1463 }
1464
1465
1466 if (host->pdata)
1467 mmc->caps |= host->pdata->caps;
1468
1469 status = mmc_add_host(mmc);
1470 if (status != 0)
1471 goto fail_add_host;
1472
1473 dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n",
1474 dev_name(&mmc->class_dev),
1475 host->dma_dev ? "" : ", no DMA",
1476 (host->pdata && host->pdata->get_ro)
1477 ? "" : ", no WP",
1478 (host->pdata && host->pdata->setpower)
1479 ? "" : ", no poweroff",
1480 (mmc->caps & MMC_CAP_NEEDS_POLL)
1481 ? ", cd polling" : "");
1482 return 0;
1483
1484fail_add_host:
1485 mmc_remove_host (mmc);
1486fail_glue_init:
1487 if (host->dma_dev)
1488 dma_unmap_single(host->dma_dev, host->data_dma,
1489 sizeof(*host->data), DMA_BIDIRECTIONAL);
1490 kfree(host->data);
1491
1492fail_nobuf1:
1493 mmc_free_host(mmc);
1494 mmc_spi_put_pdata(spi);
1495 dev_set_drvdata(&spi->dev, NULL);
1496
1497nomem:
1498 kfree(ones);
1499 return status;
1500}
1501
1502
1503static int __devexit mmc_spi_remove(struct spi_device *spi)
1504{
1505 struct mmc_host *mmc = dev_get_drvdata(&spi->dev);
1506 struct mmc_spi_host *host;
1507
1508 if (mmc) {
1509 host = mmc_priv(mmc);
1510
1511
1512 if (host->pdata && host->pdata->exit)
1513 host->pdata->exit(&spi->dev, mmc);
1514
1515 mmc_remove_host(mmc);
1516
1517 if (host->dma_dev) {
1518 dma_unmap_single(host->dma_dev, host->ones_dma,
1519 MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1520 dma_unmap_single(host->dma_dev, host->data_dma,
1521 sizeof(*host->data), DMA_BIDIRECTIONAL);
1522 }
1523
1524 kfree(host->data);
1525 kfree(host->ones);
1526
1527 spi->max_speed_hz = mmc->f_max;
1528 mmc_free_host(mmc);
1529 mmc_spi_put_pdata(spi);
1530 dev_set_drvdata(&spi->dev, NULL);
1531 }
1532 return 0;
1533}
1534
1535
1536static struct spi_driver mmc_spi_driver = {
1537 .driver = {
1538 .name = "mmc_spi",
1539 .bus = &spi_bus_type,
1540 .owner = THIS_MODULE,
1541 },
1542 .probe = mmc_spi_probe,
1543 .remove = __devexit_p(mmc_spi_remove),
1544};
1545
1546
1547static int __init mmc_spi_init(void)
1548{
1549 return spi_register_driver(&mmc_spi_driver);
1550}
1551module_init(mmc_spi_init);
1552
1553
1554static void __exit mmc_spi_exit(void)
1555{
1556 spi_unregister_driver(&mmc_spi_driver);
1557}
1558module_exit(mmc_spi_exit);
1559
1560
1561MODULE_AUTHOR("Mike Lavender, David Brownell, "
1562 "Hans-Peter Nilsson, Jan Nikitenko");
1563MODULE_DESCRIPTION("SPI SD/MMC host driver");
1564MODULE_LICENSE("GPL");
1565MODULE_ALIAS("spi:mmc_spi");
1566