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32#define DRV_NAME "3c59x"
33
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36
37
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536
41
42
43
44
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48
49
50static int rx_copybreak = 1513;
51#endif
52
53static const int mtu = 1500;
54
55static int max_interrupt_work = 32;
56
57static int watchdog = 5000;
58
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61
62
63#define tx_interrupt_mitigation 1
64
65
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
92#include <linux/jiffies.h>
93#include <asm/irq.h>
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97
98
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110MODULE_LICENSE("GPL");
111
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118
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
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123
124
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
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210enum pci_flags_bit {
211 PCI_USES_MASTER=4,
212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10,
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_TX,
239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271
272
273
274
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex",
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex",
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
291
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO",
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302
303 {"3c900 Cyclone 10Mbps TPC",
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
315
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
320 {"3c905C Tornado",
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
324 {"3c980 Cyclone",
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
326
327 {"3c980C Python-T",
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus",
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado",
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
362 {"3c920 Tornado",
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
369 {"3c905B-T4",
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
373
374 {NULL,},
375};
376
377
378static struct pci_device_id vortex_pci_tbl[] = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,}
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
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435
436
437
438#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
439#define EL3_CMD 0x0e
440#define EL3_STATUS 0x0e
441
442
443
444
445
446
447
448enum vortex_cmd {
449 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
450 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
451 UpStall = 6<<11, UpUnstall = (6<<11)+1,
452 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
453 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
454 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
455 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
456 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
457 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
458 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
459
460
461enum RxFilter {
462 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
463
464
465enum vortex_status {
466 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
467 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
468 IntReq = 0x0040, StatsFull = 0x0080,
469 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
470 DMAInProgress = 1<<11,
471 CmdInProgress = 1<<12,
472};
473
474
475
476enum Window1 {
477 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
478 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
479 TxFree = 0x1C,
480};
481enum Window0 {
482 Wn0EepromCmd = 10,
483 Wn0EepromData = 12,
484 IntrStatus=0x0E,
485};
486enum Win0_EEPROM_bits {
487 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
488 EEPROM_EWENB = 0x30,
489 EEPROM_EWDIS = 0x00,
490};
491
492enum eeprom_offset {
493 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
494 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
495 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
496 DriverTune=13, Checksum=15};
497
498enum Window2 {
499 Wn2_ResetOptions=12,
500};
501enum Window3 {
502 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
503};
504
505#define BFEXT(value, offset, bitcount) \
506 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
507
508#define BFINS(lhs, rhs, offset, bitcount) \
509 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
510 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
511
512#define RAM_SIZE(v) BFEXT(v, 0, 3)
513#define RAM_WIDTH(v) BFEXT(v, 3, 1)
514#define RAM_SPEED(v) BFEXT(v, 4, 2)
515#define ROM_SIZE(v) BFEXT(v, 6, 2)
516#define RAM_SPLIT(v) BFEXT(v, 16, 2)
517#define XCVR(v) BFEXT(v, 20, 4)
518#define AUTOSELECT(v) BFEXT(v, 24, 1)
519
520enum Window4 {
521 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
522};
523enum Win4_Media_bits {
524 Media_SQE = 0x0008,
525 Media_10TP = 0x00C0,
526 Media_Lnk = 0x0080,
527 Media_LnkBeat = 0x0800,
528};
529enum Window7 {
530 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
531 Wn7_MasterStatus = 12,
532};
533
534enum MasterCtrl {
535 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
536 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
537};
538
539
540
541
542#define LAST_FRAG 0x80000000
543#define DN_COMPLETE 0x00010000
544struct boom_rx_desc {
545 __le32 next;
546 __le32 status;
547 __le32 addr;
548 __le32 length;
549};
550
551enum rx_desc_status {
552 RxDComplete=0x00008000, RxDError=0x4000,
553
554 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
555 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
556};
557
558#ifdef MAX_SKB_FRAGS
559#define DO_ZEROCOPY 1
560#else
561#define DO_ZEROCOPY 0
562#endif
563
564struct boom_tx_desc {
565 __le32 next;
566 __le32 status;
567#if DO_ZEROCOPY
568 struct {
569 __le32 addr;
570 __le32 length;
571 } frag[1+MAX_SKB_FRAGS];
572#else
573 __le32 addr;
574 __le32 length;
575#endif
576};
577
578
579enum tx_desc_status {
580 CRCDisable=0x2000, TxDComplete=0x8000,
581 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
582 TxIntrUploaded=0x80000000,
583};
584
585
586enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
587
588struct vortex_extra_stats {
589 unsigned long tx_deferred;
590 unsigned long tx_max_collisions;
591 unsigned long tx_multiple_collisions;
592 unsigned long tx_single_collisions;
593 unsigned long rx_bad_ssd;
594};
595
596struct vortex_private {
597
598 struct boom_rx_desc* rx_ring;
599 struct boom_tx_desc* tx_ring;
600 dma_addr_t rx_ring_dma;
601 dma_addr_t tx_ring_dma;
602
603 struct sk_buff* rx_skbuff[RX_RING_SIZE];
604 struct sk_buff* tx_skbuff[TX_RING_SIZE];
605 unsigned int cur_rx, cur_tx;
606 unsigned int dirty_rx, dirty_tx;
607 struct vortex_extra_stats xstats;
608 struct sk_buff *tx_skb;
609 dma_addr_t tx_skb_dma;
610
611
612 struct device *gendev;
613 void __iomem *ioaddr;
614 void __iomem *cb_fn_base;
615
616
617 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
618 int card_idx;
619
620
621 struct timer_list timer;
622 struct timer_list rx_oom_timer;
623 int options;
624 unsigned int media_override:4,
625 default_media:4,
626 full_duplex:1, autoselect:1,
627 bus_master:1,
628 full_bus_master_tx:1, full_bus_master_rx:2,
629 flow_ctrl:1,
630 partner_flow_ctrl:1,
631 has_nway:1,
632 enable_wol:1,
633 pm_state_valid:1,
634 open:1,
635 medialock:1,
636 must_free_region:1,
637 large_frames:1;
638 int drv_flags;
639 u16 status_enable;
640 u16 intr_enable;
641 u16 available_media;
642 u16 capabilities, info1, info2;
643 u16 advertising;
644 unsigned char phys[2];
645 u16 deferred;
646
647 u16 io_size;
648 spinlock_t lock;
649 struct mii_if_info mii;
650};
651
652#ifdef CONFIG_PCI
653#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
654#else
655#define DEVICE_PCI(dev) NULL
656#endif
657
658#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
659
660#ifdef CONFIG_EISA
661#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
662#else
663#define DEVICE_EISA(dev) NULL
664#endif
665
666#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
667
668
669
670
671enum xcvr_types {
672 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
673 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
674};
675
676static const struct media_table {
677 char *name;
678 unsigned int media_bits:16,
679 mask:8,
680 next:8;
681 int wait;
682} media_tbl[] = {
683 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
684 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
685 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
686 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
687 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
688 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
689 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
691 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
692 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
693 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
694};
695
696static struct {
697 const char str[ETH_GSTRING_LEN];
698} ethtool_stats_keys[] = {
699 { "tx_deferred" },
700 { "tx_max_collisions" },
701 { "tx_multiple_collisions" },
702 { "tx_single_collisions" },
703 { "rx_bad_ssd" },
704};
705
706
707#define VORTEX_NUM_STATS 5
708
709static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
710 int chip_idx, int card_idx);
711static int vortex_up(struct net_device *dev);
712static void vortex_down(struct net_device *dev, int final);
713static int vortex_open(struct net_device *dev);
714static void mdio_sync(void __iomem *ioaddr, int bits);
715static int mdio_read(struct net_device *dev, int phy_id, int location);
716static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
717static void vortex_timer(unsigned long arg);
718static void rx_oom_timer(unsigned long arg);
719static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
720 struct net_device *dev);
721static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
722 struct net_device *dev);
723static int vortex_rx(struct net_device *dev);
724static int boomerang_rx(struct net_device *dev);
725static irqreturn_t vortex_interrupt(int irq, void *dev_id);
726static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
727static int vortex_close(struct net_device *dev);
728static void dump_tx_ring(struct net_device *dev);
729static void update_stats(void __iomem *ioaddr, struct net_device *dev);
730static struct net_device_stats *vortex_get_stats(struct net_device *dev);
731static void set_rx_mode(struct net_device *dev);
732#ifdef CONFIG_PCI
733static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
734#endif
735static void vortex_tx_timeout(struct net_device *dev);
736static void acpi_set_WOL(struct net_device *dev);
737static const struct ethtool_ops vortex_ethtool_ops;
738static void set_8021q_mode(struct net_device *dev, int enable);
739
740
741
742#define MAX_UNITS 8
743static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
744static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
745static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
746static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
747static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
748static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
749static int global_options = -1;
750static int global_full_duplex = -1;
751static int global_enable_wol = -1;
752static int global_use_mmio = -1;
753
754
755static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
756static struct net_device *compaq_net_device;
757
758static int vortex_cards_found;
759
760module_param(debug, int, 0);
761module_param(global_options, int, 0);
762module_param_array(options, int, NULL, 0);
763module_param(global_full_duplex, int, 0);
764module_param_array(full_duplex, int, NULL, 0);
765module_param_array(hw_checksums, int, NULL, 0);
766module_param_array(flow_ctrl, int, NULL, 0);
767module_param(global_enable_wol, int, 0);
768module_param_array(enable_wol, int, NULL, 0);
769module_param(rx_copybreak, int, 0);
770module_param(max_interrupt_work, int, 0);
771module_param(compaq_ioaddr, int, 0);
772module_param(compaq_irq, int, 0);
773module_param(compaq_device_id, int, 0);
774module_param(watchdog, int, 0);
775module_param(global_use_mmio, int, 0);
776module_param_array(use_mmio, int, NULL, 0);
777MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
778MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
779MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
780MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
781MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
782MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
783MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
784MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
785MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
786MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
787MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
788MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
789MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
790MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
791MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
792MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
793MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
794
795#ifdef CONFIG_NET_POLL_CONTROLLER
796static void poll_vortex(struct net_device *dev)
797{
798 struct vortex_private *vp = netdev_priv(dev);
799 unsigned long flags;
800 local_irq_save(flags);
801 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
802 local_irq_restore(flags);
803}
804#endif
805
806#ifdef CONFIG_PM
807
808static int vortex_suspend(struct device *dev)
809{
810 struct pci_dev *pdev = to_pci_dev(dev);
811 struct net_device *ndev = pci_get_drvdata(pdev);
812
813 if (!ndev || !netif_running(ndev))
814 return 0;
815
816 netif_device_detach(ndev);
817 vortex_down(ndev, 1);
818
819 return 0;
820}
821
822static int vortex_resume(struct device *dev)
823{
824 struct pci_dev *pdev = to_pci_dev(dev);
825 struct net_device *ndev = pci_get_drvdata(pdev);
826 int err;
827
828 if (!ndev || !netif_running(ndev))
829 return 0;
830
831 err = vortex_up(ndev);
832 if (err)
833 return err;
834
835 netif_device_attach(ndev);
836
837 return 0;
838}
839
840static struct dev_pm_ops vortex_pm_ops = {
841 .suspend = vortex_suspend,
842 .resume = vortex_resume,
843 .freeze = vortex_suspend,
844 .thaw = vortex_resume,
845 .poweroff = vortex_suspend,
846 .restore = vortex_resume,
847};
848
849#define VORTEX_PM_OPS (&vortex_pm_ops)
850
851#else
852
853#define VORTEX_PM_OPS NULL
854
855#endif
856
857#ifdef CONFIG_EISA
858static struct eisa_device_id vortex_eisa_ids[] = {
859 { "TCM5920", CH_3C592 },
860 { "TCM5970", CH_3C597 },
861 { "" }
862};
863MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
864
865static int __init vortex_eisa_probe(struct device *device)
866{
867 void __iomem *ioaddr;
868 struct eisa_device *edev;
869
870 edev = to_eisa_device(device);
871
872 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
873 return -EBUSY;
874
875 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
876
877 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
878 edev->id.driver_data, vortex_cards_found)) {
879 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
880 return -ENODEV;
881 }
882
883 vortex_cards_found++;
884
885 return 0;
886}
887
888static int __devexit vortex_eisa_remove(struct device *device)
889{
890 struct eisa_device *edev;
891 struct net_device *dev;
892 struct vortex_private *vp;
893 void __iomem *ioaddr;
894
895 edev = to_eisa_device(device);
896 dev = eisa_get_drvdata(edev);
897
898 if (!dev) {
899 pr_err("vortex_eisa_remove called for Compaq device!\n");
900 BUG();
901 }
902
903 vp = netdev_priv(dev);
904 ioaddr = vp->ioaddr;
905
906 unregister_netdev(dev);
907 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
908 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
909
910 free_netdev(dev);
911 return 0;
912}
913
914static struct eisa_driver vortex_eisa_driver = {
915 .id_table = vortex_eisa_ids,
916 .driver = {
917 .name = "3c59x",
918 .probe = vortex_eisa_probe,
919 .remove = __devexit_p(vortex_eisa_remove)
920 }
921};
922
923#endif
924
925
926static int __init vortex_eisa_init(void)
927{
928 int eisa_found = 0;
929 int orig_cards_found = vortex_cards_found;
930
931#ifdef CONFIG_EISA
932 int err;
933
934 err = eisa_driver_register (&vortex_eisa_driver);
935 if (!err) {
936
937
938
939
940
941
942
943 eisa_found = 1;
944 }
945#endif
946
947
948 if (compaq_ioaddr) {
949 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
950 compaq_irq, compaq_device_id, vortex_cards_found++);
951 }
952
953 return vortex_cards_found - orig_cards_found + eisa_found;
954}
955
956
957static int __devinit vortex_init_one(struct pci_dev *pdev,
958 const struct pci_device_id *ent)
959{
960 int rc, unit, pci_bar;
961 struct vortex_chip_info *vci;
962 void __iomem *ioaddr;
963
964
965 rc = pci_enable_device(pdev);
966 if (rc < 0)
967 goto out;
968
969 unit = vortex_cards_found;
970
971 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
972
973 vci = &vortex_info_tbl[ent->driver_data];
974 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
975 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
976 pci_bar = use_mmio[unit] ? 1 : 0;
977 else
978 pci_bar = global_use_mmio ? 1 : 0;
979
980 ioaddr = pci_iomap(pdev, pci_bar, 0);
981 if (!ioaddr)
982 ioaddr = pci_iomap(pdev, 0, 0);
983
984 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
985 ent->driver_data, unit);
986 if (rc < 0) {
987 pci_disable_device(pdev);
988 goto out;
989 }
990
991 vortex_cards_found++;
992
993out:
994 return rc;
995}
996
997static const struct net_device_ops boomrang_netdev_ops = {
998 .ndo_open = vortex_open,
999 .ndo_stop = vortex_close,
1000 .ndo_start_xmit = boomerang_start_xmit,
1001 .ndo_tx_timeout = vortex_tx_timeout,
1002 .ndo_get_stats = vortex_get_stats,
1003#ifdef CONFIG_PCI
1004 .ndo_do_ioctl = vortex_ioctl,
1005#endif
1006 .ndo_set_multicast_list = set_rx_mode,
1007 .ndo_change_mtu = eth_change_mtu,
1008 .ndo_set_mac_address = eth_mac_addr,
1009 .ndo_validate_addr = eth_validate_addr,
1010#ifdef CONFIG_NET_POLL_CONTROLLER
1011 .ndo_poll_controller = poll_vortex,
1012#endif
1013};
1014
1015static const struct net_device_ops vortex_netdev_ops = {
1016 .ndo_open = vortex_open,
1017 .ndo_stop = vortex_close,
1018 .ndo_start_xmit = vortex_start_xmit,
1019 .ndo_tx_timeout = vortex_tx_timeout,
1020 .ndo_get_stats = vortex_get_stats,
1021#ifdef CONFIG_PCI
1022 .ndo_do_ioctl = vortex_ioctl,
1023#endif
1024 .ndo_set_multicast_list = set_rx_mode,
1025 .ndo_change_mtu = eth_change_mtu,
1026 .ndo_set_mac_address = eth_mac_addr,
1027 .ndo_validate_addr = eth_validate_addr,
1028#ifdef CONFIG_NET_POLL_CONTROLLER
1029 .ndo_poll_controller = poll_vortex,
1030#endif
1031};
1032
1033
1034
1035
1036
1037
1038
1039static int __devinit vortex_probe1(struct device *gendev,
1040 void __iomem *ioaddr, int irq,
1041 int chip_idx, int card_idx)
1042{
1043 struct vortex_private *vp;
1044 int option;
1045 unsigned int eeprom[0x40], checksum = 0;
1046 int i, step;
1047 struct net_device *dev;
1048 static int printed_version;
1049 int retval, print_info;
1050 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1051 const char *print_name = "3c59x";
1052 struct pci_dev *pdev = NULL;
1053 struct eisa_device *edev = NULL;
1054
1055 if (!printed_version) {
1056 pr_info("%s", version);
1057 printed_version = 1;
1058 }
1059
1060 if (gendev) {
1061 if ((pdev = DEVICE_PCI(gendev))) {
1062 print_name = pci_name(pdev);
1063 }
1064
1065 if ((edev = DEVICE_EISA(gendev))) {
1066 print_name = dev_name(&edev->dev);
1067 }
1068 }
1069
1070 dev = alloc_etherdev(sizeof(*vp));
1071 retval = -ENOMEM;
1072 if (!dev) {
1073 pr_err(PFX "unable to allocate etherdev, aborting\n");
1074 goto out;
1075 }
1076 SET_NETDEV_DEV(dev, gendev);
1077 vp = netdev_priv(dev);
1078
1079 option = global_options;
1080
1081
1082 if (dev->mem_start) {
1083
1084
1085
1086
1087 option = dev->mem_start;
1088 }
1089 else if (card_idx < MAX_UNITS) {
1090 if (options[card_idx] >= 0)
1091 option = options[card_idx];
1092 }
1093
1094 if (option > 0) {
1095 if (option & 0x8000)
1096 vortex_debug = 7;
1097 if (option & 0x4000)
1098 vortex_debug = 2;
1099 if (option & 0x0400)
1100 vp->enable_wol = 1;
1101 }
1102
1103 print_info = (vortex_debug > 1);
1104 if (print_info)
1105 pr_info("See Documentation/networking/vortex.txt\n");
1106
1107 pr_info("%s: 3Com %s %s at %p.\n",
1108 print_name,
1109 pdev ? "PCI" : "EISA",
1110 vci->name,
1111 ioaddr);
1112
1113 dev->base_addr = (unsigned long)ioaddr;
1114 dev->irq = irq;
1115 dev->mtu = mtu;
1116 vp->ioaddr = ioaddr;
1117 vp->large_frames = mtu > 1500;
1118 vp->drv_flags = vci->drv_flags;
1119 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1120 vp->io_size = vci->io_size;
1121 vp->card_idx = card_idx;
1122
1123
1124 if (gendev == NULL) {
1125 compaq_net_device = dev;
1126 }
1127
1128
1129 if (pdev) {
1130
1131
1132 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1133 vp->must_free_region = 1;
1134
1135
1136 if (vci->flags & PCI_USES_MASTER)
1137 pci_set_master(pdev);
1138
1139 if (vci->drv_flags & IS_VORTEX) {
1140 u8 pci_latency;
1141 u8 new_latency = 248;
1142
1143
1144
1145
1146
1147 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1148 if (pci_latency < new_latency) {
1149 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1150 print_name, pci_latency, new_latency);
1151 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1152 }
1153 }
1154 }
1155
1156 spin_lock_init(&vp->lock);
1157 vp->gendev = gendev;
1158 vp->mii.dev = dev;
1159 vp->mii.mdio_read = mdio_read;
1160 vp->mii.mdio_write = mdio_write;
1161 vp->mii.phy_id_mask = 0x1f;
1162 vp->mii.reg_num_mask = 0x1f;
1163
1164
1165 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1166 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1167 &vp->rx_ring_dma);
1168 retval = -ENOMEM;
1169 if (!vp->rx_ring)
1170 goto free_region;
1171
1172 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1173 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1174
1175
1176
1177 if (pdev)
1178 pci_set_drvdata(pdev, dev);
1179 if (edev)
1180 eisa_set_drvdata(edev, dev);
1181
1182 vp->media_override = 7;
1183 if (option >= 0) {
1184 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1185 if (vp->media_override != 7)
1186 vp->medialock = 1;
1187 vp->full_duplex = (option & 0x200) ? 1 : 0;
1188 vp->bus_master = (option & 16) ? 1 : 0;
1189 }
1190
1191 if (global_full_duplex > 0)
1192 vp->full_duplex = 1;
1193 if (global_enable_wol > 0)
1194 vp->enable_wol = 1;
1195
1196 if (card_idx < MAX_UNITS) {
1197 if (full_duplex[card_idx] > 0)
1198 vp->full_duplex = 1;
1199 if (flow_ctrl[card_idx] > 0)
1200 vp->flow_ctrl = 1;
1201 if (enable_wol[card_idx] > 0)
1202 vp->enable_wol = 1;
1203 }
1204
1205 vp->mii.force_media = vp->full_duplex;
1206 vp->options = option;
1207
1208 EL3WINDOW(0);
1209 {
1210 int base;
1211
1212 if (vci->drv_flags & EEPROM_8BIT)
1213 base = 0x230;
1214 else if (vci->drv_flags & EEPROM_OFFSET)
1215 base = EEPROM_Read + 0x30;
1216 else
1217 base = EEPROM_Read;
1218
1219 for (i = 0; i < 0x40; i++) {
1220 int timer;
1221 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1222
1223 for (timer = 10; timer >= 0; timer--) {
1224 udelay(162);
1225 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1226 break;
1227 }
1228 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1229 }
1230 }
1231 for (i = 0; i < 0x18; i++)
1232 checksum ^= eeprom[i];
1233 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1234 if (checksum != 0x00) {
1235 while (i < 0x21)
1236 checksum ^= eeprom[i++];
1237 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1238 }
1239 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1240 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1241 for (i = 0; i < 3; i++)
1242 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1243 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1244 if (print_info)
1245 pr_cont(" %pM", dev->dev_addr);
1246
1247
1248 if (!is_valid_ether_addr(dev->dev_addr)) {
1249 retval = -EINVAL;
1250 pr_err("*** EEPROM MAC address is invalid.\n");
1251 goto free_ring;
1252 }
1253 EL3WINDOW(2);
1254 for (i = 0; i < 6; i++)
1255 iowrite8(dev->dev_addr[i], ioaddr + i);
1256
1257 if (print_info)
1258 pr_cont(", IRQ %d\n", dev->irq);
1259
1260 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1261 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1262 dev->irq);
1263
1264 EL3WINDOW(4);
1265 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1266 if (print_info) {
1267 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1268 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1269 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1270 }
1271
1272
1273 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1274 unsigned short n;
1275
1276 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1277 if (!vp->cb_fn_base) {
1278 retval = -ENOMEM;
1279 goto free_ring;
1280 }
1281
1282 if (print_info) {
1283 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1284 print_name,
1285 (unsigned long long)pci_resource_start(pdev, 2),
1286 vp->cb_fn_base);
1287 }
1288 EL3WINDOW(2);
1289
1290 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1291 if (vp->drv_flags & INVERT_LED_PWR)
1292 n |= 0x10;
1293 if (vp->drv_flags & INVERT_MII_PWR)
1294 n |= 0x4000;
1295 iowrite16(n, ioaddr + Wn2_ResetOptions);
1296 if (vp->drv_flags & WNO_XCVR_PWR) {
1297 EL3WINDOW(0);
1298 iowrite16(0x0800, ioaddr);
1299 }
1300 }
1301
1302
1303 vp->info1 = eeprom[13];
1304 vp->info2 = eeprom[15];
1305 vp->capabilities = eeprom[16];
1306
1307 if (vp->info1 & 0x8000) {
1308 vp->full_duplex = 1;
1309 if (print_info)
1310 pr_info("Full duplex capable\n");
1311 }
1312
1313 {
1314 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1315 unsigned int config;
1316 EL3WINDOW(3);
1317 vp->available_media = ioread16(ioaddr + Wn3_Options);
1318 if ((vp->available_media & 0xff) == 0)
1319 vp->available_media = 0x40;
1320 config = ioread32(ioaddr + Wn3_Config);
1321 if (print_info) {
1322 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1323 config, ioread16(ioaddr + Wn3_Options));
1324 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1325 8 << RAM_SIZE(config),
1326 RAM_WIDTH(config) ? "word" : "byte",
1327 ram_split[RAM_SPLIT(config)],
1328 AUTOSELECT(config) ? "autoselect/" : "",
1329 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1330 media_tbl[XCVR(config)].name);
1331 }
1332 vp->default_media = XCVR(config);
1333 if (vp->default_media == XCVR_NWAY)
1334 vp->has_nway = 1;
1335 vp->autoselect = AUTOSELECT(config);
1336 }
1337
1338 if (vp->media_override != 7) {
1339 pr_info("%s: Media override to transceiver type %d (%s).\n",
1340 print_name, vp->media_override,
1341 media_tbl[vp->media_override].name);
1342 dev->if_port = vp->media_override;
1343 } else
1344 dev->if_port = vp->default_media;
1345
1346 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1347 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1348 int phy, phy_idx = 0;
1349 EL3WINDOW(4);
1350 mii_preamble_required++;
1351 if (vp->drv_flags & EXTRA_PREAMBLE)
1352 mii_preamble_required++;
1353 mdio_sync(ioaddr, 32);
1354 mdio_read(dev, 24, MII_BMSR);
1355 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1356 int mii_status, phyx;
1357
1358
1359
1360
1361
1362 if (phy == 0)
1363 phyx = 24;
1364 else if (phy <= 24)
1365 phyx = phy - 1;
1366 else
1367 phyx = phy;
1368 mii_status = mdio_read(dev, phyx, MII_BMSR);
1369 if (mii_status && mii_status != 0xffff) {
1370 vp->phys[phy_idx++] = phyx;
1371 if (print_info) {
1372 pr_info(" MII transceiver found at address %d, status %4x.\n",
1373 phyx, mii_status);
1374 }
1375 if ((mii_status & 0x0040) == 0)
1376 mii_preamble_required++;
1377 }
1378 }
1379 mii_preamble_required--;
1380 if (phy_idx == 0) {
1381 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1382 vp->phys[0] = 24;
1383 } else {
1384 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1385 if (vp->full_duplex) {
1386
1387 vp->advertising &= ~0x02A0;
1388 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1389 }
1390 }
1391 vp->mii.phy_id = vp->phys[0];
1392 }
1393
1394 if (vp->capabilities & CapBusMaster) {
1395 vp->full_bus_master_tx = 1;
1396 if (print_info) {
1397 pr_info(" Enabling bus-master transmits and %s receives.\n",
1398 (vp->info2 & 1) ? "early" : "whole-frame" );
1399 }
1400 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1401 vp->bus_master = 0;
1402 }
1403
1404
1405 if (vp->full_bus_master_tx) {
1406 dev->netdev_ops = &boomrang_netdev_ops;
1407
1408 if (card_idx < MAX_UNITS &&
1409 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1410 hw_checksums[card_idx] == 1)) {
1411 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1412 }
1413 } else
1414 dev->netdev_ops = &vortex_netdev_ops;
1415
1416 if (print_info) {
1417 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1418 print_name,
1419 (dev->features & NETIF_F_SG) ? "en":"dis",
1420 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1421 }
1422
1423 dev->ethtool_ops = &vortex_ethtool_ops;
1424 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1425
1426 if (pdev) {
1427 vp->pm_state_valid = 1;
1428 pci_save_state(VORTEX_PCI(vp));
1429 acpi_set_WOL(dev);
1430 }
1431 retval = register_netdev(dev);
1432 if (retval == 0)
1433 return 0;
1434
1435free_ring:
1436 pci_free_consistent(pdev,
1437 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1438 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1439 vp->rx_ring,
1440 vp->rx_ring_dma);
1441free_region:
1442 if (vp->must_free_region)
1443 release_region(dev->base_addr, vci->io_size);
1444 free_netdev(dev);
1445 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1446out:
1447 return retval;
1448}
1449
1450static void
1451issue_and_wait(struct net_device *dev, int cmd)
1452{
1453 struct vortex_private *vp = netdev_priv(dev);
1454 void __iomem *ioaddr = vp->ioaddr;
1455 int i;
1456
1457 iowrite16(cmd, ioaddr + EL3_CMD);
1458 for (i = 0; i < 2000; i++) {
1459 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1460 return;
1461 }
1462
1463
1464 for (i = 0; i < 100000; i++) {
1465 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1466 if (vortex_debug > 1)
1467 pr_info("%s: command 0x%04x took %d usecs\n",
1468 dev->name, cmd, i * 10);
1469 return;
1470 }
1471 udelay(10);
1472 }
1473 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1474 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1475}
1476
1477static void
1478vortex_set_duplex(struct net_device *dev)
1479{
1480 struct vortex_private *vp = netdev_priv(dev);
1481 void __iomem *ioaddr = vp->ioaddr;
1482
1483 pr_info("%s: setting %s-duplex.\n",
1484 dev->name, (vp->full_duplex) ? "full" : "half");
1485
1486 EL3WINDOW(3);
1487
1488 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1489 (vp->large_frames ? 0x40 : 0) |
1490 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1491 0x100 : 0),
1492 ioaddr + Wn3_MAC_Ctrl);
1493}
1494
1495static void vortex_check_media(struct net_device *dev, unsigned int init)
1496{
1497 struct vortex_private *vp = netdev_priv(dev);
1498 unsigned int ok_to_print = 0;
1499
1500 if (vortex_debug > 3)
1501 ok_to_print = 1;
1502
1503 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1504 vp->full_duplex = vp->mii.full_duplex;
1505 vortex_set_duplex(dev);
1506 } else if (init) {
1507 vortex_set_duplex(dev);
1508 }
1509}
1510
1511static int
1512vortex_up(struct net_device *dev)
1513{
1514 struct vortex_private *vp = netdev_priv(dev);
1515 void __iomem *ioaddr = vp->ioaddr;
1516 unsigned int config;
1517 int i, mii_reg1, mii_reg5, err = 0;
1518
1519 if (VORTEX_PCI(vp)) {
1520 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
1521 if (vp->pm_state_valid)
1522 pci_restore_state(VORTEX_PCI(vp));
1523 err = pci_enable_device(VORTEX_PCI(vp));
1524 if (err) {
1525 pr_warning("%s: Could not enable device\n",
1526 dev->name);
1527 goto err_out;
1528 }
1529 }
1530
1531
1532 EL3WINDOW(3);
1533 config = ioread32(ioaddr + Wn3_Config);
1534
1535 if (vp->media_override != 7) {
1536 pr_info("%s: Media override to transceiver %d (%s).\n",
1537 dev->name, vp->media_override,
1538 media_tbl[vp->media_override].name);
1539 dev->if_port = vp->media_override;
1540 } else if (vp->autoselect) {
1541 if (vp->has_nway) {
1542 if (vortex_debug > 1)
1543 pr_info("%s: using NWAY device table, not %d\n",
1544 dev->name, dev->if_port);
1545 dev->if_port = XCVR_NWAY;
1546 } else {
1547
1548 dev->if_port = XCVR_100baseTx;
1549 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1550 dev->if_port = media_tbl[dev->if_port].next;
1551 if (vortex_debug > 1)
1552 pr_info("%s: first available media type: %s\n",
1553 dev->name, media_tbl[dev->if_port].name);
1554 }
1555 } else {
1556 dev->if_port = vp->default_media;
1557 if (vortex_debug > 1)
1558 pr_info("%s: using default media %s\n",
1559 dev->name, media_tbl[dev->if_port].name);
1560 }
1561
1562 init_timer(&vp->timer);
1563 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1564 vp->timer.data = (unsigned long)dev;
1565 vp->timer.function = vortex_timer;
1566 add_timer(&vp->timer);
1567
1568 init_timer(&vp->rx_oom_timer);
1569 vp->rx_oom_timer.data = (unsigned long)dev;
1570 vp->rx_oom_timer.function = rx_oom_timer;
1571
1572 if (vortex_debug > 1)
1573 pr_debug("%s: Initial media type %s.\n",
1574 dev->name, media_tbl[dev->if_port].name);
1575
1576 vp->full_duplex = vp->mii.force_media;
1577 config = BFINS(config, dev->if_port, 20, 4);
1578 if (vortex_debug > 6)
1579 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1580 iowrite32(config, ioaddr + Wn3_Config);
1581
1582 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1583 EL3WINDOW(4);
1584 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1585 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1586 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1587 vp->mii.full_duplex = vp->full_duplex;
1588
1589 vortex_check_media(dev, 1);
1590 }
1591 else
1592 vortex_set_duplex(dev);
1593
1594 issue_and_wait(dev, TxReset);
1595
1596
1597
1598 issue_and_wait(dev, RxReset|0x04);
1599
1600
1601 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1602
1603 if (vortex_debug > 1) {
1604 EL3WINDOW(4);
1605 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1606 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1607 }
1608
1609
1610 EL3WINDOW(2);
1611 for (i = 0; i < 6; i++)
1612 iowrite8(dev->dev_addr[i], ioaddr + i);
1613 for (; i < 12; i+=2)
1614 iowrite16(0, ioaddr + i);
1615
1616 if (vp->cb_fn_base) {
1617 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1618 if (vp->drv_flags & INVERT_LED_PWR)
1619 n |= 0x10;
1620 if (vp->drv_flags & INVERT_MII_PWR)
1621 n |= 0x4000;
1622 iowrite16(n, ioaddr + Wn2_ResetOptions);
1623 }
1624
1625 if (dev->if_port == XCVR_10base2)
1626
1627 iowrite16(StartCoax, ioaddr + EL3_CMD);
1628 if (dev->if_port != XCVR_NWAY) {
1629 EL3WINDOW(4);
1630 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1631 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1632 }
1633
1634
1635 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1636 EL3WINDOW(6);
1637 for (i = 0; i < 10; i++)
1638 ioread8(ioaddr + i);
1639 ioread16(ioaddr + 10);
1640 ioread16(ioaddr + 12);
1641
1642 EL3WINDOW(4);
1643 ioread8(ioaddr + 12);
1644
1645 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1646
1647
1648 EL3WINDOW(7);
1649
1650 if (vp->full_bus_master_rx) {
1651 vp->cur_rx = vp->dirty_rx = 0;
1652
1653 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1654 iowrite32(0x0020, ioaddr + PktStatus);
1655 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1656 }
1657 if (vp->full_bus_master_tx) {
1658 vp->cur_tx = vp->dirty_tx = 0;
1659 if (vp->drv_flags & IS_BOOMERANG)
1660 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1661
1662 for (i = 0; i < RX_RING_SIZE; i++)
1663 vp->rx_ring[i].status = 0;
1664 for (i = 0; i < TX_RING_SIZE; i++)
1665 vp->tx_skbuff[i] = NULL;
1666 iowrite32(0, ioaddr + DownListPtr);
1667 }
1668
1669 set_rx_mode(dev);
1670
1671 set_8021q_mode(dev, 1);
1672 iowrite16(StatsEnable, ioaddr + EL3_CMD);
1673
1674 iowrite16(RxEnable, ioaddr + EL3_CMD);
1675 iowrite16(TxEnable, ioaddr + EL3_CMD);
1676
1677 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1678 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1679 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1680 (vp->bus_master ? DMADone : 0);
1681 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1682 (vp->full_bus_master_rx ? 0 : RxComplete) |
1683 StatsFull | HostError | TxComplete | IntReq
1684 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1685 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1686
1687 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1688 ioaddr + EL3_CMD);
1689 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1690 if (vp->cb_fn_base)
1691 iowrite32(0x8000, vp->cb_fn_base + 4);
1692 netif_start_queue (dev);
1693err_out:
1694 return err;
1695}
1696
1697static int
1698vortex_open(struct net_device *dev)
1699{
1700 struct vortex_private *vp = netdev_priv(dev);
1701 int i;
1702 int retval;
1703
1704
1705 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1706 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1707 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1708 goto err;
1709 }
1710
1711 if (vp->full_bus_master_rx) {
1712 if (vortex_debug > 2)
1713 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1714 for (i = 0; i < RX_RING_SIZE; i++) {
1715 struct sk_buff *skb;
1716 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1717 vp->rx_ring[i].status = 0;
1718 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1719
1720 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1721 GFP_KERNEL);
1722 vp->rx_skbuff[i] = skb;
1723 if (skb == NULL)
1724 break;
1725
1726 skb_reserve(skb, NET_IP_ALIGN);
1727 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1728 }
1729 if (i != RX_RING_SIZE) {
1730 int j;
1731 pr_emerg("%s: no memory for rx ring\n", dev->name);
1732 for (j = 0; j < i; j++) {
1733 if (vp->rx_skbuff[j]) {
1734 dev_kfree_skb(vp->rx_skbuff[j]);
1735 vp->rx_skbuff[j] = NULL;
1736 }
1737 }
1738 retval = -ENOMEM;
1739 goto err_free_irq;
1740 }
1741
1742 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1743 }
1744
1745 retval = vortex_up(dev);
1746 if (!retval)
1747 goto out;
1748
1749err_free_irq:
1750 free_irq(dev->irq, dev);
1751err:
1752 if (vortex_debug > 1)
1753 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1754out:
1755 return retval;
1756}
1757
1758static void
1759vortex_timer(unsigned long data)
1760{
1761 struct net_device *dev = (struct net_device *)data;
1762 struct vortex_private *vp = netdev_priv(dev);
1763 void __iomem *ioaddr = vp->ioaddr;
1764 int next_tick = 60*HZ;
1765 int ok = 0;
1766 int media_status, old_window;
1767
1768 if (vortex_debug > 2) {
1769 pr_debug("%s: Media selection timer tick happened, %s.\n",
1770 dev->name, media_tbl[dev->if_port].name);
1771 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1772 }
1773
1774 disable_irq_lockdep(dev->irq);
1775 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1776 EL3WINDOW(4);
1777 media_status = ioread16(ioaddr + Wn4_Media);
1778 switch (dev->if_port) {
1779 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1780 if (media_status & Media_LnkBeat) {
1781 netif_carrier_on(dev);
1782 ok = 1;
1783 if (vortex_debug > 1)
1784 pr_debug("%s: Media %s has link beat, %x.\n",
1785 dev->name, media_tbl[dev->if_port].name, media_status);
1786 } else {
1787 netif_carrier_off(dev);
1788 if (vortex_debug > 1) {
1789 pr_debug("%s: Media %s has no link beat, %x.\n",
1790 dev->name, media_tbl[dev->if_port].name, media_status);
1791 }
1792 }
1793 break;
1794 case XCVR_MII: case XCVR_NWAY:
1795 {
1796 ok = 1;
1797
1798 spin_lock(&vp->lock);
1799 vortex_check_media(dev, 0);
1800 spin_unlock(&vp->lock);
1801 }
1802 break;
1803 default:
1804 if (vortex_debug > 1)
1805 pr_debug("%s: Media %s has no indication, %x.\n",
1806 dev->name, media_tbl[dev->if_port].name, media_status);
1807 ok = 1;
1808 }
1809
1810 if (!netif_carrier_ok(dev))
1811 next_tick = 5*HZ;
1812
1813 if (vp->medialock)
1814 goto leave_media_alone;
1815
1816 if (!ok) {
1817 unsigned int config;
1818
1819 do {
1820 dev->if_port = media_tbl[dev->if_port].next;
1821 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1822 if (dev->if_port == XCVR_Default) {
1823 dev->if_port = vp->default_media;
1824 if (vortex_debug > 1)
1825 pr_debug("%s: Media selection failing, using default %s port.\n",
1826 dev->name, media_tbl[dev->if_port].name);
1827 } else {
1828 if (vortex_debug > 1)
1829 pr_debug("%s: Media selection failed, now trying %s port.\n",
1830 dev->name, media_tbl[dev->if_port].name);
1831 next_tick = media_tbl[dev->if_port].wait;
1832 }
1833 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1834 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1835
1836 EL3WINDOW(3);
1837 config = ioread32(ioaddr + Wn3_Config);
1838 config = BFINS(config, dev->if_port, 20, 4);
1839 iowrite32(config, ioaddr + Wn3_Config);
1840
1841 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1842 ioaddr + EL3_CMD);
1843 if (vortex_debug > 1)
1844 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1845
1846 }
1847
1848leave_media_alone:
1849 if (vortex_debug > 2)
1850 pr_debug("%s: Media selection timer finished, %s.\n",
1851 dev->name, media_tbl[dev->if_port].name);
1852
1853 EL3WINDOW(old_window);
1854 enable_irq_lockdep(dev->irq);
1855 mod_timer(&vp->timer, RUN_AT(next_tick));
1856 if (vp->deferred)
1857 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1858 return;
1859}
1860
1861static void vortex_tx_timeout(struct net_device *dev)
1862{
1863 struct vortex_private *vp = netdev_priv(dev);
1864 void __iomem *ioaddr = vp->ioaddr;
1865
1866 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1867 dev->name, ioread8(ioaddr + TxStatus),
1868 ioread16(ioaddr + EL3_STATUS));
1869 EL3WINDOW(4);
1870 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1871 ioread16(ioaddr + Wn4_NetDiag),
1872 ioread16(ioaddr + Wn4_Media),
1873 ioread32(ioaddr + PktStatus),
1874 ioread16(ioaddr + Wn4_FIFODiag));
1875
1876 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1877 pr_err("%s: Transmitter encountered 16 collisions --"
1878 " network cable problem?\n", dev->name);
1879 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1880 pr_err("%s: Interrupt posted but not delivered --"
1881 " IRQ blocked by another device?\n", dev->name);
1882
1883 {
1884
1885
1886
1887 unsigned long flags;
1888 local_irq_save(flags);
1889 if (vp->full_bus_master_tx)
1890 boomerang_interrupt(dev->irq, dev);
1891 else
1892 vortex_interrupt(dev->irq, dev);
1893 local_irq_restore(flags);
1894 }
1895 }
1896
1897 if (vortex_debug > 0)
1898 dump_tx_ring(dev);
1899
1900 issue_and_wait(dev, TxReset);
1901
1902 dev->stats.tx_errors++;
1903 if (vp->full_bus_master_tx) {
1904 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1905 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1906 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1907 ioaddr + DownListPtr);
1908 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1909 netif_wake_queue (dev);
1910 if (vp->drv_flags & IS_BOOMERANG)
1911 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1912 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1913 } else {
1914 dev->stats.tx_dropped++;
1915 netif_wake_queue(dev);
1916 }
1917
1918
1919 iowrite16(TxEnable, ioaddr + EL3_CMD);
1920 dev->trans_start = jiffies;
1921
1922
1923 EL3WINDOW(7);
1924}
1925
1926
1927
1928
1929
1930static void
1931vortex_error(struct net_device *dev, int status)
1932{
1933 struct vortex_private *vp = netdev_priv(dev);
1934 void __iomem *ioaddr = vp->ioaddr;
1935 int do_tx_reset = 0, reset_mask = 0;
1936 unsigned char tx_status = 0;
1937
1938 if (vortex_debug > 2) {
1939 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1940 }
1941
1942 if (status & TxComplete) {
1943 tx_status = ioread8(ioaddr + TxStatus);
1944
1945 if (vortex_debug > 2
1946 || (tx_status != 0x88 && vortex_debug > 0)) {
1947 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1948 dev->name, tx_status);
1949 if (tx_status == 0x82) {
1950 pr_err("Probably a duplex mismatch. See "
1951 "Documentation/networking/vortex.txt\n");
1952 }
1953 dump_tx_ring(dev);
1954 }
1955 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1956 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1957 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1958 iowrite8(0, ioaddr + TxStatus);
1959 if (tx_status & 0x30) {
1960 do_tx_reset = 1;
1961 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) {
1962 do_tx_reset = 1;
1963 reset_mask = 0x0108;
1964 } else {
1965 iowrite16(TxEnable, ioaddr + EL3_CMD);
1966 }
1967 }
1968
1969 if (status & RxEarly) {
1970 vortex_rx(dev);
1971 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1972 }
1973 if (status & StatsFull) {
1974 static int DoneDidThat;
1975 if (vortex_debug > 4)
1976 pr_debug("%s: Updating stats.\n", dev->name);
1977 update_stats(ioaddr, dev);
1978
1979
1980 if (DoneDidThat == 0 &&
1981 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1982 pr_warning("%s: Updating statistics failed, disabling "
1983 "stats as an interrupt source.\n", dev->name);
1984 EL3WINDOW(5);
1985 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1986 vp->intr_enable &= ~StatsFull;
1987 EL3WINDOW(7);
1988 DoneDidThat++;
1989 }
1990 }
1991 if (status & IntReq) {
1992 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1993 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1994 }
1995 if (status & HostError) {
1996 u16 fifo_diag;
1997 EL3WINDOW(4);
1998 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1999 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2000 dev->name, fifo_diag);
2001
2002 if (vp->full_bus_master_tx) {
2003 int bus_status = ioread32(ioaddr + PktStatus);
2004
2005
2006 if (vortex_debug)
2007 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2008
2009
2010
2011 vortex_down(dev, 0);
2012 issue_and_wait(dev, TotalReset | 0xff);
2013 vortex_up(dev);
2014 } else if (fifo_diag & 0x0400)
2015 do_tx_reset = 1;
2016 if (fifo_diag & 0x3000) {
2017
2018 issue_and_wait(dev, RxReset|0x07);
2019
2020 set_rx_mode(dev);
2021
2022 set_8021q_mode(dev, 1);
2023 iowrite16(RxEnable, ioaddr + EL3_CMD);
2024 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2025 }
2026 }
2027
2028 if (do_tx_reset) {
2029 issue_and_wait(dev, TxReset|reset_mask);
2030 iowrite16(TxEnable, ioaddr + EL3_CMD);
2031 if (!vp->full_bus_master_tx)
2032 netif_wake_queue(dev);
2033 }
2034}
2035
2036static netdev_tx_t
2037vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2038{
2039 struct vortex_private *vp = netdev_priv(dev);
2040 void __iomem *ioaddr = vp->ioaddr;
2041
2042
2043 iowrite32(skb->len, ioaddr + TX_FIFO);
2044 if (vp->bus_master) {
2045
2046 int len = (skb->len + 3) & ~3;
2047 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2048 ioaddr + Wn7_MasterAddr);
2049 iowrite16(len, ioaddr + Wn7_MasterLen);
2050 vp->tx_skb = skb;
2051 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2052
2053 } else {
2054
2055 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2056 dev_kfree_skb (skb);
2057 if (ioread16(ioaddr + TxFree) > 1536) {
2058 netif_start_queue (dev);
2059 } else {
2060
2061 netif_stop_queue(dev);
2062 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2063 }
2064 }
2065
2066 dev->trans_start = jiffies;
2067
2068
2069 {
2070 int tx_status;
2071 int i = 32;
2072
2073 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2074 if (tx_status & 0x3C) {
2075 if (vortex_debug > 2)
2076 pr_debug("%s: Tx error, status %2.2x.\n",
2077 dev->name, tx_status);
2078 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2079 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2080 if (tx_status & 0x30) {
2081 issue_and_wait(dev, TxReset);
2082 }
2083 iowrite16(TxEnable, ioaddr + EL3_CMD);
2084 }
2085 iowrite8(0x00, ioaddr + TxStatus);
2086 }
2087 }
2088 return NETDEV_TX_OK;
2089}
2090
2091static netdev_tx_t
2092boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2093{
2094 struct vortex_private *vp = netdev_priv(dev);
2095 void __iomem *ioaddr = vp->ioaddr;
2096
2097 int entry = vp->cur_tx % TX_RING_SIZE;
2098 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2099 unsigned long flags;
2100
2101 if (vortex_debug > 6) {
2102 pr_debug("boomerang_start_xmit()\n");
2103 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2104 dev->name, vp->cur_tx);
2105 }
2106
2107 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2108 if (vortex_debug > 0)
2109 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
2110 dev->name);
2111 netif_stop_queue(dev);
2112 return NETDEV_TX_BUSY;
2113 }
2114
2115 vp->tx_skbuff[entry] = skb;
2116
2117 vp->tx_ring[entry].next = 0;
2118#if DO_ZEROCOPY
2119 if (skb->ip_summed != CHECKSUM_PARTIAL)
2120 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2121 else
2122 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2123
2124 if (!skb_shinfo(skb)->nr_frags) {
2125 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2126 skb->len, PCI_DMA_TODEVICE));
2127 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2128 } else {
2129 int i;
2130
2131 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2132 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2133 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2134
2135 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2136 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2137
2138 vp->tx_ring[entry].frag[i+1].addr =
2139 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2140 (void*)page_address(frag->page) + frag->page_offset,
2141 frag->size, PCI_DMA_TODEVICE));
2142
2143 if (i == skb_shinfo(skb)->nr_frags-1)
2144 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2145 else
2146 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2147 }
2148 }
2149#else
2150 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2151 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2152 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2153#endif
2154
2155 spin_lock_irqsave(&vp->lock, flags);
2156
2157 issue_and_wait(dev, DownStall);
2158 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2159 if (ioread32(ioaddr + DownListPtr) == 0) {
2160 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2161 vp->queued_packet++;
2162 }
2163
2164 vp->cur_tx++;
2165 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2166 netif_stop_queue (dev);
2167 } else {
2168#if defined(tx_interrupt_mitigation)
2169
2170
2171
2172 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2173#endif
2174 }
2175 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2176 spin_unlock_irqrestore(&vp->lock, flags);
2177 dev->trans_start = jiffies;
2178 return NETDEV_TX_OK;
2179}
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189static irqreturn_t
2190vortex_interrupt(int irq, void *dev_id)
2191{
2192 struct net_device *dev = dev_id;
2193 struct vortex_private *vp = netdev_priv(dev);
2194 void __iomem *ioaddr;
2195 int status;
2196 int work_done = max_interrupt_work;
2197 int handled = 0;
2198
2199 ioaddr = vp->ioaddr;
2200 spin_lock(&vp->lock);
2201
2202 status = ioread16(ioaddr + EL3_STATUS);
2203
2204 if (vortex_debug > 6)
2205 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2206
2207 if ((status & IntLatch) == 0)
2208 goto handler_exit;
2209 handled = 1;
2210
2211 if (status & IntReq) {
2212 status |= vp->deferred;
2213 vp->deferred = 0;
2214 }
2215
2216 if (status == 0xffff)
2217 goto handler_exit;
2218
2219 if (vortex_debug > 4)
2220 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2221 dev->name, status, ioread8(ioaddr + Timer));
2222
2223 do {
2224 if (vortex_debug > 5)
2225 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2226 dev->name, status);
2227 if (status & RxComplete)
2228 vortex_rx(dev);
2229
2230 if (status & TxAvailable) {
2231 if (vortex_debug > 5)
2232 pr_debug(" TX room bit was handled.\n");
2233
2234 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2235 netif_wake_queue (dev);
2236 }
2237
2238 if (status & DMADone) {
2239 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2240 iowrite16(0x1000, ioaddr + Wn7_MasterStatus);
2241 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2242 dev_kfree_skb_irq(vp->tx_skb);
2243 if (ioread16(ioaddr + TxFree) > 1536) {
2244
2245
2246
2247
2248
2249 netif_wake_queue(dev);
2250 } else {
2251 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2252 netif_stop_queue(dev);
2253 }
2254 }
2255 }
2256
2257 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2258 if (status == 0xffff)
2259 break;
2260 vortex_error(dev, status);
2261 }
2262
2263 if (--work_done < 0) {
2264 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2265 dev->name, status);
2266
2267 do {
2268 vp->deferred |= status;
2269 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2270 ioaddr + EL3_CMD);
2271 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2272 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2273
2274 mod_timer(&vp->timer, jiffies + 1*HZ);
2275 break;
2276 }
2277
2278 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2279 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2280
2281 if (vortex_debug > 4)
2282 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2283 dev->name, status);
2284handler_exit:
2285 spin_unlock(&vp->lock);
2286 return IRQ_RETVAL(handled);
2287}
2288
2289
2290
2291
2292
2293
2294static irqreturn_t
2295boomerang_interrupt(int irq, void *dev_id)
2296{
2297 struct net_device *dev = dev_id;
2298 struct vortex_private *vp = netdev_priv(dev);
2299 void __iomem *ioaddr;
2300 int status;
2301 int work_done = max_interrupt_work;
2302
2303 ioaddr = vp->ioaddr;
2304
2305
2306
2307
2308
2309 spin_lock(&vp->lock);
2310
2311 status = ioread16(ioaddr + EL3_STATUS);
2312
2313 if (vortex_debug > 6)
2314 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2315
2316 if ((status & IntLatch) == 0)
2317 goto handler_exit;
2318
2319 if (status == 0xffff) {
2320 if (vortex_debug > 1)
2321 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2322 goto handler_exit;
2323 }
2324
2325 if (status & IntReq) {
2326 status |= vp->deferred;
2327 vp->deferred = 0;
2328 }
2329
2330 if (vortex_debug > 4)
2331 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2332 dev->name, status, ioread8(ioaddr + Timer));
2333 do {
2334 if (vortex_debug > 5)
2335 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2336 dev->name, status);
2337 if (status & UpComplete) {
2338 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2339 if (vortex_debug > 5)
2340 pr_debug("boomerang_interrupt->boomerang_rx\n");
2341 boomerang_rx(dev);
2342 }
2343
2344 if (status & DownComplete) {
2345 unsigned int dirty_tx = vp->dirty_tx;
2346
2347 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2348 while (vp->cur_tx - dirty_tx > 0) {
2349 int entry = dirty_tx % TX_RING_SIZE;
2350#if 1
2351 if (ioread32(ioaddr + DownListPtr) ==
2352 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2353 break;
2354#else
2355 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2356 break;
2357#endif
2358
2359 if (vp->tx_skbuff[entry]) {
2360 struct sk_buff *skb = vp->tx_skbuff[entry];
2361#if DO_ZEROCOPY
2362 int i;
2363 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2364 pci_unmap_single(VORTEX_PCI(vp),
2365 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2366 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2367 PCI_DMA_TODEVICE);
2368#else
2369 pci_unmap_single(VORTEX_PCI(vp),
2370 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2371#endif
2372 dev_kfree_skb_irq(skb);
2373 vp->tx_skbuff[entry] = NULL;
2374 } else {
2375 pr_debug("boomerang_interrupt: no skb!\n");
2376 }
2377
2378 dirty_tx++;
2379 }
2380 vp->dirty_tx = dirty_tx;
2381 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2382 if (vortex_debug > 6)
2383 pr_debug("boomerang_interrupt: wake queue\n");
2384 netif_wake_queue (dev);
2385 }
2386 }
2387
2388
2389 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2390 vortex_error(dev, status);
2391
2392 if (--work_done < 0) {
2393 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2394 dev->name, status);
2395
2396 do {
2397 vp->deferred |= status;
2398 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2399 ioaddr + EL3_CMD);
2400 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2401 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2402
2403 mod_timer(&vp->timer, jiffies + 1*HZ);
2404 break;
2405 }
2406
2407 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2408 if (vp->cb_fn_base)
2409 iowrite32(0x8000, vp->cb_fn_base + 4);
2410
2411 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2412
2413 if (vortex_debug > 4)
2414 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2415 dev->name, status);
2416handler_exit:
2417 spin_unlock(&vp->lock);
2418 return IRQ_HANDLED;
2419}
2420
2421static int vortex_rx(struct net_device *dev)
2422{
2423 struct vortex_private *vp = netdev_priv(dev);
2424 void __iomem *ioaddr = vp->ioaddr;
2425 int i;
2426 short rx_status;
2427
2428 if (vortex_debug > 5)
2429 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2430 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2431 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2432 if (rx_status & 0x4000) {
2433 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2434 if (vortex_debug > 2)
2435 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2436 dev->stats.rx_errors++;
2437 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2438 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2439 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2440 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2441 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2442 } else {
2443
2444 int pkt_len = rx_status & 0x1fff;
2445 struct sk_buff *skb;
2446
2447 skb = dev_alloc_skb(pkt_len + 5);
2448 if (vortex_debug > 4)
2449 pr_debug("Receiving packet size %d status %4.4x.\n",
2450 pkt_len, rx_status);
2451 if (skb != NULL) {
2452 skb_reserve(skb, 2);
2453
2454 if (vp->bus_master &&
2455 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2456 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2457 pkt_len, PCI_DMA_FROMDEVICE);
2458 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2459 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2460 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2461 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2462 ;
2463 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2464 } else {
2465 ioread32_rep(ioaddr + RX_FIFO,
2466 skb_put(skb, pkt_len),
2467 (pkt_len + 3) >> 2);
2468 }
2469 iowrite16(RxDiscard, ioaddr + EL3_CMD);
2470 skb->protocol = eth_type_trans(skb, dev);
2471 netif_rx(skb);
2472 dev->stats.rx_packets++;
2473
2474 for (i = 200; i >= 0; i--)
2475 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2476 break;
2477 continue;
2478 } else if (vortex_debug > 0)
2479 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2480 dev->name, pkt_len);
2481 dev->stats.rx_dropped++;
2482 }
2483 issue_and_wait(dev, RxDiscard);
2484 }
2485
2486 return 0;
2487}
2488
2489static int
2490boomerang_rx(struct net_device *dev)
2491{
2492 struct vortex_private *vp = netdev_priv(dev);
2493 int entry = vp->cur_rx % RX_RING_SIZE;
2494 void __iomem *ioaddr = vp->ioaddr;
2495 int rx_status;
2496 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2497
2498 if (vortex_debug > 5)
2499 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2500
2501 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2502 if (--rx_work_limit < 0)
2503 break;
2504 if (rx_status & RxDError) {
2505 unsigned char rx_error = rx_status >> 16;
2506 if (vortex_debug > 2)
2507 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2508 dev->stats.rx_errors++;
2509 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2510 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2511 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2512 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2513 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2514 } else {
2515
2516 int pkt_len = rx_status & 0x1fff;
2517 struct sk_buff *skb;
2518 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2519
2520 if (vortex_debug > 4)
2521 pr_debug("Receiving packet size %d status %4.4x.\n",
2522 pkt_len, rx_status);
2523
2524
2525
2526 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
2527 skb_reserve(skb, 2);
2528 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2529
2530 memcpy(skb_put(skb, pkt_len),
2531 vp->rx_skbuff[entry]->data,
2532 pkt_len);
2533 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2534 vp->rx_copy++;
2535 } else {
2536
2537 skb = vp->rx_skbuff[entry];
2538 vp->rx_skbuff[entry] = NULL;
2539 skb_put(skb, pkt_len);
2540 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2541 vp->rx_nocopy++;
2542 }
2543 skb->protocol = eth_type_trans(skb, dev);
2544 {
2545 int csum_bits = rx_status & 0xee000000;
2546 if (csum_bits &&
2547 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2548 csum_bits == (IPChksumValid | UDPChksumValid))) {
2549 skb->ip_summed = CHECKSUM_UNNECESSARY;
2550 vp->rx_csumhits++;
2551 }
2552 }
2553 netif_rx(skb);
2554 dev->stats.rx_packets++;
2555 }
2556 entry = (++vp->cur_rx) % RX_RING_SIZE;
2557 }
2558
2559 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2560 struct sk_buff *skb;
2561 entry = vp->dirty_rx % RX_RING_SIZE;
2562 if (vp->rx_skbuff[entry] == NULL) {
2563 skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
2564 if (skb == NULL) {
2565 static unsigned long last_jif;
2566 if (time_after(jiffies, last_jif + 10 * HZ)) {
2567 pr_warning("%s: memory shortage\n", dev->name);
2568 last_jif = jiffies;
2569 }
2570 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2571 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2572 break;
2573 }
2574
2575 skb_reserve(skb, NET_IP_ALIGN);
2576 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2577 vp->rx_skbuff[entry] = skb;
2578 }
2579 vp->rx_ring[entry].status = 0;
2580 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2581 }
2582 return 0;
2583}
2584
2585
2586
2587
2588
2589static void
2590rx_oom_timer(unsigned long arg)
2591{
2592 struct net_device *dev = (struct net_device *)arg;
2593 struct vortex_private *vp = netdev_priv(dev);
2594
2595 spin_lock_irq(&vp->lock);
2596 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2597 boomerang_rx(dev);
2598 if (vortex_debug > 1) {
2599 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2600 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2601 }
2602 spin_unlock_irq(&vp->lock);
2603}
2604
2605static void
2606vortex_down(struct net_device *dev, int final_down)
2607{
2608 struct vortex_private *vp = netdev_priv(dev);
2609 void __iomem *ioaddr = vp->ioaddr;
2610
2611 netif_stop_queue (dev);
2612
2613 del_timer_sync(&vp->rx_oom_timer);
2614 del_timer_sync(&vp->timer);
2615
2616
2617 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2618
2619
2620 iowrite16(RxDisable, ioaddr + EL3_CMD);
2621 iowrite16(TxDisable, ioaddr + EL3_CMD);
2622
2623
2624 set_8021q_mode(dev, 0);
2625
2626 if (dev->if_port == XCVR_10base2)
2627
2628 iowrite16(StopCoax, ioaddr + EL3_CMD);
2629
2630 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2631
2632 update_stats(ioaddr, dev);
2633 if (vp->full_bus_master_rx)
2634 iowrite32(0, ioaddr + UpListPtr);
2635 if (vp->full_bus_master_tx)
2636 iowrite32(0, ioaddr + DownListPtr);
2637
2638 if (final_down && VORTEX_PCI(vp)) {
2639 vp->pm_state_valid = 1;
2640 pci_save_state(VORTEX_PCI(vp));
2641 acpi_set_WOL(dev);
2642 }
2643}
2644
2645static int
2646vortex_close(struct net_device *dev)
2647{
2648 struct vortex_private *vp = netdev_priv(dev);
2649 void __iomem *ioaddr = vp->ioaddr;
2650 int i;
2651
2652 if (netif_device_present(dev))
2653 vortex_down(dev, 1);
2654
2655 if (vortex_debug > 1) {
2656 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2657 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2658 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2659 " tx_queued %d Rx pre-checksummed %d.\n",
2660 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2661 }
2662
2663#if DO_ZEROCOPY
2664 if (vp->rx_csumhits &&
2665 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2666 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2667 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
2668 }
2669#endif
2670
2671 free_irq(dev->irq, dev);
2672
2673 if (vp->full_bus_master_rx) {
2674 for (i = 0; i < RX_RING_SIZE; i++)
2675 if (vp->rx_skbuff[i]) {
2676 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2677 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2678 dev_kfree_skb(vp->rx_skbuff[i]);
2679 vp->rx_skbuff[i] = NULL;
2680 }
2681 }
2682 if (vp->full_bus_master_tx) {
2683 for (i = 0; i < TX_RING_SIZE; i++) {
2684 if (vp->tx_skbuff[i]) {
2685 struct sk_buff *skb = vp->tx_skbuff[i];
2686#if DO_ZEROCOPY
2687 int k;
2688
2689 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2690 pci_unmap_single(VORTEX_PCI(vp),
2691 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2692 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2693 PCI_DMA_TODEVICE);
2694#else
2695 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2696#endif
2697 dev_kfree_skb(skb);
2698 vp->tx_skbuff[i] = NULL;
2699 }
2700 }
2701 }
2702
2703 return 0;
2704}
2705
2706static void
2707dump_tx_ring(struct net_device *dev)
2708{
2709 if (vortex_debug > 0) {
2710 struct vortex_private *vp = netdev_priv(dev);
2711 void __iomem *ioaddr = vp->ioaddr;
2712
2713 if (vp->full_bus_master_tx) {
2714 int i;
2715 int stalled = ioread32(ioaddr + PktStatus) & 0x04;
2716
2717 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2718 vp->full_bus_master_tx,
2719 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2720 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2721 pr_err(" Transmit list %8.8x vs. %p.\n",
2722 ioread32(ioaddr + DownListPtr),
2723 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2724 issue_and_wait(dev, DownStall);
2725 for (i = 0; i < TX_RING_SIZE; i++) {
2726 unsigned int length;
2727
2728#if DO_ZEROCOPY
2729 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2730#else
2731 length = le32_to_cpu(vp->tx_ring[i].length);
2732#endif
2733 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2734 i, &vp->tx_ring[i], length,
2735 le32_to_cpu(vp->tx_ring[i].status));
2736 }
2737 if (!stalled)
2738 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2739 }
2740 }
2741}
2742
2743static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2744{
2745 struct vortex_private *vp = netdev_priv(dev);
2746 void __iomem *ioaddr = vp->ioaddr;
2747 unsigned long flags;
2748
2749 if (netif_device_present(dev)) {
2750 spin_lock_irqsave (&vp->lock, flags);
2751 update_stats(ioaddr, dev);
2752 spin_unlock_irqrestore (&vp->lock, flags);
2753 }
2754 return &dev->stats;
2755}
2756
2757
2758
2759
2760
2761
2762
2763
2764static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2765{
2766 struct vortex_private *vp = netdev_priv(dev);
2767 int old_window = ioread16(ioaddr + EL3_CMD);
2768
2769 if (old_window == 0xffff)
2770 return;
2771
2772
2773 EL3WINDOW(6);
2774 dev->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2775 dev->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2776 dev->stats.tx_window_errors += ioread8(ioaddr + 4);
2777 dev->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2778 dev->stats.tx_packets += ioread8(ioaddr + 6);
2779 dev->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2780 ioread8(ioaddr + 7);
2781
2782
2783
2784 dev->stats.rx_bytes += ioread16(ioaddr + 10);
2785 dev->stats.tx_bytes += ioread16(ioaddr + 12);
2786
2787 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
2788 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
2789 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
2790 EL3WINDOW(4);
2791 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
2792
2793 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2794 + vp->xstats.tx_single_collisions
2795 + vp->xstats.tx_max_collisions;
2796
2797 {
2798 u8 up = ioread8(ioaddr + 13);
2799 dev->stats.rx_bytes += (up & 0x0f) << 16;
2800 dev->stats.tx_bytes += (up & 0xf0) << 12;
2801 }
2802
2803 EL3WINDOW(old_window >> 13);
2804 return;
2805}
2806
2807static int vortex_nway_reset(struct net_device *dev)
2808{
2809 struct vortex_private *vp = netdev_priv(dev);
2810 void __iomem *ioaddr = vp->ioaddr;
2811 unsigned long flags;
2812 int rc;
2813
2814 spin_lock_irqsave(&vp->lock, flags);
2815 EL3WINDOW(4);
2816 rc = mii_nway_restart(&vp->mii);
2817 spin_unlock_irqrestore(&vp->lock, flags);
2818 return rc;
2819}
2820
2821static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2822{
2823 struct vortex_private *vp = netdev_priv(dev);
2824 void __iomem *ioaddr = vp->ioaddr;
2825 unsigned long flags;
2826 int rc;
2827
2828 spin_lock_irqsave(&vp->lock, flags);
2829 EL3WINDOW(4);
2830 rc = mii_ethtool_gset(&vp->mii, cmd);
2831 spin_unlock_irqrestore(&vp->lock, flags);
2832 return rc;
2833}
2834
2835static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2836{
2837 struct vortex_private *vp = netdev_priv(dev);
2838 void __iomem *ioaddr = vp->ioaddr;
2839 unsigned long flags;
2840 int rc;
2841
2842 spin_lock_irqsave(&vp->lock, flags);
2843 EL3WINDOW(4);
2844 rc = mii_ethtool_sset(&vp->mii, cmd);
2845 spin_unlock_irqrestore(&vp->lock, flags);
2846 return rc;
2847}
2848
2849static u32 vortex_get_msglevel(struct net_device *dev)
2850{
2851 return vortex_debug;
2852}
2853
2854static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2855{
2856 vortex_debug = dbg;
2857}
2858
2859static int vortex_get_sset_count(struct net_device *dev, int sset)
2860{
2861 switch (sset) {
2862 case ETH_SS_STATS:
2863 return VORTEX_NUM_STATS;
2864 default:
2865 return -EOPNOTSUPP;
2866 }
2867}
2868
2869static void vortex_get_ethtool_stats(struct net_device *dev,
2870 struct ethtool_stats *stats, u64 *data)
2871{
2872 struct vortex_private *vp = netdev_priv(dev);
2873 void __iomem *ioaddr = vp->ioaddr;
2874 unsigned long flags;
2875
2876 spin_lock_irqsave(&vp->lock, flags);
2877 update_stats(ioaddr, dev);
2878 spin_unlock_irqrestore(&vp->lock, flags);
2879
2880 data[0] = vp->xstats.tx_deferred;
2881 data[1] = vp->xstats.tx_max_collisions;
2882 data[2] = vp->xstats.tx_multiple_collisions;
2883 data[3] = vp->xstats.tx_single_collisions;
2884 data[4] = vp->xstats.rx_bad_ssd;
2885}
2886
2887
2888static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2889{
2890 switch (stringset) {
2891 case ETH_SS_STATS:
2892 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2893 break;
2894 default:
2895 WARN_ON(1);
2896 break;
2897 }
2898}
2899
2900static void vortex_get_drvinfo(struct net_device *dev,
2901 struct ethtool_drvinfo *info)
2902{
2903 struct vortex_private *vp = netdev_priv(dev);
2904
2905 strcpy(info->driver, DRV_NAME);
2906 if (VORTEX_PCI(vp)) {
2907 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2908 } else {
2909 if (VORTEX_EISA(vp))
2910 strcpy(info->bus_info, dev_name(vp->gendev));
2911 else
2912 sprintf(info->bus_info, "EISA 0x%lx %d",
2913 dev->base_addr, dev->irq);
2914 }
2915}
2916
2917static const struct ethtool_ops vortex_ethtool_ops = {
2918 .get_drvinfo = vortex_get_drvinfo,
2919 .get_strings = vortex_get_strings,
2920 .get_msglevel = vortex_get_msglevel,
2921 .set_msglevel = vortex_set_msglevel,
2922 .get_ethtool_stats = vortex_get_ethtool_stats,
2923 .get_sset_count = vortex_get_sset_count,
2924 .get_settings = vortex_get_settings,
2925 .set_settings = vortex_set_settings,
2926 .get_link = ethtool_op_get_link,
2927 .nway_reset = vortex_nway_reset,
2928};
2929
2930#ifdef CONFIG_PCI
2931
2932
2933
2934static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2935{
2936 int err;
2937 struct vortex_private *vp = netdev_priv(dev);
2938 void __iomem *ioaddr = vp->ioaddr;
2939 unsigned long flags;
2940 pci_power_t state = 0;
2941
2942 if(VORTEX_PCI(vp))
2943 state = VORTEX_PCI(vp)->current_state;
2944
2945
2946
2947 if(state != 0)
2948 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2949 spin_lock_irqsave(&vp->lock, flags);
2950 EL3WINDOW(4);
2951 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2952 spin_unlock_irqrestore(&vp->lock, flags);
2953 if(state != 0)
2954 pci_set_power_state(VORTEX_PCI(vp), state);
2955
2956 return err;
2957}
2958#endif
2959
2960
2961
2962
2963
2964static void set_rx_mode(struct net_device *dev)
2965{
2966 struct vortex_private *vp = netdev_priv(dev);
2967 void __iomem *ioaddr = vp->ioaddr;
2968 int new_mode;
2969
2970 if (dev->flags & IFF_PROMISC) {
2971 if (vortex_debug > 3)
2972 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
2973 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2974 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2975 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2976 } else
2977 new_mode = SetRxFilter | RxStation | RxBroadcast;
2978
2979 iowrite16(new_mode, ioaddr + EL3_CMD);
2980}
2981
2982#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2983
2984
2985
2986
2987
2988#define VLAN_ETHER_TYPE 0x8100
2989
2990static void set_8021q_mode(struct net_device *dev, int enable)
2991{
2992 struct vortex_private *vp = netdev_priv(dev);
2993 void __iomem *ioaddr = vp->ioaddr;
2994 int old_window = ioread16(ioaddr + EL3_CMD);
2995 int mac_ctrl;
2996
2997 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2998
2999
3000
3001 int max_pkt_size = dev->mtu+14;
3002 if (enable)
3003 max_pkt_size += 4;
3004
3005 EL3WINDOW(3);
3006 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
3007
3008
3009
3010 EL3WINDOW(7);
3011 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
3012 } else {
3013
3014
3015 vp->large_frames = dev->mtu > 1500 || enable;
3016
3017 EL3WINDOW(3);
3018 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
3019 if (vp->large_frames)
3020 mac_ctrl |= 0x40;
3021 else
3022 mac_ctrl &= ~0x40;
3023 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
3024 }
3025
3026 EL3WINDOW(old_window);
3027}
3028#else
3029
3030static void set_8021q_mode(struct net_device *dev, int enable)
3031{
3032}
3033
3034
3035#endif
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045#define mdio_delay() ioread32(mdio_addr)
3046
3047#define MDIO_SHIFT_CLK 0x01
3048#define MDIO_DIR_WRITE 0x04
3049#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3050#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3051#define MDIO_DATA_READ 0x02
3052#define MDIO_ENB_IN 0x00
3053
3054
3055
3056static void mdio_sync(void __iomem *ioaddr, int bits)
3057{
3058 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3059
3060
3061 while (-- bits >= 0) {
3062 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
3063 mdio_delay();
3064 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
3065 mdio_delay();
3066 }
3067}
3068
3069static int mdio_read(struct net_device *dev, int phy_id, int location)
3070{
3071 int i;
3072 struct vortex_private *vp = netdev_priv(dev);
3073 void __iomem *ioaddr = vp->ioaddr;
3074 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3075 unsigned int retval = 0;
3076 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3077
3078 if (mii_preamble_required)
3079 mdio_sync(ioaddr, 32);
3080
3081
3082 for (i = 14; i >= 0; i--) {
3083 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3084 iowrite16(dataval, mdio_addr);
3085 mdio_delay();
3086 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3087 mdio_delay();
3088 }
3089
3090 for (i = 19; i > 0; i--) {
3091 iowrite16(MDIO_ENB_IN, mdio_addr);
3092 mdio_delay();
3093 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3094 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3095 mdio_delay();
3096 }
3097 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3098}
3099
3100static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3101{
3102 struct vortex_private *vp = netdev_priv(dev);
3103 void __iomem *ioaddr = vp->ioaddr;
3104 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3105 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3106 int i;
3107
3108 if (mii_preamble_required)
3109 mdio_sync(ioaddr, 32);
3110
3111
3112 for (i = 31; i >= 0; i--) {
3113 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3114 iowrite16(dataval, mdio_addr);
3115 mdio_delay();
3116 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3117 mdio_delay();
3118 }
3119
3120 for (i = 1; i >= 0; i--) {
3121 iowrite16(MDIO_ENB_IN, mdio_addr);
3122 mdio_delay();
3123 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3124 mdio_delay();
3125 }
3126 return;
3127}
3128
3129
3130
3131static void acpi_set_WOL(struct net_device *dev)
3132{
3133 struct vortex_private *vp = netdev_priv(dev);
3134 void __iomem *ioaddr = vp->ioaddr;
3135
3136 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3137
3138 if (vp->enable_wol) {
3139
3140 EL3WINDOW(7);
3141 iowrite16(2, ioaddr + 0x0c);
3142
3143 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3144 iowrite16(RxEnable, ioaddr + EL3_CMD);
3145
3146 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3147 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3148
3149 vp->enable_wol = 0;
3150 return;
3151 }
3152
3153
3154 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3155 }
3156}
3157
3158
3159static void __devexit vortex_remove_one(struct pci_dev *pdev)
3160{
3161 struct net_device *dev = pci_get_drvdata(pdev);
3162 struct vortex_private *vp;
3163
3164 if (!dev) {
3165 pr_err("vortex_remove_one called for Compaq device!\n");
3166 BUG();
3167 }
3168
3169 vp = netdev_priv(dev);
3170
3171 if (vp->cb_fn_base)
3172 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3173
3174 unregister_netdev(dev);
3175
3176 if (VORTEX_PCI(vp)) {
3177 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3178 if (vp->pm_state_valid)
3179 pci_restore_state(VORTEX_PCI(vp));
3180 pci_disable_device(VORTEX_PCI(vp));
3181 }
3182
3183 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3184 vp->ioaddr + EL3_CMD);
3185
3186 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3187
3188 pci_free_consistent(pdev,
3189 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3190 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3191 vp->rx_ring,
3192 vp->rx_ring_dma);
3193 if (vp->must_free_region)
3194 release_region(dev->base_addr, vp->io_size);
3195 free_netdev(dev);
3196}
3197
3198
3199static struct pci_driver vortex_driver = {
3200 .name = "3c59x",
3201 .probe = vortex_init_one,
3202 .remove = __devexit_p(vortex_remove_one),
3203 .id_table = vortex_pci_tbl,
3204 .driver.pm = VORTEX_PM_OPS,
3205};
3206
3207
3208static int vortex_have_pci;
3209static int vortex_have_eisa;
3210
3211
3212static int __init vortex_init(void)
3213{
3214 int pci_rc, eisa_rc;
3215
3216 pci_rc = pci_register_driver(&vortex_driver);
3217 eisa_rc = vortex_eisa_init();
3218
3219 if (pci_rc == 0)
3220 vortex_have_pci = 1;
3221 if (eisa_rc > 0)
3222 vortex_have_eisa = 1;
3223
3224 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3225}
3226
3227
3228static void __exit vortex_eisa_cleanup(void)
3229{
3230 struct vortex_private *vp;
3231 void __iomem *ioaddr;
3232
3233#ifdef CONFIG_EISA
3234
3235 eisa_driver_unregister(&vortex_eisa_driver);
3236#endif
3237
3238 if (compaq_net_device) {
3239 vp = netdev_priv(compaq_net_device);
3240 ioaddr = ioport_map(compaq_net_device->base_addr,
3241 VORTEX_TOTAL_SIZE);
3242
3243 unregister_netdev(compaq_net_device);
3244 iowrite16(TotalReset, ioaddr + EL3_CMD);
3245 release_region(compaq_net_device->base_addr,
3246 VORTEX_TOTAL_SIZE);
3247
3248 free_netdev(compaq_net_device);
3249 }
3250}
3251
3252
3253static void __exit vortex_cleanup(void)
3254{
3255 if (vortex_have_pci)
3256 pci_unregister_driver(&vortex_driver);
3257 if (vortex_have_eisa)
3258 vortex_eisa_cleanup();
3259}
3260
3261
3262module_init(vortex_init);
3263module_exit(vortex_cleanup);
3264