LXR linux/drivers/net/benet/be

   1/*
   2 * Copyright (C) 2005 - 2009 ServerEngines
   3 * All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License version 2
   7 * as published by the Free Software Foundation.  The full GNU General
   8 * Public License is included in this distribution in the file called COPYING.
   9 *
  10 * Contact Information:
  11 * linux-drivers@serverengines.com
  12 *
  13 * ServerEngines
  14 * 209 N. Fair Oaks Ave
  15 * Sunnyvale, CA 94085
  16 */
  17
  18/*
  19 * The driver sends configuration and managements command requests to the
  20 * firmware in the BE. These requests are communicated to the processor
  21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22 * WRB inside a MAILBOX.
  23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24 */
  25
  26struct be_sge {
  27        u32 pa_lo;
  28        u32 pa_hi;
  29        u32 len;
  30};
  31
  32#define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33#define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34#define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35struct be_mcc_wrb {
  36        u32 embedded;           /* dword 0 */
  37        u32 payload_length;     /* dword 1 */
  38        u32 tag0;               /* dword 2 */
  39        u32 tag1;               /* dword 3 */
  40        u32 rsvd;               /* dword 4 */
  41        union {
  42                u8 embedded_payload[236]; /* used by embedded cmds */
  43                struct be_sge sgl[19];    /* used by non-embedded cmds */
  44        } payload;
  45};
  46
  47#define CQE_FLAGS_VALID_MASK            (1 << 31)
  48#define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49#define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50#define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52/* Completion Status */
  53enum {
  54        MCC_STATUS_SUCCESS = 0x0,
  55/* The client does not have sufficient privileges to execute the command */
  56        MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57/* A parameter in the command was invalid. */
  58        MCC_STATUS_INVALID_PARAMETER = 0x2,
  59/* There are insufficient chip resources to execute the command */
  60        MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61/* The command is completing because the queue was getting flushed */
  62        MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63/* The command is completing with a DMA error */
  64        MCC_STATUS_DMA_FAILED = 0x5,
  65        MCC_STATUS_NOT_SUPPORTED = 66
  66};
  67
  68#define CQE_STATUS_COMPL_MASK           0xFFFF
  69#define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  70#define CQE_STATUS_EXTD_MASK            0xFFFF
  71#define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  72
  73struct be_mcc_compl {
  74        u32 status;             /* dword 0 */
  75        u32 tag0;               /* dword 1 */
  76        u32 tag1;               /* dword 2 */
  77        u32 flags;              /* dword 3 */
  78};
  79
  80/* When the async bit of mcc_compl is set, the last 4 bytes of
  81 * mcc_compl is interpreted as follows:
  82 */
  83#define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  84#define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  85#define ASYNC_EVENT_CODE_LINK_STATE     0x1
  86struct be_async_event_trailer {
  87        u32 code;
  88};
  89
  90enum {
  91        ASYNC_EVENT_LINK_DOWN   = 0x0,
  92        ASYNC_EVENT_LINK_UP     = 0x1
  93};
  94
  95/* When the event code of an async trailer is link-state, the mcc_compl
  96 * must be interpreted as follows
  97 */
  98struct be_async_event_link_state {
  99        u8 physical_port;
 100        u8 port_link_status;
 101        u8 port_duplex;
 102        u8 port_speed;
 103        u8 port_fault;
 104        u8 rsvd0[7];
 105        struct be_async_event_trailer trailer;
 106} __packed;
 107
 108struct be_mcc_mailbox {
 109        struct be_mcc_wrb wrb;
 110        struct be_mcc_compl compl;
 111};
 112
 113#define CMD_SUBSYSTEM_COMMON    0x1
 114#define CMD_SUBSYSTEM_ETH       0x3
 115
 116#define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 117#define OPCODE_COMMON_NTWK_MAC_SET                      2
 118#define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 119#define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 120#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 121#define OPCODE_COMMON_WRITE_FLASHROM                    7
 122#define OPCODE_COMMON_CQ_CREATE                         12
 123#define OPCODE_COMMON_EQ_CREATE                         13
 124#define OPCODE_COMMON_MCC_CREATE                        21
 125#define OPCODE_COMMON_NTWK_RX_FILTER                    34
 126#define OPCODE_COMMON_GET_FW_VERSION                    35
 127#define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 128#define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 129#define OPCODE_COMMON_SET_FRAME_SIZE                    39
 130#define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 131#define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 132#define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 133#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 134#define OPCODE_COMMON_MCC_DESTROY                       53
 135#define OPCODE_COMMON_CQ_DESTROY                        54
 136#define OPCODE_COMMON_EQ_DESTROY                        55
 137#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 138#define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 139#define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 140#define OPCODE_COMMON_FUNCTION_RESET                    61
 141
 142#define OPCODE_ETH_ACPI_CONFIG                          2
 143#define OPCODE_ETH_PROMISCUOUS                          3
 144#define OPCODE_ETH_GET_STATISTICS                       4
 145#define OPCODE_ETH_TX_CREATE                            7
 146#define OPCODE_ETH_RX_CREATE                            8
 147#define OPCODE_ETH_TX_DESTROY                           9
 148#define OPCODE_ETH_RX_DESTROY                           10
 149
 150struct be_cmd_req_hdr {
 151        u8 opcode;              /* dword 0 */
 152        u8 subsystem;           /* dword 0 */
 153        u8 port_number;         /* dword 0 */
 154        u8 domain;              /* dword 0 */
 155        u32 timeout;            /* dword 1 */
 156        u32 request_length;     /* dword 2 */
 157        u32 rsvd;               /* dword 3 */
 158};
 159
 160#define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 161#define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 162struct be_cmd_resp_hdr {
 163        u32 info;               /* dword 0 */
 164        u32 status;             /* dword 1 */
 165        u32 response_length;    /* dword 2 */
 166        u32 actual_resp_len;    /* dword 3 */
 167};
 168
 169struct phys_addr {
 170        u32 lo;
 171        u32 hi;
 172};
 173
 174/**************************
 175 * BE Command definitions *
 176 **************************/
 177
 178/* Pseudo amap definition in which each bit of the actual structure is defined
 179 * as a byte: used to calculate offset/shift/mask of each field */
 180struct amap_eq_context {
 181        u8 cidx[13];            /* dword 0*/
 182        u8 rsvd0[3];            /* dword 0*/
 183        u8 epidx[13];           /* dword 0*/
 184        u8 valid;               /* dword 0*/
 185        u8 rsvd1;               /* dword 0*/
 186        u8 size;                /* dword 0*/
 187        u8 pidx[13];            /* dword 1*/
 188        u8 rsvd2[3];            /* dword 1*/
 189        u8 pd[10];              /* dword 1*/
 190        u8 count[3];            /* dword 1*/
 191        u8 solevent;            /* dword 1*/
 192        u8 stalled;             /* dword 1*/
 193        u8 armed;               /* dword 1*/
 194        u8 rsvd3[4];            /* dword 2*/
 195        u8 func[8];             /* dword 2*/
 196        u8 rsvd4;               /* dword 2*/
 197        u8 delaymult[10];       /* dword 2*/
 198        u8 rsvd5[2];            /* dword 2*/
 199        u8 phase[2];            /* dword 2*/
 200        u8 nodelay;             /* dword 2*/
 201        u8 rsvd6[4];            /* dword 2*/
 202        u8 rsvd7[32];           /* dword 3*/
 203} __packed;
 204
 205struct be_cmd_req_eq_create {
 206        struct be_cmd_req_hdr hdr;
 207        u16 num_pages;          /* sword */
 208        u16 rsvd0;              /* sword */
 209        u8 context[sizeof(struct amap_eq_context) / 8];
 210        struct phys_addr pages[8];
 211} __packed;
 212
 213struct be_cmd_resp_eq_create {
 214        struct be_cmd_resp_hdr resp_hdr;
 215        u16 eq_id;              /* sword */
 216        u16 rsvd0;              /* sword */
 217} __packed;
 218
 219/******************** Mac query ***************************/
 220enum {
 221        MAC_ADDRESS_TYPE_STORAGE = 0x0,
 222        MAC_ADDRESS_TYPE_NETWORK = 0x1,
 223        MAC_ADDRESS_TYPE_PD = 0x2,
 224        MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 225};
 226
 227struct mac_addr {
 228        u16 size_of_struct;
 229        u8 addr[ETH_ALEN];
 230} __packed;
 231
 232struct be_cmd_req_mac_query {
 233        struct be_cmd_req_hdr hdr;
 234        u8 type;
 235        u8 permanent;
 236        u16 if_id;
 237} __packed;
 238
 239struct be_cmd_resp_mac_query {
 240        struct be_cmd_resp_hdr hdr;
 241        struct mac_addr mac;
 242};
 243
 244/******************** PMac Add ***************************/
 245struct be_cmd_req_pmac_add {
 246        struct be_cmd_req_hdr hdr;
 247        u32 if_id;
 248        u8 mac_address[ETH_ALEN];
 249        u8 rsvd0[2];
 250} __packed;
 251
 252struct be_cmd_resp_pmac_add {
 253        struct be_cmd_resp_hdr hdr;
 254        u32 pmac_id;
 255};
 256
 257/******************** PMac Del ***************************/
 258struct be_cmd_req_pmac_del {
 259        struct be_cmd_req_hdr hdr;
 260        u32 if_id;
 261        u32 pmac_id;
 262};
 263
 264/******************** Create CQ ***************************/
 265/* Pseudo amap definition in which each bit of the actual structure is defined
 266 * as a byte: used to calculate offset/shift/mask of each field */
 267struct amap_cq_context {
 268        u8 cidx[11];            /* dword 0*/
 269        u8 rsvd0;               /* dword 0*/
 270        u8 coalescwm[2];        /* dword 0*/
 271        u8 nodelay;             /* dword 0*/
 272        u8 epidx[11];           /* dword 0*/
 273        u8 rsvd1;               /* dword 0*/
 274        u8 count[2];            /* dword 0*/
 275        u8 valid;               /* dword 0*/
 276        u8 solevent;            /* dword 0*/
 277        u8 eventable;           /* dword 0*/
 278        u8 pidx[11];            /* dword 1*/
 279        u8 rsvd2;               /* dword 1*/
 280        u8 pd[10];              /* dword 1*/
 281        u8 eqid[8];             /* dword 1*/
 282        u8 stalled;             /* dword 1*/
 283        u8 armed;               /* dword 1*/
 284        u8 rsvd3[4];            /* dword 2*/
 285        u8 func[8];             /* dword 2*/
 286        u8 rsvd4[20];           /* dword 2*/
 287        u8 rsvd5[32];           /* dword 3*/
 288} __packed;
 289
 290struct be_cmd_req_cq_create {
 291        struct be_cmd_req_hdr hdr;
 292        u16 num_pages;
 293        u16 rsvd0;
 294        u8 context[sizeof(struct amap_cq_context) / 8];
 295        struct phys_addr pages[8];
 296} __packed;
 297
 298struct be_cmd_resp_cq_create {
 299        struct be_cmd_resp_hdr hdr;
 300        u16 cq_id;
 301        u16 rsvd0;
 302} __packed;
 303
 304/******************** Create MCCQ ***************************/
 305/* Pseudo amap definition in which each bit of the actual structure is defined
 306 * as a byte: used to calculate offset/shift/mask of each field */
 307struct amap_mcc_context {
 308        u8 con_index[14];
 309        u8 rsvd0[2];
 310        u8 ring_size[4];
 311        u8 fetch_wrb;
 312        u8 fetch_r2t;
 313        u8 cq_id[10];
 314        u8 prod_index[14];
 315        u8 fid[8];
 316        u8 pdid[9];
 317        u8 valid;
 318        u8 rsvd1[32];
 319        u8 rsvd2[32];
 320} __packed;
 321
 322struct be_cmd_req_mcc_create {
 323        struct be_cmd_req_hdr hdr;
 324        u16 num_pages;
 325        u16 rsvd0;
 326        u8 context[sizeof(struct amap_mcc_context) / 8];
 327        struct phys_addr pages[8];
 328} __packed;
 329
 330struct be_cmd_resp_mcc_create {
 331        struct be_cmd_resp_hdr hdr;
 332        u16 id;
 333        u16 rsvd0;
 334} __packed;
 335
 336/******************** Create TxQ ***************************/
 337#define BE_ETH_TX_RING_TYPE_STANDARD            2
 338#define BE_ULP1_NUM                             1
 339
 340/* Pseudo amap definition in which each bit of the actual structure is defined
 341 * as a byte: used to calculate offset/shift/mask of each field */
 342struct amap_tx_context {
 343        u8 rsvd0[16];           /* dword 0 */
 344        u8 tx_ring_size[4];     /* dword 0 */
 345        u8 rsvd1[26];           /* dword 0 */
 346        u8 pci_func_id[8];      /* dword 1 */
 347        u8 rsvd2[9];            /* dword 1 */
 348        u8 ctx_valid;           /* dword 1 */
 349        u8 cq_id_send[16];      /* dword 2 */
 350        u8 rsvd3[16];           /* dword 2 */
 351        u8 rsvd4[32];           /* dword 3 */
 352        u8 rsvd5[32];           /* dword 4 */
 353        u8 rsvd6[32];           /* dword 5 */
 354        u8 rsvd7[32];           /* dword 6 */
 355        u8 rsvd8[32];           /* dword 7 */
 356        u8 rsvd9[32];           /* dword 8 */
 357        u8 rsvd10[32];          /* dword 9 */
 358        u8 rsvd11[32];          /* dword 10 */
 359        u8 rsvd12[32];          /* dword 11 */
 360        u8 rsvd13[32];          /* dword 12 */
 361        u8 rsvd14[32];          /* dword 13 */
 362        u8 rsvd15[32];          /* dword 14 */
 363        u8 rsvd16[32];          /* dword 15 */
 364} __packed;
 365
 366struct be_cmd_req_eth_tx_create {
 367        struct be_cmd_req_hdr hdr;
 368        u8 num_pages;
 369        u8 ulp_num;
 370        u8 type;
 371        u8 bound_port;
 372        u8 context[sizeof(struct amap_tx_context) / 8];
 373        struct phys_addr pages[8];
 374} __packed;
 375
 376struct be_cmd_resp_eth_tx_create {
 377        struct be_cmd_resp_hdr hdr;
 378        u16 cid;
 379        u16 rsvd0;
 380} __packed;
 381
 382/******************** Create RxQ ***************************/
 383struct be_cmd_req_eth_rx_create {
 384        struct be_cmd_req_hdr hdr;
 385        u16 cq_id;
 386        u8 frag_size;
 387        u8 num_pages;
 388        struct phys_addr pages[2];
 389        u32 interface_id;
 390        u16 max_frame_size;
 391        u16 rsvd0;
 392        u32 rss_queue;
 393} __packed;
 394
 395struct be_cmd_resp_eth_rx_create {
 396        struct be_cmd_resp_hdr hdr;
 397        u16 id;
 398        u8 cpu_id;
 399        u8 rsvd0;
 400} __packed;
 401
 402/******************** Q Destroy  ***************************/
 403/* Type of Queue to be destroyed */
 404enum {
 405        QTYPE_EQ = 1,
 406        QTYPE_CQ,
 407        QTYPE_TXQ,
 408        QTYPE_RXQ,
 409        QTYPE_MCCQ
 410};
 411
 412struct be_cmd_req_q_destroy {
 413        struct be_cmd_req_hdr hdr;
 414        u16 id;
 415        u16 bypass_flush;       /* valid only for rx q destroy */
 416} __packed;
 417
 418/************ I/f Create (it's actually I/f Config Create)**********/
 419
 420/* Capability flags for the i/f */
 421enum be_if_flags {
 422        BE_IF_FLAGS_RSS = 0x4,
 423        BE_IF_FLAGS_PROMISCUOUS = 0x8,
 424        BE_IF_FLAGS_BROADCAST = 0x10,
 425        BE_IF_FLAGS_UNTAGGED = 0x20,
 426        BE_IF_FLAGS_ULP = 0x40,
 427        BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 428        BE_IF_FLAGS_VLAN = 0x100,
 429        BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 430        BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 431        BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
 432};
 433
 434/* An RX interface is an object with one or more MAC addresses and
 435 * filtering capabilities. */
 436struct be_cmd_req_if_create {
 437        struct be_cmd_req_hdr hdr;
 438        u32 version;            /* ignore currntly */
 439        u32 capability_flags;
 440        u32 enable_flags;
 441        u8 mac_addr[ETH_ALEN];
 442        u8 rsvd0;
 443        u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 444        u32 vlan_tag;    /* not used currently */
 445} __packed;
 446
 447struct be_cmd_resp_if_create {
 448        struct be_cmd_resp_hdr hdr;
 449        u32 interface_id;
 450        u32 pmac_id;
 451};
 452
 453/****** I/f Destroy(it's actually I/f Config Destroy )**********/
 454struct be_cmd_req_if_destroy {
 455        struct be_cmd_req_hdr hdr;
 456        u32 interface_id;
 457};
 458
 459/*************** HW Stats Get **********************************/
 460struct be_port_rxf_stats {
 461        u32 rx_bytes_lsd;       /* dword 0*/
 462        u32 rx_bytes_msd;       /* dword 1*/
 463        u32 rx_total_frames;    /* dword 2*/
 464        u32 rx_unicast_frames;  /* dword 3*/
 465        u32 rx_multicast_frames;        /* dword 4*/
 466        u32 rx_broadcast_frames;        /* dword 5*/
 467        u32 rx_crc_errors;      /* dword 6*/
 468        u32 rx_alignment_symbol_errors; /* dword 7*/
 469        u32 rx_pause_frames;    /* dword 8*/
 470        u32 rx_control_frames;  /* dword 9*/
 471        u32 rx_in_range_errors; /* dword 10*/
 472        u32 rx_out_range_errors;        /* dword 11*/
 473        u32 rx_frame_too_long;  /* dword 12*/
 474        u32 rx_address_match_errors;    /* dword 13*/
 475        u32 rx_vlan_mismatch;   /* dword 14*/
 476        u32 rx_dropped_too_small;       /* dword 15*/
 477        u32 rx_dropped_too_short;       /* dword 16*/
 478        u32 rx_dropped_header_too_small;        /* dword 17*/
 479        u32 rx_dropped_tcp_length;      /* dword 18*/
 480        u32 rx_dropped_runt;    /* dword 19*/
 481        u32 rx_64_byte_packets; /* dword 20*/
 482        u32 rx_65_127_byte_packets;     /* dword 21*/
 483        u32 rx_128_256_byte_packets;    /* dword 22*/
 484        u32 rx_256_511_byte_packets;    /* dword 23*/
 485        u32 rx_512_1023_byte_packets;   /* dword 24*/
 486        u32 rx_1024_1518_byte_packets;  /* dword 25*/
 487        u32 rx_1519_2047_byte_packets;  /* dword 26*/
 488        u32 rx_2048_4095_byte_packets;  /* dword 27*/
 489        u32 rx_4096_8191_byte_packets;  /* dword 28*/
 490        u32 rx_8192_9216_byte_packets;  /* dword 29*/
 491        u32 rx_ip_checksum_errs;        /* dword 30*/
 492        u32 rx_tcp_checksum_errs;       /* dword 31*/
 493        u32 rx_udp_checksum_errs;       /* dword 32*/
 494        u32 rx_non_rss_packets; /* dword 33*/
 495        u32 rx_ipv4_packets;    /* dword 34*/
 496        u32 rx_ipv6_packets;    /* dword 35*/
 497        u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 498        u32 rx_ipv4_bytes_msd;  /* dword 37*/
 499        u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 500        u32 rx_ipv6_bytes_msd;  /* dword 39*/
 501        u32 rx_chute1_packets;  /* dword 40*/
 502        u32 rx_chute2_packets;  /* dword 41*/
 503        u32 rx_chute3_packets;  /* dword 42*/
 504        u32 rx_management_packets;      /* dword 43*/
 505        u32 rx_switched_unicast_packets;        /* dword 44*/
 506        u32 rx_switched_multicast_packets;      /* dword 45*/
 507        u32 rx_switched_broadcast_packets;      /* dword 46*/
 508        u32 tx_bytes_lsd;       /* dword 47*/
 509        u32 tx_bytes_msd;       /* dword 48*/
 510        u32 tx_unicastframes;   /* dword 49*/
 511        u32 tx_multicastframes; /* dword 50*/
 512        u32 tx_broadcastframes; /* dword 51*/
 513        u32 tx_pauseframes;     /* dword 52*/
 514        u32 tx_controlframes;   /* dword 53*/
 515        u32 tx_64_byte_packets; /* dword 54*/
 516        u32 tx_65_127_byte_packets;     /* dword 55*/
 517        u32 tx_128_256_byte_packets;    /* dword 56*/
 518        u32 tx_256_511_byte_packets;    /* dword 57*/
 519        u32 tx_512_1023_byte_packets;   /* dword 58*/
 520        u32 tx_1024_1518_byte_packets;  /* dword 59*/
 521        u32 tx_1519_2047_byte_packets;  /* dword 60*/
 522        u32 tx_2048_4095_byte_packets;  /* dword 61*/
 523        u32 tx_4096_8191_byte_packets;  /* dword 62*/
 524        u32 tx_8192_9216_byte_packets;  /* dword 63*/
 525        u32 rx_fifo_overflow;   /* dword 64*/
 526        u32 rx_input_fifo_overflow;     /* dword 65*/
 527};
 528
 529struct be_rxf_stats {
 530        struct be_port_rxf_stats port[2];
 531        u32 rx_drops_no_pbuf;   /* dword 132*/
 532        u32 rx_drops_no_txpb;   /* dword 133*/
 533        u32 rx_drops_no_erx_descr;      /* dword 134*/
 534        u32 rx_drops_no_tpre_descr;     /* dword 135*/
 535        u32 management_rx_port_packets; /* dword 136*/
 536        u32 management_rx_port_bytes;   /* dword 137*/
 537        u32 management_rx_port_pause_frames;    /* dword 138*/
 538        u32 management_rx_port_errors;  /* dword 139*/
 539        u32 management_tx_port_packets; /* dword 140*/
 540        u32 management_tx_port_bytes;   /* dword 141*/
 541        u32 management_tx_port_pause;   /* dword 142*/
 542        u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 543        u32 rx_drops_too_many_frags;    /* dword 144*/
 544        u32 rx_drops_invalid_ring;      /* dword 145*/
 545        u32 forwarded_packets;  /* dword 146*/
 546        u32 rx_drops_mtu;       /* dword 147*/
 547        u32 rsvd0[15];
 548};
 549
 550struct be_erx_stats {
 551        u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 552        u32 debug_wdma_sent_hold;          /* dword 44*/
 553        u32 debug_wdma_pbfree_sent_hold;   /* dword 45*/
 554        u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
 555        u32 debug_pmem_pbuf_dealloc;       /* dword 47*/
 556};
 557
 558struct be_hw_stats {
 559        struct be_rxf_stats rxf;
 560        u32 rsvd[48];
 561        struct be_erx_stats erx;
 562};
 563
 564struct be_cmd_req_get_stats {
 565        struct be_cmd_req_hdr hdr;
 566        u8 rsvd[sizeof(struct be_hw_stats)];
 567};
 568
 569struct be_cmd_resp_get_stats {
 570        struct be_cmd_resp_hdr hdr;
 571        struct be_hw_stats hw_stats;
 572};
 573
 574struct be_cmd_req_vlan_config {
 575        struct be_cmd_req_hdr hdr;
 576        u8 interface_id;
 577        u8 promiscuous;
 578        u8 untagged;
 579        u8 num_vlan;
 580        u16 normal_vlan[64];
 581} __packed;
 582
 583struct be_cmd_req_promiscuous_config {
 584        struct be_cmd_req_hdr hdr;
 585        u8 port0_promiscuous;
 586        u8 port1_promiscuous;
 587        u16 rsvd0;
 588} __packed;
 589
 590struct macaddr {
 591        u8 byte[ETH_ALEN];
 592};
 593
 594struct be_cmd_req_mcast_mac_config {
 595        struct be_cmd_req_hdr hdr;
 596        u16 num_mac;
 597        u8 promiscuous;
 598        u8 interface_id;
 599        struct macaddr mac[32];
 600} __packed;
 601
 602static inline struct be_hw_stats *
 603hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
 604{
 605        return &cmd->hw_stats;
 606}
 607
 608/******************** Link Status Query *******************/
 609struct be_cmd_req_link_status {
 610        struct be_cmd_req_hdr hdr;
 611        u32 rsvd;
 612};
 613
 614enum {
 615        PHY_LINK_DUPLEX_NONE = 0x0,
 616        PHY_LINK_DUPLEX_HALF = 0x1,
 617        PHY_LINK_DUPLEX_FULL = 0x2
 618};
 619
 620enum {
 621        PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 622        PHY_LINK_SPEED_10MBPS = 0x1,
 623        PHY_LINK_SPEED_100MBPS = 0x2,
 624        PHY_LINK_SPEED_1GBPS = 0x3,
 625        PHY_LINK_SPEED_10GBPS = 0x4
 626};
 627
 628struct be_cmd_resp_link_status {
 629        struct be_cmd_resp_hdr hdr;
 630        u8 physical_port;
 631        u8 mac_duplex;
 632        u8 mac_speed;
 633        u8 mac_fault;
 634        u8 mgmt_mac_duplex;
 635        u8 mgmt_mac_speed;
 636        u16 rsvd0;
 637} __packed;
 638
 639/******************** Get FW Version *******************/
 640struct be_cmd_req_get_fw_version {
 641        struct be_cmd_req_hdr hdr;
 642        u8 rsvd0[FW_VER_LEN];
 643        u8 rsvd1[FW_VER_LEN];
 644} __packed;
 645
 646struct be_cmd_resp_get_fw_version {
 647        struct be_cmd_resp_hdr hdr;
 648        u8 firmware_version_string[FW_VER_LEN];
 649        u8 fw_on_flash_version_string[FW_VER_LEN];
 650} __packed;
 651
 652/******************** Set Flow Contrl *******************/
 653struct be_cmd_req_set_flow_control {
 654        struct be_cmd_req_hdr hdr;
 655        u16 tx_flow_control;
 656        u16 rx_flow_control;
 657} __packed;
 658
 659/******************** Get Flow Contrl *******************/
 660struct be_cmd_req_get_flow_control {
 661        struct be_cmd_req_hdr hdr;
 662        u32 rsvd;
 663};
 664
 665struct be_cmd_resp_get_flow_control {
 666        struct be_cmd_resp_hdr hdr;
 667        u16 tx_flow_control;
 668        u16 rx_flow_control;
 669} __packed;
 670
 671/******************** Modify EQ Delay *******************/
 672struct be_cmd_req_modify_eq_delay {
 673        struct be_cmd_req_hdr hdr;
 674        u32 num_eq;
 675        struct {
 676                u32 eq_id;
 677                u32 phase;
 678                u32 delay_multiplier;
 679        } delay[8];
 680} __packed;
 681
 682struct be_cmd_resp_modify_eq_delay {
 683        struct be_cmd_resp_hdr hdr;
 684        u32 rsvd0;
 685} __packed;
 686
 687/******************** Get FW Config *******************/
 688struct be_cmd_req_query_fw_cfg {
 689        struct be_cmd_req_hdr hdr;
 690        u32 rsvd[30];
 691};
 692
 693struct be_cmd_resp_query_fw_cfg {
 694        struct be_cmd_resp_hdr hdr;
 695        u32 be_config_number;
 696        u32 asic_revision;
 697        u32 phys_port;
 698        u32 function_cap;
 699        u32 rsvd[26];
 700};
 701
 702/****************** Firmware Flash ******************/
 703struct flashrom_params {
 704        u32 op_code;
 705        u32 op_type;
 706        u32 data_buf_size;
 707        u32 offset;
 708        u8 data_buf[4];
 709};
 710
 711struct be_cmd_write_flashrom {
 712        struct be_cmd_req_hdr hdr;
 713        struct flashrom_params params;
 714};
 715
 716extern int be_pci_fnum_get(struct be_adapter *adapter);
 717extern int be_cmd_POST(struct be_adapter *adapter);
 718extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 719                        u8 type, bool permanent, u32 if_handle);
 720extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 721                        u32 if_id, u32 *pmac_id);
 722extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
 723extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
 724                        u32 en_flags, u8 *mac, bool pmac_invalid,
 725                        u32 *if_handle, u32 *pmac_id);
 726extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
 727extern int be_cmd_eq_create(struct be_adapter *adapter,
 728                        struct be_queue_info *eq, int eq_delay);
 729extern int be_cmd_cq_create(struct be_adapter *adapter,
 730                        struct be_queue_info *cq, struct be_queue_info *eq,
 731                        bool sol_evts, bool no_delay,
 732                        int num_cqe_dma_coalesce);
 733extern int be_cmd_mccq_create(struct be_adapter *adapter,
 734                        struct be_queue_info *mccq,
 735                        struct be_queue_info *cq);
 736extern int be_cmd_txq_create(struct be_adapter *adapter,
 737                        struct be_queue_info *txq,
 738                        struct be_queue_info *cq);
 739extern int be_cmd_rxq_create(struct be_adapter *adapter,
 740                        struct be_queue_info *rxq, u16 cq_id,
 741                        u16 frag_size, u16 max_frame_size, u32 if_id,
 742                        u32 rss);
 743extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 744                        int type);
 745extern int be_cmd_link_status_query(struct be_adapter *adapter,
 746                        bool *link_up);
 747extern int be_cmd_reset(struct be_adapter *adapter);
 748extern int be_cmd_get_stats(struct be_adapter *adapter,
 749                        struct be_dma_mem *nonemb_cmd);
 750extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
 751
 752extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
 753extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
 754                        u16 *vtag_array, u32 num, bool untagged,
 755                        bool promiscuous);
 756extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
 757                        u8 port_num, bool en);
 758extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
 759                        struct dev_mc_list *mc_list, u32 mc_count);
 760extern int be_cmd_set_flow_control(struct be_adapter *adapter,
 761                        u32 tx_fc, u32 rx_fc);
 762extern int be_cmd_get_flow_control(struct be_adapter *adapter,
 763                        u32 *tx_fc, u32 *rx_fc);
 764extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
 765                        u32 *port_num, u32 *cap);
 766extern int be_cmd_reset_function(struct be_adapter *adapter);
 767extern int be_process_mcc(struct be_adapter *adapter);
 768extern int be_cmd_write_flashrom(struct be_adapter *adapter,
 769                        struct be_dma_mem *cmd, u32 flash_oper,
 770                        u32 flash_opcode, u32 buf_size);
 771