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14#ifndef BNX2X_H
15#define BNX2X_H
16
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20
21
22
23#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24#define BCM_VLAN 1
25#endif
26
27
28#define BNX2X_MULTI_QUEUE
29
30#define BNX2X_NEW_NAPI
31
32
33
34#include <linux/mdio.h>
35#include "bnx2x_reg.h"
36#include "bnx2x_fw_defs.h"
37#include "bnx2x_hsi.h"
38#include "bnx2x_link.h"
39
40
41
42#define DRV_MODULE_NAME "bnx2x"
43#define PFX DRV_MODULE_NAME ": "
44
45
46#define BNX2X_MSG_OFF 0
47#define BNX2X_MSG_MCP 0x010000
48#define BNX2X_MSG_STATS 0x020000
49#define BNX2X_MSG_NVM 0x040000
50#define BNX2X_MSG_DMAE 0x080000
51#define BNX2X_MSG_SP 0x100000
52#define BNX2X_MSG_FP 0x200000
53
54#define DP_LEVEL KERN_NOTICE
55
56
57#define DP(__mask, __fmt, __args...) do { \
58 if (bp->msglevel & (__mask)) \
59 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
60 bp->dev ? (bp->dev->name) : "?", ##__args); \
61 } while (0)
62
63
64#define BNX2X_DBG_ERR(__fmt, __args...) do { \
65 if (bp->msglevel & NETIF_MSG_PROBE) \
66 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
67 bp->dev ? (bp->dev->name) : "?", ##__args); \
68 } while (0)
69
70
71#define BNX2X_ERR(__fmt, __args...) do { \
72 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
73 bp->dev ? (bp->dev->name) : "?", ##__args); \
74 } while (0)
75
76
77#define BNX2X_DEV_INFO(__fmt, __args...) do { \
78 if (bp->msglevel & NETIF_MSG_PROBE) \
79 dev_info(&bp->pdev->dev, __fmt, ##__args); \
80 } while (0)
81
82
83#ifdef BNX2X_STOP_ON_ERROR
84#define bnx2x_panic() do { \
85 bp->panic = 1; \
86 BNX2X_ERR("driver assert\n"); \
87 bnx2x_int_disable(bp); \
88 bnx2x_panic_dump(bp); \
89 } while (0)
90#else
91#define bnx2x_panic() do { \
92 bp->panic = 1; \
93 BNX2X_ERR("driver assert\n"); \
94 bnx2x_panic_dump(bp); \
95 } while (0)
96#endif
97
98
99#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
100#define U64_HI(x) (u32)(((u64)(x)) >> 32)
101#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
102
103
104#define REG_ADDR(bp, offset) (bp->regview + offset)
105
106#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
107#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
108
109#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
110#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
111#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
112
113#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
114#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
115
116#define REG_RD_DMAE(bp, offset, valp, len32) \
117 do { \
118 bnx2x_read_dmae(bp, offset, len32);\
119 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
120 } while (0)
121
122#define REG_WR_DMAE(bp, offset, valp, len32) \
123 do { \
124 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
125 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
126 offset, len32); \
127 } while (0)
128
129#define VIRT_WR_DMAE_LEN(bp, data, addr, len32) \
130 do { \
131 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
132 bnx2x_write_big_buf_wb(bp, addr, len32); \
133 } while (0)
134
135#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
136 offsetof(struct shmem_region, field))
137#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
138#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
139
140#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
141 offsetof(struct shmem2_region, field))
142#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
143#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
144
145#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
146#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
147
148
149
150
151struct sw_rx_bd {
152 struct sk_buff *skb;
153 DECLARE_PCI_UNMAP_ADDR(mapping)
154};
155
156struct sw_tx_bd {
157 struct sk_buff *skb;
158 u16 first_bd;
159 u8 flags;
160
161#define BNX2X_TSO_SPLIT_BD (1<<0)
162};
163
164struct sw_rx_page {
165 struct page *page;
166 DECLARE_PCI_UNMAP_ADDR(mapping)
167};
168
169union db_prod {
170 struct doorbell_set_prod data;
171 u32 raw;
172};
173
174
175
176#define BCM_PAGE_SHIFT 12
177#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
178#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
179#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
180
181#define PAGES_PER_SGE_SHIFT 0
182#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
183#define SGE_PAGE_SIZE PAGE_SIZE
184#define SGE_PAGE_SHIFT PAGE_SHIFT
185#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
186
187
188#define NUM_RX_SGE_PAGES 2
189#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
190#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
191
192#define RX_SGE_MASK (RX_SGE_CNT - 1)
193#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
194#define MAX_RX_SGE (NUM_RX_SGE - 1)
195#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
196 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
197#define RX_SGE(x) ((x) & MAX_RX_SGE)
198
199
200
201#define RX_SGE_MASK_ELEM_SZ 64
202#define RX_SGE_MASK_ELEM_SHIFT 6
203#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
204
205
206
207#define RX_SGE_ONES_MASK(idx) \
208 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
209#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
210
211
212#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
213 RX_SGE_MASK_ELEM_SZ)
214#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
215#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
216
217
218struct bnx2x_eth_q_stats {
219 u32 total_bytes_received_hi;
220 u32 total_bytes_received_lo;
221 u32 total_bytes_transmitted_hi;
222 u32 total_bytes_transmitted_lo;
223 u32 total_unicast_packets_received_hi;
224 u32 total_unicast_packets_received_lo;
225 u32 total_multicast_packets_received_hi;
226 u32 total_multicast_packets_received_lo;
227 u32 total_broadcast_packets_received_hi;
228 u32 total_broadcast_packets_received_lo;
229 u32 total_unicast_packets_transmitted_hi;
230 u32 total_unicast_packets_transmitted_lo;
231 u32 total_multicast_packets_transmitted_hi;
232 u32 total_multicast_packets_transmitted_lo;
233 u32 total_broadcast_packets_transmitted_hi;
234 u32 total_broadcast_packets_transmitted_lo;
235 u32 valid_bytes_received_hi;
236 u32 valid_bytes_received_lo;
237
238 u32 error_bytes_received_hi;
239 u32 error_bytes_received_lo;
240 u32 etherstatsoverrsizepkts_hi;
241 u32 etherstatsoverrsizepkts_lo;
242 u32 no_buff_discard_hi;
243 u32 no_buff_discard_lo;
244
245 u32 driver_xoff;
246 u32 rx_err_discard_pkt;
247 u32 rx_skb_alloc_failed;
248 u32 hw_csum_err;
249};
250
251#define BNX2X_NUM_Q_STATS 11
252#define Q_STATS_OFFSET32(stat_name) \
253 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
254
255struct bnx2x_fastpath {
256
257 struct napi_struct napi;
258
259 u8 is_rx_queue;
260
261 struct host_status_block *status_blk;
262 dma_addr_t status_blk_mapping;
263
264 struct sw_tx_bd *tx_buf_ring;
265
266 union eth_tx_bd_types *tx_desc_ring;
267 dma_addr_t tx_desc_mapping;
268
269 struct sw_rx_bd *rx_buf_ring;
270 struct sw_rx_page *rx_page_ring;
271
272 struct eth_rx_bd *rx_desc_ring;
273 dma_addr_t rx_desc_mapping;
274
275 union eth_rx_cqe *rx_comp_ring;
276 dma_addr_t rx_comp_mapping;
277
278
279 struct eth_rx_sge *rx_sge_ring;
280 dma_addr_t rx_sge_mapping;
281
282 u64 sge_mask[RX_SGE_MASK_LEN];
283
284 int state;
285#define BNX2X_FP_STATE_CLOSED 0
286#define BNX2X_FP_STATE_IRQ 0x80000
287#define BNX2X_FP_STATE_OPENING 0x90000
288#define BNX2X_FP_STATE_OPEN 0xa0000
289#define BNX2X_FP_STATE_HALTING 0xb0000
290#define BNX2X_FP_STATE_HALTED 0xc0000
291
292 u8 index;
293 u8 cl_id;
294 u8 sb_id;
295
296 union db_prod tx_db;
297
298 u16 tx_pkt_prod;
299 u16 tx_pkt_cons;
300 u16 tx_bd_prod;
301 u16 tx_bd_cons;
302 __le16 *tx_cons_sb;
303
304 __le16 fp_c_idx;
305 __le16 fp_u_idx;
306
307 u16 rx_bd_prod;
308 u16 rx_bd_cons;
309 u16 rx_comp_prod;
310 u16 rx_comp_cons;
311 u16 rx_sge_prod;
312
313 u16 last_max_sge;
314 __le16 *rx_cons_sb;
315 __le16 *rx_bd_cons_sb;
316
317
318 unsigned long tx_pkt,
319 rx_pkt,
320 rx_calls;
321
322
323 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
324 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
325#define BNX2X_TPA_START 1
326#define BNX2X_TPA_STOP 2
327 u8 disable_tpa;
328#ifdef BNX2X_STOP_ON_ERROR
329 u64 tpa_queue_used;
330#endif
331
332 struct tstorm_per_client_stats old_tclient;
333 struct ustorm_per_client_stats old_uclient;
334 struct xstorm_per_client_stats old_xclient;
335 struct bnx2x_eth_q_stats eth_q_stats;
336
337
338
339
340
341#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
342 char name[FP_NAME_SIZE];
343 struct bnx2x *bp;
344};
345
346#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
347
348
349
350#define MAX_FETCH_BD 13
351#define RX_COPY_THRESH 92
352
353#define NUM_TX_RINGS 16
354#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
355#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
356#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
357#define MAX_TX_BD (NUM_TX_BD - 1)
358#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
359#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
360 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
361#define TX_BD(x) ((x) & MAX_TX_BD)
362#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
363
364
365#define NUM_RX_RINGS 8
366#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
367#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
368#define RX_DESC_MASK (RX_DESC_CNT - 1)
369#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
370#define MAX_RX_BD (NUM_RX_BD - 1)
371#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
372#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
373 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
374#define RX_BD(x) ((x) & MAX_RX_BD)
375
376
377
378
379#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
380#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
381#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
382#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
383#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
384#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
385#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
386 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
387#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
388
389
390
391#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
392
393#define __SGE_MASK_SET_BIT(el, bit) \
394 do { \
395 el = ((el) | ((u64)0x1 << (bit))); \
396 } while (0)
397
398#define __SGE_MASK_CLEAR_BIT(el, bit) \
399 do { \
400 el = ((el) & (~((u64)0x1 << (bit)))); \
401 } while (0)
402
403#define SGE_MASK_SET_BIT(fp, idx) \
404 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
405 ((idx) & RX_SGE_MASK_ELEM_MASK))
406
407#define SGE_MASK_CLEAR_BIT(fp, idx) \
408 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
409 ((idx) & RX_SGE_MASK_ELEM_MASK))
410
411
412
413#define SW_CID(x) (le32_to_cpu(x) & \
414 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
415#define CQE_CMD(x) (le32_to_cpu(x) >> \
416 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
417
418#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
419 le32_to_cpu((bd)->addr_lo))
420#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
421
422
423#define DPM_TRIGER_TYPE 0x40
424#define DOORBELL(bp, cid, val) \
425 do { \
426 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
427 DPM_TRIGER_TYPE); \
428 } while (0)
429
430
431
432#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
433 skb->csum_offset)
434#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
435 skb->csum_offset))
436
437#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
438
439#define XMIT_PLAIN 0
440#define XMIT_CSUM_V4 0x1
441#define XMIT_CSUM_V6 0x2
442#define XMIT_CSUM_TCP 0x4
443#define XMIT_GSO_V4 0x8
444#define XMIT_GSO_V6 0x10
445
446#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
447#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
448
449
450
451
452#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
453
454#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
455#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
456#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
457 (TPA_TYPE_START | TPA_TYPE_END))
458
459#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
460
461#define BNX2X_IP_CSUM_ERR(cqe) \
462 (!((cqe)->fast_path_cqe.status_flags & \
463 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
464 ((cqe)->fast_path_cqe.type_error_flags & \
465 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
466
467#define BNX2X_L4_CSUM_ERR(cqe) \
468 (!((cqe)->fast_path_cqe.status_flags & \
469 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
470 ((cqe)->fast_path_cqe.type_error_flags & \
471 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
472
473#define BNX2X_RX_CSUM_OK(cqe) \
474 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
475
476#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
477 (((le16_to_cpu(flags) & \
478 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
479 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
480 == PRS_FLAG_OVERETH_IPV4)
481#define BNX2X_RX_SUM_FIX(cqe) \
482 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
483
484
485#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
486#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
487
488#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
489#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
490#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
491
492#define BNX2X_RX_SB_INDEX \
493 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
494
495#define BNX2X_RX_SB_BD_INDEX \
496 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
497
498#define BNX2X_RX_SB_INDEX_NUM \
499 (((U_SB_ETH_RX_CQ_INDEX << \
500 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
501 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
502 ((U_SB_ETH_RX_BD_INDEX << \
503 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
504 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
505
506#define BNX2X_TX_SB_INDEX \
507 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
508
509
510
511
512
513
514struct bnx2x_common {
515
516 u32 chip_id;
517
518#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
519
520#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
521#define CHIP_NUM_57710 0x164e
522#define CHIP_NUM_57711 0x164f
523#define CHIP_NUM_57711E 0x1650
524#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
525#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
526#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
527#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
528 CHIP_IS_57711E(bp))
529#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
530
531#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
532#define CHIP_REV_Ax 0x00000000
533
534#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
535
536#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
537 !(CHIP_REV(bp) & 0x00001000))
538
539#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
540 (CHIP_REV(bp) & 0x00001000))
541
542#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
543 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
544
545#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
546#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
547
548 int flash_size;
549#define NVRAM_1MB_SIZE 0x20000
550#define NVRAM_TIMEOUT_COUNT 30000
551#define NVRAM_PAGE_SIZE 256
552
553 u32 shmem_base;
554 u32 shmem2_base;
555
556 u32 hw_config;
557
558 u32 bc_ver;
559};
560
561
562
563
564
565
566struct nig_stats {
567 u32 brb_discard;
568 u32 brb_packet;
569 u32 brb_truncate;
570 u32 flow_ctrl_discard;
571 u32 flow_ctrl_octets;
572 u32 flow_ctrl_packet;
573 u32 mng_discard;
574 u32 mng_octet_inp;
575 u32 mng_octet_out;
576 u32 mng_packet_inp;
577 u32 mng_packet_out;
578 u32 pbf_octets;
579 u32 pbf_packet;
580 u32 safc_inp;
581 u32 egress_mac_pkt0_lo;
582 u32 egress_mac_pkt0_hi;
583 u32 egress_mac_pkt1_lo;
584 u32 egress_mac_pkt1_hi;
585};
586
587struct bnx2x_port {
588 u32 pmf;
589
590 u32 link_config;
591
592 u32 supported;
593
594#define SUPPORTED_2500baseX_Full (1 << 15)
595
596 u32 advertising;
597
598#define ADVERTISED_2500baseX_Full (1 << 15)
599
600 u32 phy_addr;
601
602
603 struct mutex phy_mutex;
604 int need_hw_lock;
605
606 u32 port_stx;
607
608 struct nig_stats old_nig_stats;
609};
610
611
612
613
614enum bnx2x_stats_event {
615 STATS_EVENT_PMF = 0,
616 STATS_EVENT_LINK_UP,
617 STATS_EVENT_UPDATE,
618 STATS_EVENT_STOP,
619 STATS_EVENT_MAX
620};
621
622enum bnx2x_stats_state {
623 STATS_STATE_DISABLED = 0,
624 STATS_STATE_ENABLED,
625 STATS_STATE_MAX
626};
627
628struct bnx2x_eth_stats {
629 u32 total_bytes_received_hi;
630 u32 total_bytes_received_lo;
631 u32 total_bytes_transmitted_hi;
632 u32 total_bytes_transmitted_lo;
633 u32 total_unicast_packets_received_hi;
634 u32 total_unicast_packets_received_lo;
635 u32 total_multicast_packets_received_hi;
636 u32 total_multicast_packets_received_lo;
637 u32 total_broadcast_packets_received_hi;
638 u32 total_broadcast_packets_received_lo;
639 u32 total_unicast_packets_transmitted_hi;
640 u32 total_unicast_packets_transmitted_lo;
641 u32 total_multicast_packets_transmitted_hi;
642 u32 total_multicast_packets_transmitted_lo;
643 u32 total_broadcast_packets_transmitted_hi;
644 u32 total_broadcast_packets_transmitted_lo;
645 u32 valid_bytes_received_hi;
646 u32 valid_bytes_received_lo;
647
648 u32 error_bytes_received_hi;
649 u32 error_bytes_received_lo;
650 u32 etherstatsoverrsizepkts_hi;
651 u32 etherstatsoverrsizepkts_lo;
652 u32 no_buff_discard_hi;
653 u32 no_buff_discard_lo;
654
655 u32 rx_stat_ifhcinbadoctets_hi;
656 u32 rx_stat_ifhcinbadoctets_lo;
657 u32 tx_stat_ifhcoutbadoctets_hi;
658 u32 tx_stat_ifhcoutbadoctets_lo;
659 u32 rx_stat_dot3statsfcserrors_hi;
660 u32 rx_stat_dot3statsfcserrors_lo;
661 u32 rx_stat_dot3statsalignmenterrors_hi;
662 u32 rx_stat_dot3statsalignmenterrors_lo;
663 u32 rx_stat_dot3statscarriersenseerrors_hi;
664 u32 rx_stat_dot3statscarriersenseerrors_lo;
665 u32 rx_stat_falsecarriererrors_hi;
666 u32 rx_stat_falsecarriererrors_lo;
667 u32 rx_stat_etherstatsundersizepkts_hi;
668 u32 rx_stat_etherstatsundersizepkts_lo;
669 u32 rx_stat_dot3statsframestoolong_hi;
670 u32 rx_stat_dot3statsframestoolong_lo;
671 u32 rx_stat_etherstatsfragments_hi;
672 u32 rx_stat_etherstatsfragments_lo;
673 u32 rx_stat_etherstatsjabbers_hi;
674 u32 rx_stat_etherstatsjabbers_lo;
675 u32 rx_stat_maccontrolframesreceived_hi;
676 u32 rx_stat_maccontrolframesreceived_lo;
677 u32 rx_stat_bmac_xpf_hi;
678 u32 rx_stat_bmac_xpf_lo;
679 u32 rx_stat_bmac_xcf_hi;
680 u32 rx_stat_bmac_xcf_lo;
681 u32 rx_stat_xoffstateentered_hi;
682 u32 rx_stat_xoffstateentered_lo;
683 u32 rx_stat_xonpauseframesreceived_hi;
684 u32 rx_stat_xonpauseframesreceived_lo;
685 u32 rx_stat_xoffpauseframesreceived_hi;
686 u32 rx_stat_xoffpauseframesreceived_lo;
687 u32 tx_stat_outxonsent_hi;
688 u32 tx_stat_outxonsent_lo;
689 u32 tx_stat_outxoffsent_hi;
690 u32 tx_stat_outxoffsent_lo;
691 u32 tx_stat_flowcontroldone_hi;
692 u32 tx_stat_flowcontroldone_lo;
693 u32 tx_stat_etherstatscollisions_hi;
694 u32 tx_stat_etherstatscollisions_lo;
695 u32 tx_stat_dot3statssinglecollisionframes_hi;
696 u32 tx_stat_dot3statssinglecollisionframes_lo;
697 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
698 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
699 u32 tx_stat_dot3statsdeferredtransmissions_hi;
700 u32 tx_stat_dot3statsdeferredtransmissions_lo;
701 u32 tx_stat_dot3statsexcessivecollisions_hi;
702 u32 tx_stat_dot3statsexcessivecollisions_lo;
703 u32 tx_stat_dot3statslatecollisions_hi;
704 u32 tx_stat_dot3statslatecollisions_lo;
705 u32 tx_stat_etherstatspkts64octets_hi;
706 u32 tx_stat_etherstatspkts64octets_lo;
707 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
708 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
709 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
710 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
711 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
712 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
713 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
714 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
715 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
716 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
717 u32 tx_stat_etherstatspktsover1522octets_hi;
718 u32 tx_stat_etherstatspktsover1522octets_lo;
719 u32 tx_stat_bmac_2047_hi;
720 u32 tx_stat_bmac_2047_lo;
721 u32 tx_stat_bmac_4095_hi;
722 u32 tx_stat_bmac_4095_lo;
723 u32 tx_stat_bmac_9216_hi;
724 u32 tx_stat_bmac_9216_lo;
725 u32 tx_stat_bmac_16383_hi;
726 u32 tx_stat_bmac_16383_lo;
727 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
728 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
729 u32 tx_stat_bmac_ufl_hi;
730 u32 tx_stat_bmac_ufl_lo;
731
732 u32 pause_frames_received_hi;
733 u32 pause_frames_received_lo;
734 u32 pause_frames_sent_hi;
735 u32 pause_frames_sent_lo;
736
737 u32 etherstatspkts1024octetsto1522octets_hi;
738 u32 etherstatspkts1024octetsto1522octets_lo;
739 u32 etherstatspktsover1522octets_hi;
740 u32 etherstatspktsover1522octets_lo;
741
742 u32 brb_drop_hi;
743 u32 brb_drop_lo;
744 u32 brb_truncate_hi;
745 u32 brb_truncate_lo;
746
747 u32 mac_filter_discard;
748 u32 xxoverflow_discard;
749 u32 brb_truncate_discard;
750 u32 mac_discard;
751
752 u32 driver_xoff;
753 u32 rx_err_discard_pkt;
754 u32 rx_skb_alloc_failed;
755 u32 hw_csum_err;
756
757 u32 nig_timer_max;
758};
759
760#define BNX2X_NUM_STATS 41
761#define STATS_OFFSET32(stat_name) \
762 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
763
764
765#define MAX_CONTEXT 16
766
767union cdu_context {
768 struct eth_context eth;
769 char pad[1024];
770};
771
772#define MAX_DMAE_C 8
773
774
775struct bnx2x_slowpath {
776 union cdu_context context[MAX_CONTEXT];
777 struct eth_stats_query fw_stats;
778 struct mac_configuration_cmd mac_config;
779 struct mac_configuration_cmd mcast_config;
780
781
782 struct dmae_command dmae[MAX_DMAE_C];
783
784 u32 stats_comp;
785 union mac_stats mac_stats;
786 struct nig_stats nig_stats;
787 struct host_port_stats port_stats;
788 struct host_func_stats func_stats;
789 struct host_func_stats func_stats_base;
790
791 u32 wb_comp;
792 u32 wb_data[4];
793};
794
795#define bnx2x_sp(bp, var) (&bp->slowpath->var)
796#define bnx2x_sp_mapping(bp, var) \
797 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
798
799
800
801#define MAX_DYNAMIC_ATTN_GRPS 8
802
803struct attn_route {
804 u32 sig[4];
805};
806
807struct bnx2x {
808
809
810
811 struct bnx2x_fastpath fp[MAX_CONTEXT];
812 void __iomem *regview;
813 void __iomem *doorbells;
814#define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
815
816 struct net_device *dev;
817 struct pci_dev *pdev;
818
819 atomic_t intr_sem;
820 struct msix_entry msix_table[MAX_CONTEXT+1];
821#define INT_MODE_INTx 1
822#define INT_MODE_MSI 2
823#define INT_MODE_MSIX 3
824
825 int tx_ring_size;
826
827#ifdef BCM_VLAN
828 struct vlan_group *vlgrp;
829#endif
830
831 u32 rx_csum;
832 u32 rx_buf_size;
833#define ETH_OVREHEAD (ETH_HLEN + 8)
834#define ETH_MIN_PACKET_SIZE 60
835#define ETH_MAX_PACKET_SIZE 1500
836#define ETH_MAX_JUMBO_PACKET_SIZE 9600
837
838
839#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
840 L1_CACHE_SHIFT : 8)
841#define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
842
843 struct host_def_status_block *def_status_blk;
844#define DEF_SB_ID 16
845 __le16 def_c_idx;
846 __le16 def_u_idx;
847 __le16 def_x_idx;
848 __le16 def_t_idx;
849 __le16 def_att_idx;
850 u32 attn_state;
851 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
852
853
854 struct eth_spe *spq;
855 dma_addr_t spq_mapping;
856 u16 spq_prod_idx;
857 struct eth_spe *spq_prod_bd;
858 struct eth_spe *spq_last_bd;
859 __le16 *dsb_sp_prod;
860 u16 spq_left;
861
862 spinlock_t spq_lock;
863
864
865
866 u8 stats_pending;
867 u8 set_mac_pending;
868
869
870
871 int panic;
872 int msglevel;
873
874 u32 flags;
875#define PCIX_FLAG 1
876#define PCI_32BIT_FLAG 2
877#define ONE_PORT_FLAG 4
878#define NO_WOL_FLAG 8
879#define USING_DAC_FLAG 0x10
880#define USING_MSIX_FLAG 0x20
881#define USING_MSI_FLAG 0x40
882#define TPA_ENABLE_FLAG 0x80
883#define NO_MCP_FLAG 0x100
884#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
885#define HW_VLAN_TX_FLAG 0x400
886#define HW_VLAN_RX_FLAG 0x800
887
888 int func;
889#define BP_PORT(bp) (bp->func % PORT_MAX)
890#define BP_FUNC(bp) (bp->func)
891#define BP_E1HVN(bp) (bp->func >> 1)
892#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
893
894 int pm_cap;
895 int pcie_cap;
896 int mrrs;
897
898 struct delayed_work sp_task;
899 struct work_struct reset_task;
900
901 struct timer_list timer;
902 int current_interval;
903
904 u16 fw_seq;
905 u16 fw_drv_pulse_wr_seq;
906 u32 func_stx;
907
908 struct link_params link_params;
909 struct link_vars link_vars;
910 struct mdio_if_info mdio;
911
912 struct bnx2x_common common;
913 struct bnx2x_port port;
914
915 struct cmng_struct_per_port cmng;
916 u32 vn_weight_sum;
917
918 u32 mf_config;
919 u16 e1hov;
920 u8 e1hmf;
921#define IS_E1HMF(bp) (bp->e1hmf != 0)
922
923 u8 wol;
924
925 int rx_ring_size;
926
927 u16 tx_quick_cons_trip_int;
928 u16 tx_quick_cons_trip;
929 u16 tx_ticks_int;
930 u16 tx_ticks;
931
932 u16 rx_quick_cons_trip_int;
933 u16 rx_quick_cons_trip;
934 u16 rx_ticks_int;
935 u16 rx_ticks;
936
937 u32 lin_cnt;
938
939 int state;
940#define BNX2X_STATE_CLOSED 0
941#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
942#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
943#define BNX2X_STATE_OPEN 0x3000
944#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
945#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
946#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
947#define BNX2X_STATE_DISABLED 0xd000
948#define BNX2X_STATE_DIAG 0xe000
949#define BNX2X_STATE_ERROR 0xf000
950
951 int multi_mode;
952 int num_rx_queues;
953 int num_tx_queues;
954
955 u32 rx_mode;
956#define BNX2X_RX_MODE_NONE 0
957#define BNX2X_RX_MODE_NORMAL 1
958#define BNX2X_RX_MODE_ALLMULTI 2
959#define BNX2X_RX_MODE_PROMISC 3
960#define BNX2X_MAX_MULTICAST 64
961#define BNX2X_MAX_EMUL_MULTI 16
962
963 dma_addr_t def_status_blk_mapping;
964
965 struct bnx2x_slowpath *slowpath;
966 dma_addr_t slowpath_mapping;
967
968#ifdef BCM_ISCSI
969 void *t1;
970 dma_addr_t t1_mapping;
971 void *t2;
972 dma_addr_t t2_mapping;
973 void *timers;
974 dma_addr_t timers_mapping;
975 void *qm;
976 dma_addr_t qm_mapping;
977#endif
978
979 int dropless_fc;
980
981 int dmae_ready;
982
983 struct mutex dmae_mutex;
984
985
986 int stats_state;
987
988 struct dmae_command stats_dmae;
989 int executer_idx;
990
991 u16 stats_counter;
992 struct bnx2x_eth_stats eth_stats;
993
994 struct z_stream_s *strm;
995 void *gunzip_buf;
996 dma_addr_t gunzip_mapping;
997 int gunzip_outlen;
998#define FW_BUF_SIZE 0x8000
999#define GUNZIP_BUF(bp) (bp->gunzip_buf)
1000#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1001#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1002
1003 struct raw_op *init_ops;
1004
1005 u16 *init_ops_offsets;
1006
1007 u32 *init_data;
1008
1009 const u8 *tsem_int_table_data;
1010 const u8 *tsem_pram_data;
1011 const u8 *usem_int_table_data;
1012 const u8 *usem_pram_data;
1013 const u8 *xsem_int_table_data;
1014 const u8 *xsem_pram_data;
1015 const u8 *csem_int_table_data;
1016 const u8 *csem_pram_data;
1017#define INIT_OPS(bp) (bp->init_ops)
1018#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1019#define INIT_DATA(bp) (bp->init_data)
1020#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1021#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1022#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1023#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1024#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1025#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1026#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1027#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1028
1029 const struct firmware *firmware;
1030};
1031
1032
1033#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
1034 : (MAX_CONTEXT/2))
1035#define BNX2X_NUM_QUEUES(bp) (bp->num_rx_queues + bp->num_tx_queues)
1036#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 2)
1037
1038#define for_each_rx_queue(bp, var) \
1039 for (var = 0; var < bp->num_rx_queues; var++)
1040#define for_each_tx_queue(bp, var) \
1041 for (var = bp->num_rx_queues; \
1042 var < BNX2X_NUM_QUEUES(bp); var++)
1043#define for_each_queue(bp, var) \
1044 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1045#define for_each_nondefault_queue(bp, var) \
1046 for (var = 1; var < bp->num_rx_queues; var++)
1047
1048
1049void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1050void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1051 u32 len32);
1052int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1053int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1054int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1055u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1056void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1057void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1058 u32 addr, u32 len);
1059
1060static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1061 int wait)
1062{
1063 u32 val;
1064
1065 do {
1066 val = REG_RD(bp, reg);
1067 if (val == expected)
1068 break;
1069 ms -= wait;
1070 msleep(wait);
1071
1072 } while (ms > 0);
1073
1074 return val;
1075}
1076
1077
1078
1079#define LOAD_NORMAL 0
1080#define LOAD_OPEN 1
1081#define LOAD_DIAG 2
1082#define UNLOAD_NORMAL 0
1083#define UNLOAD_CLOSE 1
1084
1085
1086
1087#define DMAE_CMD_SRC_PCI 0
1088#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1089
1090#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1091#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1092
1093#define DMAE_CMD_C_DST_PCI 0
1094#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1095
1096#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1097
1098#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1099#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1100#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1101#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1102
1103#define DMAE_CMD_PORT_0 0
1104#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1105
1106#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1107#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1108#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1109
1110#define DMAE_LEN32_RD_MAX 0x80
1111#define DMAE_LEN32_WR_MAX 0x400
1112
1113#define DMAE_COMP_VAL 0xe0d0d0ae
1114
1115#define MAX_DMAE_C_PER_PORT 8
1116#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1117 BP_E1HVN(bp))
1118#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1119 E1HVN_MAX)
1120
1121
1122
1123#define PCICFG_LINK_WIDTH 0x1f00000
1124#define PCICFG_LINK_WIDTH_SHIFT 20
1125#define PCICFG_LINK_SPEED 0xf0000
1126#define PCICFG_LINK_SPEED_SHIFT 16
1127
1128
1129#define BNX2X_NUM_TESTS 7
1130
1131#define BNX2X_PHY_LOOPBACK 0
1132#define BNX2X_MAC_LOOPBACK 1
1133#define BNX2X_PHY_LOOPBACK_FAILED 1
1134#define BNX2X_MAC_LOOPBACK_FAILED 2
1135#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1136 BNX2X_PHY_LOOPBACK_FAILED)
1137
1138
1139#define STROM_ASSERT_ARRAY_SIZE 50
1140
1141
1142
1143#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1144 (BP_E1HVN(bp) << 17) | (x))
1145
1146#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1147#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1148
1149
1150#define BNX2X_BTR 3
1151#define MAX_SPQ_PENDING 8
1152
1153
1154
1155
1156#define DEF_MIN_RATE 100
1157
1158#define RS_PERIODIC_TIMEOUT_USEC 100
1159
1160
1161#define T_FAIR_COEF 10000000
1162
1163
1164#define QM_ARB_BYTES 40000
1165#define FAIR_MEM 2
1166
1167
1168#define ATTN_NIG_FOR_FUNC (1L << 8)
1169#define ATTN_SW_TIMER_4_FUNC (1L << 9)
1170#define GPIO_2_FUNC (1L << 10)
1171#define GPIO_3_FUNC (1L << 11)
1172#define GPIO_4_FUNC (1L << 12)
1173#define ATTN_GENERAL_ATTN_1 (1L << 13)
1174#define ATTN_GENERAL_ATTN_2 (1L << 14)
1175#define ATTN_GENERAL_ATTN_3 (1L << 15)
1176#define ATTN_GENERAL_ATTN_4 (1L << 13)
1177#define ATTN_GENERAL_ATTN_5 (1L << 14)
1178#define ATTN_GENERAL_ATTN_6 (1L << 15)
1179
1180#define ATTN_HARD_WIRED_MASK 0xff00
1181#define ATTENTION_ID 4
1182
1183
1184
1185
1186#define BNX2X_PMF_LINK_ASSERT \
1187 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1188
1189#define BNX2X_MC_ASSERT_BITS \
1190 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1191 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1192 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1193 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1194
1195#define BNX2X_MCP_ASSERT \
1196 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1197
1198#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1199#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1200 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1201 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1202 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1203 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1204 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1205
1206#define HW_INTERRUT_ASSERT_SET_0 \
1207 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1208 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1209 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1210 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1211#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1212 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1213 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1214 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1215 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1216#define HW_INTERRUT_ASSERT_SET_1 \
1217 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1218 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1219 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1220 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1221 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1222 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1223 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1224 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1225 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1226 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1227 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1228#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1229 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1230 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1231 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1232 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1233 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1234 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1235 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1236 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1237 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1238 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1239#define HW_INTERRUT_ASSERT_SET_2 \
1240 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1241 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1242 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1243 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1244 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1245#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1246 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1247 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1248 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1249 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1250 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1251 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1252
1253
1254#define MULTI_FLAGS(bp) \
1255 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1256 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1257 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1258 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1259 (bp->multi_mode << \
1260 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1261#define MULTI_MASK 0x7f
1262
1263
1264#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1265#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1266#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1267#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1268
1269#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1270
1271#define BNX2X_SP_DSB_INDEX \
1272(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1273
1274
1275#define CAM_IS_INVALID(x) \
1276(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1277
1278#define CAM_INVALIDATE(x) \
1279 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1280
1281
1282
1283#define MC_HASH_SIZE 8
1284#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1285 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1286
1287
1288#ifndef PXP2_REG_PXP2_INT_STS
1289#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1290#endif
1291
1292
1293
1294#endif
1295
