LXR linux/drivers/net/chelsio/cphy.h

   1/*****************************************************************************
   2 *                                                                           *
   3 * File: cphy.h                                                              *
   4 * $Revision: 1.7 $                                                          *
   5 * $Date: 2005/06/21 18:29:47 $                                              *
   6 * Description:                                                              *
   7 *  part of the Chelsio 10Gb Ethernet Driver.                                *
   8 *                                                                           *
   9 * This program is free software; you can redistribute it and/or modify      *
  10 * it under the terms of the GNU General Public License, version 2, as       *
  11 * published by the Free Software Foundation.                                *
  12 *                                                                           *
  13 * You should have received a copy of the GNU General Public License along   *
  14 * with this program; if not, write to the Free Software Foundation, Inc.,   *
  15 * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
  16 *                                                                           *
  17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  20 *                                                                           *
  21 * http://www.chelsio.com                                                    *
  22 *                                                                           *
  23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  24 * All rights reserved.                                                      *
  25 *                                                                           *
  26 * Maintainers: maintainers@chelsio.com                                      *
  27 *                                                                           *
  28 * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  29 *          Tina Yang               <tainay@chelsio.com>                     *
  30 *          Felix Marti             <felix@chelsio.com>                      *
  31 *          Scott Bardone           <sbardone@chelsio.com>                   *
  32 *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  33 *          Frank DiMambro          <frank@chelsio.com>                      *
  34 *                                                                           *
  35 * History:                                                                  *
  36 *                                                                           *
  37 ****************************************************************************/
  38
  39#ifndef _CXGB_CPHY_H_
  40#define _CXGB_CPHY_H_
  41
  42#include "common.h"
  43
  44struct mdio_ops {
  45        void (*init)(adapter_t *adapter, const struct board_info *bi);
  46        int  (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
  47                     u16 reg_addr);
  48        int  (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
  49                      u16 reg_addr, u16 val);
  50        unsigned mode_support;
  51};
  52
  53/* PHY interrupt types */
  54enum {
  55        cphy_cause_link_change = 0x1,
  56        cphy_cause_error = 0x2,
  57        cphy_cause_fifo_error = 0x3
  58};
  59
  60enum {
  61        PHY_LINK_UP = 0x1,
  62        PHY_AUTONEG_RDY = 0x2,
  63        PHY_AUTONEG_EN = 0x4
  64};
  65
  66struct cphy;
  67
  68/* PHY operations */
  69struct cphy_ops {
  70        void (*destroy)(struct cphy *);
  71        int (*reset)(struct cphy *, int wait);
  72
  73        int (*interrupt_enable)(struct cphy *);
  74        int (*interrupt_disable)(struct cphy *);
  75        int (*interrupt_clear)(struct cphy *);
  76        int (*interrupt_handler)(struct cphy *);
  77
  78        int (*autoneg_enable)(struct cphy *);
  79        int (*autoneg_disable)(struct cphy *);
  80        int (*autoneg_restart)(struct cphy *);
  81
  82        int (*advertise)(struct cphy *phy, unsigned int advertise_map);
  83        int (*set_loopback)(struct cphy *, int on);
  84        int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
  85        int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
  86                               int *duplex, int *fc);
  87
  88        u32 mmds;
  89};
  90
  91/* A PHY instance */
  92struct cphy {
  93        int state;      /* Link status state machine */
  94        adapter_t *adapter;                  /* associated adapter */
  95
  96        struct delayed_work phy_update;
  97
  98        u16 bmsr;
  99        int count;
 100        int act_count;
 101        int act_on;
 102
 103        u32 elmer_gpo;
 104
 105        const struct cphy_ops *ops;            /* PHY operations */
 106        struct mdio_if_info mdio;
 107        struct cphy_instance *instance;
 108};
 109
 110/* Convenience MDIO read/write wrappers */
 111static inline int cphy_mdio_read(struct cphy *cphy, int mmd, int reg,
 112                                 unsigned int *valp)
 113{
 114        int rc = cphy->mdio.mdio_read(cphy->mdio.dev, cphy->mdio.prtad, mmd,
 115                                      reg);
 116        *valp = (rc >= 0) ? rc : -1;
 117        return (rc >= 0) ? 0 : rc;
 118}
 119
 120static inline int cphy_mdio_write(struct cphy *cphy, int mmd, int reg,
 121                                  unsigned int val)
 122{
 123        return cphy->mdio.mdio_write(cphy->mdio.dev, cphy->mdio.prtad, mmd,
 124                                     reg, val);
 125}
 126
 127static inline int simple_mdio_read(struct cphy *cphy, int reg,
 128                                   unsigned int *valp)
 129{
 130        return cphy_mdio_read(cphy, MDIO_DEVAD_NONE, reg, valp);
 131}
 132
 133static inline int simple_mdio_write(struct cphy *cphy, int reg,
 134                                    unsigned int val)
 135{
 136        return cphy_mdio_write(cphy, MDIO_DEVAD_NONE, reg, val);
 137}
 138
 139/* Convenience initializer */
 140static inline void cphy_init(struct cphy *phy, struct net_device *dev,
 141                             int phy_addr, struct cphy_ops *phy_ops,
 142                             const struct mdio_ops *mdio_ops)
 143{
 144        struct adapter *adapter = netdev_priv(dev);
 145        phy->adapter = adapter;
 146        phy->ops     = phy_ops;
 147        if (mdio_ops) {
 148                phy->mdio.prtad = phy_addr;
 149                phy->mdio.mmds = phy_ops->mmds;
 150                phy->mdio.mode_support = mdio_ops->mode_support;
 151                phy->mdio.mdio_read = mdio_ops->read;
 152                phy->mdio.mdio_write = mdio_ops->write;
 153        }
 154        phy->mdio.dev = dev;
 155}
 156
 157/* Operations of the PHY-instance factory */
 158struct gphy {
 159        /* Construct a PHY instance with the given PHY address */
 160        struct cphy *(*create)(struct net_device *dev, int phy_addr,
 161                               const struct mdio_ops *mdio_ops);
 162
 163        /*
 164         * Reset the PHY chip.  This resets the whole PHY chip, not individual
 165         * ports.
 166         */
 167        int (*reset)(adapter_t *adapter);
 168};
 169
 170extern const struct gphy t1_my3126_ops;
 171extern const struct gphy t1_mv88e1xxx_ops;
 172extern const struct gphy t1_vsc8244_ops;
 173extern const struct gphy t1_mv88x201x_ops;
 174
 175#endif /* _CXGB_CPHY_H_ */
 176