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33#include "e1000_hw.h"
34
35static s32 e1000_check_downshift(struct e1000_hw *hw);
36static s32 e1000_check_polarity(struct e1000_hw *hw,
37 e1000_rev_polarity *polarity);
38static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39static void e1000_clear_vfta(struct e1000_hw *hw);
40static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
41 bool link_up);
42static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
44static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
45static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
46 u16 *max_length);
47static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
48static s32 e1000_id_led_init(struct e1000_hw *hw);
49static void e1000_init_rx_addrs(struct e1000_hw *hw);
50static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
51 struct e1000_phy_info *phy_info);
52static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
53 struct e1000_phy_info *phy_info);
54static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
55static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57static s32 e1000_set_phy_type(struct e1000_hw *hw);
58static void e1000_phy_init_script(struct e1000_hw *hw);
59static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
66static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
67static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
70 u16 words, u16 *data);
71static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
72 u16 words, u16 *data);
73static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
76static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
77static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
78 u16 phy_data);
79static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
80 u16 *phy_data);
81static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
83static void e1000_release_eeprom(struct e1000_hw *hw);
84static void e1000_standby_eeprom(struct e1000_hw *hw);
85static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87static s32 e1000_set_phy_mode(struct e1000_hw *hw);
88static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
89 u16 *data);
90static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
91 u16 *data);
92
93
94static const
95u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
102 100,
103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
104 110, 110,
105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
106 120, 120
107};
108
109static DEFINE_SPINLOCK(e1000_eeprom_lock);
110
111
112
113
114
115static s32 e1000_set_phy_type(struct e1000_hw *hw)
116{
117 DEBUGFUNC("e1000_set_phy_type");
118
119 if (hw->mac_type == e1000_undefined)
120 return -E1000_ERR_PHY_TYPE;
121
122 switch (hw->phy_id) {
123 case M88E1000_E_PHY_ID:
124 case M88E1000_I_PHY_ID:
125 case M88E1011_I_PHY_ID:
126 case M88E1111_I_PHY_ID:
127 hw->phy_type = e1000_phy_m88;
128 break;
129 case IGP01E1000_I_PHY_ID:
130 if (hw->mac_type == e1000_82541 ||
131 hw->mac_type == e1000_82541_rev_2 ||
132 hw->mac_type == e1000_82547 ||
133 hw->mac_type == e1000_82547_rev_2) {
134 hw->phy_type = e1000_phy_igp;
135 break;
136 }
137 default:
138
139 hw->phy_type = e1000_phy_undefined;
140 return -E1000_ERR_PHY_TYPE;
141 }
142
143 return E1000_SUCCESS;
144}
145
146
147
148
149
150static void e1000_phy_init_script(struct e1000_hw *hw)
151{
152 u32 ret_val;
153 u16 phy_saved_data;
154
155 DEBUGFUNC("e1000_phy_init_script");
156
157 if (hw->phy_init_script) {
158 msleep(20);
159
160
161
162 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
163
164
165 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
166 msleep(20);
167
168 e1000_write_phy_reg(hw, 0x0000, 0x0140);
169 msleep(5);
170
171 switch (hw->mac_type) {
172 case e1000_82541:
173 case e1000_82547:
174 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
175 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
176 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
177 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
178 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
179 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
180 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
181 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
182 e1000_write_phy_reg(hw, 0x2010, 0x0008);
183 break;
184
185 case e1000_82541_rev_2:
186 case e1000_82547_rev_2:
187 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
188 break;
189 default:
190 break;
191 }
192
193 e1000_write_phy_reg(hw, 0x0000, 0x3300);
194 msleep(20);
195
196
197 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
198
199 if (hw->mac_type == e1000_82547) {
200 u16 fused, fine, coarse;
201
202
203 e1000_read_phy_reg(hw,
204 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
205 &fused);
206
207 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
208 e1000_read_phy_reg(hw,
209 IGP01E1000_ANALOG_FUSE_STATUS,
210 &fused);
211
212 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
213 coarse =
214 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
215
216 if (coarse >
217 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
218 coarse -=
219 IGP01E1000_ANALOG_FUSE_COARSE_10;
220 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
221 } else if (coarse ==
222 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
223 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
224
225 fused =
226 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
227 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
228 (coarse &
229 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
230
231 e1000_write_phy_reg(hw,
232 IGP01E1000_ANALOG_FUSE_CONTROL,
233 fused);
234 e1000_write_phy_reg(hw,
235 IGP01E1000_ANALOG_FUSE_BYPASS,
236 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
237 }
238 }
239 }
240}
241
242
243
244
245
246s32 e1000_set_mac_type(struct e1000_hw *hw)
247{
248 DEBUGFUNC("e1000_set_mac_type");
249
250 switch (hw->device_id) {
251 case E1000_DEV_ID_82542:
252 switch (hw->revision_id) {
253 case E1000_82542_2_0_REV_ID:
254 hw->mac_type = e1000_82542_rev2_0;
255 break;
256 case E1000_82542_2_1_REV_ID:
257 hw->mac_type = e1000_82542_rev2_1;
258 break;
259 default:
260
261 return -E1000_ERR_MAC_TYPE;
262 }
263 break;
264 case E1000_DEV_ID_82543GC_FIBER:
265 case E1000_DEV_ID_82543GC_COPPER:
266 hw->mac_type = e1000_82543;
267 break;
268 case E1000_DEV_ID_82544EI_COPPER:
269 case E1000_DEV_ID_82544EI_FIBER:
270 case E1000_DEV_ID_82544GC_COPPER:
271 case E1000_DEV_ID_82544GC_LOM:
272 hw->mac_type = e1000_82544;
273 break;
274 case E1000_DEV_ID_82540EM:
275 case E1000_DEV_ID_82540EM_LOM:
276 case E1000_DEV_ID_82540EP:
277 case E1000_DEV_ID_82540EP_LOM:
278 case E1000_DEV_ID_82540EP_LP:
279 hw->mac_type = e1000_82540;
280 break;
281 case E1000_DEV_ID_82545EM_COPPER:
282 case E1000_DEV_ID_82545EM_FIBER:
283 hw->mac_type = e1000_82545;
284 break;
285 case E1000_DEV_ID_82545GM_COPPER:
286 case E1000_DEV_ID_82545GM_FIBER:
287 case E1000_DEV_ID_82545GM_SERDES:
288 hw->mac_type = e1000_82545_rev_3;
289 break;
290 case E1000_DEV_ID_82546EB_COPPER:
291 case E1000_DEV_ID_82546EB_FIBER:
292 case E1000_DEV_ID_82546EB_QUAD_COPPER:
293 hw->mac_type = e1000_82546;
294 break;
295 case E1000_DEV_ID_82546GB_COPPER:
296 case E1000_DEV_ID_82546GB_FIBER:
297 case E1000_DEV_ID_82546GB_SERDES:
298 case E1000_DEV_ID_82546GB_PCIE:
299 case E1000_DEV_ID_82546GB_QUAD_COPPER:
300 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
301 hw->mac_type = e1000_82546_rev_3;
302 break;
303 case E1000_DEV_ID_82541EI:
304 case E1000_DEV_ID_82541EI_MOBILE:
305 case E1000_DEV_ID_82541ER_LOM:
306 hw->mac_type = e1000_82541;
307 break;
308 case E1000_DEV_ID_82541ER:
309 case E1000_DEV_ID_82541GI:
310 case E1000_DEV_ID_82541GI_LF:
311 case E1000_DEV_ID_82541GI_MOBILE:
312 hw->mac_type = e1000_82541_rev_2;
313 break;
314 case E1000_DEV_ID_82547EI:
315 case E1000_DEV_ID_82547EI_MOBILE:
316 hw->mac_type = e1000_82547;
317 break;
318 case E1000_DEV_ID_82547GI:
319 hw->mac_type = e1000_82547_rev_2;
320 break;
321 default:
322
323 return -E1000_ERR_MAC_TYPE;
324 }
325
326 switch (hw->mac_type) {
327 case e1000_82541:
328 case e1000_82547:
329 case e1000_82541_rev_2:
330 case e1000_82547_rev_2:
331 hw->asf_firmware_present = true;
332 break;
333 default:
334 break;
335 }
336
337
338
339
340 if (hw->mac_type == e1000_82543)
341 hw->bad_tx_carr_stats_fd = true;
342
343 if (hw->mac_type > e1000_82544)
344 hw->has_smbus = true;
345
346 return E1000_SUCCESS;
347}
348
349
350
351
352
353void e1000_set_media_type(struct e1000_hw *hw)
354{
355 u32 status;
356
357 DEBUGFUNC("e1000_set_media_type");
358
359 if (hw->mac_type != e1000_82543) {
360
361 hw->tbi_compatibility_en = false;
362 }
363
364 switch (hw->device_id) {
365 case E1000_DEV_ID_82545GM_SERDES:
366 case E1000_DEV_ID_82546GB_SERDES:
367 hw->media_type = e1000_media_type_internal_serdes;
368 break;
369 default:
370 switch (hw->mac_type) {
371 case e1000_82542_rev2_0:
372 case e1000_82542_rev2_1:
373 hw->media_type = e1000_media_type_fiber;
374 break;
375 default:
376 status = er32(STATUS);
377 if (status & E1000_STATUS_TBIMODE) {
378 hw->media_type = e1000_media_type_fiber;
379
380 hw->tbi_compatibility_en = false;
381 } else {
382 hw->media_type = e1000_media_type_copper;
383 }
384 break;
385 }
386 }
387}
388
389
390
391
392
393
394
395s32 e1000_reset_hw(struct e1000_hw *hw)
396{
397 u32 ctrl;
398 u32 ctrl_ext;
399 u32 icr;
400 u32 manc;
401 u32 led_ctrl;
402 s32 ret_val;
403
404 DEBUGFUNC("e1000_reset_hw");
405
406
407 if (hw->mac_type == e1000_82542_rev2_0) {
408 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
409 e1000_pci_clear_mwi(hw);
410 }
411
412
413 DEBUGOUT("Masking off all interrupts\n");
414 ew32(IMC, 0xffffffff);
415
416
417
418
419
420 ew32(RCTL, 0);
421 ew32(TCTL, E1000_TCTL_PSP);
422 E1000_WRITE_FLUSH();
423
424
425 hw->tbi_compatibility_on = false;
426
427
428
429
430 msleep(10);
431
432 ctrl = er32(CTRL);
433
434
435 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
436 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
437 msleep(5);
438 }
439
440
441
442
443
444
445 DEBUGOUT("Issuing a global reset to MAC\n");
446
447 switch (hw->mac_type) {
448 case e1000_82544:
449 case e1000_82540:
450 case e1000_82545:
451 case e1000_82546:
452 case e1000_82541:
453 case e1000_82541_rev_2:
454
455
456 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
457 break;
458 case e1000_82545_rev_3:
459 case e1000_82546_rev_3:
460
461 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
462 break;
463 default:
464 ew32(CTRL, (ctrl | E1000_CTRL_RST));
465 break;
466 }
467
468
469
470
471
472 switch (hw->mac_type) {
473 case e1000_82542_rev2_0:
474 case e1000_82542_rev2_1:
475 case e1000_82543:
476 case e1000_82544:
477
478 udelay(10);
479 ctrl_ext = er32(CTRL_EXT);
480 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
481 ew32(CTRL_EXT, ctrl_ext);
482 E1000_WRITE_FLUSH();
483
484 msleep(2);
485 break;
486 case e1000_82541:
487 case e1000_82541_rev_2:
488 case e1000_82547:
489 case e1000_82547_rev_2:
490
491 msleep(20);
492 break;
493 default:
494
495 ret_val = e1000_get_auto_rd_done(hw);
496 if (ret_val)
497 return ret_val;
498 break;
499 }
500
501
502 if (hw->mac_type >= e1000_82540) {
503 manc = er32(MANC);
504 manc &= ~(E1000_MANC_ARP_EN);
505 ew32(MANC, manc);
506 }
507
508 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
509 e1000_phy_init_script(hw);
510
511
512 led_ctrl = er32(LEDCTL);
513 led_ctrl &= IGP_ACTIVITY_LED_MASK;
514 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
515 ew32(LEDCTL, led_ctrl);
516 }
517
518
519 DEBUGOUT("Masking off all interrupts\n");
520 ew32(IMC, 0xffffffff);
521
522
523 icr = er32(ICR);
524
525
526 if (hw->mac_type == e1000_82542_rev2_0) {
527 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
528 e1000_pci_set_mwi(hw);
529 }
530
531 return E1000_SUCCESS;
532}
533
534
535
536
537
538
539
540
541
542
543
544s32 e1000_init_hw(struct e1000_hw *hw)
545{
546 u32 ctrl;
547 u32 i;
548 s32 ret_val;
549 u32 mta_size;
550 u32 ctrl_ext;
551
552 DEBUGFUNC("e1000_init_hw");
553
554
555 ret_val = e1000_id_led_init(hw);
556 if (ret_val) {
557 DEBUGOUT("Error Initializing Identification LED\n");
558 return ret_val;
559 }
560
561
562 e1000_set_media_type(hw);
563
564
565 DEBUGOUT("Initializing the IEEE VLAN\n");
566 if (hw->mac_type < e1000_82545_rev_3)
567 ew32(VET, 0);
568 e1000_clear_vfta(hw);
569
570
571 if (hw->mac_type == e1000_82542_rev2_0) {
572 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
573 e1000_pci_clear_mwi(hw);
574 ew32(RCTL, E1000_RCTL_RST);
575 E1000_WRITE_FLUSH();
576 msleep(5);
577 }
578
579
580
581
582 e1000_init_rx_addrs(hw);
583
584
585 if (hw->mac_type == e1000_82542_rev2_0) {
586 ew32(RCTL, 0);
587 E1000_WRITE_FLUSH();
588 msleep(1);
589 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
590 e1000_pci_set_mwi(hw);
591 }
592
593
594 DEBUGOUT("Zeroing the MTA\n");
595 mta_size = E1000_MC_TBL_SIZE;
596 for (i = 0; i < mta_size; i++) {
597 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
598
599
600 E1000_WRITE_FLUSH();
601 }
602
603
604
605
606
607
608 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
609 ctrl = er32(CTRL);
610 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
611 }
612
613 switch (hw->mac_type) {
614 case e1000_82545_rev_3:
615 case e1000_82546_rev_3:
616 break;
617 default:
618
619 if (hw->bus_type == e1000_bus_type_pcix
620 && e1000_pcix_get_mmrbc(hw) > 2048)
621 e1000_pcix_set_mmrbc(hw, 2048);
622 break;
623 }
624
625
626 ret_val = e1000_setup_link(hw);
627
628
629 if (hw->mac_type > e1000_82544) {
630 ctrl = er32(TXDCTL);
631 ctrl =
632 (ctrl & ~E1000_TXDCTL_WTHRESH) |
633 E1000_TXDCTL_FULL_TX_DESC_WB;
634 ew32(TXDCTL, ctrl);
635 }
636
637
638
639
640
641
642 e1000_clear_hw_cntrs(hw);
643
644 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
645 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
646 ctrl_ext = er32(CTRL_EXT);
647
648
649 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
650 ew32(CTRL_EXT, ctrl_ext);
651 }
652
653 return ret_val;
654}
655
656
657
658
659
660static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
661{
662 u16 eeprom_data;
663 s32 ret_val;
664
665 DEBUGFUNC("e1000_adjust_serdes_amplitude");
666
667 if (hw->media_type != e1000_media_type_internal_serdes)
668 return E1000_SUCCESS;
669
670 switch (hw->mac_type) {
671 case e1000_82545_rev_3:
672 case e1000_82546_rev_3:
673 break;
674 default:
675 return E1000_SUCCESS;
676 }
677
678 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
679 &eeprom_data);
680 if (ret_val) {
681 return ret_val;
682 }
683
684 if (eeprom_data != EEPROM_RESERVED_WORD) {
685
686 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
687 ret_val =
688 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
689 if (ret_val)
690 return ret_val;
691 }
692
693 return E1000_SUCCESS;
694}
695
696
697
698
699
700
701
702
703
704
705
706s32 e1000_setup_link(struct e1000_hw *hw)
707{
708 u32 ctrl_ext;
709 s32 ret_val;
710 u16 eeprom_data;
711
712 DEBUGFUNC("e1000_setup_link");
713
714
715
716
717
718
719
720
721
722 if (hw->fc == E1000_FC_DEFAULT) {
723 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
724 1, &eeprom_data);
725 if (ret_val) {
726 DEBUGOUT("EEPROM Read Error\n");
727 return -E1000_ERR_EEPROM;
728 }
729 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
730 hw->fc = E1000_FC_NONE;
731 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
732 EEPROM_WORD0F_ASM_DIR)
733 hw->fc = E1000_FC_TX_PAUSE;
734 else
735 hw->fc = E1000_FC_FULL;
736 }
737
738
739
740
741
742 if (hw->mac_type == e1000_82542_rev2_0)
743 hw->fc &= (~E1000_FC_TX_PAUSE);
744
745 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
746 hw->fc &= (~E1000_FC_RX_PAUSE);
747
748 hw->original_fc = hw->fc;
749
750 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
751
752
753
754
755
756
757
758
759 if (hw->mac_type == e1000_82543) {
760 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
761 1, &eeprom_data);
762 if (ret_val) {
763 DEBUGOUT("EEPROM Read Error\n");
764 return -E1000_ERR_EEPROM;
765 }
766 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
767 SWDPIO__EXT_SHIFT);
768 ew32(CTRL_EXT, ctrl_ext);
769 }
770
771
772 ret_val = (hw->media_type == e1000_media_type_copper) ?
773 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
774
775
776
777
778
779
780 DEBUGOUT
781 ("Initializing the Flow Control address, type and timer regs\n");
782
783 ew32(FCT, FLOW_CONTROL_TYPE);
784 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
785 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
786
787 ew32(FCTTV, hw->fc_pause_time);
788
789
790
791
792
793
794
795 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
796 ew32(FCRTL, 0);
797 ew32(FCRTH, 0);
798 } else {
799
800
801
802 if (hw->fc_send_xon) {
803 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
804 ew32(FCRTH, hw->fc_high_water);
805 } else {
806 ew32(FCRTL, hw->fc_low_water);
807 ew32(FCRTH, hw->fc_high_water);
808 }
809 }
810 return ret_val;
811}
812
813
814
815
816
817
818
819
820
821static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
822{
823 u32 ctrl;
824 u32 status;
825 u32 txcw = 0;
826 u32 i;
827 u32 signal = 0;
828 s32 ret_val;
829
830 DEBUGFUNC("e1000_setup_fiber_serdes_link");
831
832
833
834
835
836
837
838 ctrl = er32(CTRL);
839 if (hw->media_type == e1000_media_type_fiber)
840 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
841
842 ret_val = e1000_adjust_serdes_amplitude(hw);
843 if (ret_val)
844 return ret_val;
845
846
847 ctrl &= ~(E1000_CTRL_LRST);
848
849
850 ret_val = e1000_set_vco_speed(hw);
851 if (ret_val)
852 return ret_val;
853
854 e1000_config_collision_dist(hw);
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871 switch (hw->fc) {
872 case E1000_FC_NONE:
873
874 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
875 break;
876 case E1000_FC_RX_PAUSE:
877
878
879
880
881
882
883 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
884 break;
885 case E1000_FC_TX_PAUSE:
886
887
888
889 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
890 break;
891 case E1000_FC_FULL:
892
893 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
894 break;
895 default:
896 DEBUGOUT("Flow control param set incorrectly\n");
897 return -E1000_ERR_CONFIG;
898 break;
899 }
900
901
902
903
904
905
906
907 DEBUGOUT("Auto-negotiation enabled\n");
908
909 ew32(TXCW, txcw);
910 ew32(CTRL, ctrl);
911 E1000_WRITE_FLUSH();
912
913 hw->txcw = txcw;
914 msleep(1);
915
916
917
918
919
920
921
922 if (hw->media_type == e1000_media_type_internal_serdes ||
923 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
924 DEBUGOUT("Looking for Link\n");
925 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
926 msleep(10);
927 status = er32(STATUS);
928 if (status & E1000_STATUS_LU)
929 break;
930 }
931 if (i == (LINK_UP_TIMEOUT / 10)) {
932 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
933 hw->autoneg_failed = 1;
934
935
936
937
938
939 ret_val = e1000_check_for_link(hw);
940 if (ret_val) {
941 DEBUGOUT("Error while checking for link\n");
942 return ret_val;
943 }
944 hw->autoneg_failed = 0;
945 } else {
946 hw->autoneg_failed = 0;
947 DEBUGOUT("Valid Link Found\n");
948 }
949 } else {
950 DEBUGOUT("No Signal Detected\n");
951 }
952 return E1000_SUCCESS;
953}
954
955
956
957
958
959
960
961static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
962{
963 u32 ctrl;
964 s32 ret_val;
965 u16 phy_data;
966
967 DEBUGFUNC("e1000_copper_link_preconfig");
968
969 ctrl = er32(CTRL);
970
971
972
973
974 if (hw->mac_type > e1000_82543) {
975 ctrl |= E1000_CTRL_SLU;
976 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
977 ew32(CTRL, ctrl);
978 } else {
979 ctrl |=
980 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
981 ew32(CTRL, ctrl);
982 ret_val = e1000_phy_hw_reset(hw);
983 if (ret_val)
984 return ret_val;
985 }
986
987
988 ret_val = e1000_detect_gig_phy(hw);
989 if (ret_val) {
990 DEBUGOUT("Error, did not detect valid phy.\n");
991 return ret_val;
992 }
993 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
994
995
996 ret_val = e1000_set_phy_mode(hw);
997 if (ret_val)
998 return ret_val;
999
1000 if ((hw->mac_type == e1000_82545_rev_3) ||
1001 (hw->mac_type == e1000_82546_rev_3)) {
1002 ret_val =
1003 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1004 phy_data |= 0x00000008;
1005 ret_val =
1006 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1007 }
1008
1009 if (hw->mac_type <= e1000_82543 ||
1010 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1011 hw->mac_type == e1000_82541_rev_2
1012 || hw->mac_type == e1000_82547_rev_2)
1013 hw->phy_reset_disable = false;
1014
1015 return E1000_SUCCESS;
1016}
1017
1018
1019
1020
1021
1022static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1023{
1024 u32 led_ctrl;
1025 s32 ret_val;
1026 u16 phy_data;
1027
1028 DEBUGFUNC("e1000_copper_link_igp_setup");
1029
1030 if (hw->phy_reset_disable)
1031 return E1000_SUCCESS;
1032
1033 ret_val = e1000_phy_reset(hw);
1034 if (ret_val) {
1035 DEBUGOUT("Error Resetting the PHY\n");
1036 return ret_val;
1037 }
1038
1039
1040 msleep(15);
1041
1042 led_ctrl = er32(LEDCTL);
1043 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1044 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1045 ew32(LEDCTL, led_ctrl);
1046
1047
1048 if (hw->phy_type == e1000_phy_igp) {
1049
1050 ret_val = e1000_set_d3_lplu_state(hw, false);
1051 if (ret_val) {
1052 DEBUGOUT("Error Disabling LPLU D3\n");
1053 return ret_val;
1054 }
1055 }
1056
1057
1058 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1059 if (ret_val)
1060 return ret_val;
1061
1062 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1063 hw->dsp_config_state = e1000_dsp_config_disabled;
1064
1065 phy_data &=
1066 ~(IGP01E1000_PSCR_AUTO_MDIX |
1067 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1068 hw->mdix = 1;
1069
1070 } else {
1071 hw->dsp_config_state = e1000_dsp_config_enabled;
1072 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1073
1074 switch (hw->mdix) {
1075 case 1:
1076 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1077 break;
1078 case 2:
1079 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1080 break;
1081 case 0:
1082 default:
1083 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1084 break;
1085 }
1086 }
1087 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1088 if (ret_val)
1089 return ret_val;
1090
1091
1092 if (hw->autoneg) {
1093 e1000_ms_type phy_ms_setting = hw->master_slave;
1094
1095 if (hw->ffe_config_state == e1000_ffe_config_active)
1096 hw->ffe_config_state = e1000_ffe_config_enabled;
1097
1098 if (hw->dsp_config_state == e1000_dsp_config_activated)
1099 hw->dsp_config_state = e1000_dsp_config_enabled;
1100
1101
1102
1103
1104 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1105
1106 ret_val =
1107 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1108 &phy_data);
1109 if (ret_val)
1110 return ret_val;
1111 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1112 ret_val =
1113 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1114 phy_data);
1115 if (ret_val)
1116 return ret_val;
1117
1118 ret_val =
1119 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1120 if (ret_val)
1121 return ret_val;
1122 phy_data &= ~CR_1000T_MS_ENABLE;
1123 ret_val =
1124 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1125 if (ret_val)
1126 return ret_val;
1127 }
1128
1129 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1130 if (ret_val)
1131 return ret_val;
1132
1133
1134 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1135 ((phy_data & CR_1000T_MS_VALUE) ?
1136 e1000_ms_force_master :
1137 e1000_ms_force_slave) : e1000_ms_auto;
1138
1139 switch (phy_ms_setting) {
1140 case e1000_ms_force_master:
1141 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1142 break;
1143 case e1000_ms_force_slave:
1144 phy_data |= CR_1000T_MS_ENABLE;
1145 phy_data &= ~(CR_1000T_MS_VALUE);
1146 break;
1147 case e1000_ms_auto:
1148 phy_data &= ~CR_1000T_MS_ENABLE;
1149 default:
1150 break;
1151 }
1152 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1153 if (ret_val)
1154 return ret_val;
1155 }
1156
1157 return E1000_SUCCESS;
1158}
1159
1160
1161
1162
1163
1164static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1165{
1166 s32 ret_val;
1167 u16 phy_data;
1168
1169 DEBUGFUNC("e1000_copper_link_mgp_setup");
1170
1171 if (hw->phy_reset_disable)
1172 return E1000_SUCCESS;
1173
1174
1175 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1176 if (ret_val)
1177 return ret_val;
1178
1179 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1180
1181
1182
1183
1184
1185
1186
1187
1188 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1189
1190 switch (hw->mdix) {
1191 case 1:
1192 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1193 break;
1194 case 2:
1195 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1196 break;
1197 case 3:
1198 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1199 break;
1200 case 0:
1201 default:
1202 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1203 break;
1204 }
1205
1206
1207
1208
1209
1210
1211
1212 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1213 if (hw->disable_polarity_correction == 1)
1214 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1215 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1216 if (ret_val)
1217 return ret_val;
1218
1219 if (hw->phy_revision < M88E1011_I_REV_4) {
1220
1221
1222
1223 ret_val =
1224 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1225 &phy_data);
1226 if (ret_val)
1227 return ret_val;
1228
1229 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1230
1231 if ((hw->phy_revision == E1000_REVISION_2) &&
1232 (hw->phy_id == M88E1111_I_PHY_ID)) {
1233
1234 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1235 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1236 ret_val = e1000_write_phy_reg(hw,
1237 M88E1000_EXT_PHY_SPEC_CTRL,
1238 phy_data);
1239 if (ret_val)
1240 return ret_val;
1241 } else {
1242
1243 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1244 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1245 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1246 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1247 ret_val = e1000_write_phy_reg(hw,
1248 M88E1000_EXT_PHY_SPEC_CTRL,
1249 phy_data);
1250 if (ret_val)
1251 return ret_val;
1252 }
1253 }
1254
1255
1256 ret_val = e1000_phy_reset(hw);
1257 if (ret_val) {
1258 DEBUGOUT("Error Resetting the PHY\n");
1259 return ret_val;
1260 }
1261
1262 return E1000_SUCCESS;
1263}
1264
1265
1266
1267
1268
1269
1270
1271
1272static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1273{
1274 s32 ret_val;
1275 u16 phy_data;
1276
1277 DEBUGFUNC("e1000_copper_link_autoneg");
1278
1279
1280
1281
1282 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1283
1284
1285
1286
1287 if (hw->autoneg_advertised == 0)
1288 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1289
1290 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1291 ret_val = e1000_phy_setup_autoneg(hw);
1292 if (ret_val) {
1293 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1294 return ret_val;
1295 }
1296 DEBUGOUT("Restarting Auto-Neg\n");
1297
1298
1299
1300
1301 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1302 if (ret_val)
1303 return ret_val;
1304
1305 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1306 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1307 if (ret_val)
1308 return ret_val;
1309
1310
1311
1312
1313 if (hw->wait_autoneg_complete) {
1314 ret_val = e1000_wait_autoneg(hw);
1315 if (ret_val) {
1316 DEBUGOUT
1317 ("Error while waiting for autoneg to complete\n");
1318 return ret_val;
1319 }
1320 }
1321
1322 hw->get_link_status = true;
1323
1324 return E1000_SUCCESS;
1325}
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1341{
1342 s32 ret_val;
1343 DEBUGFUNC("e1000_copper_link_postconfig");
1344
1345 if (hw->mac_type >= e1000_82544) {
1346 e1000_config_collision_dist(hw);
1347 } else {
1348 ret_val = e1000_config_mac_to_phy(hw);
1349 if (ret_val) {
1350 DEBUGOUT("Error configuring MAC to PHY settings\n");
1351 return ret_val;
1352 }
1353 }
1354 ret_val = e1000_config_fc_after_link_up(hw);
1355 if (ret_val) {
1356 DEBUGOUT("Error Configuring Flow Control\n");
1357 return ret_val;
1358 }
1359
1360
1361 if (hw->phy_type == e1000_phy_igp) {
1362 ret_val = e1000_config_dsp_after_link_change(hw, true);
1363 if (ret_val) {
1364 DEBUGOUT("Error Configuring DSP after link up\n");
1365 return ret_val;
1366 }
1367 }
1368
1369 return E1000_SUCCESS;
1370}
1371
1372
1373
1374
1375
1376
1377
1378static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1379{
1380 s32 ret_val;
1381 u16 i;
1382 u16 phy_data;
1383
1384 DEBUGFUNC("e1000_setup_copper_link");
1385
1386
1387 ret_val = e1000_copper_link_preconfig(hw);
1388 if (ret_val)
1389 return ret_val;
1390
1391 if (hw->phy_type == e1000_phy_igp) {
1392 ret_val = e1000_copper_link_igp_setup(hw);
1393 if (ret_val)
1394 return ret_val;
1395 } else if (hw->phy_type == e1000_phy_m88) {
1396 ret_val = e1000_copper_link_mgp_setup(hw);
1397 if (ret_val)
1398 return ret_val;
1399 }
1400
1401 if (hw->autoneg) {
1402
1403
1404 ret_val = e1000_copper_link_autoneg(hw);
1405 if (ret_val)
1406 return ret_val;
1407 } else {
1408
1409
1410 DEBUGOUT("Forcing speed and duplex\n");
1411 ret_val = e1000_phy_force_speed_duplex(hw);
1412 if (ret_val) {
1413 DEBUGOUT("Error Forcing Speed and Duplex\n");
1414 return ret_val;
1415 }
1416 }
1417
1418
1419
1420
1421 for (i = 0; i < 10; i++) {
1422 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1423 if (ret_val)
1424 return ret_val;
1425 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1426 if (ret_val)
1427 return ret_val;
1428
1429 if (phy_data & MII_SR_LINK_STATUS) {
1430
1431 ret_val = e1000_copper_link_postconfig(hw);
1432 if (ret_val)
1433 return ret_val;
1434
1435 DEBUGOUT("Valid link established!!!\n");
1436 return E1000_SUCCESS;
1437 }
1438 udelay(10);
1439 }
1440
1441 DEBUGOUT("Unable to establish link!!!\n");
1442 return E1000_SUCCESS;
1443}
1444
1445
1446
1447
1448
1449
1450
1451s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1452{
1453 s32 ret_val;
1454 u16 mii_autoneg_adv_reg;
1455 u16 mii_1000t_ctrl_reg;
1456
1457 DEBUGFUNC("e1000_phy_setup_autoneg");
1458
1459
1460 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1461 if (ret_val)
1462 return ret_val;
1463
1464
1465 ret_val =
1466 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1467 if (ret_val)
1468 return ret_val;
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1482 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1483
1484 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1485
1486
1487 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1488 DEBUGOUT("Advertise 10mb Half duplex\n");
1489 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1490 }
1491
1492
1493 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1494 DEBUGOUT("Advertise 10mb Full duplex\n");
1495 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1496 }
1497
1498
1499 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1500 DEBUGOUT("Advertise 100mb Half duplex\n");
1501 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1502 }
1503
1504
1505 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1506 DEBUGOUT("Advertise 100mb Full duplex\n");
1507 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1508 }
1509
1510
1511 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1512 DEBUGOUT
1513 ("Advertise 1000mb Half duplex requested, request denied!\n");
1514 }
1515
1516
1517 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1518 DEBUGOUT("Advertise 1000mb Full duplex\n");
1519 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1520 }
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538 switch (hw->fc) {
1539 case E1000_FC_NONE:
1540
1541
1542
1543 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1544 break;
1545 case E1000_FC_RX_PAUSE:
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1556 break;
1557 case E1000_FC_TX_PAUSE:
1558
1559
1560
1561 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1562 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1563 break;
1564 case E1000_FC_FULL:
1565
1566
1567
1568 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1569 break;
1570 default:
1571 DEBUGOUT("Flow control param set incorrectly\n");
1572 return -E1000_ERR_CONFIG;
1573 }
1574
1575 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1576 if (ret_val)
1577 return ret_val;
1578
1579 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1580
1581 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1582 if (ret_val)
1583 return ret_val;
1584
1585 return E1000_SUCCESS;
1586}
1587
1588
1589
1590
1591
1592
1593
1594static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1595{
1596 u32 ctrl;
1597 s32 ret_val;
1598 u16 mii_ctrl_reg;
1599 u16 mii_status_reg;
1600 u16 phy_data;
1601 u16 i;
1602
1603 DEBUGFUNC("e1000_phy_force_speed_duplex");
1604
1605
1606 hw->fc = E1000_FC_NONE;
1607
1608 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1609
1610
1611 ctrl = er32(CTRL);
1612
1613
1614 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1615 ctrl &= ~(DEVICE_SPEED_MASK);
1616
1617
1618 ctrl &= ~E1000_CTRL_ASDE;
1619
1620
1621 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1622 if (ret_val)
1623 return ret_val;
1624
1625
1626
1627 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1628
1629
1630 if (hw->forced_speed_duplex == e1000_100_full ||
1631 hw->forced_speed_duplex == e1000_10_full) {
1632
1633
1634
1635 ctrl |= E1000_CTRL_FD;
1636 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1637 DEBUGOUT("Full Duplex\n");
1638 } else {
1639
1640
1641
1642 ctrl &= ~E1000_CTRL_FD;
1643 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1644 DEBUGOUT("Half Duplex\n");
1645 }
1646
1647
1648 if (hw->forced_speed_duplex == e1000_100_full ||
1649 hw->forced_speed_duplex == e1000_100_half) {
1650
1651 ctrl |= E1000_CTRL_SPD_100;
1652 mii_ctrl_reg |= MII_CR_SPEED_100;
1653 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1654 DEBUGOUT("Forcing 100mb ");
1655 } else {
1656
1657 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1658 mii_ctrl_reg |= MII_CR_SPEED_10;
1659 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1660 DEBUGOUT("Forcing 10mb ");
1661 }
1662
1663 e1000_config_collision_dist(hw);
1664
1665
1666 ew32(CTRL, ctrl);
1667
1668 if (hw->phy_type == e1000_phy_m88) {
1669 ret_val =
1670 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1671 if (ret_val)
1672 return ret_val;
1673
1674
1675
1676
1677 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1678 ret_val =
1679 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1680 if (ret_val)
1681 return ret_val;
1682
1683 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1684
1685
1686 mii_ctrl_reg |= MII_CR_RESET;
1687
1688
1689 } else {
1690
1691
1692
1693 ret_val =
1694 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1695 if (ret_val)
1696 return ret_val;
1697
1698 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1699 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1700
1701 ret_val =
1702 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1703 if (ret_val)
1704 return ret_val;
1705 }
1706
1707
1708 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1709 if (ret_val)
1710 return ret_val;
1711
1712 udelay(1);
1713
1714
1715
1716
1717
1718
1719
1720
1721 if (hw->wait_autoneg_complete) {
1722
1723 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1724 mii_status_reg = 0;
1725
1726
1727 for (i = PHY_FORCE_TIME; i > 0; i--) {
1728
1729
1730
1731 ret_val =
1732 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1733 if (ret_val)
1734 return ret_val;
1735
1736 ret_val =
1737 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1738 if (ret_val)
1739 return ret_val;
1740
1741 if (mii_status_reg & MII_SR_LINK_STATUS)
1742 break;
1743 msleep(100);
1744 }
1745 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1746
1747 ret_val = e1000_phy_reset_dsp(hw);
1748 if (ret_val) {
1749 DEBUGOUT("Error Resetting PHY DSP\n");
1750 return ret_val;
1751 }
1752 }
1753
1754 for (i = PHY_FORCE_TIME; i > 0; i--) {
1755 if (mii_status_reg & MII_SR_LINK_STATUS)
1756 break;
1757 msleep(100);
1758
1759
1760
1761 ret_val =
1762 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1763 if (ret_val)
1764 return ret_val;
1765
1766 ret_val =
1767 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1768 if (ret_val)
1769 return ret_val;
1770 }
1771 }
1772
1773 if (hw->phy_type == e1000_phy_m88) {
1774
1775
1776
1777
1778 ret_val =
1779 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1780 &phy_data);
1781 if (ret_val)
1782 return ret_val;
1783
1784 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1785 ret_val =
1786 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1787 phy_data);
1788 if (ret_val)
1789 return ret_val;
1790
1791
1792
1793
1794 ret_val =
1795 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1796 if (ret_val)
1797 return ret_val;
1798
1799 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1800 ret_val =
1801 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1802 if (ret_val)
1803 return ret_val;
1804
1805 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
1806 && (!hw->autoneg)
1807 && (hw->forced_speed_duplex == e1000_10_full
1808 || hw->forced_speed_duplex == e1000_10_half)) {
1809 ret_val = e1000_polarity_reversal_workaround(hw);
1810 if (ret_val)
1811 return ret_val;
1812 }
1813 }
1814 return E1000_SUCCESS;
1815}
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825void e1000_config_collision_dist(struct e1000_hw *hw)
1826{
1827 u32 tctl, coll_dist;
1828
1829 DEBUGFUNC("e1000_config_collision_dist");
1830
1831 if (hw->mac_type < e1000_82543)
1832 coll_dist = E1000_COLLISION_DISTANCE_82542;
1833 else
1834 coll_dist = E1000_COLLISION_DISTANCE;
1835
1836 tctl = er32(TCTL);
1837
1838 tctl &= ~E1000_TCTL_COLD;
1839 tctl |= coll_dist << E1000_COLD_SHIFT;
1840
1841 ew32(TCTL, tctl);
1842 E1000_WRITE_FLUSH();
1843}
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1855{
1856 u32 ctrl;
1857 s32 ret_val;
1858 u16 phy_data;
1859
1860 DEBUGFUNC("e1000_config_mac_to_phy");
1861
1862
1863
1864 if (hw->mac_type >= e1000_82544)
1865 return E1000_SUCCESS;
1866
1867
1868
1869
1870 ctrl = er32(CTRL);
1871 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1872 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1873
1874
1875
1876
1877 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1878 if (ret_val)
1879 return ret_val;
1880
1881 if (phy_data & M88E1000_PSSR_DPLX)
1882 ctrl |= E1000_CTRL_FD;
1883 else
1884 ctrl &= ~E1000_CTRL_FD;
1885
1886 e1000_config_collision_dist(hw);
1887
1888
1889
1890
1891 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1892 ctrl |= E1000_CTRL_SPD_1000;
1893 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1894 ctrl |= E1000_CTRL_SPD_100;
1895
1896
1897 ew32(CTRL, ctrl);
1898 return E1000_SUCCESS;
1899}
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912s32 e1000_force_mac_fc(struct e1000_hw *hw)
1913{
1914 u32 ctrl;
1915
1916 DEBUGFUNC("e1000_force_mac_fc");
1917
1918
1919 ctrl = er32(CTRL);
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939 switch (hw->fc) {
1940 case E1000_FC_NONE:
1941 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1942 break;
1943 case E1000_FC_RX_PAUSE:
1944 ctrl &= (~E1000_CTRL_TFCE);
1945 ctrl |= E1000_CTRL_RFCE;
1946 break;
1947 case E1000_FC_TX_PAUSE:
1948 ctrl &= (~E1000_CTRL_RFCE);
1949 ctrl |= E1000_CTRL_TFCE;
1950 break;
1951 case E1000_FC_FULL:
1952 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1953 break;
1954 default:
1955 DEBUGOUT("Flow control param set incorrectly\n");
1956 return -E1000_ERR_CONFIG;
1957 }
1958
1959
1960 if (hw->mac_type == e1000_82542_rev2_0)
1961 ctrl &= (~E1000_CTRL_TFCE);
1962
1963 ew32(CTRL, ctrl);
1964 return E1000_SUCCESS;
1965}
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1979{
1980 s32 ret_val;
1981 u16 mii_status_reg;
1982 u16 mii_nway_adv_reg;
1983 u16 mii_nway_lp_ability_reg;
1984 u16 speed;
1985 u16 duplex;
1986
1987 DEBUGFUNC("e1000_config_fc_after_link_up");
1988
1989
1990
1991
1992
1993 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
1994 || ((hw->media_type == e1000_media_type_internal_serdes)
1995 && (hw->autoneg_failed))
1996 || ((hw->media_type == e1000_media_type_copper)
1997 && (!hw->autoneg))) {
1998 ret_val = e1000_force_mac_fc(hw);
1999 if (ret_val) {
2000 DEBUGOUT("Error forcing flow control settings\n");
2001 return ret_val;
2002 }
2003 }
2004
2005
2006
2007
2008
2009
2010 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2011
2012
2013
2014
2015 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2016 if (ret_val)
2017 return ret_val;
2018 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2019 if (ret_val)
2020 return ret_val;
2021
2022 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2023
2024
2025
2026
2027
2028
2029 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2030 &mii_nway_adv_reg);
2031 if (ret_val)
2032 return ret_val;
2033 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2034 &mii_nway_lp_ability_reg);
2035 if (ret_val)
2036 return ret_val;
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2073 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2074
2075
2076
2077
2078
2079
2080 if (hw->original_fc == E1000_FC_FULL) {
2081 hw->fc = E1000_FC_FULL;
2082 DEBUGOUT("Flow Control = FULL.\n");
2083 } else {
2084 hw->fc = E1000_FC_RX_PAUSE;
2085 DEBUGOUT
2086 ("Flow Control = RX PAUSE frames only.\n");
2087 }
2088 }
2089
2090
2091
2092
2093
2094
2095
2096
2097 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2098 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2099 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2100 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2101 {
2102 hw->fc = E1000_FC_TX_PAUSE;
2103 DEBUGOUT
2104 ("Flow Control = TX PAUSE frames only.\n");
2105 }
2106
2107
2108
2109
2110
2111
2112
2113
2114 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2115 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2116 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2117 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2118 {
2119 hw->fc = E1000_FC_RX_PAUSE;
2120 DEBUGOUT
2121 ("Flow Control = RX PAUSE frames only.\n");
2122 }
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143 else if ((hw->original_fc == E1000_FC_NONE ||
2144 hw->original_fc == E1000_FC_TX_PAUSE) ||
2145 hw->fc_strict_ieee) {
2146 hw->fc = E1000_FC_NONE;
2147 DEBUGOUT("Flow Control = NONE.\n");
2148 } else {
2149 hw->fc = E1000_FC_RX_PAUSE;
2150 DEBUGOUT
2151 ("Flow Control = RX PAUSE frames only.\n");
2152 }
2153
2154
2155
2156
2157
2158 ret_val =
2159 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2160 if (ret_val) {
2161 DEBUGOUT
2162 ("Error getting link speed and duplex\n");
2163 return ret_val;
2164 }
2165
2166 if (duplex == HALF_DUPLEX)
2167 hw->fc = E1000_FC_NONE;
2168
2169
2170
2171
2172 ret_val = e1000_force_mac_fc(hw);
2173 if (ret_val) {
2174 DEBUGOUT
2175 ("Error forcing flow control settings\n");
2176 return ret_val;
2177 }
2178 } else {
2179 DEBUGOUT
2180 ("Copper PHY and Auto Neg has not completed.\n");
2181 }
2182 }
2183 return E1000_SUCCESS;
2184}
2185
2186
2187
2188
2189
2190
2191
2192
2193static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2194{
2195 u32 rxcw;
2196 u32 ctrl;
2197 u32 status;
2198 s32 ret_val = E1000_SUCCESS;
2199
2200 DEBUGFUNC("e1000_check_for_serdes_link_generic");
2201
2202 ctrl = er32(CTRL);
2203 status = er32(STATUS);
2204 rxcw = er32(RXCW);
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2215 if (hw->autoneg_failed == 0) {
2216 hw->autoneg_failed = 1;
2217 goto out;
2218 }
2219 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
2220
2221
2222 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2223
2224
2225 ctrl = er32(CTRL);
2226 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2227 ew32(CTRL, ctrl);
2228
2229
2230 ret_val = e1000_config_fc_after_link_up(hw);
2231 if (ret_val) {
2232 DEBUGOUT("Error configuring flow control\n");
2233 goto out;
2234 }
2235 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2236
2237
2238
2239
2240
2241
2242 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2243 ew32(TXCW, hw->txcw);
2244 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2245
2246 hw->serdes_has_link = true;
2247 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2248
2249
2250
2251
2252
2253
2254 udelay(10);
2255 rxcw = er32(RXCW);
2256 if (rxcw & E1000_RXCW_SYNCH) {
2257 if (!(rxcw & E1000_RXCW_IV)) {
2258 hw->serdes_has_link = true;
2259 DEBUGOUT("SERDES: Link up - forced.\n");
2260 }
2261 } else {
2262 hw->serdes_has_link = false;
2263 DEBUGOUT("SERDES: Link down - force failed.\n");
2264 }
2265 }
2266
2267 if (E1000_TXCW_ANE & er32(TXCW)) {
2268 status = er32(STATUS);
2269 if (status & E1000_STATUS_LU) {
2270
2271 udelay(10);
2272 rxcw = er32(RXCW);
2273 if (rxcw & E1000_RXCW_SYNCH) {
2274 if (!(rxcw & E1000_RXCW_IV)) {
2275 hw->serdes_has_link = true;
2276 DEBUGOUT("SERDES: Link up - autoneg "
2277 "completed successfully.\n");
2278 } else {
2279 hw->serdes_has_link = false;
2280 DEBUGOUT("SERDES: Link down - invalid"
2281 "codewords detected in autoneg.\n");
2282 }
2283 } else {
2284 hw->serdes_has_link = false;
2285 DEBUGOUT("SERDES: Link down - no sync.\n");
2286 }
2287 } else {
2288 hw->serdes_has_link = false;
2289 DEBUGOUT("SERDES: Link down - autoneg failed\n");
2290 }
2291 }
2292
2293 out:
2294 return ret_val;
2295}
2296
2297
2298
2299
2300
2301
2302
2303
2304s32 e1000_check_for_link(struct e1000_hw *hw)
2305{
2306 u32 rxcw = 0;
2307 u32 ctrl;
2308 u32 status;
2309 u32 rctl;
2310 u32 icr;
2311 u32 signal = 0;
2312 s32 ret_val;
2313 u16 phy_data;
2314
2315 DEBUGFUNC("e1000_check_for_link");
2316
2317 ctrl = er32(CTRL);
2318 status = er32(STATUS);
2319
2320
2321
2322
2323
2324 if ((hw->media_type == e1000_media_type_fiber) ||
2325 (hw->media_type == e1000_media_type_internal_serdes)) {
2326 rxcw = er32(RXCW);
2327
2328 if (hw->media_type == e1000_media_type_fiber) {
2329 signal =
2330 (hw->mac_type >
2331 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2332 if (status & E1000_STATUS_LU)
2333 hw->get_link_status = false;
2334 }
2335 }
2336
2337
2338
2339
2340
2341
2342
2343 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2344
2345
2346
2347
2348
2349 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2350 if (ret_val)
2351 return ret_val;
2352 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2353 if (ret_val)
2354 return ret_val;
2355
2356 if (phy_data & MII_SR_LINK_STATUS) {
2357 hw->get_link_status = false;
2358
2359
2360 e1000_check_downshift(hw);
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370 if ((hw->mac_type == e1000_82544
2371 || hw->mac_type == e1000_82543) && (!hw->autoneg)
2372 && (hw->forced_speed_duplex == e1000_10_full
2373 || hw->forced_speed_duplex == e1000_10_half)) {
2374 ew32(IMC, 0xffffffff);
2375 ret_val =
2376 e1000_polarity_reversal_workaround(hw);
2377 icr = er32(ICR);
2378 ew32(ICS, (icr & ~E1000_ICS_LSC));
2379 ew32(IMS, IMS_ENABLE_MASK);
2380 }
2381
2382 } else {
2383
2384 e1000_config_dsp_after_link_change(hw, false);
2385 return 0;
2386 }
2387
2388
2389
2390
2391 if (!hw->autoneg)
2392 return -E1000_ERR_CONFIG;
2393
2394
2395 e1000_config_dsp_after_link_change(hw, true);
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405 if (hw->mac_type >= e1000_82544)
2406 e1000_config_collision_dist(hw);
2407 else {
2408 ret_val = e1000_config_mac_to_phy(hw);
2409 if (ret_val) {
2410 DEBUGOUT
2411 ("Error configuring MAC to PHY settings\n");
2412 return ret_val;
2413 }
2414 }
2415
2416
2417
2418
2419
2420 ret_val = e1000_config_fc_after_link_up(hw);
2421 if (ret_val) {
2422 DEBUGOUT("Error configuring flow control\n");
2423 return ret_val;
2424 }
2425
2426
2427
2428
2429
2430
2431
2432
2433 if (hw->tbi_compatibility_en) {
2434 u16 speed, duplex;
2435 ret_val =
2436 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2437 if (ret_val) {
2438 DEBUGOUT
2439 ("Error getting link speed and duplex\n");
2440 return ret_val;
2441 }
2442 if (speed != SPEED_1000) {
2443
2444
2445
2446 if (hw->tbi_compatibility_on) {
2447
2448 rctl = er32(RCTL);
2449 rctl &= ~E1000_RCTL_SBP;
2450 ew32(RCTL, rctl);
2451 hw->tbi_compatibility_on = false;
2452 }
2453 } else {
2454
2455
2456
2457
2458
2459 if (!hw->tbi_compatibility_on) {
2460 hw->tbi_compatibility_on = true;
2461 rctl = er32(RCTL);
2462 rctl |= E1000_RCTL_SBP;
2463 ew32(RCTL, rctl);
2464 }
2465 }
2466 }
2467 }
2468
2469 if ((hw->media_type == e1000_media_type_fiber) ||
2470 (hw->media_type == e1000_media_type_internal_serdes))
2471 e1000_check_for_serdes_link_generic(hw);
2472
2473 return E1000_SUCCESS;
2474}
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2485{
2486 u32 status;
2487 s32 ret_val;
2488 u16 phy_data;
2489
2490 DEBUGFUNC("e1000_get_speed_and_duplex");
2491
2492 if (hw->mac_type >= e1000_82543) {
2493 status = er32(STATUS);
2494 if (status & E1000_STATUS_SPEED_1000) {
2495 *speed = SPEED_1000;
2496 DEBUGOUT("1000 Mbs, ");
2497 } else if (status & E1000_STATUS_SPEED_100) {
2498 *speed = SPEED_100;
2499 DEBUGOUT("100 Mbs, ");
2500 } else {
2501 *speed = SPEED_10;
2502 DEBUGOUT("10 Mbs, ");
2503 }
2504
2505 if (status & E1000_STATUS_FD) {
2506 *duplex = FULL_DUPLEX;
2507 DEBUGOUT("Full Duplex\n");
2508 } else {
2509 *duplex = HALF_DUPLEX;
2510 DEBUGOUT(" Half Duplex\n");
2511 }
2512 } else {
2513 DEBUGOUT("1000 Mbs, Full Duplex\n");
2514 *speed = SPEED_1000;
2515 *duplex = FULL_DUPLEX;
2516 }
2517
2518
2519
2520
2521
2522 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2523 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2524 if (ret_val)
2525 return ret_val;
2526
2527 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2528 *duplex = HALF_DUPLEX;
2529 else {
2530 ret_val =
2531 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2532 if (ret_val)
2533 return ret_val;
2534 if ((*speed == SPEED_100
2535 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
2536 || (*speed == SPEED_10
2537 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2538 *duplex = HALF_DUPLEX;
2539 }
2540 }
2541
2542 return E1000_SUCCESS;
2543}
2544
2545
2546
2547
2548
2549
2550
2551static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2552{
2553 s32 ret_val;
2554 u16 i;
2555 u16 phy_data;
2556
2557 DEBUGFUNC("e1000_wait_autoneg");
2558 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2559
2560
2561 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2562
2563
2564
2565 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2566 if (ret_val)
2567 return ret_val;
2568 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2569 if (ret_val)
2570 return ret_val;
2571 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2572 return E1000_SUCCESS;
2573 }
2574 msleep(100);
2575 }
2576 return E1000_SUCCESS;
2577}
2578
2579
2580
2581
2582
2583
2584static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2585{
2586
2587
2588
2589 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2590 E1000_WRITE_FLUSH();
2591 udelay(10);
2592}
2593
2594
2595
2596
2597
2598
2599static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2600{
2601
2602
2603
2604 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2605 E1000_WRITE_FLUSH();
2606 udelay(10);
2607}
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2618{
2619 u32 ctrl;
2620 u32 mask;
2621
2622
2623
2624
2625
2626 mask = 0x01;
2627 mask <<= (count - 1);
2628
2629 ctrl = er32(CTRL);
2630
2631
2632 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2633
2634 while (mask) {
2635
2636
2637
2638
2639
2640 if (data & mask)
2641 ctrl |= E1000_CTRL_MDIO;
2642 else
2643 ctrl &= ~E1000_CTRL_MDIO;
2644
2645 ew32(CTRL, ctrl);
2646 E1000_WRITE_FLUSH();
2647
2648 udelay(10);
2649
2650 e1000_raise_mdi_clk(hw, &ctrl);
2651 e1000_lower_mdi_clk(hw, &ctrl);
2652
2653 mask = mask >> 1;
2654 }
2655}
2656
2657
2658
2659
2660
2661
2662
2663static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2664{
2665 u32 ctrl;
2666 u16 data = 0;
2667 u8 i;
2668
2669
2670
2671
2672
2673
2674
2675
2676 ctrl = er32(CTRL);
2677
2678
2679 ctrl &= ~E1000_CTRL_MDIO_DIR;
2680 ctrl &= ~E1000_CTRL_MDIO;
2681
2682 ew32(CTRL, ctrl);
2683 E1000_WRITE_FLUSH();
2684
2685
2686
2687
2688
2689 e1000_raise_mdi_clk(hw, &ctrl);
2690 e1000_lower_mdi_clk(hw, &ctrl);
2691
2692 for (data = 0, i = 0; i < 16; i++) {
2693 data = data << 1;
2694 e1000_raise_mdi_clk(hw, &ctrl);
2695 ctrl = er32(CTRL);
2696
2697 if (ctrl & E1000_CTRL_MDIO)
2698 data |= 1;
2699 e1000_lower_mdi_clk(hw, &ctrl);
2700 }
2701
2702 e1000_raise_mdi_clk(hw, &ctrl);
2703 e1000_lower_mdi_clk(hw, &ctrl);
2704
2705 return data;
2706}
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2718{
2719 u32 ret_val;
2720
2721 DEBUGFUNC("e1000_read_phy_reg");
2722
2723 if ((hw->phy_type == e1000_phy_igp) &&
2724 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2725 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2726 (u16) reg_addr);
2727 if (ret_val)
2728 return ret_val;
2729 }
2730
2731 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2732 phy_data);
2733
2734 return ret_val;
2735}
2736
2737static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2738 u16 *phy_data)
2739{
2740 u32 i;
2741 u32 mdic = 0;
2742 const u32 phy_addr = 1;
2743
2744 DEBUGFUNC("e1000_read_phy_reg_ex");
2745
2746 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2747 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2748 return -E1000_ERR_PARAM;
2749 }
2750
2751 if (hw->mac_type > e1000_82543) {
2752
2753
2754
2755
2756 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2757 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2758 (E1000_MDIC_OP_READ));
2759
2760 ew32(MDIC, mdic);
2761
2762
2763 for (i = 0; i < 64; i++) {
2764 udelay(50);
2765 mdic = er32(MDIC);
2766 if (mdic & E1000_MDIC_READY)
2767 break;
2768 }
2769 if (!(mdic & E1000_MDIC_READY)) {
2770 DEBUGOUT("MDI Read did not complete\n");
2771 return -E1000_ERR_PHY;
2772 }
2773 if (mdic & E1000_MDIC_ERROR) {
2774 DEBUGOUT("MDI Error\n");
2775 return -E1000_ERR_PHY;
2776 }
2777 *phy_data = (u16) mdic;
2778 } else {
2779
2780
2781
2782
2783 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796 mdic = ((reg_addr) | (phy_addr << 5) |
2797 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2798
2799 e1000_shift_out_mdi_bits(hw, mdic, 14);
2800
2801
2802
2803
2804
2805 *phy_data = e1000_shift_in_mdi_bits(hw);
2806 }
2807 return E1000_SUCCESS;
2808}
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2820{
2821 u32 ret_val;
2822
2823 DEBUGFUNC("e1000_write_phy_reg");
2824
2825 if ((hw->phy_type == e1000_phy_igp) &&
2826 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2827 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2828 (u16) reg_addr);
2829 if (ret_val)
2830 return ret_val;
2831 }
2832
2833 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2834 phy_data);
2835
2836 return ret_val;
2837}
2838
2839static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2840 u16 phy_data)
2841{
2842 u32 i;
2843 u32 mdic = 0;
2844 const u32 phy_addr = 1;
2845
2846 DEBUGFUNC("e1000_write_phy_reg_ex");
2847
2848 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2849 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2850 return -E1000_ERR_PARAM;
2851 }
2852
2853 if (hw->mac_type > e1000_82543) {
2854
2855
2856
2857
2858 mdic = (((u32) phy_data) |
2859 (reg_addr << E1000_MDIC_REG_SHIFT) |
2860 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2861 (E1000_MDIC_OP_WRITE));
2862
2863 ew32(MDIC, mdic);
2864
2865
2866 for (i = 0; i < 641; i++) {
2867 udelay(5);
2868 mdic = er32(MDIC);
2869 if (mdic & E1000_MDIC_READY)
2870 break;
2871 }
2872 if (!(mdic & E1000_MDIC_READY)) {
2873 DEBUGOUT("MDI Write did not complete\n");
2874 return -E1000_ERR_PHY;
2875 }
2876 } else {
2877
2878
2879
2880
2881
2882 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2883
2884
2885
2886
2887
2888
2889
2890 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2891 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2892 mdic <<= 16;
2893 mdic |= (u32) phy_data;
2894
2895 e1000_shift_out_mdi_bits(hw, mdic, 32);
2896 }
2897
2898 return E1000_SUCCESS;
2899}
2900
2901
2902
2903
2904
2905
2906
2907s32 e1000_phy_hw_reset(struct e1000_hw *hw)
2908{
2909 u32 ctrl, ctrl_ext;
2910 u32 led_ctrl;
2911 s32 ret_val;
2912
2913 DEBUGFUNC("e1000_phy_hw_reset");
2914
2915 DEBUGOUT("Resetting Phy...\n");
2916
2917 if (hw->mac_type > e1000_82543) {
2918
2919
2920
2921
2922
2923 ctrl = er32(CTRL);
2924 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2925 E1000_WRITE_FLUSH();
2926
2927 msleep(10);
2928
2929 ew32(CTRL, ctrl);
2930 E1000_WRITE_FLUSH();
2931
2932 } else {
2933
2934
2935
2936 ctrl_ext = er32(CTRL_EXT);
2937 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2938 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2939 ew32(CTRL_EXT, ctrl_ext);
2940 E1000_WRITE_FLUSH();
2941 msleep(10);
2942 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2943 ew32(CTRL_EXT, ctrl_ext);
2944 E1000_WRITE_FLUSH();
2945 }
2946 udelay(150);
2947
2948 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2949
2950 led_ctrl = er32(LEDCTL);
2951 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2952 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2953 ew32(LEDCTL, led_ctrl);
2954 }
2955
2956
2957 ret_val = e1000_get_phy_cfg_done(hw);
2958 if (ret_val != E1000_SUCCESS)
2959 return ret_val;
2960
2961 return ret_val;
2962}
2963
2964
2965
2966
2967
2968
2969
2970
2971s32 e1000_phy_reset(struct e1000_hw *hw)
2972{
2973 s32 ret_val;
2974 u16 phy_data;
2975
2976 DEBUGFUNC("e1000_phy_reset");
2977
2978 switch (hw->phy_type) {
2979 case e1000_phy_igp:
2980 ret_val = e1000_phy_hw_reset(hw);
2981 if (ret_val)
2982 return ret_val;
2983 break;
2984 default:
2985 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2986 if (ret_val)
2987 return ret_val;
2988
2989 phy_data |= MII_CR_RESET;
2990 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2991 if (ret_val)
2992 return ret_val;
2993
2994 udelay(1);
2995 break;
2996 }
2997
2998 if (hw->phy_type == e1000_phy_igp)
2999 e1000_phy_init_script(hw);
3000
3001 return E1000_SUCCESS;
3002}
3003
3004
3005
3006
3007
3008
3009
3010static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3011{
3012 s32 phy_init_status, ret_val;
3013 u16 phy_id_high, phy_id_low;
3014 bool match = false;
3015
3016 DEBUGFUNC("e1000_detect_gig_phy");
3017
3018 if (hw->phy_id != 0)
3019 return E1000_SUCCESS;
3020
3021
3022 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3023 if (ret_val)
3024 return ret_val;
3025
3026 hw->phy_id = (u32) (phy_id_high << 16);
3027 udelay(20);
3028 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3029 if (ret_val)
3030 return ret_val;
3031
3032 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
3033 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
3034
3035 switch (hw->mac_type) {
3036 case e1000_82543:
3037 if (hw->phy_id == M88E1000_E_PHY_ID)
3038 match = true;
3039 break;
3040 case e1000_82544:
3041 if (hw->phy_id == M88E1000_I_PHY_ID)
3042 match = true;
3043 break;
3044 case e1000_82540:
3045 case e1000_82545:
3046 case e1000_82545_rev_3:
3047 case e1000_82546:
3048 case e1000_82546_rev_3:
3049 if (hw->phy_id == M88E1011_I_PHY_ID)
3050 match = true;
3051 break;
3052 case e1000_82541:
3053 case e1000_82541_rev_2:
3054 case e1000_82547:
3055 case e1000_82547_rev_2:
3056 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3057 match = true;
3058 break;
3059 default:
3060 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3061 return -E1000_ERR_CONFIG;
3062 }
3063 phy_init_status = e1000_set_phy_type(hw);
3064
3065 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3066 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3067 return E1000_SUCCESS;
3068 }
3069 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3070 return -E1000_ERR_PHY;
3071}
3072
3073
3074
3075
3076
3077
3078
3079static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3080{
3081 s32 ret_val;
3082 DEBUGFUNC("e1000_phy_reset_dsp");
3083
3084 do {
3085 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3086 if (ret_val)
3087 break;
3088 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3089 if (ret_val)
3090 break;
3091 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3092 if (ret_val)
3093 break;
3094 ret_val = E1000_SUCCESS;
3095 } while (0);
3096
3097 return ret_val;
3098}
3099
3100
3101
3102
3103
3104
3105
3106
3107static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3108 struct e1000_phy_info *phy_info)
3109{
3110 s32 ret_val;
3111 u16 phy_data, min_length, max_length, average;
3112 e1000_rev_polarity polarity;
3113
3114 DEBUGFUNC("e1000_phy_igp_get_info");
3115
3116
3117
3118 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3119
3120
3121 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3122
3123
3124 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3125
3126
3127 ret_val = e1000_check_polarity(hw, &polarity);
3128 if (ret_val)
3129 return ret_val;
3130
3131 phy_info->cable_polarity = polarity;
3132
3133 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3134 if (ret_val)
3135 return ret_val;
3136
3137 phy_info->mdix_mode =
3138 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3139 IGP01E1000_PSSR_MDIX_SHIFT);
3140
3141 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3142 IGP01E1000_PSSR_SPEED_1000MBPS) {
3143
3144 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3145 if (ret_val)
3146 return ret_val;
3147
3148 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3149 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3150 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3151 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3152 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3153 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3154
3155
3156 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3157 if (ret_val)
3158 return ret_val;
3159
3160
3161 average = (max_length + min_length) / 2;
3162
3163 if (average <= e1000_igp_cable_length_50)
3164 phy_info->cable_length = e1000_cable_length_50;
3165 else if (average <= e1000_igp_cable_length_80)
3166 phy_info->cable_length = e1000_cable_length_50_80;
3167 else if (average <= e1000_igp_cable_length_110)
3168 phy_info->cable_length = e1000_cable_length_80_110;
3169 else if (average <= e1000_igp_cable_length_140)
3170 phy_info->cable_length = e1000_cable_length_110_140;
3171 else
3172 phy_info->cable_length = e1000_cable_length_140;
3173 }
3174
3175 return E1000_SUCCESS;
3176}
3177
3178
3179
3180
3181
3182
3183
3184
3185static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3186 struct e1000_phy_info *phy_info)
3187{
3188 s32 ret_val;
3189 u16 phy_data;
3190 e1000_rev_polarity polarity;
3191
3192 DEBUGFUNC("e1000_phy_m88_get_info");
3193
3194
3195
3196 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3197
3198 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3199 if (ret_val)
3200 return ret_val;
3201
3202 phy_info->extended_10bt_distance =
3203 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3204 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3205 e1000_10bt_ext_dist_enable_lower :
3206 e1000_10bt_ext_dist_enable_normal;
3207
3208 phy_info->polarity_correction =
3209 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3210 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3211 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3212
3213
3214 ret_val = e1000_check_polarity(hw, &polarity);
3215 if (ret_val)
3216 return ret_val;
3217 phy_info->cable_polarity = polarity;
3218
3219 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3220 if (ret_val)
3221 return ret_val;
3222
3223 phy_info->mdix_mode =
3224 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3225 M88E1000_PSSR_MDIX_SHIFT);
3226
3227 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3228
3229
3230
3231 phy_info->cable_length =
3232 (e1000_cable_length) ((phy_data &
3233 M88E1000_PSSR_CABLE_LENGTH) >>
3234 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3235
3236 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3237 if (ret_val)
3238 return ret_val;
3239
3240 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3241 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3242 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3243 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3244 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3245 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3246
3247 }
3248
3249 return E1000_SUCCESS;
3250}
3251
3252
3253
3254
3255
3256
3257
3258
3259s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3260{
3261 s32 ret_val;
3262 u16 phy_data;
3263
3264 DEBUGFUNC("e1000_phy_get_info");
3265
3266 phy_info->cable_length = e1000_cable_length_undefined;
3267 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3268 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3269 phy_info->downshift = e1000_downshift_undefined;
3270 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3271 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3272 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3273 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3274
3275 if (hw->media_type != e1000_media_type_copper) {
3276 DEBUGOUT("PHY info is only valid for copper media\n");
3277 return -E1000_ERR_CONFIG;
3278 }
3279
3280 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3281 if (ret_val)
3282 return ret_val;
3283
3284 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3285 if (ret_val)
3286 return ret_val;
3287
3288 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3289 DEBUGOUT("PHY info is only valid if link is up\n");
3290 return -E1000_ERR_CONFIG;
3291 }
3292
3293 if (hw->phy_type == e1000_phy_igp)
3294 return e1000_phy_igp_get_info(hw, phy_info);
3295 else
3296 return e1000_phy_m88_get_info(hw, phy_info);
3297}
3298
3299s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3300{
3301 DEBUGFUNC("e1000_validate_mdi_settings");
3302
3303 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3304 DEBUGOUT("Invalid MDI setting detected\n");
3305 hw->mdix = 1;
3306 return -E1000_ERR_CONFIG;
3307 }
3308 return E1000_SUCCESS;
3309}
3310
3311
3312
3313
3314
3315
3316
3317
3318s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3319{
3320 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3321 u32 eecd = er32(EECD);
3322 s32 ret_val = E1000_SUCCESS;
3323 u16 eeprom_size;
3324
3325 DEBUGFUNC("e1000_init_eeprom_params");
3326
3327 switch (hw->mac_type) {
3328 case e1000_82542_rev2_0:
3329 case e1000_82542_rev2_1:
3330 case e1000_82543:
3331 case e1000_82544:
3332 eeprom->type = e1000_eeprom_microwire;
3333 eeprom->word_size = 64;
3334 eeprom->opcode_bits = 3;
3335 eeprom->address_bits = 6;
3336 eeprom->delay_usec = 50;
3337 break;
3338 case e1000_82540:
3339 case e1000_82545:
3340 case e1000_82545_rev_3:
3341 case e1000_82546:
3342 case e1000_82546_rev_3:
3343 eeprom->type = e1000_eeprom_microwire;
3344 eeprom->opcode_bits = 3;
3345 eeprom->delay_usec = 50;
3346 if (eecd & E1000_EECD_SIZE) {
3347 eeprom->word_size = 256;
3348 eeprom->address_bits = 8;
3349 } else {
3350 eeprom->word_size = 64;
3351 eeprom->address_bits = 6;
3352 }
3353 break;
3354 case e1000_82541:
3355 case e1000_82541_rev_2:
3356 case e1000_82547:
3357 case e1000_82547_rev_2:
3358 if (eecd & E1000_EECD_TYPE) {
3359 eeprom->type = e1000_eeprom_spi;
3360 eeprom->opcode_bits = 8;
3361 eeprom->delay_usec = 1;
3362 if (eecd & E1000_EECD_ADDR_BITS) {
3363 eeprom->page_size = 32;
3364 eeprom->address_bits = 16;
3365 } else {
3366 eeprom->page_size = 8;
3367 eeprom->address_bits = 8;
3368 }
3369 } else {
3370 eeprom->type = e1000_eeprom_microwire;
3371 eeprom->opcode_bits = 3;
3372 eeprom->delay_usec = 50;
3373 if (eecd & E1000_EECD_ADDR_BITS) {
3374 eeprom->word_size = 256;
3375 eeprom->address_bits = 8;
3376 } else {
3377 eeprom->word_size = 64;
3378 eeprom->address_bits = 6;
3379 }
3380 }
3381 break;
3382 default:
3383 break;
3384 }
3385
3386 if (eeprom->type == e1000_eeprom_spi) {
3387
3388
3389
3390
3391 eeprom->word_size = 64;
3392 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3393 if (ret_val)
3394 return ret_val;
3395 eeprom_size =
3396 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3397
3398
3399
3400 if (eeprom_size)
3401 eeprom_size++;
3402
3403 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3404 }
3405 return ret_val;
3406}
3407
3408
3409
3410
3411
3412
3413static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3414{
3415
3416
3417
3418 *eecd = *eecd | E1000_EECD_SK;
3419 ew32(EECD, *eecd);
3420 E1000_WRITE_FLUSH();
3421 udelay(hw->eeprom.delay_usec);
3422}
3423
3424
3425
3426
3427
3428
3429static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3430{
3431
3432
3433
3434 *eecd = *eecd & ~E1000_EECD_SK;
3435 ew32(EECD, *eecd);
3436 E1000_WRITE_FLUSH();
3437 udelay(hw->eeprom.delay_usec);
3438}
3439
3440
3441
3442
3443
3444
3445
3446static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3447{
3448 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3449 u32 eecd;
3450 u32 mask;
3451
3452
3453
3454
3455
3456 mask = 0x01 << (count - 1);
3457 eecd = er32(EECD);
3458 if (eeprom->type == e1000_eeprom_microwire) {
3459 eecd &= ~E1000_EECD_DO;
3460 } else if (eeprom->type == e1000_eeprom_spi) {
3461 eecd |= E1000_EECD_DO;
3462 }
3463 do {
3464
3465
3466
3467
3468
3469 eecd &= ~E1000_EECD_DI;
3470
3471 if (data & mask)
3472 eecd |= E1000_EECD_DI;
3473
3474 ew32(EECD, eecd);
3475 E1000_WRITE_FLUSH();
3476
3477 udelay(eeprom->delay_usec);
3478
3479 e1000_raise_ee_clk(hw, &eecd);
3480 e1000_lower_ee_clk(hw, &eecd);
3481
3482 mask = mask >> 1;
3483
3484 } while (mask);
3485
3486
3487 eecd &= ~E1000_EECD_DI;
3488 ew32(EECD, eecd);
3489}
3490
3491
3492
3493
3494
3495
3496static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3497{
3498 u32 eecd;
3499 u32 i;
3500 u16 data;
3501
3502
3503
3504
3505
3506
3507
3508
3509 eecd = er32(EECD);
3510
3511 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3512 data = 0;
3513
3514 for (i = 0; i < count; i++) {
3515 data = data << 1;
3516 e1000_raise_ee_clk(hw, &eecd);
3517
3518 eecd = er32(EECD);
3519
3520 eecd &= ~(E1000_EECD_DI);
3521 if (eecd & E1000_EECD_DO)
3522 data |= 1;
3523
3524 e1000_lower_ee_clk(hw, &eecd);
3525 }
3526
3527 return data;
3528}
3529
3530
3531
3532
3533
3534
3535
3536
3537static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3538{
3539 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3540 u32 eecd, i = 0;
3541
3542 DEBUGFUNC("e1000_acquire_eeprom");
3543
3544 eecd = er32(EECD);
3545
3546
3547 if (hw->mac_type > e1000_82544) {
3548 eecd |= E1000_EECD_REQ;
3549 ew32(EECD, eecd);
3550 eecd = er32(EECD);
3551 while ((!(eecd & E1000_EECD_GNT)) &&
3552 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3553 i++;
3554 udelay(5);
3555 eecd = er32(EECD);
3556 }
3557 if (!(eecd & E1000_EECD_GNT)) {
3558 eecd &= ~E1000_EECD_REQ;
3559 ew32(EECD, eecd);
3560 DEBUGOUT("Could not acquire EEPROM grant\n");
3561 return -E1000_ERR_EEPROM;
3562 }
3563 }
3564
3565
3566
3567 if (eeprom->type == e1000_eeprom_microwire) {
3568
3569 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3570 ew32(EECD, eecd);
3571
3572
3573 eecd |= E1000_EECD_CS;
3574 ew32(EECD, eecd);
3575 } else if (eeprom->type == e1000_eeprom_spi) {
3576
3577 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3578 ew32(EECD, eecd);
3579 udelay(1);
3580 }
3581
3582 return E1000_SUCCESS;
3583}
3584
3585
3586
3587
3588
3589static void e1000_standby_eeprom(struct e1000_hw *hw)
3590{
3591 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3592 u32 eecd;
3593
3594 eecd = er32(EECD);
3595
3596 if (eeprom->type == e1000_eeprom_microwire) {
3597 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3598 ew32(EECD, eecd);
3599 E1000_WRITE_FLUSH();
3600 udelay(eeprom->delay_usec);
3601
3602
3603 eecd |= E1000_EECD_SK;
3604 ew32(EECD, eecd);
3605 E1000_WRITE_FLUSH();
3606 udelay(eeprom->delay_usec);
3607
3608
3609 eecd |= E1000_EECD_CS;
3610 ew32(EECD, eecd);
3611 E1000_WRITE_FLUSH();
3612 udelay(eeprom->delay_usec);
3613
3614
3615 eecd &= ~E1000_EECD_SK;
3616 ew32(EECD, eecd);
3617 E1000_WRITE_FLUSH();
3618 udelay(eeprom->delay_usec);
3619 } else if (eeprom->type == e1000_eeprom_spi) {
3620
3621 eecd |= E1000_EECD_CS;
3622 ew32(EECD, eecd);
3623 E1000_WRITE_FLUSH();
3624 udelay(eeprom->delay_usec);
3625 eecd &= ~E1000_EECD_CS;
3626 ew32(EECD, eecd);
3627 E1000_WRITE_FLUSH();
3628 udelay(eeprom->delay_usec);
3629 }
3630}
3631
3632
3633
3634
3635
3636
3637
3638static void e1000_release_eeprom(struct e1000_hw *hw)
3639{
3640 u32 eecd;
3641
3642 DEBUGFUNC("e1000_release_eeprom");
3643
3644 eecd = er32(EECD);
3645
3646 if (hw->eeprom.type == e1000_eeprom_spi) {
3647 eecd |= E1000_EECD_CS;
3648 eecd &= ~E1000_EECD_SK;
3649
3650 ew32(EECD, eecd);
3651
3652 udelay(hw->eeprom.delay_usec);
3653 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3654
3655
3656
3657 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3658
3659 ew32(EECD, eecd);
3660
3661
3662 eecd |= E1000_EECD_SK;
3663 ew32(EECD, eecd);
3664 E1000_WRITE_FLUSH();
3665 udelay(hw->eeprom.delay_usec);
3666
3667
3668 eecd &= ~E1000_EECD_SK;
3669 ew32(EECD, eecd);
3670 E1000_WRITE_FLUSH();
3671 udelay(hw->eeprom.delay_usec);
3672 }
3673
3674
3675 if (hw->mac_type > e1000_82544) {
3676 eecd &= ~E1000_EECD_REQ;
3677 ew32(EECD, eecd);
3678 }
3679}
3680
3681
3682
3683
3684
3685static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3686{
3687 u16 retry_count = 0;
3688 u8 spi_stat_reg;
3689
3690 DEBUGFUNC("e1000_spi_eeprom_ready");
3691
3692
3693
3694
3695
3696
3697 retry_count = 0;
3698 do {
3699 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3700 hw->eeprom.opcode_bits);
3701 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3702 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3703 break;
3704
3705 udelay(5);
3706 retry_count += 5;
3707
3708 e1000_standby_eeprom(hw);
3709 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3710
3711
3712
3713
3714 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3715 DEBUGOUT("SPI EEPROM Status error\n");
3716 return -E1000_ERR_EEPROM;
3717 }
3718
3719 return E1000_SUCCESS;
3720}
3721
3722
3723
3724
3725
3726
3727
3728
3729s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3730{
3731 s32 ret;
3732 spin_lock(&e1000_eeprom_lock);
3733 ret = e1000_do_read_eeprom(hw, offset, words, data);
3734 spin_unlock(&e1000_eeprom_lock);
3735 return ret;
3736}
3737
3738static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3739 u16 *data)
3740{
3741 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3742 u32 i = 0;
3743
3744 DEBUGFUNC("e1000_read_eeprom");
3745
3746
3747 if (eeprom->word_size == 0)
3748 e1000_init_eeprom_params(hw);
3749
3750
3751
3752
3753 if ((offset >= eeprom->word_size)
3754 || (words > eeprom->word_size - offset) || (words == 0)) {
3755 DEBUGOUT2
3756 ("\"words\" parameter out of bounds. Words = %d, size = %d\n",
3757 offset, eeprom->word_size);
3758 return -E1000_ERR_EEPROM;
3759 }
3760
3761
3762
3763
3764
3765
3766 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3767 return -E1000_ERR_EEPROM;
3768
3769
3770
3771 if (eeprom->type == e1000_eeprom_spi) {
3772 u16 word_in;
3773 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3774
3775 if (e1000_spi_eeprom_ready(hw)) {
3776 e1000_release_eeprom(hw);
3777 return -E1000_ERR_EEPROM;
3778 }
3779
3780 e1000_standby_eeprom(hw);
3781
3782
3783 if ((eeprom->address_bits == 8) && (offset >= 128))
3784 read_opcode |= EEPROM_A8_OPCODE_SPI;
3785
3786
3787 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3788 e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3789 eeprom->address_bits);
3790
3791
3792
3793
3794
3795
3796 for (i = 0; i < words; i++) {
3797 word_in = e1000_shift_in_ee_bits(hw, 16);
3798 data[i] = (word_in >> 8) | (word_in << 8);
3799 }
3800 } else if (eeprom->type == e1000_eeprom_microwire) {
3801 for (i = 0; i < words; i++) {
3802
3803 e1000_shift_out_ee_bits(hw,
3804 EEPROM_READ_OPCODE_MICROWIRE,
3805 eeprom->opcode_bits);
3806 e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3807 eeprom->address_bits);
3808
3809
3810
3811 data[i] = e1000_shift_in_ee_bits(hw, 16);
3812 e1000_standby_eeprom(hw);
3813 }
3814 }
3815
3816
3817 e1000_release_eeprom(hw);
3818
3819 return E1000_SUCCESS;
3820}
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3831{
3832 u16 checksum = 0;
3833 u16 i, eeprom_data;
3834
3835 DEBUGFUNC("e1000_validate_eeprom_checksum");
3836
3837 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3838 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3839 DEBUGOUT("EEPROM Read Error\n");
3840 return -E1000_ERR_EEPROM;
3841 }
3842 checksum += eeprom_data;
3843 }
3844
3845 if (checksum == (u16) EEPROM_SUM)
3846 return E1000_SUCCESS;
3847 else {
3848 DEBUGOUT("EEPROM Checksum Invalid\n");
3849 return -E1000_ERR_EEPROM;
3850 }
3851}
3852
3853
3854
3855
3856
3857
3858
3859
3860s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
3861{
3862 u16 checksum = 0;
3863 u16 i, eeprom_data;
3864
3865 DEBUGFUNC("e1000_update_eeprom_checksum");
3866
3867 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3868 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3869 DEBUGOUT("EEPROM Read Error\n");
3870 return -E1000_ERR_EEPROM;
3871 }
3872 checksum += eeprom_data;
3873 }
3874 checksum = (u16) EEPROM_SUM - checksum;
3875 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3876 DEBUGOUT("EEPROM Write Error\n");
3877 return -E1000_ERR_EEPROM;
3878 }
3879 return E1000_SUCCESS;
3880}
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3893{
3894 s32 ret;
3895 spin_lock(&e1000_eeprom_lock);
3896 ret = e1000_do_write_eeprom(hw, offset, words, data);
3897 spin_unlock(&e1000_eeprom_lock);
3898 return ret;
3899}
3900
3901static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3902 u16 *data)
3903{
3904 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3905 s32 status = 0;
3906
3907 DEBUGFUNC("e1000_write_eeprom");
3908
3909
3910 if (eeprom->word_size == 0)
3911 e1000_init_eeprom_params(hw);
3912
3913
3914
3915
3916 if ((offset >= eeprom->word_size)
3917 || (words > eeprom->word_size - offset) || (words == 0)) {
3918 DEBUGOUT("\"words\" parameter out of bounds\n");
3919 return -E1000_ERR_EEPROM;
3920 }
3921
3922
3923 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3924 return -E1000_ERR_EEPROM;
3925
3926 if (eeprom->type == e1000_eeprom_microwire) {
3927 status = e1000_write_eeprom_microwire(hw, offset, words, data);
3928 } else {
3929 status = e1000_write_eeprom_spi(hw, offset, words, data);
3930 msleep(10);
3931 }
3932
3933
3934 e1000_release_eeprom(hw);
3935
3936 return status;
3937}
3938
3939
3940
3941
3942
3943
3944
3945
3946static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
3947 u16 *data)
3948{
3949 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3950 u16 widx = 0;
3951
3952 DEBUGFUNC("e1000_write_eeprom_spi");
3953
3954 while (widx < words) {
3955 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
3956
3957 if (e1000_spi_eeprom_ready(hw))
3958 return -E1000_ERR_EEPROM;
3959
3960 e1000_standby_eeprom(hw);
3961
3962
3963 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3964 eeprom->opcode_bits);
3965
3966 e1000_standby_eeprom(hw);
3967
3968
3969 if ((eeprom->address_bits == 8) && (offset >= 128))
3970 write_opcode |= EEPROM_A8_OPCODE_SPI;
3971
3972
3973 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3974
3975 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
3976 eeprom->address_bits);
3977
3978
3979
3980
3981 while (widx < words) {
3982 u16 word_out = data[widx];
3983 word_out = (word_out >> 8) | (word_out << 8);
3984 e1000_shift_out_ee_bits(hw, word_out, 16);
3985 widx++;
3986
3987
3988
3989
3990
3991 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
3992 e1000_standby_eeprom(hw);
3993 break;
3994 }
3995 }
3996 }
3997
3998 return E1000_SUCCESS;
3999}
4000
4001
4002
4003
4004
4005
4006
4007
4008static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4009 u16 words, u16 *data)
4010{
4011 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4012 u32 eecd;
4013 u16 words_written = 0;
4014 u16 i = 0;
4015
4016 DEBUGFUNC("e1000_write_eeprom_microwire");
4017
4018
4019
4020
4021
4022
4023
4024 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4025 (u16) (eeprom->opcode_bits + 2));
4026
4027 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4028
4029
4030 e1000_standby_eeprom(hw);
4031
4032 while (words_written < words) {
4033
4034 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4035 eeprom->opcode_bits);
4036
4037 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
4038 eeprom->address_bits);
4039
4040
4041 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4042
4043
4044
4045
4046 e1000_standby_eeprom(hw);
4047
4048
4049
4050
4051
4052 for (i = 0; i < 200; i++) {
4053 eecd = er32(EECD);
4054 if (eecd & E1000_EECD_DO)
4055 break;
4056 udelay(50);
4057 }
4058 if (i == 200) {
4059 DEBUGOUT("EEPROM Write did not complete\n");
4060 return -E1000_ERR_EEPROM;
4061 }
4062
4063
4064 e1000_standby_eeprom(hw);
4065
4066 words_written++;
4067 }
4068
4069
4070
4071
4072
4073
4074
4075 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4076 (u16) (eeprom->opcode_bits + 2));
4077
4078 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4079
4080 return E1000_SUCCESS;
4081}
4082
4083
4084
4085
4086
4087
4088
4089
4090s32 e1000_read_mac_addr(struct e1000_hw *hw)
4091{
4092 u16 offset;
4093 u16 eeprom_data, i;
4094
4095 DEBUGFUNC("e1000_read_mac_addr");
4096
4097 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4098 offset = i >> 1;
4099 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4100 DEBUGOUT("EEPROM Read Error\n");
4101 return -E1000_ERR_EEPROM;
4102 }
4103 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
4104 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
4105 }
4106
4107 switch (hw->mac_type) {
4108 default:
4109 break;
4110 case e1000_82546:
4111 case e1000_82546_rev_3:
4112 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4113 hw->perm_mac_addr[5] ^= 0x01;
4114 break;
4115 }
4116
4117 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4118 hw->mac_addr[i] = hw->perm_mac_addr[i];
4119 return E1000_SUCCESS;
4120}
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130static void e1000_init_rx_addrs(struct e1000_hw *hw)
4131{
4132 u32 i;
4133 u32 rar_num;
4134
4135 DEBUGFUNC("e1000_init_rx_addrs");
4136
4137
4138 DEBUGOUT("Programming MAC Address into RAR[0]\n");
4139
4140 e1000_rar_set(hw, hw->mac_addr, 0);
4141
4142 rar_num = E1000_RAR_ENTRIES;
4143
4144
4145 DEBUGOUT("Clearing RAR[1-15]\n");
4146 for (i = 1; i < rar_num; i++) {
4147 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4148 E1000_WRITE_FLUSH();
4149 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4150 E1000_WRITE_FLUSH();
4151 }
4152}
4153
4154
4155
4156
4157
4158
4159u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4160{
4161 u32 hash_value = 0;
4162
4163
4164
4165
4166 switch (hw->mc_filter_type) {
4167
4168
4169
4170
4171 case 0:
4172
4173 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
4174 break;
4175 case 1:
4176
4177 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
4178 break;
4179 case 2:
4180
4181 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
4182 break;
4183 case 3:
4184
4185 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
4186 break;
4187 }
4188
4189 hash_value &= 0xFFF;
4190 return hash_value;
4191}
4192
4193
4194
4195
4196
4197
4198
4199void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4200{
4201 u32 rar_low, rar_high;
4202
4203
4204
4205
4206 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
4207 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
4208 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228 switch (hw->mac_type) {
4229 default:
4230
4231 rar_high |= E1000_RAH_AV;
4232 break;
4233 }
4234
4235 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4236 E1000_WRITE_FLUSH();
4237 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4238 E1000_WRITE_FLUSH();
4239}
4240
4241
4242
4243
4244
4245
4246
4247void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4248{
4249 u32 temp;
4250
4251 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4252 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4253 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4254 E1000_WRITE_FLUSH();
4255 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4256 E1000_WRITE_FLUSH();
4257 } else {
4258 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4259 E1000_WRITE_FLUSH();
4260 }
4261}
4262
4263
4264
4265
4266
4267static void e1000_clear_vfta(struct e1000_hw *hw)
4268{
4269 u32 offset;
4270 u32 vfta_value = 0;
4271 u32 vfta_offset = 0;
4272 u32 vfta_bit_in_reg = 0;
4273
4274 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4275
4276
4277
4278 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4279 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4280 E1000_WRITE_FLUSH();
4281 }
4282}
4283
4284static s32 e1000_id_led_init(struct e1000_hw *hw)
4285{
4286 u32 ledctl;
4287 const u32 ledctl_mask = 0x000000FF;
4288 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4289 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4290 u16 eeprom_data, i, temp;
4291 const u16 led_mask = 0x0F;
4292
4293 DEBUGFUNC("e1000_id_led_init");
4294
4295 if (hw->mac_type < e1000_82540) {
4296
4297 return E1000_SUCCESS;
4298 }
4299
4300 ledctl = er32(LEDCTL);
4301 hw->ledctl_default = ledctl;
4302 hw->ledctl_mode1 = hw->ledctl_default;
4303 hw->ledctl_mode2 = hw->ledctl_default;
4304
4305 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4306 DEBUGOUT("EEPROM Read Error\n");
4307 return -E1000_ERR_EEPROM;
4308 }
4309
4310 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4311 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4312 eeprom_data = ID_LED_DEFAULT;
4313 }
4314
4315 for (i = 0; i < 4; i++) {
4316 temp = (eeprom_data >> (i << 2)) & led_mask;
4317 switch (temp) {
4318 case ID_LED_ON1_DEF2:
4319 case ID_LED_ON1_ON2:
4320 case ID_LED_ON1_OFF2:
4321 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4322 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4323 break;
4324 case ID_LED_OFF1_DEF2:
4325 case ID_LED_OFF1_ON2:
4326 case ID_LED_OFF1_OFF2:
4327 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4328 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4329 break;
4330 default:
4331
4332 break;
4333 }
4334 switch (temp) {
4335 case ID_LED_DEF1_ON2:
4336 case ID_LED_ON1_ON2:
4337 case ID_LED_OFF1_ON2:
4338 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4339 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4340 break;
4341 case ID_LED_DEF1_OFF2:
4342 case ID_LED_ON1_OFF2:
4343 case ID_LED_OFF1_OFF2:
4344 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4345 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4346 break;
4347 default:
4348
4349 break;
4350 }
4351 }
4352 return E1000_SUCCESS;
4353}
4354
4355
4356
4357
4358
4359
4360
4361s32 e1000_setup_led(struct e1000_hw *hw)
4362{
4363 u32 ledctl;
4364 s32 ret_val = E1000_SUCCESS;
4365
4366 DEBUGFUNC("e1000_setup_led");
4367
4368 switch (hw->mac_type) {
4369 case e1000_82542_rev2_0:
4370 case e1000_82542_rev2_1:
4371 case e1000_82543:
4372 case e1000_82544:
4373
4374 break;
4375 case e1000_82541:
4376 case e1000_82547:
4377 case e1000_82541_rev_2:
4378 case e1000_82547_rev_2:
4379
4380 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4381 &hw->phy_spd_default);
4382 if (ret_val)
4383 return ret_val;
4384 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4385 (u16) (hw->phy_spd_default &
4386 ~IGP01E1000_GMII_SPD));
4387 if (ret_val)
4388 return ret_val;
4389
4390 default:
4391 if (hw->media_type == e1000_media_type_fiber) {
4392 ledctl = er32(LEDCTL);
4393
4394 hw->ledctl_default = ledctl;
4395
4396 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4397 E1000_LEDCTL_LED0_BLINK |
4398 E1000_LEDCTL_LED0_MODE_MASK);
4399 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4400 E1000_LEDCTL_LED0_MODE_SHIFT);
4401 ew32(LEDCTL, ledctl);
4402 } else if (hw->media_type == e1000_media_type_copper)
4403 ew32(LEDCTL, hw->ledctl_mode1);
4404 break;
4405 }
4406
4407 return E1000_SUCCESS;
4408}
4409
4410
4411
4412
4413
4414s32 e1000_cleanup_led(struct e1000_hw *hw)
4415{
4416 s32 ret_val = E1000_SUCCESS;
4417
4418 DEBUGFUNC("e1000_cleanup_led");
4419
4420 switch (hw->mac_type) {
4421 case e1000_82542_rev2_0:
4422 case e1000_82542_rev2_1:
4423 case e1000_82543:
4424 case e1000_82544:
4425
4426 break;
4427 case e1000_82541:
4428 case e1000_82547:
4429 case e1000_82541_rev_2:
4430 case e1000_82547_rev_2:
4431
4432 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4433 hw->phy_spd_default);
4434 if (ret_val)
4435 return ret_val;
4436
4437 default:
4438
4439 ew32(LEDCTL, hw->ledctl_default);
4440 break;
4441 }
4442
4443 return E1000_SUCCESS;
4444}
4445
4446
4447
4448
4449
4450s32 e1000_led_on(struct e1000_hw *hw)
4451{
4452 u32 ctrl = er32(CTRL);
4453
4454 DEBUGFUNC("e1000_led_on");
4455
4456 switch (hw->mac_type) {
4457 case e1000_82542_rev2_0:
4458 case e1000_82542_rev2_1:
4459 case e1000_82543:
4460
4461 ctrl |= E1000_CTRL_SWDPIN0;
4462 ctrl |= E1000_CTRL_SWDPIO0;
4463 break;
4464 case e1000_82544:
4465 if (hw->media_type == e1000_media_type_fiber) {
4466
4467 ctrl |= E1000_CTRL_SWDPIN0;
4468 ctrl |= E1000_CTRL_SWDPIO0;
4469 } else {
4470
4471 ctrl &= ~E1000_CTRL_SWDPIN0;
4472 ctrl |= E1000_CTRL_SWDPIO0;
4473 }
4474 break;
4475 default:
4476 if (hw->media_type == e1000_media_type_fiber) {
4477
4478 ctrl &= ~E1000_CTRL_SWDPIN0;
4479 ctrl |= E1000_CTRL_SWDPIO0;
4480 } else if (hw->media_type == e1000_media_type_copper) {
4481 ew32(LEDCTL, hw->ledctl_mode2);
4482 return E1000_SUCCESS;
4483 }
4484 break;
4485 }
4486
4487 ew32(CTRL, ctrl);
4488
4489 return E1000_SUCCESS;
4490}
4491
4492
4493
4494
4495
4496s32 e1000_led_off(struct e1000_hw *hw)
4497{
4498 u32 ctrl = er32(CTRL);
4499
4500 DEBUGFUNC("e1000_led_off");
4501
4502 switch (hw->mac_type) {
4503 case e1000_82542_rev2_0:
4504 case e1000_82542_rev2_1:
4505 case e1000_82543:
4506
4507 ctrl &= ~E1000_CTRL_SWDPIN0;
4508 ctrl |= E1000_CTRL_SWDPIO0;
4509 break;
4510 case e1000_82544:
4511 if (hw->media_type == e1000_media_type_fiber) {
4512
4513 ctrl &= ~E1000_CTRL_SWDPIN0;
4514 ctrl |= E1000_CTRL_SWDPIO0;
4515 } else {
4516
4517 ctrl |= E1000_CTRL_SWDPIN0;
4518 ctrl |= E1000_CTRL_SWDPIO0;
4519 }
4520 break;
4521 default:
4522 if (hw->media_type == e1000_media_type_fiber) {
4523
4524 ctrl |= E1000_CTRL_SWDPIN0;
4525 ctrl |= E1000_CTRL_SWDPIO0;
4526 } else if (hw->media_type == e1000_media_type_copper) {
4527 ew32(LEDCTL, hw->ledctl_mode1);
4528 return E1000_SUCCESS;
4529 }
4530 break;
4531 }
4532
4533 ew32(CTRL, ctrl);
4534
4535 return E1000_SUCCESS;
4536}
4537
4538
4539
4540
4541
4542static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4543{
4544 volatile u32 temp;
4545
4546 temp = er32(CRCERRS);
4547 temp = er32(SYMERRS);
4548 temp = er32(MPC);
4549 temp = er32(SCC);
4550 temp = er32(ECOL);
4551 temp = er32(MCC);
4552 temp = er32(LATECOL);
4553 temp = er32(COLC);
4554 temp = er32(DC);
4555 temp = er32(SEC);
4556 temp = er32(RLEC);
4557 temp = er32(XONRXC);
4558 temp = er32(XONTXC);
4559 temp = er32(XOFFRXC);
4560 temp = er32(XOFFTXC);
4561 temp = er32(FCRUC);
4562
4563 temp = er32(PRC64);
4564 temp = er32(PRC127);
4565 temp = er32(PRC255);
4566 temp = er32(PRC511);
4567 temp = er32(PRC1023);
4568 temp = er32(PRC1522);
4569
4570 temp = er32(GPRC);
4571 temp = er32(BPRC);
4572 temp = er32(MPRC);
4573 temp = er32(GPTC);
4574 temp = er32(GORCL);
4575 temp = er32(GORCH);
4576 temp = er32(GOTCL);
4577 temp = er32(GOTCH);
4578 temp = er32(RNBC);
4579 temp = er32(RUC);
4580 temp = er32(RFC);
4581 temp = er32(ROC);
4582 temp = er32(RJC);
4583 temp = er32(TORL);
4584 temp = er32(TORH);
4585 temp = er32(TOTL);
4586 temp = er32(TOTH);
4587 temp = er32(TPR);
4588 temp = er32(TPT);
4589
4590 temp = er32(PTC64);
4591 temp = er32(PTC127);
4592 temp = er32(PTC255);
4593 temp = er32(PTC511);
4594 temp = er32(PTC1023);
4595 temp = er32(PTC1522);
4596
4597 temp = er32(MPTC);
4598 temp = er32(BPTC);
4599
4600 if (hw->mac_type < e1000_82543)
4601 return;
4602
4603 temp = er32(ALGNERRC);
4604 temp = er32(RXERRC);
4605 temp = er32(TNCRS);
4606 temp = er32(CEXTERR);
4607 temp = er32(TSCTC);
4608 temp = er32(TSCTFC);
4609
4610 if (hw->mac_type <= e1000_82544)
4611 return;
4612
4613 temp = er32(MGTPRC);
4614 temp = er32(MGTPDC);
4615 temp = er32(MGTPTC);
4616}
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627void e1000_reset_adaptive(struct e1000_hw *hw)
4628{
4629 DEBUGFUNC("e1000_reset_adaptive");
4630
4631 if (hw->adaptive_ifs) {
4632 if (!hw->ifs_params_forced) {
4633 hw->current_ifs_val = 0;
4634 hw->ifs_min_val = IFS_MIN;
4635 hw->ifs_max_val = IFS_MAX;
4636 hw->ifs_step_size = IFS_STEP;
4637 hw->ifs_ratio = IFS_RATIO;
4638 }
4639 hw->in_ifs_mode = false;
4640 ew32(AIT, 0);
4641 } else {
4642 DEBUGOUT("Not in Adaptive IFS mode!\n");
4643 }
4644}
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655void e1000_update_adaptive(struct e1000_hw *hw)
4656{
4657 DEBUGFUNC("e1000_update_adaptive");
4658
4659 if (hw->adaptive_ifs) {
4660 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
4661 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4662 hw->in_ifs_mode = true;
4663 if (hw->current_ifs_val < hw->ifs_max_val) {
4664 if (hw->current_ifs_val == 0)
4665 hw->current_ifs_val =
4666 hw->ifs_min_val;
4667 else
4668 hw->current_ifs_val +=
4669 hw->ifs_step_size;
4670 ew32(AIT, hw->current_ifs_val);
4671 }
4672 }
4673 } else {
4674 if (hw->in_ifs_mode
4675 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4676 hw->current_ifs_val = 0;
4677 hw->in_ifs_mode = false;
4678 ew32(AIT, 0);
4679 }
4680 }
4681 } else {
4682 DEBUGOUT("Not in Adaptive IFS mode!\n");
4683 }
4684}
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
4695 u32 frame_len, u8 *mac_addr)
4696{
4697 u64 carry_bit;
4698
4699
4700 frame_len--;
4701
4702
4703
4704
4705
4706 stats->crcerrs--;
4707
4708 stats->gprc++;
4709
4710
4711 carry_bit = 0x80000000 & stats->gorcl;
4712 stats->gorcl += frame_len;
4713
4714
4715
4716
4717
4718
4719
4720 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
4721 stats->gorch++;
4722
4723
4724
4725
4726 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
4727
4728 stats->bprc++;
4729 else if (*mac_addr & 0x01)
4730
4731 stats->mprc++;
4732
4733 if (frame_len == hw->max_frame_size) {
4734
4735
4736
4737 if (stats->roc > 0)
4738 stats->roc--;
4739 }
4740
4741
4742
4743
4744 if (frame_len == 64) {
4745 stats->prc64++;
4746 stats->prc127--;
4747 } else if (frame_len == 127) {
4748 stats->prc127++;
4749 stats->prc255--;
4750 } else if (frame_len == 255) {
4751 stats->prc255++;
4752 stats->prc511--;
4753 } else if (frame_len == 511) {
4754 stats->prc511++;
4755 stats->prc1023--;
4756 } else if (frame_len == 1023) {
4757 stats->prc1023++;
4758 stats->prc1522--;
4759 } else if (frame_len == 1522) {
4760 stats->prc1522++;
4761 }
4762}
4763
4764
4765
4766
4767
4768
4769
4770void e1000_get_bus_info(struct e1000_hw *hw)
4771{
4772 u32 status;
4773
4774 switch (hw->mac_type) {
4775 case e1000_82542_rev2_0:
4776 case e1000_82542_rev2_1:
4777 hw->bus_type = e1000_bus_type_pci;
4778 hw->bus_speed = e1000_bus_speed_unknown;
4779 hw->bus_width = e1000_bus_width_unknown;
4780 break;
4781 default:
4782 status = er32(STATUS);
4783 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4784 e1000_bus_type_pcix : e1000_bus_type_pci;
4785
4786 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4787 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4788 e1000_bus_speed_66 : e1000_bus_speed_120;
4789 } else if (hw->bus_type == e1000_bus_type_pci) {
4790 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4791 e1000_bus_speed_66 : e1000_bus_speed_33;
4792 } else {
4793 switch (status & E1000_STATUS_PCIX_SPEED) {
4794 case E1000_STATUS_PCIX_SPEED_66:
4795 hw->bus_speed = e1000_bus_speed_66;
4796 break;
4797 case E1000_STATUS_PCIX_SPEED_100:
4798 hw->bus_speed = e1000_bus_speed_100;
4799 break;
4800 case E1000_STATUS_PCIX_SPEED_133:
4801 hw->bus_speed = e1000_bus_speed_133;
4802 break;
4803 default:
4804 hw->bus_speed = e1000_bus_speed_reserved;
4805 break;
4806 }
4807 }
4808 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4809 e1000_bus_width_64 : e1000_bus_width_32;
4810 break;
4811 }
4812}
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4824{
4825 unsigned long io_addr = hw->io_base;
4826 unsigned long io_data = hw->io_base + 4;
4827
4828 e1000_io_write(hw, io_addr, offset);
4829 e1000_io_write(hw, io_data, value);
4830}
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4847 u16 *max_length)
4848{
4849 s32 ret_val;
4850 u16 agc_value = 0;
4851 u16 i, phy_data;
4852 u16 cable_length;
4853
4854 DEBUGFUNC("e1000_get_cable_length");
4855
4856 *min_length = *max_length = 0;
4857
4858
4859 if (hw->phy_type == e1000_phy_m88) {
4860
4861 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4862 &phy_data);
4863 if (ret_val)
4864 return ret_val;
4865 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4866 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4867
4868
4869 switch (cable_length) {
4870 case e1000_cable_length_50:
4871 *min_length = 0;
4872 *max_length = e1000_igp_cable_length_50;
4873 break;
4874 case e1000_cable_length_50_80:
4875 *min_length = e1000_igp_cable_length_50;
4876 *max_length = e1000_igp_cable_length_80;
4877 break;
4878 case e1000_cable_length_80_110:
4879 *min_length = e1000_igp_cable_length_80;
4880 *max_length = e1000_igp_cable_length_110;
4881 break;
4882 case e1000_cable_length_110_140:
4883 *min_length = e1000_igp_cable_length_110;
4884 *max_length = e1000_igp_cable_length_140;
4885 break;
4886 case e1000_cable_length_140:
4887 *min_length = e1000_igp_cable_length_140;
4888 *max_length = e1000_igp_cable_length_170;
4889 break;
4890 default:
4891 return -E1000_ERR_PHY;
4892 break;
4893 }
4894 } else if (hw->phy_type == e1000_phy_igp) {
4895 u16 cur_agc_value;
4896 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4897 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4898 { IGP01E1000_PHY_AGC_A,
4899 IGP01E1000_PHY_AGC_B,
4900 IGP01E1000_PHY_AGC_C,
4901 IGP01E1000_PHY_AGC_D
4902 };
4903
4904 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4905
4906 ret_val =
4907 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4908 if (ret_val)
4909 return ret_val;
4910
4911 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4912
4913
4914 if ((cur_agc_value >=
4915 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
4916 || (cur_agc_value == 0))
4917 return -E1000_ERR_PHY;
4918
4919 agc_value += cur_agc_value;
4920
4921
4922 if (min_agc_value > cur_agc_value)
4923 min_agc_value = cur_agc_value;
4924 }
4925
4926
4927 if (agc_value <
4928 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4929 agc_value -= min_agc_value;
4930
4931
4932 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4933 } else {
4934
4935 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4936 }
4937
4938
4939 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4940 IGP01E1000_AGC_RANGE) > 0) ?
4941 (e1000_igp_cable_length_table[agc_value] -
4942 IGP01E1000_AGC_RANGE) : 0;
4943 *max_length = e1000_igp_cable_length_table[agc_value] +
4944 IGP01E1000_AGC_RANGE;
4945 }
4946
4947 return E1000_SUCCESS;
4948}
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965static s32 e1000_check_polarity(struct e1000_hw *hw,
4966 e1000_rev_polarity *polarity)
4967{
4968 s32 ret_val;
4969 u16 phy_data;
4970
4971 DEBUGFUNC("e1000_check_polarity");
4972
4973 if (hw->phy_type == e1000_phy_m88) {
4974
4975 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4976 &phy_data);
4977 if (ret_val)
4978 return ret_val;
4979 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
4980 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
4981 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4982
4983 } else if (hw->phy_type == e1000_phy_igp) {
4984
4985 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4986 &phy_data);
4987 if (ret_val)
4988 return ret_val;
4989
4990
4991
4992 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4993 IGP01E1000_PSSR_SPEED_1000MBPS) {
4994
4995
4996 ret_val =
4997 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4998 &phy_data);
4999 if (ret_val)
5000 return ret_val;
5001
5002
5003 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5004 e1000_rev_polarity_reversed :
5005 e1000_rev_polarity_normal;
5006 } else {
5007
5008
5009 *polarity =
5010 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5011 e1000_rev_polarity_reversed :
5012 e1000_rev_polarity_normal;
5013 }
5014 }
5015 return E1000_SUCCESS;
5016}
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032static s32 e1000_check_downshift(struct e1000_hw *hw)
5033{
5034 s32 ret_val;
5035 u16 phy_data;
5036
5037 DEBUGFUNC("e1000_check_downshift");
5038
5039 if (hw->phy_type == e1000_phy_igp) {
5040 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5041 &phy_data);
5042 if (ret_val)
5043 return ret_val;
5044
5045 hw->speed_downgraded =
5046 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5047 } else if (hw->phy_type == e1000_phy_m88) {
5048 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5049 &phy_data);
5050 if (ret_val)
5051 return ret_val;
5052
5053 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5054 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5055 }
5056
5057 return E1000_SUCCESS;
5058}
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5073{
5074 s32 ret_val;
5075 u16 phy_data, phy_saved_data, speed, duplex, i;
5076 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5077 { IGP01E1000_PHY_AGC_PARAM_A,
5078 IGP01E1000_PHY_AGC_PARAM_B,
5079 IGP01E1000_PHY_AGC_PARAM_C,
5080 IGP01E1000_PHY_AGC_PARAM_D
5081 };
5082 u16 min_length, max_length;
5083
5084 DEBUGFUNC("e1000_config_dsp_after_link_change");
5085
5086 if (hw->phy_type != e1000_phy_igp)
5087 return E1000_SUCCESS;
5088
5089 if (link_up) {
5090 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5091 if (ret_val) {
5092 DEBUGOUT("Error getting link speed and duplex\n");
5093 return ret_val;
5094 }
5095
5096 if (speed == SPEED_1000) {
5097
5098 ret_val =
5099 e1000_get_cable_length(hw, &min_length,
5100 &max_length);
5101 if (ret_val)
5102 return ret_val;
5103
5104 if ((hw->dsp_config_state == e1000_dsp_config_enabled)
5105 && min_length >= e1000_igp_cable_length_50) {
5106
5107 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5108 ret_val =
5109 e1000_read_phy_reg(hw,
5110 dsp_reg_array[i],
5111 &phy_data);
5112 if (ret_val)
5113 return ret_val;
5114
5115 phy_data &=
5116 ~IGP01E1000_PHY_EDAC_MU_INDEX;
5117
5118 ret_val =
5119 e1000_write_phy_reg(hw,
5120 dsp_reg_array
5121 [i], phy_data);
5122 if (ret_val)
5123 return ret_val;
5124 }
5125 hw->dsp_config_state =
5126 e1000_dsp_config_activated;
5127 }
5128
5129 if ((hw->ffe_config_state == e1000_ffe_config_enabled)
5130 && (min_length < e1000_igp_cable_length_50)) {
5131
5132 u16 ffe_idle_err_timeout =
5133 FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5134 u32 idle_errs = 0;
5135
5136
5137 ret_val =
5138 e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5139 &phy_data);
5140 if (ret_val)
5141 return ret_val;
5142
5143 for (i = 0; i < ffe_idle_err_timeout; i++) {
5144 udelay(1000);
5145 ret_val =
5146 e1000_read_phy_reg(hw,
5147 PHY_1000T_STATUS,
5148 &phy_data);
5149 if (ret_val)
5150 return ret_val;
5151
5152 idle_errs +=
5153 (phy_data &
5154 SR_1000T_IDLE_ERROR_CNT);
5155 if (idle_errs >
5156 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
5157 {
5158 hw->ffe_config_state =
5159 e1000_ffe_config_active;
5160
5161 ret_val =
5162 e1000_write_phy_reg(hw,
5163 IGP01E1000_PHY_DSP_FFE,
5164 IGP01E1000_PHY_DSP_FFE_CM_CP);
5165 if (ret_val)
5166 return ret_val;
5167 break;
5168 }
5169
5170 if (idle_errs)
5171 ffe_idle_err_timeout =
5172 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5173 }
5174 }
5175 }
5176 } else {
5177 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5178
5179
5180 ret_val =
5181 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5182
5183 if (ret_val)
5184 return ret_val;
5185
5186
5187 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5188
5189 if (ret_val)
5190 return ret_val;
5191
5192 mdelay(20);
5193
5194 ret_val = e1000_write_phy_reg(hw, 0x0000,
5195 IGP01E1000_IEEE_FORCE_GIGA);
5196 if (ret_val)
5197 return ret_val;
5198 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5199 ret_val =
5200 e1000_read_phy_reg(hw, dsp_reg_array[i],
5201 &phy_data);
5202 if (ret_val)
5203 return ret_val;
5204
5205 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5206 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5207
5208 ret_val =
5209 e1000_write_phy_reg(hw, dsp_reg_array[i],
5210 phy_data);
5211 if (ret_val)
5212 return ret_val;
5213 }
5214
5215 ret_val = e1000_write_phy_reg(hw, 0x0000,
5216 IGP01E1000_IEEE_RESTART_AUTONEG);
5217 if (ret_val)
5218 return ret_val;
5219
5220 mdelay(20);
5221
5222
5223 ret_val =
5224 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5225
5226 if (ret_val)
5227 return ret_val;
5228
5229 hw->dsp_config_state = e1000_dsp_config_enabled;
5230 }
5231
5232 if (hw->ffe_config_state == e1000_ffe_config_active) {
5233
5234
5235 ret_val =
5236 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5237
5238 if (ret_val)
5239 return ret_val;
5240
5241
5242 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5243
5244 if (ret_val)
5245 return ret_val;
5246
5247 mdelay(20);
5248
5249 ret_val = e1000_write_phy_reg(hw, 0x0000,
5250 IGP01E1000_IEEE_FORCE_GIGA);
5251 if (ret_val)
5252 return ret_val;
5253 ret_val =
5254 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5255 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5256 if (ret_val)
5257 return ret_val;
5258
5259 ret_val = e1000_write_phy_reg(hw, 0x0000,
5260 IGP01E1000_IEEE_RESTART_AUTONEG);
5261 if (ret_val)
5262 return ret_val;
5263
5264 mdelay(20);
5265
5266
5267 ret_val =
5268 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5269
5270 if (ret_val)
5271 return ret_val;
5272
5273 hw->ffe_config_state = e1000_ffe_config_enabled;
5274 }
5275 }
5276 return E1000_SUCCESS;
5277}
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5288{
5289 s32 ret_val;
5290 u16 eeprom_data;
5291
5292 DEBUGFUNC("e1000_set_phy_mode");
5293
5294 if ((hw->mac_type == e1000_82545_rev_3) &&
5295 (hw->media_type == e1000_media_type_copper)) {
5296 ret_val =
5297 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5298 &eeprom_data);
5299 if (ret_val) {
5300 return ret_val;
5301 }
5302
5303 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5304 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5305 ret_val =
5306 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5307 0x000B);
5308 if (ret_val)
5309 return ret_val;
5310 ret_val =
5311 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5312 0x8104);
5313 if (ret_val)
5314 return ret_val;
5315
5316 hw->phy_reset_disable = false;
5317 }
5318 }
5319
5320 return E1000_SUCCESS;
5321}
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5337{
5338 s32 ret_val;
5339 u16 phy_data;
5340 DEBUGFUNC("e1000_set_d3_lplu_state");
5341
5342 if (hw->phy_type != e1000_phy_igp)
5343 return E1000_SUCCESS;
5344
5345
5346
5347
5348 if (hw->mac_type == e1000_82541_rev_2
5349 || hw->mac_type == e1000_82547_rev_2) {
5350 ret_val =
5351 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5352 if (ret_val)
5353 return ret_val;
5354 }
5355
5356 if (!active) {
5357 if (hw->mac_type == e1000_82541_rev_2 ||
5358 hw->mac_type == e1000_82547_rev_2) {
5359 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5360 ret_val =
5361 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5362 phy_data);
5363 if (ret_val)
5364 return ret_val;
5365 }
5366
5367
5368
5369
5370
5371 if (hw->smart_speed == e1000_smart_speed_on) {
5372 ret_val =
5373 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5374 &phy_data);
5375 if (ret_val)
5376 return ret_val;
5377
5378 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5379 ret_val =
5380 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5381 phy_data);
5382 if (ret_val)
5383 return ret_val;
5384 } else if (hw->smart_speed == e1000_smart_speed_off) {
5385 ret_val =
5386 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5387 &phy_data);
5388 if (ret_val)
5389 return ret_val;
5390
5391 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5392 ret_val =
5393 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5394 phy_data);
5395 if (ret_val)
5396 return ret_val;
5397 }
5398 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5399 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5400 || (hw->autoneg_advertised ==
5401 AUTONEG_ADVERTISE_10_100_ALL)) {
5402
5403 if (hw->mac_type == e1000_82541_rev_2 ||
5404 hw->mac_type == e1000_82547_rev_2) {
5405 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5406 ret_val =
5407 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5408 phy_data);
5409 if (ret_val)
5410 return ret_val;
5411 }
5412
5413
5414 ret_val =
5415 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5416 &phy_data);
5417 if (ret_val)
5418 return ret_val;
5419
5420 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5421 ret_val =
5422 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5423 phy_data);
5424 if (ret_val)
5425 return ret_val;
5426
5427 }
5428 return E1000_SUCCESS;
5429}
5430
5431
5432
5433
5434
5435
5436
5437static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5438{
5439 s32 ret_val;
5440 u16 default_page = 0;
5441 u16 phy_data;
5442
5443 DEBUGFUNC("e1000_set_vco_speed");
5444
5445 switch (hw->mac_type) {
5446 case e1000_82545_rev_3:
5447 case e1000_82546_rev_3:
5448 break;
5449 default:
5450 return E1000_SUCCESS;
5451 }
5452
5453
5454
5455 ret_val =
5456 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5457 if (ret_val)
5458 return ret_val;
5459
5460 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5461 if (ret_val)
5462 return ret_val;
5463
5464 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5465 if (ret_val)
5466 return ret_val;
5467
5468 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5469 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5470 if (ret_val)
5471 return ret_val;
5472
5473
5474
5475 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5476 if (ret_val)
5477 return ret_val;
5478
5479 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5480 if (ret_val)
5481 return ret_val;
5482
5483 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5484 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5485 if (ret_val)
5486 return ret_val;
5487
5488 ret_val =
5489 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5490 if (ret_val)
5491 return ret_val;
5492
5493 return E1000_SUCCESS;
5494}
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5505{
5506 u32 manc;
5507
5508 if (hw->asf_firmware_present) {
5509 manc = er32(MANC);
5510
5511 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5512 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5513 return false;
5514 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5515 return true;
5516 }
5517 return false;
5518}
5519
5520static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5521{
5522 s32 ret_val;
5523 u16 mii_status_reg;
5524 u16 i;
5525
5526
5527
5528
5529
5530 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5531 if (ret_val)
5532 return ret_val;
5533 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5534 if (ret_val)
5535 return ret_val;
5536
5537 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5538 if (ret_val)
5539 return ret_val;
5540
5541
5542 for (i = PHY_FORCE_TIME; i > 0; i--) {
5543
5544
5545
5546
5547 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5548 if (ret_val)
5549 return ret_val;
5550
5551 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5552 if (ret_val)
5553 return ret_val;
5554
5555 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5556 break;
5557 mdelay(100);
5558 }
5559
5560
5561 mdelay(1000);
5562
5563
5564
5565 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5566 if (ret_val)
5567 return ret_val;
5568 mdelay(50);
5569 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5570 if (ret_val)
5571 return ret_val;
5572 mdelay(50);
5573 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5574 if (ret_val)
5575 return ret_val;
5576 mdelay(50);
5577 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5578 if (ret_val)
5579 return ret_val;
5580
5581 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5582 if (ret_val)
5583 return ret_val;
5584
5585
5586 for (i = PHY_FORCE_TIME; i > 0; i--) {
5587
5588
5589
5590
5591 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5592 if (ret_val)
5593 return ret_val;
5594
5595 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5596 if (ret_val)
5597 return ret_val;
5598
5599 if (mii_status_reg & MII_SR_LINK_STATUS)
5600 break;
5601 mdelay(100);
5602 }
5603 return E1000_SUCCESS;
5604}
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5615{
5616 DEBUGFUNC("e1000_get_auto_rd_done");
5617 msleep(5);
5618 return E1000_SUCCESS;
5619}
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5630{
5631 DEBUGFUNC("e1000_get_phy_cfg_done");
5632 mdelay(10);
5633 return E1000_SUCCESS;
5634}
5635