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57#include <linux/netdevice.h>
58#include <linux/ethtool.h>
59#include <linux/delay.h>
60#include <linux/pci.h>
61
62#include "e1000.h"
63
64#define ICH_FLASH_GFPREG 0x0000
65#define ICH_FLASH_HSFSTS 0x0004
66#define ICH_FLASH_HSFCTL 0x0006
67#define ICH_FLASH_FADDR 0x0008
68#define ICH_FLASH_FDATA0 0x0010
69#define ICH_FLASH_PR0 0x0074
70
71#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
72#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
73#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
74#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
75#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
76
77#define ICH_CYCLE_READ 0
78#define ICH_CYCLE_WRITE 2
79#define ICH_CYCLE_ERASE 3
80
81#define FLASH_GFPREG_BASE_MASK 0x1FFF
82#define FLASH_SECTOR_ADDR_SHIFT 12
83
84#define ICH_FLASH_SEG_SIZE_256 256
85#define ICH_FLASH_SEG_SIZE_4K 4096
86#define ICH_FLASH_SEG_SIZE_8K 8192
87#define ICH_FLASH_SEG_SIZE_64K 65536
88
89
90#define E1000_ICH_FWSM_RSPCIPHY 0x00000040
91
92#define E1000_ICH_MNG_IAMT_MODE 0x2
93
94#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
95 (ID_LED_DEF1_OFF2 << 8) | \
96 (ID_LED_DEF1_ON2 << 4) | \
97 (ID_LED_DEF1_DEF2))
98
99#define E1000_ICH_NVM_SIG_WORD 0x13
100#define E1000_ICH_NVM_SIG_MASK 0xC000
101#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
102#define E1000_ICH_NVM_SIG_VALUE 0x80
103
104#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
105
106#define E1000_FEXTNVM_SW_CONFIG 1
107#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27)
108
109#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
110
111#define E1000_ICH_RAR_ENTRIES 7
112
113#define PHY_PAGE_SHIFT 5
114#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
115 ((reg) & MAX_PHY_REG_ADDRESS))
116#define IGP3_KMRN_DIAG PHY_REG(770, 19)
117#define IGP3_VR_CTRL PHY_REG(776, 18)
118
119#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
120#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
121#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
122
123#define HV_LED_CONFIG PHY_REG(768, 30)
124
125#define SW_FLAG_TIMEOUT 1000
126
127
128#define HV_SMB_ADDR PHY_REG(768, 26)
129#define HV_SMB_ADDR_PEC_EN 0x0200
130#define HV_SMB_ADDR_VALID 0x0080
131
132
133#define E1000_STRAP 0x0000C
134#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
135#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
136
137
138#define HV_OEM_BITS PHY_REG(768, 25)
139#define HV_OEM_BITS_LPLU 0x0004
140#define HV_OEM_BITS_GBE_DIS 0x0040
141#define HV_OEM_BITS_RESTART_AN 0x0400
142
143#define E1000_NVM_K1_CONFIG 0x1B
144#define E1000_NVM_K1_ENABLE 0x1
145
146
147
148union ich8_hws_flash_status {
149 struct ich8_hsfsts {
150 u16 flcdone :1;
151 u16 flcerr :1;
152 u16 dael :1;
153 u16 berasesz :2;
154 u16 flcinprog :1;
155 u16 reserved1 :2;
156 u16 reserved2 :6;
157 u16 fldesvalid :1;
158 u16 flockdn :1;
159 } hsf_status;
160 u16 regval;
161};
162
163
164
165union ich8_hws_flash_ctrl {
166 struct ich8_hsflctl {
167 u16 flcgo :1;
168 u16 flcycle :2;
169 u16 reserved :5;
170 u16 fldbcount :2;
171 u16 flockdn :6;
172 } hsf_ctrl;
173 u16 regval;
174};
175
176
177union ich8_hws_flash_regacc {
178 struct ich8_flracc {
179 u32 grra :8;
180 u32 grwa :8;
181 u32 gmrag :8;
182 u32 gmwag :8;
183 } hsf_flregacc;
184 u16 regval;
185};
186
187
188union ich8_flash_protected_range {
189 struct ich8_pr {
190 u32 base:13;
191 u32 reserved1:2;
192 u32 rpe:1;
193 u32 limit:13;
194 u32 reserved2:2;
195 u32 wpe:1;
196 } range;
197 u32 regval;
198};
199
200static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
201static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
202static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
203static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
204static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
205static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
206 u32 offset, u8 byte);
207static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
208 u8 *data);
209static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
210 u16 *data);
211static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
212 u8 size, u16 *data);
213static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
214static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
215static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
216static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
217static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
218static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
219static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
220static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
221static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
222static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
223static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
224static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
225static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
226static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
227static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
228
229static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
230{
231 return readw(hw->flash_address + reg);
232}
233
234static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
235{
236 return readl(hw->flash_address + reg);
237}
238
239static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
240{
241 writew(val, hw->flash_address + reg);
242}
243
244static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
245{
246 writel(val, hw->flash_address + reg);
247}
248
249#define er16flash(reg) __er16flash(hw, (reg))
250#define er32flash(reg) __er32flash(hw, (reg))
251#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
252#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
253
254
255
256
257
258
259
260static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
261{
262 struct e1000_phy_info *phy = &hw->phy;
263 s32 ret_val = 0;
264
265 phy->addr = 1;
266 phy->reset_delay_us = 100;
267
268 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
269 phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
270 phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked;
271 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
272 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
273 phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
274 phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
275 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
276
277 phy->id = e1000_phy_unknown;
278 e1000e_get_phy_id(hw);
279 phy->type = e1000e_get_phy_type_from_id(phy->id);
280
281 if (phy->type == e1000_phy_82577) {
282 phy->ops.check_polarity = e1000_check_polarity_82577;
283 phy->ops.force_speed_duplex =
284 e1000_phy_force_speed_duplex_82577;
285 phy->ops.get_cable_length = e1000_get_cable_length_82577;
286 phy->ops.get_phy_info = e1000_get_phy_info_82577;
287 phy->ops.commit_phy = e1000e_phy_sw_reset;
288 }
289
290 return ret_val;
291}
292
293
294
295
296
297
298
299static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
300{
301 struct e1000_phy_info *phy = &hw->phy;
302 s32 ret_val;
303 u16 i = 0;
304
305 phy->addr = 1;
306 phy->reset_delay_us = 100;
307
308
309
310
311
312 ret_val = e1000e_determine_phy_address(hw);
313 if (ret_val) {
314 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
315 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
316 ret_val = e1000e_determine_phy_address(hw);
317 if (ret_val)
318 return ret_val;
319 }
320
321 phy->id = 0;
322 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
323 (i++ < 100)) {
324 msleep(1);
325 ret_val = e1000e_get_phy_id(hw);
326 if (ret_val)
327 return ret_val;
328 }
329
330
331 switch (phy->id) {
332 case IGP03E1000_E_PHY_ID:
333 phy->type = e1000_phy_igp_3;
334 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
335 phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
336 phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
337 break;
338 case IFE_E_PHY_ID:
339 case IFE_PLUS_E_PHY_ID:
340 case IFE_C_E_PHY_ID:
341 phy->type = e1000_phy_ife;
342 phy->autoneg_mask = E1000_ALL_NOT_GIG;
343 break;
344 case BME1000_E_PHY_ID:
345 phy->type = e1000_phy_bm;
346 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
347 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
348 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
349 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
350 break;
351 default:
352 return -E1000_ERR_PHY;
353 break;
354 }
355
356 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
357
358 return 0;
359}
360
361
362
363
364
365
366
367
368static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
369{
370 struct e1000_nvm_info *nvm = &hw->nvm;
371 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
372 u32 gfpreg, sector_base_addr, sector_end_addr;
373 u16 i;
374
375
376 if (!hw->flash_address) {
377 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
378 return -E1000_ERR_CONFIG;
379 }
380
381 nvm->type = e1000_nvm_flash_sw;
382
383 gfpreg = er32flash(ICH_FLASH_GFPREG);
384
385
386
387
388
389
390 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
391 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
392
393
394 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
395
396
397
398
399
400 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
401 << FLASH_SECTOR_ADDR_SHIFT;
402 nvm->flash_bank_size /= 2;
403
404 nvm->flash_bank_size /= sizeof(u16);
405
406 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
407
408
409 for (i = 0; i < nvm->word_size; i++) {
410 dev_spec->shadow_ram[i].modified = 0;
411 dev_spec->shadow_ram[i].value = 0xFFFF;
412 }
413
414 return 0;
415}
416
417
418
419
420
421
422
423
424static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
425{
426 struct e1000_hw *hw = &adapter->hw;
427 struct e1000_mac_info *mac = &hw->mac;
428
429
430 hw->phy.media_type = e1000_media_type_copper;
431
432
433 mac->mta_reg_count = 32;
434
435 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
436 if (mac->type == e1000_ich8lan)
437 mac->rar_entry_count--;
438
439 mac->arc_subsystem_valid = 1;
440
441
442 switch (mac->type) {
443 case e1000_ich8lan:
444 case e1000_ich9lan:
445 case e1000_ich10lan:
446
447 mac->ops.id_led_init = e1000e_id_led_init;
448
449 mac->ops.setup_led = e1000e_setup_led_generic;
450
451 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
452
453 mac->ops.led_on = e1000_led_on_ich8lan;
454 mac->ops.led_off = e1000_led_off_ich8lan;
455 break;
456 case e1000_pchlan:
457
458 mac->ops.id_led_init = e1000_id_led_init_pchlan;
459
460 mac->ops.setup_led = e1000_setup_led_pchlan;
461
462 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
463
464 mac->ops.led_on = e1000_led_on_pchlan;
465 mac->ops.led_off = e1000_led_off_pchlan;
466 break;
467 default:
468 break;
469 }
470
471
472 if (mac->type == e1000_ich8lan)
473 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
474
475 return 0;
476}
477
478
479
480
481
482
483
484
485
486static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
487{
488 struct e1000_mac_info *mac = &hw->mac;
489 s32 ret_val;
490 bool link;
491
492
493
494
495
496
497
498 if (!mac->get_link_status) {
499 ret_val = 0;
500 goto out;
501 }
502
503
504
505
506
507
508 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
509 if (ret_val)
510 goto out;
511
512 if (hw->mac.type == e1000_pchlan) {
513 ret_val = e1000_k1_gig_workaround_hv(hw, link);
514 if (ret_val)
515 goto out;
516 }
517
518 if (!link)
519 goto out;
520
521 mac->get_link_status = false;
522
523 if (hw->phy.type == e1000_phy_82578) {
524 ret_val = e1000_link_stall_workaround_hv(hw);
525 if (ret_val)
526 goto out;
527 }
528
529
530
531
532
533 e1000e_check_downshift(hw);
534
535
536
537
538
539 if (!mac->autoneg) {
540 ret_val = -E1000_ERR_CONFIG;
541 goto out;
542 }
543
544
545
546
547
548
549 e1000e_config_collision_dist(hw);
550
551
552
553
554
555
556
557 ret_val = e1000e_config_fc_after_link_up(hw);
558 if (ret_val)
559 hw_dbg(hw, "Error configuring flow control\n");
560
561out:
562 return ret_val;
563}
564
565static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
566{
567 struct e1000_hw *hw = &adapter->hw;
568 s32 rc;
569
570 rc = e1000_init_mac_params_ich8lan(adapter);
571 if (rc)
572 return rc;
573
574 rc = e1000_init_nvm_params_ich8lan(hw);
575 if (rc)
576 return rc;
577
578 if (hw->mac.type == e1000_pchlan)
579 rc = e1000_init_phy_params_pchlan(hw);
580 else
581 rc = e1000_init_phy_params_ich8lan(hw);
582 if (rc)
583 return rc;
584
585 if (adapter->hw.phy.type == e1000_phy_ife) {
586 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
587 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
588 }
589
590 if ((adapter->hw.mac.type == e1000_ich8lan) &&
591 (adapter->hw.phy.type == e1000_phy_igp_3))
592 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
593
594 return 0;
595}
596
597static DEFINE_MUTEX(nvm_mutex);
598
599
600
601
602
603
604
605static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
606{
607 mutex_lock(&nvm_mutex);
608
609 return 0;
610}
611
612
613
614
615
616
617
618static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
619{
620 mutex_unlock(&nvm_mutex);
621
622 return;
623}
624
625static DEFINE_MUTEX(swflag_mutex);
626
627
628
629
630
631
632
633
634static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
635{
636 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
637 s32 ret_val = 0;
638
639 might_sleep();
640
641 mutex_lock(&swflag_mutex);
642
643 while (timeout) {
644 extcnf_ctrl = er32(EXTCNF_CTRL);
645 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
646 break;
647
648 mdelay(1);
649 timeout--;
650 }
651
652 if (!timeout) {
653 hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
654 ret_val = -E1000_ERR_CONFIG;
655 goto out;
656 }
657
658 timeout = SW_FLAG_TIMEOUT;
659
660 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
661 ew32(EXTCNF_CTRL, extcnf_ctrl);
662
663 while (timeout) {
664 extcnf_ctrl = er32(EXTCNF_CTRL);
665 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
666 break;
667
668 mdelay(1);
669 timeout--;
670 }
671
672 if (!timeout) {
673 hw_dbg(hw, "Failed to acquire the semaphore.\n");
674 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
675 ew32(EXTCNF_CTRL, extcnf_ctrl);
676 ret_val = -E1000_ERR_CONFIG;
677 goto out;
678 }
679
680out:
681 if (ret_val)
682 mutex_unlock(&swflag_mutex);
683
684 return ret_val;
685}
686
687
688
689
690
691
692
693
694static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
695{
696 u32 extcnf_ctrl;
697
698 extcnf_ctrl = er32(EXTCNF_CTRL);
699 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
700 ew32(EXTCNF_CTRL, extcnf_ctrl);
701
702 mutex_unlock(&swflag_mutex);
703
704 return;
705}
706
707
708
709
710
711
712
713
714
715static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
716{
717 u32 fwsm = er32(FWSM);
718
719 return (fwsm & E1000_FWSM_MODE_MASK) ==
720 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
721}
722
723
724
725
726
727
728
729
730
731static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
732{
733 u32 fwsm;
734
735 fwsm = er32(FWSM);
736
737 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
738}
739
740
741
742
743
744
745
746
747
748static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
749{
750 struct e1000_phy_info *phy = &hw->phy;
751 s32 ret_val;
752 u16 data;
753 bool link;
754
755 if (phy->type != e1000_phy_ife) {
756 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
757 return ret_val;
758 }
759
760 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
761 if (ret_val)
762 return ret_val;
763
764 e1000e_phy_force_speed_duplex_setup(hw, &data);
765
766 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
767 if (ret_val)
768 return ret_val;
769
770
771 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
772 if (ret_val)
773 return ret_val;
774
775 data &= ~IFE_PMC_AUTO_MDIX;
776 data &= ~IFE_PMC_FORCE_MDIX;
777
778 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
779 if (ret_val)
780 return ret_val;
781
782 hw_dbg(hw, "IFE PMC: %X\n", data);
783
784 udelay(1);
785
786 if (phy->autoneg_wait_to_complete) {
787 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
788
789 ret_val = e1000e_phy_has_link_generic(hw,
790 PHY_FORCE_LIMIT,
791 100000,
792 &link);
793 if (ret_val)
794 return ret_val;
795
796 if (!link)
797 hw_dbg(hw, "Link taking longer than expected.\n");
798
799
800 ret_val = e1000e_phy_has_link_generic(hw,
801 PHY_FORCE_LIMIT,
802 100000,
803 &link);
804 if (ret_val)
805 return ret_val;
806 }
807
808 return 0;
809}
810
811
812
813
814
815
816
817
818static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
819{
820 struct e1000_phy_info *phy = &hw->phy;
821 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
822 s32 ret_val;
823 u16 word_addr, reg_data, reg_addr, phy_page = 0;
824
825 ret_val = hw->phy.ops.acquire_phy(hw);
826 if (ret_val)
827 return ret_val;
828
829
830
831
832
833
834
835
836 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
837 (hw->mac.type == e1000_pchlan)) {
838 struct e1000_adapter *adapter = hw->adapter;
839
840
841 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
842 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
843 (hw->mac.type == e1000_pchlan))
844 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
845 else
846 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
847
848 data = er32(FEXTNVM);
849 if (!(data & sw_cfg_mask))
850 goto out;
851
852
853 e1000_lan_init_done_ich8lan(hw);
854
855
856
857
858
859 data = er32(EXTCNF_CTRL);
860 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
861 goto out;
862
863 cnf_size = er32(EXTCNF_SIZE);
864 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
865 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
866 if (!cnf_size)
867 goto out;
868
869 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
870 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
871
872 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
873 (hw->mac.type == e1000_pchlan)) {
874
875
876
877
878
879
880 data = er32(STRAP);
881 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
882 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
883 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
884 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
885 reg_data);
886 if (ret_val)
887 goto out;
888
889 data = er32(LEDCTL);
890 ret_val = e1000_write_phy_reg_hv_locked(hw,
891 HV_LED_CONFIG,
892 (u16)data);
893 if (ret_val)
894 goto out;
895 }
896
897
898
899 word_addr = (u16)(cnf_base_addr << 1);
900
901 for (i = 0; i < cnf_size; i++) {
902 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
903 ®_data);
904 if (ret_val)
905 goto out;
906
907 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
908 1, ®_addr);
909 if (ret_val)
910 goto out;
911
912
913 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
914 phy_page = reg_data;
915 continue;
916 }
917
918 reg_addr &= PHY_REG_MASK;
919 reg_addr |= phy_page;
920
921 ret_val = phy->ops.write_phy_reg_locked(hw,
922 (u32)reg_addr,
923 reg_data);
924 if (ret_val)
925 goto out;
926 }
927 }
928
929out:
930 hw->phy.ops.release_phy(hw);
931 return ret_val;
932}
933
934
935
936
937
938
939
940
941
942
943
944static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
945{
946 s32 ret_val = 0;
947 u16 status_reg = 0;
948 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
949
950 if (hw->mac.type != e1000_pchlan)
951 goto out;
952
953
954 ret_val = hw->phy.ops.acquire_phy(hw);
955 if (ret_val)
956 goto out;
957
958
959 if (link) {
960 if (hw->phy.type == e1000_phy_82578) {
961 ret_val = hw->phy.ops.read_phy_reg_locked(hw,
962 BM_CS_STATUS,
963 &status_reg);
964 if (ret_val)
965 goto release;
966
967 status_reg &= BM_CS_STATUS_LINK_UP |
968 BM_CS_STATUS_RESOLVED |
969 BM_CS_STATUS_SPEED_MASK;
970
971 if (status_reg == (BM_CS_STATUS_LINK_UP |
972 BM_CS_STATUS_RESOLVED |
973 BM_CS_STATUS_SPEED_1000))
974 k1_enable = false;
975 }
976
977 if (hw->phy.type == e1000_phy_82577) {
978 ret_val = hw->phy.ops.read_phy_reg_locked(hw,
979 HV_M_STATUS,
980 &status_reg);
981 if (ret_val)
982 goto release;
983
984 status_reg &= HV_M_STATUS_LINK_UP |
985 HV_M_STATUS_AUTONEG_COMPLETE |
986 HV_M_STATUS_SPEED_MASK;
987
988 if (status_reg == (HV_M_STATUS_LINK_UP |
989 HV_M_STATUS_AUTONEG_COMPLETE |
990 HV_M_STATUS_SPEED_1000))
991 k1_enable = false;
992 }
993
994
995 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
996 0x0100);
997 if (ret_val)
998 goto release;
999
1000 } else {
1001
1002 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
1003 0x4100);
1004 if (ret_val)
1005 goto release;
1006 }
1007
1008 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1009
1010release:
1011 hw->phy.ops.release_phy(hw);
1012out:
1013 return ret_val;
1014}
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1027{
1028 s32 ret_val = 0;
1029 u32 ctrl_reg = 0;
1030 u32 ctrl_ext = 0;
1031 u32 reg = 0;
1032 u16 kmrn_reg = 0;
1033
1034 ret_val = e1000e_read_kmrn_reg_locked(hw,
1035 E1000_KMRNCTRLSTA_K1_CONFIG,
1036 &kmrn_reg);
1037 if (ret_val)
1038 goto out;
1039
1040 if (k1_enable)
1041 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1042 else
1043 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1044
1045 ret_val = e1000e_write_kmrn_reg_locked(hw,
1046 E1000_KMRNCTRLSTA_K1_CONFIG,
1047 kmrn_reg);
1048 if (ret_val)
1049 goto out;
1050
1051 udelay(20);
1052 ctrl_ext = er32(CTRL_EXT);
1053 ctrl_reg = er32(CTRL);
1054
1055 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1056 reg |= E1000_CTRL_FRCSPD;
1057 ew32(CTRL, reg);
1058
1059 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1060 udelay(20);
1061 ew32(CTRL, ctrl_reg);
1062 ew32(CTRL_EXT, ctrl_ext);
1063 udelay(20);
1064
1065out:
1066 return ret_val;
1067}
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1079{
1080 s32 ret_val = 0;
1081 u32 mac_reg;
1082 u16 oem_reg;
1083
1084 if (hw->mac.type != e1000_pchlan)
1085 return ret_val;
1086
1087 ret_val = hw->phy.ops.acquire_phy(hw);
1088 if (ret_val)
1089 return ret_val;
1090
1091 mac_reg = er32(EXTCNF_CTRL);
1092 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1093 goto out;
1094
1095 mac_reg = er32(FEXTNVM);
1096 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1097 goto out;
1098
1099 mac_reg = er32(PHY_CTRL);
1100
1101 ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1102 if (ret_val)
1103 goto out;
1104
1105 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1106
1107 if (d0_state) {
1108 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1109 oem_reg |= HV_OEM_BITS_GBE_DIS;
1110
1111 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1112 oem_reg |= HV_OEM_BITS_LPLU;
1113 } else {
1114 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1115 oem_reg |= HV_OEM_BITS_GBE_DIS;
1116
1117 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1118 oem_reg |= HV_OEM_BITS_LPLU;
1119 }
1120
1121 if (!e1000_check_reset_block(hw))
1122 oem_reg |= HV_OEM_BITS_RESTART_AN;
1123 ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg);
1124
1125out:
1126 hw->phy.ops.release_phy(hw);
1127
1128 return ret_val;
1129}
1130
1131
1132
1133
1134
1135
1136static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1137{
1138 s32 ret_val = 0;
1139
1140 if (hw->mac.type != e1000_pchlan)
1141 return ret_val;
1142
1143 if (((hw->phy.type == e1000_phy_82577) &&
1144 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1145 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1146
1147 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1148 if (ret_val)
1149 return ret_val;
1150
1151
1152 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1153 if (ret_val)
1154 return ret_val;
1155 }
1156
1157 if (hw->phy.type == e1000_phy_82578) {
1158
1159
1160
1161
1162 if (hw->phy.revision < 2) {
1163 e1000e_phy_sw_reset(hw);
1164 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1165 }
1166 }
1167
1168
1169 ret_val = hw->phy.ops.acquire_phy(hw);
1170 if (ret_val)
1171 return ret_val;
1172
1173 hw->phy.addr = 1;
1174 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1175 if (ret_val)
1176 goto out;
1177 hw->phy.ops.release_phy(hw);
1178
1179
1180
1181
1182
1183 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1184
1185out:
1186 return ret_val;
1187}
1188
1189
1190
1191
1192
1193
1194
1195
1196static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1197{
1198 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1199
1200
1201 do {
1202 data = er32(STATUS);
1203 data &= E1000_STATUS_LAN_INIT_DONE;
1204 udelay(100);
1205 } while ((!data) && --loop);
1206
1207
1208
1209
1210
1211
1212 if (loop == 0)
1213 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
1214
1215
1216 data = er32(STATUS);
1217 data &= ~E1000_STATUS_LAN_INIT_DONE;
1218 ew32(STATUS, data);
1219}
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1230{
1231 s32 ret_val = 0;
1232 u16 reg;
1233
1234 ret_val = e1000e_phy_hw_reset_generic(hw);
1235 if (ret_val)
1236 return ret_val;
1237
1238
1239 mdelay(10);
1240
1241 if (hw->mac.type == e1000_pchlan) {
1242 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1243 if (ret_val)
1244 return ret_val;
1245 }
1246
1247
1248 if (hw->mac.type == e1000_pchlan)
1249 e1e_rphy(hw, BM_WUC, ®);
1250
1251
1252 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1253 if (ret_val)
1254 goto out;
1255
1256
1257 if (hw->mac.type == e1000_pchlan)
1258 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1259
1260out:
1261 return 0;
1262}
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1273{
1274 struct e1000_phy_info *phy = &hw->phy;
1275 s32 ret_val;
1276 u16 data;
1277 bool link;
1278
1279 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1280 if (ret_val)
1281 return ret_val;
1282
1283 if (!link) {
1284 hw_dbg(hw, "Phy info is only valid if link is up\n");
1285 return -E1000_ERR_CONFIG;
1286 }
1287
1288 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1289 if (ret_val)
1290 return ret_val;
1291 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
1292
1293 if (phy->polarity_correction) {
1294 ret_val = phy->ops.check_polarity(hw);
1295 if (ret_val)
1296 return ret_val;
1297 } else {
1298
1299 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1300 ? e1000_rev_polarity_reversed
1301 : e1000_rev_polarity_normal;
1302 }
1303
1304 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1305 if (ret_val)
1306 return ret_val;
1307
1308 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1309
1310
1311 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1312 phy->local_rx = e1000_1000t_rx_status_undefined;
1313 phy->remote_rx = e1000_1000t_rx_status_undefined;
1314
1315 return 0;
1316}
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1327{
1328 switch (hw->phy.type) {
1329 case e1000_phy_ife:
1330 return e1000_get_phy_info_ife_ich8lan(hw);
1331 break;
1332 case e1000_phy_igp_3:
1333 case e1000_phy_bm:
1334 case e1000_phy_82578:
1335 case e1000_phy_82577:
1336 return e1000e_get_phy_info_igp(hw);
1337 break;
1338 default:
1339 break;
1340 }
1341
1342 return -E1000_ERR_PHY_TYPE;
1343}
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1354{
1355 struct e1000_phy_info *phy = &hw->phy;
1356 s32 ret_val;
1357 u16 phy_data, offset, mask;
1358
1359
1360
1361
1362 if (phy->polarity_correction) {
1363 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1364 mask = IFE_PESC_POLARITY_REVERSED;
1365 } else {
1366 offset = IFE_PHY_SPECIAL_CONTROL;
1367 mask = IFE_PSC_FORCE_POLARITY;
1368 }
1369
1370 ret_val = e1e_rphy(hw, offset, &phy_data);
1371
1372 if (!ret_val)
1373 phy->cable_polarity = (phy_data & mask)
1374 ? e1000_rev_polarity_reversed
1375 : e1000_rev_polarity_normal;
1376
1377 return ret_val;
1378}
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1392{
1393 s32 ret_val = 0;
1394 u16 oem_reg;
1395
1396 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1397 if (ret_val)
1398 goto out;
1399
1400 if (active)
1401 oem_reg |= HV_OEM_BITS_LPLU;
1402 else
1403 oem_reg &= ~HV_OEM_BITS_LPLU;
1404
1405 oem_reg |= HV_OEM_BITS_RESTART_AN;
1406 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1407
1408out:
1409 return ret_val;
1410}
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1426{
1427 struct e1000_phy_info *phy = &hw->phy;
1428 u32 phy_ctrl;
1429 s32 ret_val = 0;
1430 u16 data;
1431
1432 if (phy->type == e1000_phy_ife)
1433 return ret_val;
1434
1435 phy_ctrl = er32(PHY_CTRL);
1436
1437 if (active) {
1438 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1439 ew32(PHY_CTRL, phy_ctrl);
1440
1441 if (phy->type != e1000_phy_igp_3)
1442 return 0;
1443
1444
1445
1446
1447
1448 if (hw->mac.type == e1000_ich8lan)
1449 e1000e_gig_downshift_workaround_ich8lan(hw);
1450
1451
1452 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1453 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1454 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1455 if (ret_val)
1456 return ret_val;
1457 } else {
1458 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1459 ew32(PHY_CTRL, phy_ctrl);
1460
1461 if (phy->type != e1000_phy_igp_3)
1462 return 0;
1463
1464
1465
1466
1467
1468
1469
1470 if (phy->smart_speed == e1000_smart_speed_on) {
1471 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1472 &data);
1473 if (ret_val)
1474 return ret_val;
1475
1476 data |= IGP01E1000_PSCFR_SMART_SPEED;
1477 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1478 data);
1479 if (ret_val)
1480 return ret_val;
1481 } else if (phy->smart_speed == e1000_smart_speed_off) {
1482 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1483 &data);
1484 if (ret_val)
1485 return ret_val;
1486
1487 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1488 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1489 data);
1490 if (ret_val)
1491 return ret_val;
1492 }
1493 }
1494
1495 return 0;
1496}
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1512{
1513 struct e1000_phy_info *phy = &hw->phy;
1514 u32 phy_ctrl;
1515 s32 ret_val;
1516 u16 data;
1517
1518 phy_ctrl = er32(PHY_CTRL);
1519
1520 if (!active) {
1521 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1522 ew32(PHY_CTRL, phy_ctrl);
1523
1524 if (phy->type != e1000_phy_igp_3)
1525 return 0;
1526
1527
1528
1529
1530
1531
1532
1533 if (phy->smart_speed == e1000_smart_speed_on) {
1534 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1535 &data);
1536 if (ret_val)
1537 return ret_val;
1538
1539 data |= IGP01E1000_PSCFR_SMART_SPEED;
1540 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1541 data);
1542 if (ret_val)
1543 return ret_val;
1544 } else if (phy->smart_speed == e1000_smart_speed_off) {
1545 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1546 &data);
1547 if (ret_val)
1548 return ret_val;
1549
1550 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1551 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1552 data);
1553 if (ret_val)
1554 return ret_val;
1555 }
1556 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1557 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1558 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1559 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1560 ew32(PHY_CTRL, phy_ctrl);
1561
1562 if (phy->type != e1000_phy_igp_3)
1563 return 0;
1564
1565
1566
1567
1568
1569 if (hw->mac.type == e1000_ich8lan)
1570 e1000e_gig_downshift_workaround_ich8lan(hw);
1571
1572
1573 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1574 if (ret_val)
1575 return ret_val;
1576
1577 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1578 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1579 }
1580
1581 return 0;
1582}
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1593{
1594 u32 eecd;
1595 struct e1000_nvm_info *nvm = &hw->nvm;
1596 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1597 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1598 u8 sig_byte = 0;
1599 s32 ret_val = 0;
1600
1601 switch (hw->mac.type) {
1602 case e1000_ich8lan:
1603 case e1000_ich9lan:
1604 eecd = er32(EECD);
1605 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1606 E1000_EECD_SEC1VAL_VALID_MASK) {
1607 if (eecd & E1000_EECD_SEC1VAL)
1608 *bank = 1;
1609 else
1610 *bank = 0;
1611
1612 return 0;
1613 }
1614 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1615 "reading flash signature\n");
1616
1617 default:
1618
1619 *bank = 0;
1620
1621
1622 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1623 &sig_byte);
1624 if (ret_val)
1625 return ret_val;
1626 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1627 E1000_ICH_NVM_SIG_VALUE) {
1628 *bank = 0;
1629 return 0;
1630 }
1631
1632
1633 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1634 bank1_offset,
1635 &sig_byte);
1636 if (ret_val)
1637 return ret_val;
1638 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1639 E1000_ICH_NVM_SIG_VALUE) {
1640 *bank = 1;
1641 return 0;
1642 }
1643
1644 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1645 return -E1000_ERR_NVM;
1646 }
1647
1648 return 0;
1649}
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1661 u16 *data)
1662{
1663 struct e1000_nvm_info *nvm = &hw->nvm;
1664 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1665 u32 act_offset;
1666 s32 ret_val = 0;
1667 u32 bank = 0;
1668 u16 i, word;
1669
1670 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1671 (words == 0)) {
1672 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1673 ret_val = -E1000_ERR_NVM;
1674 goto out;
1675 }
1676
1677 nvm->ops.acquire_nvm(hw);
1678
1679 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1680 if (ret_val) {
1681 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1682 bank = 0;
1683 }
1684
1685 act_offset = (bank) ? nvm->flash_bank_size : 0;
1686 act_offset += offset;
1687
1688 ret_val = 0;
1689 for (i = 0; i < words; i++) {
1690 if ((dev_spec->shadow_ram) &&
1691 (dev_spec->shadow_ram[offset+i].modified)) {
1692 data[i] = dev_spec->shadow_ram[offset+i].value;
1693 } else {
1694 ret_val = e1000_read_flash_word_ich8lan(hw,
1695 act_offset + i,
1696 &word);
1697 if (ret_val)
1698 break;
1699 data[i] = word;
1700 }
1701 }
1702
1703 nvm->ops.release_nvm(hw);
1704
1705out:
1706 if (ret_val)
1707 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1708
1709 return ret_val;
1710}
1711
1712
1713
1714
1715
1716
1717
1718
1719static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1720{
1721 union ich8_hws_flash_status hsfsts;
1722 s32 ret_val = -E1000_ERR_NVM;
1723 s32 i = 0;
1724
1725 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1726
1727
1728 if (hsfsts.hsf_status.fldesvalid == 0) {
1729 hw_dbg(hw, "Flash descriptor invalid. "
1730 "SW Sequencing must be used.");
1731 return -E1000_ERR_NVM;
1732 }
1733
1734
1735 hsfsts.hsf_status.flcerr = 1;
1736 hsfsts.hsf_status.dael = 1;
1737
1738 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749 if (hsfsts.hsf_status.flcinprog == 0) {
1750
1751
1752
1753
1754
1755 hsfsts.hsf_status.flcdone = 1;
1756 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1757 ret_val = 0;
1758 } else {
1759
1760
1761
1762
1763 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1764 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1765 if (hsfsts.hsf_status.flcinprog == 0) {
1766 ret_val = 0;
1767 break;
1768 }
1769 udelay(1);
1770 }
1771 if (ret_val == 0) {
1772
1773
1774
1775
1776 hsfsts.hsf_status.flcdone = 1;
1777 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1778 } else {
1779 hw_dbg(hw, "Flash controller busy, cannot get access");
1780 }
1781 }
1782
1783 return ret_val;
1784}
1785
1786
1787
1788
1789
1790
1791
1792
1793static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1794{
1795 union ich8_hws_flash_ctrl hsflctl;
1796 union ich8_hws_flash_status hsfsts;
1797 s32 ret_val = -E1000_ERR_NVM;
1798 u32 i = 0;
1799
1800
1801 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1802 hsflctl.hsf_ctrl.flcgo = 1;
1803 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1804
1805
1806 do {
1807 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1808 if (hsfsts.hsf_status.flcdone == 1)
1809 break;
1810 udelay(1);
1811 } while (i++ < timeout);
1812
1813 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1814 return 0;
1815
1816 return ret_val;
1817}
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1829 u16 *data)
1830{
1831
1832 offset <<= 1;
1833
1834 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1835}
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1846 u8 *data)
1847{
1848 s32 ret_val;
1849 u16 word = 0;
1850
1851 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1852 if (ret_val)
1853 return ret_val;
1854
1855 *data = (u8)word;
1856
1857 return 0;
1858}
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1870 u8 size, u16 *data)
1871{
1872 union ich8_hws_flash_status hsfsts;
1873 union ich8_hws_flash_ctrl hsflctl;
1874 u32 flash_linear_addr;
1875 u32 flash_data = 0;
1876 s32 ret_val = -E1000_ERR_NVM;
1877 u8 count = 0;
1878
1879 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1880 return -E1000_ERR_NVM;
1881
1882 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1883 hw->nvm.flash_base_addr;
1884
1885 do {
1886 udelay(1);
1887
1888 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1889 if (ret_val != 0)
1890 break;
1891
1892 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1893
1894 hsflctl.hsf_ctrl.fldbcount = size - 1;
1895 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1896 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1897
1898 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1899
1900 ret_val = e1000_flash_cycle_ich8lan(hw,
1901 ICH_FLASH_READ_COMMAND_TIMEOUT);
1902
1903
1904
1905
1906
1907
1908
1909 if (ret_val == 0) {
1910 flash_data = er32flash(ICH_FLASH_FDATA0);
1911 if (size == 1) {
1912 *data = (u8)(flash_data & 0x000000FF);
1913 } else if (size == 2) {
1914 *data = (u16)(flash_data & 0x0000FFFF);
1915 }
1916 break;
1917 } else {
1918
1919
1920
1921
1922
1923
1924 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1925 if (hsfsts.hsf_status.flcerr == 1) {
1926
1927 continue;
1928 } else if (hsfsts.hsf_status.flcdone == 0) {
1929 hw_dbg(hw, "Timeout error - flash cycle "
1930 "did not complete.");
1931 break;
1932 }
1933 }
1934 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1935
1936 return ret_val;
1937}
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1949 u16 *data)
1950{
1951 struct e1000_nvm_info *nvm = &hw->nvm;
1952 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1953 u16 i;
1954
1955 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1956 (words == 0)) {
1957 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1958 return -E1000_ERR_NVM;
1959 }
1960
1961 nvm->ops.acquire_nvm(hw);
1962
1963 for (i = 0; i < words; i++) {
1964 dev_spec->shadow_ram[offset+i].modified = 1;
1965 dev_spec->shadow_ram[offset+i].value = data[i];
1966 }
1967
1968 nvm->ops.release_nvm(hw);
1969
1970 return 0;
1971}
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1985{
1986 struct e1000_nvm_info *nvm = &hw->nvm;
1987 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1988 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1989 s32 ret_val;
1990 u16 data;
1991
1992 ret_val = e1000e_update_nvm_checksum_generic(hw);
1993 if (ret_val)
1994 goto out;
1995
1996 if (nvm->type != e1000_nvm_flash_sw)
1997 goto out;
1998
1999 nvm->ops.acquire_nvm(hw);
2000
2001
2002
2003
2004
2005
2006 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2007 if (ret_val) {
2008 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
2009 bank = 0;
2010 }
2011
2012 if (bank == 0) {
2013 new_bank_offset = nvm->flash_bank_size;
2014 old_bank_offset = 0;
2015 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2016 if (ret_val) {
2017 nvm->ops.release_nvm(hw);
2018 goto out;
2019 }
2020 } else {
2021 old_bank_offset = nvm->flash_bank_size;
2022 new_bank_offset = 0;
2023 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2024 if (ret_val) {
2025 nvm->ops.release_nvm(hw);
2026 goto out;
2027 }
2028 }
2029
2030 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2031
2032
2033
2034
2035
2036 if (dev_spec->shadow_ram[i].modified) {
2037 data = dev_spec->shadow_ram[i].value;
2038 } else {
2039 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2040 old_bank_offset,
2041 &data);
2042 if (ret_val)
2043 break;
2044 }
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054 if (i == E1000_ICH_NVM_SIG_WORD)
2055 data |= E1000_ICH_NVM_SIG_MASK;
2056
2057
2058 act_offset = (i + new_bank_offset) << 1;
2059
2060 udelay(100);
2061
2062 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2063 act_offset,
2064 (u8)data);
2065 if (ret_val)
2066 break;
2067
2068 udelay(100);
2069 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2070 act_offset + 1,
2071 (u8)(data >> 8));
2072 if (ret_val)
2073 break;
2074 }
2075
2076
2077
2078
2079
2080 if (ret_val) {
2081
2082 hw_dbg(hw, "Flash commit failed.\n");
2083 nvm->ops.release_nvm(hw);
2084 goto out;
2085 }
2086
2087
2088
2089
2090
2091
2092
2093 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2094 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2095 if (ret_val) {
2096 nvm->ops.release_nvm(hw);
2097 goto out;
2098 }
2099 data &= 0xBFFF;
2100 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2101 act_offset * 2 + 1,
2102 (u8)(data >> 8));
2103 if (ret_val) {
2104 nvm->ops.release_nvm(hw);
2105 goto out;
2106 }
2107
2108
2109
2110
2111
2112
2113
2114 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2115 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2116 if (ret_val) {
2117 nvm->ops.release_nvm(hw);
2118 goto out;
2119 }
2120
2121
2122 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2123 dev_spec->shadow_ram[i].modified = 0;
2124 dev_spec->shadow_ram[i].value = 0xFFFF;
2125 }
2126
2127 nvm->ops.release_nvm(hw);
2128
2129
2130
2131
2132
2133 e1000e_reload_nvm(hw);
2134 msleep(10);
2135
2136out:
2137 if (ret_val)
2138 hw_dbg(hw, "NVM update error: %d\n", ret_val);
2139
2140 return ret_val;
2141}
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2152{
2153 s32 ret_val;
2154 u16 data;
2155
2156
2157
2158
2159
2160
2161
2162 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2163 if (ret_val)
2164 return ret_val;
2165
2166 if ((data & 0x40) == 0) {
2167 data |= 0x40;
2168 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2169 if (ret_val)
2170 return ret_val;
2171 ret_val = e1000e_update_nvm_checksum(hw);
2172 if (ret_val)
2173 return ret_val;
2174 }
2175
2176 return e1000e_validate_nvm_checksum_generic(hw);
2177}
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2190{
2191 struct e1000_nvm_info *nvm = &hw->nvm;
2192 union ich8_flash_protected_range pr0;
2193 union ich8_hws_flash_status hsfsts;
2194 u32 gfpreg;
2195
2196 nvm->ops.acquire_nvm(hw);
2197
2198 gfpreg = er32flash(ICH_FLASH_GFPREG);
2199
2200
2201 pr0.regval = er32flash(ICH_FLASH_PR0);
2202 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2203 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2204 pr0.range.wpe = true;
2205 ew32flash(ICH_FLASH_PR0, pr0.regval);
2206
2207
2208
2209
2210
2211
2212
2213 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2214 hsfsts.hsf_status.flockdn = true;
2215 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2216
2217 nvm->ops.release_nvm(hw);
2218}
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2230 u8 size, u16 data)
2231{
2232 union ich8_hws_flash_status hsfsts;
2233 union ich8_hws_flash_ctrl hsflctl;
2234 u32 flash_linear_addr;
2235 u32 flash_data = 0;
2236 s32 ret_val;
2237 u8 count = 0;
2238
2239 if (size < 1 || size > 2 || data > size * 0xff ||
2240 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2241 return -E1000_ERR_NVM;
2242
2243 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2244 hw->nvm.flash_base_addr;
2245
2246 do {
2247 udelay(1);
2248
2249 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2250 if (ret_val)
2251 break;
2252
2253 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2254
2255 hsflctl.hsf_ctrl.fldbcount = size -1;
2256 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2257 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2258
2259 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2260
2261 if (size == 1)
2262 flash_data = (u32)data & 0x00FF;
2263 else
2264 flash_data = (u32)data;
2265
2266 ew32flash(ICH_FLASH_FDATA0, flash_data);
2267
2268
2269
2270
2271
2272 ret_val = e1000_flash_cycle_ich8lan(hw,
2273 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2274 if (!ret_val)
2275 break;
2276
2277
2278
2279
2280
2281
2282
2283 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2284 if (hsfsts.hsf_status.flcerr == 1)
2285
2286 continue;
2287 if (hsfsts.hsf_status.flcdone == 0) {
2288 hw_dbg(hw, "Timeout error - flash cycle "
2289 "did not complete.");
2290 break;
2291 }
2292 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2293
2294 return ret_val;
2295}
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2306 u8 data)
2307{
2308 u16 word = (u16)data;
2309
2310 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2311}
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2323 u32 offset, u8 byte)
2324{
2325 s32 ret_val;
2326 u16 program_retries;
2327
2328 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2329 if (!ret_val)
2330 return ret_val;
2331
2332 for (program_retries = 0; program_retries < 100; program_retries++) {
2333 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
2334 udelay(100);
2335 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2336 if (!ret_val)
2337 break;
2338 }
2339 if (program_retries == 100)
2340 return -E1000_ERR_NVM;
2341
2342 return 0;
2343}
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2354{
2355 struct e1000_nvm_info *nvm = &hw->nvm;
2356 union ich8_hws_flash_status hsfsts;
2357 union ich8_hws_flash_ctrl hsflctl;
2358 u32 flash_linear_addr;
2359
2360 u32 flash_bank_size = nvm->flash_bank_size * 2;
2361 s32 ret_val;
2362 s32 count = 0;
2363 s32 iteration;
2364 s32 sector_size;
2365 s32 j;
2366
2367 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382 switch (hsfsts.hsf_status.berasesz) {
2383 case 0:
2384
2385 sector_size = ICH_FLASH_SEG_SIZE_256;
2386 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2387 break;
2388 case 1:
2389 sector_size = ICH_FLASH_SEG_SIZE_4K;
2390 iteration = 1;
2391 break;
2392 case 2:
2393 sector_size = ICH_FLASH_SEG_SIZE_8K;
2394 iteration = 1;
2395 break;
2396 case 3:
2397 sector_size = ICH_FLASH_SEG_SIZE_64K;
2398 iteration = 1;
2399 break;
2400 default:
2401 return -E1000_ERR_NVM;
2402 }
2403
2404
2405 flash_linear_addr = hw->nvm.flash_base_addr;
2406 flash_linear_addr += (bank) ? flash_bank_size : 0;
2407
2408 for (j = 0; j < iteration ; j++) {
2409 do {
2410
2411 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2412 if (ret_val)
2413 return ret_val;
2414
2415
2416
2417
2418
2419 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2420 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2421 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2422
2423
2424
2425
2426
2427
2428 flash_linear_addr += (j * sector_size);
2429 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2430
2431 ret_val = e1000_flash_cycle_ich8lan(hw,
2432 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2433 if (ret_val == 0)
2434 break;
2435
2436
2437
2438
2439
2440
2441 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2442 if (hsfsts.hsf_status.flcerr == 1)
2443
2444 continue;
2445 else if (hsfsts.hsf_status.flcdone == 0)
2446 return ret_val;
2447 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2448 }
2449
2450 return 0;
2451}
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2463{
2464 s32 ret_val;
2465
2466 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2467 if (ret_val) {
2468 hw_dbg(hw, "NVM Read Error\n");
2469 return ret_val;
2470 }
2471
2472 if (*data == ID_LED_RESERVED_0000 ||
2473 *data == ID_LED_RESERVED_FFFF)
2474 *data = ID_LED_DEFAULT_ICH8LAN;
2475
2476 return 0;
2477}
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2493{
2494 struct e1000_mac_info *mac = &hw->mac;
2495 s32 ret_val;
2496 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2497 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2498 u16 data, i, temp, shift;
2499
2500
2501 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2502 if (ret_val)
2503 goto out;
2504
2505 mac->ledctl_default = er32(LEDCTL);
2506 mac->ledctl_mode1 = mac->ledctl_default;
2507 mac->ledctl_mode2 = mac->ledctl_default;
2508
2509 for (i = 0; i < 4; i++) {
2510 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2511 shift = (i * 5);
2512 switch (temp) {
2513 case ID_LED_ON1_DEF2:
2514 case ID_LED_ON1_ON2:
2515 case ID_LED_ON1_OFF2:
2516 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2517 mac->ledctl_mode1 |= (ledctl_on << shift);
2518 break;
2519 case ID_LED_OFF1_DEF2:
2520 case ID_LED_OFF1_ON2:
2521 case ID_LED_OFF1_OFF2:
2522 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2523 mac->ledctl_mode1 |= (ledctl_off << shift);
2524 break;
2525 default:
2526
2527 break;
2528 }
2529 switch (temp) {
2530 case ID_LED_DEF1_ON2:
2531 case ID_LED_ON1_ON2:
2532 case ID_LED_OFF1_ON2:
2533 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2534 mac->ledctl_mode2 |= (ledctl_on << shift);
2535 break;
2536 case ID_LED_DEF1_OFF2:
2537 case ID_LED_ON1_OFF2:
2538 case ID_LED_OFF1_OFF2:
2539 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2540 mac->ledctl_mode2 |= (ledctl_off << shift);
2541 break;
2542 default:
2543
2544 break;
2545 }
2546 }
2547
2548out:
2549 return ret_val;
2550}
2551
2552
2553
2554
2555
2556
2557
2558
2559static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2560{
2561 struct e1000_bus_info *bus = &hw->bus;
2562 s32 ret_val;
2563
2564 ret_val = e1000e_get_bus_info_pcie(hw);
2565
2566
2567
2568
2569
2570
2571
2572 if (bus->width == e1000_bus_width_unknown)
2573 bus->width = e1000_bus_width_pcie_x1;
2574
2575 return ret_val;
2576}
2577
2578
2579
2580
2581
2582
2583
2584
2585static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2586{
2587 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2588 u16 reg;
2589 u32 ctrl, icr, kab;
2590 s32 ret_val;
2591
2592
2593
2594
2595
2596 ret_val = e1000e_disable_pcie_master(hw);
2597 if (ret_val) {
2598 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2599 }
2600
2601 hw_dbg(hw, "Masking off all interrupts\n");
2602 ew32(IMC, 0xffffffff);
2603
2604
2605
2606
2607
2608
2609 ew32(RCTL, 0);
2610 ew32(TCTL, E1000_TCTL_PSP);
2611 e1e_flush();
2612
2613 msleep(10);
2614
2615
2616 if (hw->mac.type == e1000_ich8lan) {
2617
2618 ew32(PBA, E1000_PBA_8K);
2619
2620 ew32(PBS, E1000_PBS_16K);
2621 }
2622
2623 if (hw->mac.type == e1000_pchlan) {
2624
2625 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
2626 if (ret_val)
2627 return ret_val;
2628
2629 if (reg & E1000_NVM_K1_ENABLE)
2630 dev_spec->nvm_k1_enabled = true;
2631 else
2632 dev_spec->nvm_k1_enabled = false;
2633 }
2634
2635 ctrl = er32(CTRL);
2636
2637 if (!e1000_check_reset_block(hw)) {
2638
2639 if (hw->mac.type >= e1000_pchlan) {
2640 u32 status = er32(STATUS);
2641 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2642 }
2643
2644
2645
2646
2647
2648
2649 ctrl |= E1000_CTRL_PHY_RST;
2650 }
2651 ret_val = e1000_acquire_swflag_ich8lan(hw);
2652
2653 hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2654 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2655 msleep(20);
2656
2657 if (!ret_val)
2658 e1000_release_swflag_ich8lan(hw);
2659
2660 if (ctrl & E1000_CTRL_PHY_RST)
2661 ret_val = hw->phy.ops.get_cfg_done(hw);
2662
2663 if (hw->mac.type >= e1000_ich10lan) {
2664 e1000_lan_init_done_ich8lan(hw);
2665 } else {
2666 ret_val = e1000e_get_auto_rd_done(hw);
2667 if (ret_val) {
2668
2669
2670
2671
2672
2673 hw_dbg(hw, "Auto Read Done did not complete\n");
2674 }
2675 }
2676
2677 if (hw->mac.type == e1000_pchlan)
2678 e1e_rphy(hw, BM_WUC, ®);
2679
2680 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2681 if (ret_val)
2682 goto out;
2683
2684 if (hw->mac.type == e1000_pchlan) {
2685 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2686 if (ret_val)
2687 goto out;
2688 }
2689
2690
2691
2692
2693
2694 if (hw->mac.type == e1000_pchlan)
2695 ew32(CRC_OFFSET, 0x65656565);
2696
2697 ew32(IMC, 0xffffffff);
2698 icr = er32(ICR);
2699
2700 kab = er32(KABGTXD);
2701 kab |= E1000_KABGTXD_BGSQLBIAS;
2702 ew32(KABGTXD, kab);
2703
2704 if (hw->mac.type == e1000_pchlan)
2705 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2706
2707out:
2708 return ret_val;
2709}
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2724{
2725 struct e1000_mac_info *mac = &hw->mac;
2726 u32 ctrl_ext, txdctl, snoop;
2727 s32 ret_val;
2728 u16 i;
2729
2730 e1000_initialize_hw_bits_ich8lan(hw);
2731
2732
2733 ret_val = mac->ops.id_led_init(hw);
2734 if (ret_val) {
2735 hw_dbg(hw, "Error initializing identification LED\n");
2736 return ret_val;
2737 }
2738
2739
2740 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2741
2742
2743 hw_dbg(hw, "Zeroing the MTA\n");
2744 for (i = 0; i < mac->mta_reg_count; i++)
2745 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2746
2747
2748
2749
2750
2751
2752 if (hw->phy.type == e1000_phy_82578) {
2753 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2754 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2755 if (ret_val)
2756 return ret_val;
2757 }
2758
2759
2760 ret_val = e1000_setup_link_ich8lan(hw);
2761
2762
2763 txdctl = er32(TXDCTL(0));
2764 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2765 E1000_TXDCTL_FULL_TX_DESC_WB;
2766 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2767 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2768 ew32(TXDCTL(0), txdctl);
2769 txdctl = er32(TXDCTL(1));
2770 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2771 E1000_TXDCTL_FULL_TX_DESC_WB;
2772 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2773 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2774 ew32(TXDCTL(1), txdctl);
2775
2776
2777
2778
2779
2780 if (mac->type == e1000_ich8lan)
2781 snoop = PCIE_ICH8_SNOOP_ALL;
2782 else
2783 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2784 e1000e_set_pcie_no_snoop(hw, snoop);
2785
2786 ctrl_ext = er32(CTRL_EXT);
2787 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2788 ew32(CTRL_EXT, ctrl_ext);
2789
2790
2791
2792
2793
2794
2795
2796 e1000_clear_hw_cntrs_ich8lan(hw);
2797
2798 return 0;
2799}
2800
2801
2802
2803
2804
2805
2806
2807static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2808{
2809 u32 reg;
2810
2811
2812 reg = er32(CTRL_EXT);
2813 reg |= (1 << 22);
2814
2815 if (hw->mac.type >= e1000_pchlan)
2816 reg |= E1000_CTRL_EXT_PHYPDEN;
2817 ew32(CTRL_EXT, reg);
2818
2819
2820 reg = er32(TXDCTL(0));
2821 reg |= (1 << 22);
2822 ew32(TXDCTL(0), reg);
2823
2824
2825 reg = er32(TXDCTL(1));
2826 reg |= (1 << 22);
2827 ew32(TXDCTL(1), reg);
2828
2829
2830 reg = er32(TARC(0));
2831 if (hw->mac.type == e1000_ich8lan)
2832 reg |= (1 << 28) | (1 << 29);
2833 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2834 ew32(TARC(0), reg);
2835
2836
2837 reg = er32(TARC(1));
2838 if (er32(TCTL) & E1000_TCTL_MULR)
2839 reg &= ~(1 << 28);
2840 else
2841 reg |= (1 << 28);
2842 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2843 ew32(TARC(1), reg);
2844
2845
2846 if (hw->mac.type == e1000_ich8lan) {
2847 reg = er32(STATUS);
2848 reg &= ~(1 << 31);
2849 ew32(STATUS, reg);
2850 }
2851}
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2864{
2865 s32 ret_val;
2866
2867 if (e1000_check_reset_block(hw))
2868 return 0;
2869
2870
2871
2872
2873
2874
2875 if (hw->fc.requested_mode == e1000_fc_default) {
2876
2877 if (hw->mac.type == e1000_pchlan)
2878 hw->fc.requested_mode = e1000_fc_rx_pause;
2879 else
2880 hw->fc.requested_mode = e1000_fc_full;
2881 }
2882
2883
2884
2885
2886
2887 hw->fc.current_mode = hw->fc.requested_mode;
2888
2889 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2890 hw->fc.current_mode);
2891
2892
2893 ret_val = e1000_setup_copper_link_ich8lan(hw);
2894 if (ret_val)
2895 return ret_val;
2896
2897 ew32(FCTTV, hw->fc.pause_time);
2898 if ((hw->phy.type == e1000_phy_82578) ||
2899 (hw->phy.type == e1000_phy_82577)) {
2900 ret_val = hw->phy.ops.write_phy_reg(hw,
2901 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2902 hw->fc.pause_time);
2903 if (ret_val)
2904 return ret_val;
2905 }
2906
2907 return e1000e_set_fc_watermarks(hw);
2908}
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2919{
2920 u32 ctrl;
2921 s32 ret_val;
2922 u16 reg_data;
2923
2924 ctrl = er32(CTRL);
2925 ctrl |= E1000_CTRL_SLU;
2926 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2927 ew32(CTRL, ctrl);
2928
2929
2930
2931
2932
2933
2934 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2935 if (ret_val)
2936 return ret_val;
2937 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
2938 if (ret_val)
2939 return ret_val;
2940 reg_data |= 0x3F;
2941 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2942 if (ret_val)
2943 return ret_val;
2944
2945 switch (hw->phy.type) {
2946 case e1000_phy_igp_3:
2947 ret_val = e1000e_copper_link_setup_igp(hw);
2948 if (ret_val)
2949 return ret_val;
2950 break;
2951 case e1000_phy_bm:
2952 case e1000_phy_82578:
2953 ret_val = e1000e_copper_link_setup_m88(hw);
2954 if (ret_val)
2955 return ret_val;
2956 break;
2957 case e1000_phy_82577:
2958 ret_val = e1000_copper_link_setup_82577(hw);
2959 if (ret_val)
2960 return ret_val;
2961 break;
2962 case e1000_phy_ife:
2963 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2964 ®_data);
2965 if (ret_val)
2966 return ret_val;
2967
2968 reg_data &= ~IFE_PMC_AUTO_MDIX;
2969
2970 switch (hw->phy.mdix) {
2971 case 1:
2972 reg_data &= ~IFE_PMC_FORCE_MDIX;
2973 break;
2974 case 2:
2975 reg_data |= IFE_PMC_FORCE_MDIX;
2976 break;
2977 case 0:
2978 default:
2979 reg_data |= IFE_PMC_AUTO_MDIX;
2980 break;
2981 }
2982 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2983 reg_data);
2984 if (ret_val)
2985 return ret_val;
2986 break;
2987 default:
2988 break;
2989 }
2990 return e1000e_setup_copper_link(hw);
2991}
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3004 u16 *duplex)
3005{
3006 s32 ret_val;
3007
3008 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3009 if (ret_val)
3010 return ret_val;
3011
3012 if ((hw->mac.type == e1000_ich8lan) &&
3013 (hw->phy.type == e1000_phy_igp_3) &&
3014 (*speed == SPEED_1000)) {
3015 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3016 }
3017
3018 return ret_val;
3019}
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3037{
3038 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3039 u32 phy_ctrl;
3040 s32 ret_val;
3041 u16 i, data;
3042 bool link;
3043
3044 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3045 return 0;
3046
3047
3048
3049
3050
3051
3052 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3053 if (!link)
3054 return 0;
3055
3056 for (i = 0; i < 10; i++) {
3057
3058 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3059 if (ret_val)
3060 return ret_val;
3061
3062 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3063 if (ret_val)
3064 return ret_val;
3065
3066
3067 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3068 return 0;
3069
3070
3071 e1000_phy_hw_reset(hw);
3072 mdelay(5);
3073 }
3074
3075 phy_ctrl = er32(PHY_CTRL);
3076 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3077 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3078 ew32(PHY_CTRL, phy_ctrl);
3079
3080
3081
3082
3083
3084 e1000e_gig_downshift_workaround_ich8lan(hw);
3085
3086
3087 return -E1000_ERR_PHY;
3088}
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3099 bool state)
3100{
3101 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3102
3103 if (hw->mac.type != e1000_ich8lan) {
3104 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
3105 return;
3106 }
3107
3108 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3109}
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3122{
3123 u32 reg;
3124 u16 data;
3125 u8 retry = 0;
3126
3127 if (hw->phy.type != e1000_phy_igp_3)
3128 return;
3129
3130
3131 do {
3132
3133 reg = er32(PHY_CTRL);
3134 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3135 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3136 ew32(PHY_CTRL, reg);
3137
3138
3139
3140
3141
3142 if (hw->mac.type == e1000_ich8lan)
3143 e1000e_gig_downshift_workaround_ich8lan(hw);
3144
3145
3146 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3147 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3148 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3149
3150
3151 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3152 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3153 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3154 break;
3155
3156
3157 reg = er32(CTRL);
3158 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3159 retry++;
3160 } while (retry);
3161}
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3174{
3175 s32 ret_val;
3176 u16 reg_data;
3177
3178 if ((hw->mac.type != e1000_ich8lan) ||
3179 (hw->phy.type != e1000_phy_igp_3))
3180 return;
3181
3182 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3183 ®_data);
3184 if (ret_val)
3185 return;
3186 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3187 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3188 reg_data);
3189 if (ret_val)
3190 return;
3191 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3192 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3193 reg_data);
3194}
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3208{
3209 u32 phy_ctrl;
3210
3211 switch (hw->mac.type) {
3212 case e1000_ich9lan:
3213 case e1000_ich10lan:
3214 case e1000_pchlan:
3215 phy_ctrl = er32(PHY_CTRL);
3216 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3217 E1000_PHY_CTRL_GBE_DISABLE;
3218 ew32(PHY_CTRL, phy_ctrl);
3219
3220 if (hw->mac.type == e1000_pchlan)
3221 e1000_phy_hw_reset_ich8lan(hw);
3222 default:
3223 break;
3224 }
3225
3226 return;
3227}
3228
3229
3230
3231
3232
3233
3234
3235static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3236{
3237 if (hw->phy.type == e1000_phy_ife)
3238 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3239
3240 ew32(LEDCTL, hw->mac.ledctl_default);
3241 return 0;
3242}
3243
3244
3245
3246
3247
3248
3249
3250static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3251{
3252 if (hw->phy.type == e1000_phy_ife)
3253 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3254 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3255
3256 ew32(LEDCTL, hw->mac.ledctl_mode2);
3257 return 0;
3258}
3259
3260
3261
3262
3263
3264
3265
3266static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3267{
3268 if (hw->phy.type == e1000_phy_ife)
3269 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3270 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3271
3272 ew32(LEDCTL, hw->mac.ledctl_mode1);
3273 return 0;
3274}
3275
3276
3277
3278
3279
3280
3281
3282static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3283{
3284 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3285 (u16)hw->mac.ledctl_mode1);
3286}
3287
3288
3289
3290
3291
3292
3293
3294static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3295{
3296 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3297 (u16)hw->mac.ledctl_default);
3298}
3299
3300
3301
3302
3303
3304
3305
3306static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3307{
3308 u16 data = (u16)hw->mac.ledctl_mode2;
3309 u32 i, led;
3310
3311
3312
3313
3314
3315 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3316 for (i = 0; i < 3; i++) {
3317 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3318 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3319 E1000_LEDCTL_MODE_LINK_UP)
3320 continue;
3321 if (led & E1000_PHY_LED0_IVRT)
3322 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3323 else
3324 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3325 }
3326 }
3327
3328 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3329}
3330
3331
3332
3333
3334
3335
3336
3337static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3338{
3339 u16 data = (u16)hw->mac.ledctl_mode1;
3340 u32 i, led;
3341
3342
3343
3344
3345
3346 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3347 for (i = 0; i < 3; i++) {
3348 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3349 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3350 E1000_LEDCTL_MODE_LINK_UP)
3351 continue;
3352 if (led & E1000_PHY_LED0_IVRT)
3353 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3354 else
3355 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3356 }
3357 }
3358
3359 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3360}
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3373{
3374 u32 bank = 0;
3375
3376 if (hw->mac.type >= e1000_pchlan) {
3377 u32 status = er32(STATUS);
3378
3379 if (status & E1000_STATUS_PHYRA)
3380 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3381 else
3382 hw_dbg(hw,
3383 "PHY Reset Asserted not set - needs delay\n");
3384 }
3385
3386 e1000e_get_cfg_done(hw);
3387
3388
3389 if ((hw->mac.type != e1000_ich10lan) &&
3390 (hw->mac.type != e1000_pchlan)) {
3391 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3392 (hw->phy.type == e1000_phy_igp_3)) {
3393 e1000e_phy_init_script_igp3(hw);
3394 }
3395 } else {
3396 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3397
3398 hw_dbg(hw, "EEPROM not present\n");
3399 return -E1000_ERR_CONFIG;
3400 }
3401 }
3402
3403 return 0;
3404}
3405
3406
3407
3408
3409
3410
3411
3412
3413static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3414{
3415 u32 temp;
3416 u16 phy_data;
3417
3418 e1000e_clear_hw_cntrs_base(hw);
3419
3420 temp = er32(ALGNERRC);
3421 temp = er32(RXERRC);
3422 temp = er32(TNCRS);
3423 temp = er32(CEXTERR);
3424 temp = er32(TSCTC);
3425 temp = er32(TSCTFC);
3426
3427 temp = er32(MGTPRC);
3428 temp = er32(MGTPDC);
3429 temp = er32(MGTPTC);
3430
3431 temp = er32(IAC);
3432 temp = er32(ICRXOC);
3433
3434
3435 if ((hw->phy.type == e1000_phy_82578) ||
3436 (hw->phy.type == e1000_phy_82577)) {
3437 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3438 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3439 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3440 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3441 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3442 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3443 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3444 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3445 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3446 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3447 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3448 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3449 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3450 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3451 }
3452}
3453
3454static struct e1000_mac_operations ich8_mac_ops = {
3455 .id_led_init = e1000e_id_led_init,
3456 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3457 .check_for_link = e1000_check_for_copper_link_ich8lan,
3458
3459 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3460 .get_bus_info = e1000_get_bus_info_ich8lan,
3461 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3462
3463
3464 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3465 .reset_hw = e1000_reset_hw_ich8lan,
3466 .init_hw = e1000_init_hw_ich8lan,
3467 .setup_link = e1000_setup_link_ich8lan,
3468 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3469
3470};
3471
3472static struct e1000_phy_operations ich8_phy_ops = {
3473 .acquire_phy = e1000_acquire_swflag_ich8lan,
3474 .check_reset_block = e1000_check_reset_block_ich8lan,
3475 .commit_phy = NULL,
3476 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
3477 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3478 .get_cable_length = e1000e_get_cable_length_igp_2,
3479 .get_phy_info = e1000_get_phy_info_ich8lan,
3480 .read_phy_reg = e1000e_read_phy_reg_igp,
3481 .release_phy = e1000_release_swflag_ich8lan,
3482 .reset_phy = e1000_phy_hw_reset_ich8lan,
3483 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3484 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3485 .write_phy_reg = e1000e_write_phy_reg_igp,
3486};
3487
3488static struct e1000_nvm_operations ich8_nvm_ops = {
3489 .acquire_nvm = e1000_acquire_nvm_ich8lan,
3490 .read_nvm = e1000_read_nvm_ich8lan,
3491 .release_nvm = e1000_release_nvm_ich8lan,
3492 .update_nvm = e1000_update_nvm_checksum_ich8lan,
3493 .valid_led_default = e1000_valid_led_default_ich8lan,
3494 .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
3495 .write_nvm = e1000_write_nvm_ich8lan,
3496};
3497
3498struct e1000_info e1000_ich8_info = {
3499 .mac = e1000_ich8lan,
3500 .flags = FLAG_HAS_WOL
3501 | FLAG_IS_ICH
3502 | FLAG_RX_CSUM_ENABLED
3503 | FLAG_HAS_CTRLEXT_ON_LOAD
3504 | FLAG_HAS_AMT
3505 | FLAG_HAS_FLASH
3506 | FLAG_APME_IN_WUC,
3507 .pba = 8,
3508 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3509 .get_variants = e1000_get_variants_ich8lan,
3510 .mac_ops = &ich8_mac_ops,
3511 .phy_ops = &ich8_phy_ops,
3512 .nvm_ops = &ich8_nvm_ops,
3513};
3514
3515struct e1000_info e1000_ich9_info = {
3516 .mac = e1000_ich9lan,
3517 .flags = FLAG_HAS_JUMBO_FRAMES
3518 | FLAG_IS_ICH
3519 | FLAG_HAS_WOL
3520 | FLAG_RX_CSUM_ENABLED
3521 | FLAG_HAS_CTRLEXT_ON_LOAD
3522 | FLAG_HAS_AMT
3523 | FLAG_HAS_ERT
3524 | FLAG_HAS_FLASH
3525 | FLAG_APME_IN_WUC,
3526 .pba = 10,
3527 .max_hw_frame_size = DEFAULT_JUMBO,
3528 .get_variants = e1000_get_variants_ich8lan,
3529 .mac_ops = &ich8_mac_ops,
3530 .phy_ops = &ich8_phy_ops,
3531 .nvm_ops = &ich8_nvm_ops,
3532};
3533
3534struct e1000_info e1000_ich10_info = {
3535 .mac = e1000_ich10lan,
3536 .flags = FLAG_HAS_JUMBO_FRAMES
3537 | FLAG_IS_ICH
3538 | FLAG_HAS_WOL
3539 | FLAG_RX_CSUM_ENABLED
3540 | FLAG_HAS_CTRLEXT_ON_LOAD
3541 | FLAG_HAS_AMT
3542 | FLAG_HAS_ERT
3543 | FLAG_HAS_FLASH
3544 | FLAG_APME_IN_WUC,
3545 .pba = 10,
3546 .max_hw_frame_size = DEFAULT_JUMBO,
3547 .get_variants = e1000_get_variants_ich8lan,
3548 .mac_ops = &ich8_mac_ops,
3549 .phy_ops = &ich8_phy_ops,
3550 .nvm_ops = &ich8_nvm_ops,
3551};
3552
3553struct e1000_info e1000_pch_info = {
3554 .mac = e1000_pchlan,
3555 .flags = FLAG_IS_ICH
3556 | FLAG_HAS_WOL
3557 | FLAG_RX_CSUM_ENABLED
3558 | FLAG_HAS_CTRLEXT_ON_LOAD
3559 | FLAG_HAS_AMT
3560 | FLAG_HAS_FLASH
3561 | FLAG_HAS_JUMBO_FRAMES
3562 | FLAG_DISABLE_FC_PAUSE_TIME
3563 | FLAG_APME_IN_WUC,
3564 .pba = 26,
3565 .max_hw_frame_size = 4096,
3566 .get_variants = e1000_get_variants_ich8lan,
3567 .mac_ops = &ich8_mac_ops,
3568 .phy_ops = &ich8_phy_ops,
3569 .nvm_ops = &ich8_nvm_ops,
3570};
3571