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146#include <linux/module.h>
147#include <linux/kernel.h>
148#include <linux/sched.h>
149#include <linux/string.h>
150#include <linux/errno.h>
151#include <linux/ioport.h>
152#include <linux/slab.h>
153#include <linux/interrupt.h>
154#include <linux/delay.h>
155#include <linux/init.h>
156#include <linux/crc32.h>
157#include <linux/netdevice.h>
158#include <linux/etherdevice.h>
159#include <linux/skbuff.h>
160#include <linux/ethtool.h>
161#include <linux/time.h>
162#include <linux/types.h>
163#include <linux/unistd.h>
164#include <linux/ctype.h>
165#include <linux/bitops.h>
166
167#include <asm/io.h>
168#include <asm/dma.h>
169#include <asm/uaccess.h>
170
171#include "ewrk3.h"
172
173#define DRV_NAME "ewrk3"
174#define DRV_VERSION "0.48"
175
176static char version[] __initdata =
177DRV_NAME ":v" DRV_VERSION " 2002/10/18 davies@maniac.ultranet.com\n";
178
179#ifdef EWRK3_DEBUG
180static int ewrk3_debug = EWRK3_DEBUG;
181#else
182static int ewrk3_debug = 1;
183#endif
184
185#define EWRK3_NDA 0xffe0
186
187#define PROBE_LENGTH 32
188#define ETH_PROM_SIG 0xAA5500FFUL
189
190#ifndef EWRK3_SIGNATURE
191#define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
192#define EWRK3_STRLEN 8
193#endif
194
195#ifndef EWRK3_RAM_BASE_ADDRESSES
196#define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
197#endif
198
199
200
201
202#define EWRK3_IO_BASE 0x100
203#define EWRK3_IOP_INC 0x20
204#define EWRK3_TOTAL_SIZE 0x20
205
206#ifndef MAX_NUM_EWRK3S
207#define MAX_NUM_EWRK3S 21
208#endif
209
210#ifndef EWRK3_EISA_IO_PORTS
211#define EWRK3_EISA_IO_PORTS 0x0c00
212#endif
213
214#ifndef MAX_EISA_SLOTS
215#define MAX_EISA_SLOTS 16
216#define EISA_SLOT_INC 0x1000
217#endif
218
219#define QUEUE_PKT_TIMEOUT (1*HZ)
220
221
222
223
224#define IO_ONLY 0x00
225#define SHMEM_2K 0x800
226#define SHMEM_32K 0x8000
227#define SHMEM_64K 0x10000
228
229
230
231
232#define ENABLE_IRQs { \
233 icr |= lp->irq_mask;\
234 outb(icr, EWRK3_ICR); \
235}
236
237#define DISABLE_IRQs { \
238 icr = inb(EWRK3_ICR);\
239 icr &= ~lp->irq_mask;\
240 outb(icr, EWRK3_ICR); \
241}
242
243
244
245
246#define START_EWRK3 { \
247 csr = inb(EWRK3_CSR);\
248 csr &= ~(CSR_TXD|CSR_RXD);\
249 outb(csr, EWRK3_CSR); \
250}
251
252#define STOP_EWRK3 { \
253 csr = (CSR_TXD|CSR_RXD);\
254 outb(csr, EWRK3_CSR); \
255}
256
257
258
259
260#define EWRK3_PKT_STAT_SZ 16
261#define EWRK3_PKT_BIN_SZ 128
262
263
264struct ewrk3_stats {
265 u32 bins[EWRK3_PKT_STAT_SZ];
266 u32 unicast;
267 u32 multicast;
268 u32 broadcast;
269 u32 excessive_collisions;
270 u32 tx_underruns;
271 u32 excessive_underruns;
272};
273
274struct ewrk3_private {
275 char adapter_name[80];
276 u_long shmem_base;
277 void __iomem *shmem;
278 u_long shmem_length;
279 struct ewrk3_stats pktStats;
280 u_char irq_mask;
281 u_char mPage;
282 u_char lemac;
283 u_char hard_strapped;
284 u_char txc;
285 void __iomem *mctbl;
286 u_char led_mask;
287 spinlock_t hw_lock;
288};
289
290
291
292
293#define FORCE_2K_MODE { \
294 shmem_length = SHMEM_2K;\
295 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR);\
296}
297
298
299
300
301static int ewrk3_open(struct net_device *dev);
302static netdev_tx_t ewrk3_queue_pkt(struct sk_buff *skb, struct net_device *dev);
303static irqreturn_t ewrk3_interrupt(int irq, void *dev_id);
304static int ewrk3_close(struct net_device *dev);
305static void set_multicast_list(struct net_device *dev);
306static int ewrk3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
307static const struct ethtool_ops ethtool_ops_203;
308static const struct ethtool_ops ethtool_ops;
309
310
311
312
313static int ewrk3_hw_init(struct net_device *dev, u_long iobase);
314static void ewrk3_init(struct net_device *dev);
315static int ewrk3_rx(struct net_device *dev);
316static int ewrk3_tx(struct net_device *dev);
317static void ewrk3_timeout(struct net_device *dev);
318
319static void EthwrkSignature(char *name, char *eeprom_image);
320static int DevicePresent(u_long iobase);
321static void SetMulticastFilter(struct net_device *dev);
322static int EISA_signature(char *name, s32 eisa_id);
323
324static int Read_EEPROM(u_long iobase, u_char eaddr);
325static int Write_EEPROM(short data, u_long iobase, u_char eaddr);
326static u_char get_hw_addr(struct net_device *dev, u_char * eeprom_image, char chipType);
327
328static int ewrk3_probe1(struct net_device *dev, u_long iobase, int irq);
329static int isa_probe(struct net_device *dev, u_long iobase);
330static int eisa_probe(struct net_device *dev, u_long iobase);
331
332static u_char irq[MAX_NUM_EWRK3S+1] = {5, 0, 10, 3, 11, 9, 15, 12};
333
334static char name[EWRK3_STRLEN + 1];
335static int num_ewrks3s;
336
337
338
339
340#define INIT_EWRK3 {\
341 outb(EEPROM_INIT, EWRK3_IOPR);\
342 mdelay(1);\
343}
344
345#ifndef MODULE
346struct net_device * __init ewrk3_probe(int unit)
347{
348 struct net_device *dev = alloc_etherdev(sizeof(struct ewrk3_private));
349 int err;
350
351 if (!dev)
352 return ERR_PTR(-ENOMEM);
353
354 if (unit >= 0) {
355 sprintf(dev->name, "eth%d", unit);
356 netdev_boot_setup_check(dev);
357 }
358
359 err = ewrk3_probe1(dev, dev->base_addr, dev->irq);
360 if (err)
361 goto out;
362 return dev;
363out:
364 free_netdev(dev);
365 return ERR_PTR(err);
366
367}
368#endif
369
370static int __init ewrk3_probe1(struct net_device *dev, u_long iobase, int irq)
371{
372 int err;
373
374 dev->base_addr = iobase;
375 dev->irq = irq;
376
377
378 err = isa_probe(dev, iobase);
379 if (err != 0)
380 err = eisa_probe(dev, iobase);
381
382 if (err)
383 return err;
384
385 err = register_netdev(dev);
386 if (err)
387 release_region(dev->base_addr, EWRK3_TOTAL_SIZE);
388
389 return err;
390}
391
392static const struct net_device_ops ewrk3_netdev_ops = {
393 .ndo_open = ewrk3_open,
394 .ndo_start_xmit = ewrk3_queue_pkt,
395 .ndo_stop = ewrk3_close,
396 .ndo_set_multicast_list = set_multicast_list,
397 .ndo_do_ioctl = ewrk3_ioctl,
398 .ndo_tx_timeout = ewrk3_timeout,
399 .ndo_change_mtu = eth_change_mtu,
400 .ndo_set_mac_address = eth_mac_addr,
401 .ndo_validate_addr = eth_validate_addr,
402};
403
404static int __init
405ewrk3_hw_init(struct net_device *dev, u_long iobase)
406{
407 struct ewrk3_private *lp;
408 int i, status = 0;
409 u_long mem_start, shmem_length;
410 u_char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
411 u_char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
412
413
414
415
416
417 if (iobase > 0x400)
418 eisa_cr = inb(EISA_CR);
419 INIT_EWRK3;
420
421 nicsr = inb(EWRK3_CSR);
422
423 icr = inb(EWRK3_ICR);
424 icr &= 0x70;
425 outb(icr, EWRK3_ICR);
426
427 if (nicsr != (CSR_TXD | CSR_RXD))
428 return -ENXIO;
429
430
431 for (chksum = 0, i = 0; i < EEPROM_MAX; i += 2) {
432 union {
433 short val;
434 char c[2];
435 } tmp;
436
437 tmp.val = (short) Read_EEPROM(iobase, (i >> 1));
438 eeprom_image[i] = tmp.c[0];
439 eeprom_image[i + 1] = tmp.c[1];
440 chksum += eeprom_image[i] + eeprom_image[i + 1];
441 }
442
443 if (chksum != 0) {
444 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
445 return -ENXIO;
446 }
447
448 EthwrkSignature(name, eeprom_image);
449 if (*name == '\0')
450 return -ENXIO;
451
452 dev->base_addr = iobase;
453
454 if (iobase > 0x400) {
455 outb(eisa_cr, EISA_CR);
456 }
457 lemac = eeprom_image[EEPROM_CHIPVER];
458 cmr = inb(EWRK3_CMR);
459
460 if (((lemac == LeMAC) && ((cmr & CMR_NO_EEPROM) != CMR_NO_EEPROM)) ||
461 ((lemac == LeMAC2) && !(cmr & CMR_HS))) {
462 printk("%s: %s at %#4lx", dev->name, name, iobase);
463 hard_strapped = 1;
464 } else if ((iobase & 0x0fff) == EWRK3_EISA_IO_PORTS) {
465
466 printk("%s: %s at %#4lx (EISA slot %ld)",
467 dev->name, name, iobase, ((iobase >> 12) & 0x0f));
468 } else {
469 printk("%s: %s at %#4lx", dev->name, name, iobase);
470 }
471
472 printk(", h/w address ");
473 if (lemac != LeMAC2)
474 DevicePresent(iobase);
475 status = get_hw_addr(dev, eeprom_image, lemac);
476 printk("%pM\n", dev->dev_addr);
477
478 if (status) {
479 printk(" which has an EEPROM CRC error.\n");
480 return -ENXIO;
481 }
482
483 if (lemac == LeMAC2) {
484 cmr &= ~(CMR_RA | CMR_WB | CMR_LINK | CMR_POLARITY | CMR_0WS);
485 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD)
486 cmr |= CMR_RA;
487 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND)
488 cmr |= CMR_WB;
489 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL)
490 cmr |= CMR_POLARITY;
491 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK)
492 cmr |= CMR_LINK;
493 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA)
494 cmr |= CMR_0WS;
495 }
496 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM)
497 cmr |= CMR_DRAM;
498 outb(cmr, EWRK3_CMR);
499
500 cr = inb(EWRK3_CR);
501 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
502 if (cr & SETUP_APD)
503 cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
504 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
505 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
506 outb(cr, EWRK3_CR);
507
508
509
510
511
512 mem_start = inb(EWRK3_MBR);
513 shmem_length = 0;
514 if (mem_start != 0) {
515 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
516 mem_start *= SHMEM_64K;
517 shmem_length = SHMEM_64K;
518 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
519 mem_start *= SHMEM_32K;
520 shmem_length = SHMEM_32K;
521 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
522 mem_start = mem_start * SHMEM_2K + 0x80000;
523 shmem_length = SHMEM_2K;
524 } else {
525 return -ENXIO;
526 }
527 }
528
529
530
531
532
533
534 if (hard_strapped) {
535 printk(" is hard strapped.\n");
536 } else if (mem_start) {
537 printk(" has a %dk RAM window", (int) (shmem_length >> 10));
538 printk(" at 0x%.5lx", mem_start);
539 } else {
540 printk(" is in I/O only mode");
541 }
542
543 lp = netdev_priv(dev);
544 lp->shmem_base = mem_start;
545 lp->shmem = ioremap(mem_start, shmem_length);
546 if (!lp->shmem)
547 return -ENOMEM;
548 lp->shmem_length = shmem_length;
549 lp->lemac = lemac;
550 lp->hard_strapped = hard_strapped;
551 lp->led_mask = CR_LED;
552 spin_lock_init(&lp->hw_lock);
553
554 lp->mPage = 64;
555 if (cmr & CMR_DRAM)
556 lp->mPage <<= 1;
557
558 sprintf(lp->adapter_name, "%s (%s)", name, dev->name);
559
560 lp->irq_mask = ICR_TNEM | ICR_TXDM | ICR_RNEM | ICR_RXDM;
561
562 if (!hard_strapped) {
563
564
565
566 icr |= ICR_IE;
567 outb(icr, EWRK3_ICR);
568
569
570 dev->dma = 0;
571
572
573
574 if (dev->irq < 2) {
575#ifndef MODULE
576 u_char irqnum;
577 unsigned long irq_mask;
578
579
580 irq_mask = probe_irq_on();
581
582
583
584
585 icr |= ICR_TNEM;
586 outb(1, EWRK3_TDQ);
587 outb(icr, EWRK3_ICR);
588
589 irqnum = irq[((icr & IRQ_SEL) >> 4)];
590
591 mdelay(20);
592 dev->irq = probe_irq_off(irq_mask);
593 if ((dev->irq) && (irqnum == dev->irq)) {
594 printk(" and uses IRQ%d.\n", dev->irq);
595 } else {
596 if (!dev->irq) {
597 printk(" and failed to detect IRQ line.\n");
598 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
599 printk(" and an illegal IRQ line detected.\n");
600 } else {
601 printk(", but incorrect IRQ line detected.\n");
602 }
603 iounmap(lp->shmem);
604 return -ENXIO;
605 }
606
607 DISABLE_IRQs;
608
609#endif
610 } else {
611 printk(" and requires IRQ%d.\n", dev->irq);
612 }
613 }
614
615 if (ewrk3_debug > 1) {
616 printk(version);
617 }
618
619 dev->netdev_ops = &ewrk3_netdev_ops;
620 if (lp->adapter_name[4] == '3')
621 SET_ETHTOOL_OPS(dev, ðtool_ops_203);
622 else
623 SET_ETHTOOL_OPS(dev, ðtool_ops);
624 dev->watchdog_timeo = QUEUE_PKT_TIMEOUT;
625
626 dev->mem_start = 0;
627
628 return 0;
629}
630
631
632static int ewrk3_open(struct net_device *dev)
633{
634 struct ewrk3_private *lp = netdev_priv(dev);
635 u_long iobase = dev->base_addr;
636 int status = 0;
637 u_char icr, csr;
638
639
640
641
642 STOP_EWRK3;
643
644 if (!lp->hard_strapped) {
645 if (request_irq(dev->irq, (void *) ewrk3_interrupt, 0, "ewrk3", dev)) {
646 printk("ewrk3_open(): Requested IRQ%d is busy\n", dev->irq);
647 status = -EAGAIN;
648 } else {
649
650
651
652
653 ewrk3_init(dev);
654
655 if (ewrk3_debug > 1) {
656 printk("%s: ewrk3 open with irq %d\n", dev->name, dev->irq);
657 printk(" physical address: %pM\n", dev->dev_addr);
658 if (lp->shmem_length == 0) {
659 printk(" no shared memory, I/O only mode\n");
660 } else {
661 printk(" start of shared memory: 0x%08lx\n", lp->shmem_base);
662 printk(" window length: 0x%04lx\n", lp->shmem_length);
663 }
664 printk(" # of DRAMS: %d\n", ((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
665 printk(" csr: 0x%02x\n", inb(EWRK3_CSR));
666 printk(" cr: 0x%02x\n", inb(EWRK3_CR));
667 printk(" icr: 0x%02x\n", inb(EWRK3_ICR));
668 printk(" cmr: 0x%02x\n", inb(EWRK3_CMR));
669 printk(" fmqc: 0x%02x\n", inb(EWRK3_FMQC));
670 }
671 netif_start_queue(dev);
672
673
674
675 icr = inb(EWRK3_ICR);
676 ENABLE_IRQs;
677
678 }
679 } else {
680 printk(KERN_ERR "%s: ewrk3 available for hard strapped set up only.\n", dev->name);
681 printk(KERN_ERR " Run the 'ewrk3setup' utility or remove the hard straps.\n");
682 return -EINVAL;
683 }
684
685 return status;
686}
687
688
689
690
691static void ewrk3_init(struct net_device *dev)
692{
693 struct ewrk3_private *lp = netdev_priv(dev);
694 u_char csr, page;
695 u_long iobase = dev->base_addr;
696 int i;
697
698
699
700
701 set_multicast_list(dev);
702
703
704
705
706
707 for (i=0; i<ETH_ALEN; i++)
708 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
709
710
711
712
713 while (inb(EWRK3_TQ));
714 while (inb(EWRK3_TDQ));
715 while (inb(EWRK3_RQ));
716 while (inb(EWRK3_FMQ));
717
718
719
720
721 for (page = 1; page < lp->mPage; page++) {
722 outb(page, EWRK3_FMQ);
723 }
724
725 START_EWRK3;
726}
727
728
729
730
731
732static void ewrk3_timeout(struct net_device *dev)
733{
734 struct ewrk3_private *lp = netdev_priv(dev);
735 u_char icr, csr;
736 u_long iobase = dev->base_addr;
737
738 if (!lp->hard_strapped)
739 {
740 printk(KERN_WARNING"%s: transmit timed/locked out, status %04x, resetting.\n",
741 dev->name, inb(EWRK3_CSR));
742
743
744
745
746 DISABLE_IRQs;
747
748
749
750
751 STOP_EWRK3;
752
753 ewrk3_init(dev);
754
755
756
757
758 ENABLE_IRQs;
759
760 dev->trans_start = jiffies;
761 netif_wake_queue(dev);
762 }
763}
764
765
766
767
768static netdev_tx_t ewrk3_queue_pkt(struct sk_buff *skb, struct net_device *dev)
769{
770 struct ewrk3_private *lp = netdev_priv(dev);
771 u_long iobase = dev->base_addr;
772 void __iomem *buf = NULL;
773 u_char icr;
774 u_char page;
775
776 spin_lock_irq (&lp->hw_lock);
777 DISABLE_IRQs;
778
779
780 if (inb (EWRK3_FMQC) == 0) {
781 printk (KERN_WARNING "%s: ewrk3_queue_pkt(): No free resources...\n",
782 dev->name);
783 printk (KERN_WARNING "%s: ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",
784 dev->name, inb (EWRK3_CSR), inb (EWRK3_ICR),
785 inb (EWRK3_FMQC));
786 goto err_out;
787 }
788
789
790
791
792 if ((page = inb (EWRK3_FMQ)) >= lp->mPage) {
793 printk ("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
794 (u_char) page);
795 goto err_out;
796 }
797
798
799
800
801
802 if (lp->shmem_length == IO_ONLY) {
803 outb (page, EWRK3_IOPR);
804 } else if (lp->shmem_length == SHMEM_2K) {
805 buf = lp->shmem;
806 outb (page, EWRK3_MPR);
807 } else if (lp->shmem_length == SHMEM_32K) {
808 buf = (((short) page << 11) & 0x7800) + lp->shmem;
809 outb ((page >> 4), EWRK3_MPR);
810 } else if (lp->shmem_length == SHMEM_64K) {
811 buf = (((short) page << 11) & 0xf800) + lp->shmem;
812 outb ((page >> 5), EWRK3_MPR);
813 } else {
814 printk (KERN_ERR "%s: Oops - your private data area is hosed!\n",
815 dev->name);
816 BUG ();
817 }
818
819
820
821
822
823 if (lp->shmem_length == IO_ONLY) {
824 int i;
825 u_char *p = skb->data;
826 outb ((char) (TCR_QMODE | TCR_PAD | TCR_IFC), EWRK3_DATA);
827 outb ((char) (skb->len & 0xff), EWRK3_DATA);
828 outb ((char) ((skb->len >> 8) & 0xff), EWRK3_DATA);
829 outb ((char) 0x04, EWRK3_DATA);
830 for (i = 0; i < skb->len; i++) {
831 outb (*p++, EWRK3_DATA);
832 }
833 outb (page, EWRK3_TQ);
834 } else {
835 writeb ((char) (TCR_QMODE | TCR_PAD | TCR_IFC), buf);
836 buf += 1;
837 writeb ((char) (skb->len & 0xff), buf);
838 buf += 1;
839 if (lp->txc) {
840 writeb(((skb->len >> 8) & 0xff) | XCT, buf);
841 buf += 1;
842 writeb (0x04, buf);
843 buf += 1;
844 writeb (0x00, (buf + skb->len));
845 memcpy_toio (buf, skb->data, PRELOAD);
846 outb (page, EWRK3_TQ);
847 memcpy_toio (buf + PRELOAD,
848 skb->data + PRELOAD,
849 skb->len - PRELOAD);
850 writeb (0xff, (buf + skb->len));
851 } else {
852 writeb ((skb->len >> 8) & 0xff, buf);
853 buf += 1;
854 writeb (0x04, buf);
855 buf += 1;
856 memcpy_toio (buf, skb->data, skb->len);
857 outb (page, EWRK3_TQ);
858 }
859 }
860
861 ENABLE_IRQs;
862 spin_unlock_irq (&lp->hw_lock);
863
864 dev->stats.tx_bytes += skb->len;
865 dev->trans_start = jiffies;
866 dev_kfree_skb (skb);
867
868
869 if (inb (EWRK3_FMQC) == 0)
870 netif_stop_queue (dev);
871
872 return NETDEV_TX_OK;
873
874err_out:
875 ENABLE_IRQs;
876 spin_unlock_irq (&lp->hw_lock);
877 return NETDEV_TX_BUSY;
878}
879
880
881
882
883static irqreturn_t ewrk3_interrupt(int irq, void *dev_id)
884{
885 struct net_device *dev = dev_id;
886 struct ewrk3_private *lp;
887 u_long iobase;
888 u_char icr, cr, csr;
889
890 lp = netdev_priv(dev);
891 iobase = dev->base_addr;
892
893
894 csr = inb(EWRK3_CSR);
895
896
897
898
899 spin_lock(&lp->hw_lock);
900 DISABLE_IRQs;
901
902 cr = inb(EWRK3_CR);
903 cr |= lp->led_mask;
904 outb(cr, EWRK3_CR);
905
906 if (csr & CSR_RNE)
907 ewrk3_rx(dev);
908
909 if (csr & CSR_TNE)
910 ewrk3_tx(dev);
911
912
913
914
915
916
917
918 if (inb(EWRK3_FMQC)) {
919 lp->irq_mask |= ICR_TXDM | ICR_RXDM;
920 csr &= ~(CSR_TXD | CSR_RXD);
921 outb(csr, EWRK3_CSR);
922 netif_wake_queue(dev);
923 } else {
924 lp->irq_mask &= ~(ICR_TXDM | ICR_RXDM);
925 }
926
927
928 cr &= ~(lp->led_mask);
929 outb(cr, EWRK3_CR);
930 ENABLE_IRQs;
931 spin_unlock(&lp->hw_lock);
932 return IRQ_HANDLED;
933}
934
935
936static int ewrk3_rx(struct net_device *dev)
937{
938 struct ewrk3_private *lp = netdev_priv(dev);
939 u_long iobase = dev->base_addr;
940 int i, status = 0;
941 u_char page;
942 void __iomem *buf = NULL;
943
944 while (inb(EWRK3_RQC) && !status) {
945 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
946
947
948
949 if (lp->shmem_length == IO_ONLY) {
950 outb(page, EWRK3_IOPR);
951 } else if (lp->shmem_length == SHMEM_2K) {
952 buf = lp->shmem;
953 outb(page, EWRK3_MPR);
954 } else if (lp->shmem_length == SHMEM_32K) {
955 buf = (((short) page << 11) & 0x7800) + lp->shmem;
956 outb((page >> 4), EWRK3_MPR);
957 } else if (lp->shmem_length == SHMEM_64K) {
958 buf = (((short) page << 11) & 0xf800) + lp->shmem;
959 outb((page >> 5), EWRK3_MPR);
960 } else {
961 status = -1;
962 printk("%s: Oops - your private data area is hosed!\n", dev->name);
963 }
964
965 if (!status) {
966 char rx_status;
967 int pkt_len;
968
969 if (lp->shmem_length == IO_ONLY) {
970 rx_status = inb(EWRK3_DATA);
971 pkt_len = inb(EWRK3_DATA);
972 pkt_len |= ((u_short) inb(EWRK3_DATA) << 8);
973 } else {
974 rx_status = readb(buf);
975 buf += 1;
976 pkt_len = readw(buf);
977 buf += 3;
978 }
979
980 if (!(rx_status & R_ROK)) {
981 dev->stats.rx_errors++;
982 if (rx_status & R_DBE)
983 dev->stats.rx_frame_errors++;
984 if (rx_status & R_CRC)
985 dev->stats.rx_crc_errors++;
986 if (rx_status & R_PLL)
987 dev->stats.rx_fifo_errors++;
988 } else {
989 struct sk_buff *skb;
990
991 if ((skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
992 unsigned char *p;
993 skb_reserve(skb, 2);
994 p = skb_put(skb, pkt_len);
995
996 if (lp->shmem_length == IO_ONLY) {
997 *p = inb(EWRK3_DATA);
998 for (i = 0; i < pkt_len; i++) {
999 *p++ = inb(EWRK3_DATA);
1000 }
1001 } else {
1002 memcpy_fromio(p, buf, pkt_len);
1003 }
1004
1005 for (i = 1; i < EWRK3_PKT_STAT_SZ - 1; i++) {
1006 if (pkt_len < i * EWRK3_PKT_BIN_SZ) {
1007 lp->pktStats.bins[i]++;
1008 i = EWRK3_PKT_STAT_SZ;
1009 }
1010 }
1011 p = skb->data;
1012 if (p[0] & 0x01) {
1013 if ((*(s16 *) & p[0] == -1) && (*(s16 *) & p[2] == -1) && (*(s16 *) & p[4] == -1)) {
1014 lp->pktStats.broadcast++;
1015 } else {
1016 lp->pktStats.multicast++;
1017 }
1018 } else if ((*(s16 *) & p[0] == *(s16 *) & dev->dev_addr[0]) &&
1019 (*(s16 *) & p[2] == *(s16 *) & dev->dev_addr[2]) &&
1020 (*(s16 *) & p[4] == *(s16 *) & dev->dev_addr[4])) {
1021 lp->pktStats.unicast++;
1022 }
1023 lp->pktStats.bins[0]++;
1024 if (lp->pktStats.bins[0] == 0) {
1025 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1026 }
1027
1028
1029
1030
1031 skb->protocol = eth_type_trans(skb, dev);
1032 netif_rx(skb);
1033
1034
1035
1036
1037 dev->stats.rx_packets++;
1038 dev->stats.rx_bytes += pkt_len;
1039 } else {
1040 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1041 dev->stats.rx_dropped++;
1042 break;
1043 }
1044 }
1045 }
1046
1047
1048
1049 outb(page, EWRK3_FMQ);
1050 } else {
1051 printk("ewrk3_rx(): Illegal page number, page %d\n", page);
1052 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n", inb(EWRK3_CSR), inb(EWRK3_ICR), inb(EWRK3_FMQC));
1053 }
1054 }
1055 return status;
1056}
1057
1058
1059
1060
1061
1062static int ewrk3_tx(struct net_device *dev)
1063{
1064 struct ewrk3_private *lp = netdev_priv(dev);
1065 u_long iobase = dev->base_addr;
1066 u_char tx_status;
1067
1068 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1069 if (tx_status & T_VSTS) {
1070 if (tx_status & T_TXE) {
1071 dev->stats.tx_errors++;
1072 if (tx_status & T_NCL)
1073 dev->stats.tx_carrier_errors++;
1074 if (tx_status & T_LCL)
1075 dev->stats.tx_window_errors++;
1076 if (tx_status & T_CTU) {
1077 if ((tx_status & T_COLL) ^ T_XUR) {
1078 lp->pktStats.tx_underruns++;
1079 } else {
1080 lp->pktStats.excessive_underruns++;
1081 }
1082 } else if (tx_status & T_COLL) {
1083 if ((tx_status & T_COLL) ^ T_XCOLL) {
1084 dev->stats.collisions++;
1085 } else {
1086 lp->pktStats.excessive_collisions++;
1087 }
1088 }
1089 } else {
1090 dev->stats.tx_packets++;
1091 }
1092 }
1093 }
1094
1095 return 0;
1096}
1097
1098static int ewrk3_close(struct net_device *dev)
1099{
1100 struct ewrk3_private *lp = netdev_priv(dev);
1101 u_long iobase = dev->base_addr;
1102 u_char icr, csr;
1103
1104 netif_stop_queue(dev);
1105
1106 if (ewrk3_debug > 1) {
1107 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1108 dev->name, inb(EWRK3_CSR));
1109 }
1110
1111
1112
1113 DISABLE_IRQs;
1114
1115 STOP_EWRK3;
1116
1117
1118
1119
1120
1121
1122
1123 while (inb(EWRK3_TQ));
1124 while (inb(EWRK3_TDQ));
1125 while (inb(EWRK3_RQ));
1126
1127 if (!lp->hard_strapped) {
1128 free_irq(dev->irq, dev);
1129 }
1130 return 0;
1131}
1132
1133
1134
1135
1136static void set_multicast_list(struct net_device *dev)
1137{
1138 struct ewrk3_private *lp = netdev_priv(dev);
1139 u_long iobase = dev->base_addr;
1140 u_char csr;
1141
1142 csr = inb(EWRK3_CSR);
1143
1144 if (lp->shmem_length == IO_ONLY) {
1145 lp->mctbl = NULL;
1146 } else {
1147 lp->mctbl = lp->shmem + PAGE0_HTE;
1148 }
1149
1150 csr &= ~(CSR_PME | CSR_MCE);
1151 if (dev->flags & IFF_PROMISC) {
1152 csr |= CSR_PME;
1153 outb(csr, EWRK3_CSR);
1154 } else {
1155 SetMulticastFilter(dev);
1156 csr |= CSR_MCE;
1157 outb(csr, EWRK3_CSR);
1158 }
1159}
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169static void SetMulticastFilter(struct net_device *dev)
1170{
1171 struct ewrk3_private *lp = netdev_priv(dev);
1172 struct dev_mc_list *dmi = dev->mc_list;
1173 u_long iobase = dev->base_addr;
1174 int i;
1175 char *addrs, bit, byte;
1176 short __iomem *p = lp->mctbl;
1177 u16 hashcode;
1178 u32 crc;
1179
1180 spin_lock_irq(&lp->hw_lock);
1181
1182 if (lp->shmem_length == IO_ONLY) {
1183 outb(0, EWRK3_IOPR);
1184 outw(PAGE0_HTE, EWRK3_PIR1);
1185 } else {
1186 outb(0, EWRK3_MPR);
1187 }
1188
1189 if (dev->flags & IFF_ALLMULTI) {
1190 for (i = 0; i < (HASH_TABLE_LEN >> 3); i++) {
1191 if (lp->shmem_length == IO_ONLY) {
1192 outb(0xff, EWRK3_DATA);
1193 } else {
1194 writew(0xffff, p);
1195 p++;
1196 i++;
1197 }
1198 }
1199 } else {
1200
1201 if (lp->shmem_length == IO_ONLY) {
1202 for (i = 0; i < (HASH_TABLE_LEN >> 4) - 1; i++) {
1203 outb(0x00, EWRK3_DATA);
1204 }
1205 outb(0x80, EWRK3_DATA);
1206 i++;
1207 for (; i < (HASH_TABLE_LEN >> 3); i++) {
1208 outb(0x00, EWRK3_DATA);
1209 }
1210 } else {
1211 memset_io(lp->mctbl, 0, HASH_TABLE_LEN >> 3);
1212 writeb(0x80, lp->mctbl + (HASH_TABLE_LEN >> 4) - 1);
1213 }
1214
1215
1216 for (i = 0; i < dev->mc_count; i++) {
1217 addrs = dmi->dmi_addr;
1218 dmi = dmi->next;
1219 if ((*addrs & 0x01) == 1) {
1220 crc = ether_crc_le(ETH_ALEN, addrs);
1221 hashcode = crc & ((1 << 9) - 1);
1222
1223 byte = hashcode >> 3;
1224 bit = 1 << (hashcode & 0x07);
1225
1226 if (lp->shmem_length == IO_ONLY) {
1227 u_char tmp;
1228
1229 outw(PAGE0_HTE + byte, EWRK3_PIR1);
1230 tmp = inb(EWRK3_DATA);
1231 tmp |= bit;
1232 outw(PAGE0_HTE + byte, EWRK3_PIR1);
1233 outb(tmp, EWRK3_DATA);
1234 } else {
1235 writeb(readb(lp->mctbl + byte) | bit, lp->mctbl + byte);
1236 }
1237 }
1238 }
1239 }
1240
1241 spin_unlock_irq(&lp->hw_lock);
1242}
1243
1244
1245
1246
1247static int __init isa_probe(struct net_device *dev, u_long ioaddr)
1248{
1249 int i = num_ewrks3s, maxSlots;
1250 int ret = -ENODEV;
1251
1252 u_long iobase;
1253
1254 if (ioaddr >= 0x400)
1255 goto out;
1256
1257 if (ioaddr == 0) {
1258 iobase = EWRK3_IO_BASE;
1259 maxSlots = 24;
1260 } else {
1261 iobase = ioaddr;
1262 maxSlots = i + 1;
1263 }
1264
1265 for (; (i < maxSlots) && (dev != NULL);
1266 iobase += EWRK3_IOP_INC, i++)
1267 {
1268 if (request_region(iobase, EWRK3_TOTAL_SIZE, DRV_NAME)) {
1269 if (DevicePresent(iobase) == 0) {
1270 int irq = dev->irq;
1271 ret = ewrk3_hw_init(dev, iobase);
1272 if (!ret)
1273 break;
1274 dev->irq = irq;
1275 }
1276 release_region(iobase, EWRK3_TOTAL_SIZE);
1277 }
1278 }
1279 out:
1280
1281 return ret;
1282}
1283
1284
1285
1286
1287
1288static int __init eisa_probe(struct net_device *dev, u_long ioaddr)
1289{
1290 int i, maxSlots;
1291 u_long iobase;
1292 int ret = -ENODEV;
1293
1294 if (ioaddr < 0x1000)
1295 goto out;
1296
1297 iobase = ioaddr;
1298 i = (ioaddr >> 12);
1299 maxSlots = i + 1;
1300
1301 for (i = 1; (i < maxSlots) && (dev != NULL); i++, iobase += EISA_SLOT_INC) {
1302 if (EISA_signature(name, EISA_ID) == 0) {
1303 if (request_region(iobase, EWRK3_TOTAL_SIZE, DRV_NAME) &&
1304 DevicePresent(iobase) == 0) {
1305 int irq = dev->irq;
1306 ret = ewrk3_hw_init(dev, iobase);
1307 if (!ret)
1308 break;
1309 dev->irq = irq;
1310 }
1311 release_region(iobase, EWRK3_TOTAL_SIZE);
1312 }
1313 }
1314
1315 out:
1316 return ret;
1317}
1318
1319
1320
1321
1322
1323static int Read_EEPROM(u_long iobase, u_char eaddr)
1324{
1325 int i;
1326
1327 outb((eaddr & 0x3f), EWRK3_PIR1);
1328 outb(EEPROM_RD, EWRK3_IOPR);
1329 for (i = 0; i < 5000; i++)
1330 inb(EWRK3_CSR);
1331
1332 return inw(EWRK3_EPROM1);
1333}
1334
1335
1336
1337
1338static int Write_EEPROM(short data, u_long iobase, u_char eaddr)
1339{
1340 int i;
1341
1342 outb(EEPROM_WR_EN, EWRK3_IOPR);
1343 for (i = 0; i < 5000; i++)
1344 inb(EWRK3_CSR);
1345 outw(data, EWRK3_EPROM1);
1346 outb((eaddr & 0x3f), EWRK3_PIR1);
1347 outb(EEPROM_WR, EWRK3_IOPR);
1348 for (i = 0; i < 75000; i++)
1349 inb(EWRK3_CSR);
1350 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1351 for (i = 0; i < 5000; i++)
1352 inb(EWRK3_CSR);
1353
1354 return 0;
1355}
1356
1357
1358
1359
1360static void __init EthwrkSignature(char *name, char *eeprom_image)
1361{
1362 int i;
1363 char *signatures[] = EWRK3_SIGNATURE;
1364
1365 for (i=0; *signatures[i] != '\0'; i++)
1366 if( !strncmp(eeprom_image+EEPROM_PNAME7, signatures[i], strlen(signatures[i])) )
1367 break;
1368
1369 if (*signatures[i] != '\0') {
1370 memcpy(name, eeprom_image+EEPROM_PNAME7, EWRK3_STRLEN);
1371 name[EWRK3_STRLEN] = '\0';
1372 } else
1373 name[0] = '\0';
1374
1375 return;
1376}
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390static int __init DevicePresent(u_long iobase)
1391{
1392 union {
1393 struct {
1394 u32 a;
1395 u32 b;
1396 } llsig;
1397 char Sig[sizeof(u32) << 1];
1398 }
1399 dev;
1400 short sigLength;
1401 char data;
1402 int i, j, status = 0;
1403
1404 dev.llsig.a = ETH_PROM_SIG;
1405 dev.llsig.b = ETH_PROM_SIG;
1406 sigLength = sizeof(u32) << 1;
1407
1408 for (i = 0, j = 0; j < sigLength && i < PROBE_LENGTH + sigLength - 1; i++) {
1409 data = inb(EWRK3_APROM);
1410 if (dev.Sig[j] == data) {
1411 j++;
1412 } else {
1413 if (data == dev.Sig[0]) {
1414 j = 1;
1415 } else {
1416 j = 0;
1417 }
1418 }
1419 }
1420
1421 if (j != sigLength) {
1422 status = -ENODEV;
1423 }
1424 return status;
1425}
1426
1427static u_char __init get_hw_addr(struct net_device *dev, u_char * eeprom_image, char chipType)
1428{
1429 int i, j, k;
1430 u_short chksum;
1431 u_char crc, lfsr, sd, status = 0;
1432 u_long iobase = dev->base_addr;
1433 u16 tmp;
1434
1435 if (chipType == LeMAC2) {
1436 for (crc = 0x6a, j = 0; j < ETH_ALEN; j++) {
1437 sd = dev->dev_addr[j] = eeprom_image[EEPROM_PADDR0 + j];
1438 outb(dev->dev_addr[j], EWRK3_PAR0 + j);
1439 for (k = 0; k < 8; k++, sd >>= 1) {
1440 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1441 crc = (crc >> 1) + lfsr;
1442 }
1443 }
1444 if (crc != eeprom_image[EEPROM_PA_CRC])
1445 status = -1;
1446 } else {
1447 for (i = 0, k = 0; i < ETH_ALEN;) {
1448 k <<= 1;
1449 if (k > 0xffff)
1450 k -= 0xffff;
1451
1452 k += (u_char) (tmp = inb(EWRK3_APROM));
1453 dev->dev_addr[i] = (u_char) tmp;
1454 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1455 i++;
1456 k += (u_short) ((tmp = inb(EWRK3_APROM)) << 8);
1457 dev->dev_addr[i] = (u_char) tmp;
1458 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1459 i++;
1460
1461 if (k > 0xffff)
1462 k -= 0xffff;
1463 }
1464 if (k == 0xffff)
1465 k = 0;
1466 chksum = inb(EWRK3_APROM);
1467 chksum |= (inb(EWRK3_APROM) << 8);
1468 if (k != chksum)
1469 status = -1;
1470 }
1471
1472 return status;
1473}
1474
1475
1476
1477
1478static int __init EISA_signature(char *name, s32 eisa_id)
1479{
1480 u_long i;
1481 char *signatures[] = EWRK3_SIGNATURE;
1482 char ManCode[EWRK3_STRLEN];
1483 union {
1484 s32 ID;
1485 char Id[4];
1486 } Eisa;
1487 int status = 0;
1488
1489 *name = '\0';
1490 for (i = 0; i < 4; i++) {
1491 Eisa.Id[i] = inb(eisa_id + i);
1492 }
1493
1494 ManCode[0] = (((Eisa.Id[0] >> 2) & 0x1f) + 0x40);
1495 ManCode[1] = (((Eisa.Id[1] & 0xe0) >> 5) + ((Eisa.Id[0] & 0x03) << 3) + 0x40);
1496 ManCode[2] = (((Eisa.Id[2] >> 4) & 0x0f) + 0x30);
1497 ManCode[3] = ((Eisa.Id[2] & 0x0f) + 0x30);
1498 ManCode[4] = (((Eisa.Id[3] >> 4) & 0x0f) + 0x30);
1499 ManCode[5] = '\0';
1500
1501 for (i = 0; (*signatures[i] != '\0') && (*name == '\0'); i++) {
1502 if (strstr(ManCode, signatures[i]) != NULL) {
1503 strcpy(name, ManCode);
1504 status = 1;
1505 }
1506 }
1507
1508 return status;
1509}
1510
1511static void ewrk3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1512{
1513 int fwrev = Read_EEPROM(dev->base_addr, EEPROM_REVLVL);
1514
1515 strcpy(info->driver, DRV_NAME);
1516 strcpy(info->version, DRV_VERSION);
1517 sprintf(info->fw_version, "%d", fwrev);
1518 strcpy(info->bus_info, "N/A");
1519 info->eedump_len = EEPROM_MAX;
1520}
1521
1522static int ewrk3_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1523{
1524 struct ewrk3_private *lp = netdev_priv(dev);
1525 unsigned long iobase = dev->base_addr;
1526 u8 cr = inb(EWRK3_CR);
1527
1528 switch (lp->adapter_name[4]) {
1529 case '3':
1530 ecmd->supported = SUPPORTED_BNC;
1531 ecmd->port = PORT_BNC;
1532 break;
1533
1534 case '4':
1535 ecmd->supported = SUPPORTED_TP;
1536 ecmd->port = PORT_TP;
1537 break;
1538
1539 case '5':
1540 ecmd->supported = SUPPORTED_TP | SUPPORTED_BNC | SUPPORTED_AUI;
1541 ecmd->autoneg = !(cr & CR_APD);
1542
1543
1544
1545
1546 if (!ecmd->autoneg)
1547 ecmd->port = (cr & CR_PSEL) ? PORT_BNC : PORT_TP;
1548 break;
1549 }
1550
1551 ecmd->supported |= SUPPORTED_10baseT_Half;
1552 ecmd->speed = SPEED_10;
1553 ecmd->duplex = DUPLEX_HALF;
1554 return 0;
1555}
1556
1557static int ewrk3_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1558{
1559 struct ewrk3_private *lp = netdev_priv(dev);
1560 unsigned long iobase = dev->base_addr;
1561 unsigned long flags;
1562 u8 cr;
1563
1564
1565 if (lp->adapter_name[4] != '5')
1566 return -EOPNOTSUPP;
1567
1568
1569 if (ecmd->speed != SPEED_10)
1570 return -EINVAL;
1571 if (ecmd->port != PORT_TP && ecmd->port != PORT_BNC)
1572 return -EINVAL;
1573 if (ecmd->transceiver != XCVR_INTERNAL)
1574 return -EINVAL;
1575 if (ecmd->duplex != DUPLEX_HALF)
1576 return -EINVAL;
1577 if (ecmd->phy_address != 0)
1578 return -EINVAL;
1579
1580 spin_lock_irqsave(&lp->hw_lock, flags);
1581 cr = inb(EWRK3_CR);
1582
1583
1584
1585 if (ecmd->autoneg) {
1586 cr &= ~CR_APD;
1587 } else {
1588 cr |= CR_APD;
1589 if (ecmd->port == PORT_TP)
1590 cr &= ~CR_PSEL;
1591 else
1592 cr |= CR_PSEL;
1593 }
1594
1595
1596 outb(cr, EWRK3_CR);
1597 spin_unlock_irqrestore(&lp->hw_lock, flags);
1598 return 0;
1599}
1600
1601static u32 ewrk3_get_link(struct net_device *dev)
1602{
1603 unsigned long iobase = dev->base_addr;
1604 u8 cmr = inb(EWRK3_CMR);
1605
1606
1607
1608 return !(cmr & CMR_LINK);
1609}
1610
1611static int ewrk3_phys_id(struct net_device *dev, u32 data)
1612{
1613 struct ewrk3_private *lp = netdev_priv(dev);
1614 unsigned long iobase = dev->base_addr;
1615 unsigned long flags;
1616 u8 cr;
1617 int count;
1618
1619
1620 count = data << 2;
1621
1622 spin_lock_irqsave(&lp->hw_lock, flags);
1623
1624
1625 if (lp->led_mask == 0) {
1626 spin_unlock_irqrestore(&lp->hw_lock, flags);
1627 return -EBUSY;
1628 }
1629
1630
1631 lp->led_mask = 0;
1632
1633 while (count--) {
1634
1635 cr = inb(EWRK3_CR);
1636 outb(cr ^ CR_LED, EWRK3_CR);
1637
1638
1639 spin_unlock_irqrestore(&lp->hw_lock, flags);
1640 msleep(250);
1641 spin_lock_irqsave(&lp->hw_lock, flags);
1642
1643
1644 if (signal_pending(current))
1645 break;
1646 }
1647
1648 lp->led_mask = CR_LED;
1649 cr = inb(EWRK3_CR);
1650 outb(cr & ~CR_LED, EWRK3_CR);
1651 spin_unlock_irqrestore(&lp->hw_lock, flags);
1652 return signal_pending(current) ? -ERESTARTSYS : 0;
1653}
1654
1655static const struct ethtool_ops ethtool_ops_203 = {
1656 .get_drvinfo = ewrk3_get_drvinfo,
1657 .get_settings = ewrk3_get_settings,
1658 .set_settings = ewrk3_set_settings,
1659 .phys_id = ewrk3_phys_id,
1660};
1661
1662static const struct ethtool_ops ethtool_ops = {
1663 .get_drvinfo = ewrk3_get_drvinfo,
1664 .get_settings = ewrk3_get_settings,
1665 .set_settings = ewrk3_set_settings,
1666 .get_link = ewrk3_get_link,
1667 .phys_id = ewrk3_phys_id,
1668};
1669
1670
1671
1672
1673
1674static int ewrk3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1675{
1676 struct ewrk3_private *lp = netdev_priv(dev);
1677 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_ifru;
1678 u_long iobase = dev->base_addr;
1679 int i, j, status = 0;
1680 u_char csr;
1681 unsigned long flags;
1682 union ewrk3_addr {
1683 u_char addr[HASH_TABLE_LEN * ETH_ALEN];
1684 u_short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1685 };
1686
1687 union ewrk3_addr *tmp;
1688
1689
1690 if (cmd != EWRK3IOCTL)
1691 return -EOPNOTSUPP;
1692
1693 tmp = kmalloc(sizeof(union ewrk3_addr), GFP_KERNEL);
1694 if(tmp==NULL)
1695 return -ENOMEM;
1696
1697 switch (ioc->cmd) {
1698 case EWRK3_GET_HWADDR:
1699 for (i = 0; i < ETH_ALEN; i++) {
1700 tmp->addr[i] = dev->dev_addr[i];
1701 }
1702 ioc->len = ETH_ALEN;
1703 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1704 status = -EFAULT;
1705 break;
1706
1707 case EWRK3_SET_HWADDR:
1708 if (capable(CAP_NET_ADMIN)) {
1709 spin_lock_irqsave(&lp->hw_lock, flags);
1710 csr = inb(EWRK3_CSR);
1711 csr |= (CSR_TXD | CSR_RXD);
1712 outb(csr, EWRK3_CSR);
1713 spin_unlock_irqrestore(&lp->hw_lock, flags);
1714
1715 if (copy_from_user(tmp->addr, ioc->data, ETH_ALEN)) {
1716 status = -EFAULT;
1717 break;
1718 }
1719 spin_lock_irqsave(&lp->hw_lock, flags);
1720 for (i = 0; i < ETH_ALEN; i++) {
1721 dev->dev_addr[i] = tmp->addr[i];
1722 outb(tmp->addr[i], EWRK3_PAR0 + i);
1723 }
1724
1725 csr = inb(EWRK3_CSR);
1726 csr &= ~(CSR_TXD | CSR_RXD);
1727 outb(csr, EWRK3_CSR);
1728 spin_unlock_irqrestore(&lp->hw_lock, flags);
1729 } else {
1730 status = -EPERM;
1731 }
1732
1733 break;
1734 case EWRK3_SET_PROM:
1735 if (capable(CAP_NET_ADMIN)) {
1736 spin_lock_irqsave(&lp->hw_lock, flags);
1737 csr = inb(EWRK3_CSR);
1738 csr |= CSR_PME;
1739 csr &= ~CSR_MCE;
1740 outb(csr, EWRK3_CSR);
1741 spin_unlock_irqrestore(&lp->hw_lock, flags);
1742 } else {
1743 status = -EPERM;
1744 }
1745
1746 break;
1747 case EWRK3_CLR_PROM:
1748 if (capable(CAP_NET_ADMIN)) {
1749 spin_lock_irqsave(&lp->hw_lock, flags);
1750 csr = inb(EWRK3_CSR);
1751 csr &= ~CSR_PME;
1752 outb(csr, EWRK3_CSR);
1753 spin_unlock_irqrestore(&lp->hw_lock, flags);
1754 } else {
1755 status = -EPERM;
1756 }
1757
1758 break;
1759 case EWRK3_GET_MCA:
1760 spin_lock_irqsave(&lp->hw_lock, flags);
1761 if (lp->shmem_length == IO_ONLY) {
1762 outb(0, EWRK3_IOPR);
1763 outw(PAGE0_HTE, EWRK3_PIR1);
1764 for (i = 0; i < (HASH_TABLE_LEN >> 3); i++) {
1765 tmp->addr[i] = inb(EWRK3_DATA);
1766 }
1767 } else {
1768 outb(0, EWRK3_MPR);
1769 memcpy_fromio(tmp->addr, lp->shmem + PAGE0_HTE, (HASH_TABLE_LEN >> 3));
1770 }
1771 spin_unlock_irqrestore(&lp->hw_lock, flags);
1772
1773 ioc->len = (HASH_TABLE_LEN >> 3);
1774 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1775 status = -EFAULT;
1776
1777 break;
1778 case EWRK3_SET_MCA:
1779 if (capable(CAP_NET_ADMIN)) {
1780 if (ioc->len > 1024)
1781 {
1782 status = -EINVAL;
1783 break;
1784 }
1785 if (copy_from_user(tmp->addr, ioc->data, ETH_ALEN * ioc->len)) {
1786 status = -EFAULT;
1787 break;
1788 }
1789 set_multicast_list(dev);
1790 } else {
1791 status = -EPERM;
1792 }
1793
1794 break;
1795 case EWRK3_CLR_MCA:
1796 if (capable(CAP_NET_ADMIN)) {
1797 set_multicast_list(dev);
1798 } else {
1799 status = -EPERM;
1800 }
1801
1802 break;
1803 case EWRK3_MCA_EN:
1804 if (capable(CAP_NET_ADMIN)) {
1805 spin_lock_irqsave(&lp->hw_lock, flags);
1806 csr = inb(EWRK3_CSR);
1807 csr |= CSR_MCE;
1808 csr &= ~CSR_PME;
1809 outb(csr, EWRK3_CSR);
1810 spin_unlock_irqrestore(&lp->hw_lock, flags);
1811 } else {
1812 status = -EPERM;
1813 }
1814
1815 break;
1816 case EWRK3_GET_STATS: {
1817 struct ewrk3_stats *tmp_stats =
1818 kmalloc(sizeof(lp->pktStats), GFP_KERNEL);
1819 if (!tmp_stats) {
1820 status = -ENOMEM;
1821 break;
1822 }
1823
1824 spin_lock_irqsave(&lp->hw_lock, flags);
1825 memcpy(tmp_stats, &lp->pktStats, sizeof(lp->pktStats));
1826 spin_unlock_irqrestore(&lp->hw_lock, flags);
1827
1828 ioc->len = sizeof(lp->pktStats);
1829 if (copy_to_user(ioc->data, tmp_stats, sizeof(lp->pktStats)))
1830 status = -EFAULT;
1831 kfree(tmp_stats);
1832 break;
1833 }
1834 case EWRK3_CLR_STATS:
1835 if (capable(CAP_NET_ADMIN)) {
1836 spin_lock_irqsave(&lp->hw_lock, flags);
1837 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1838 spin_unlock_irqrestore(&lp->hw_lock,flags);
1839 } else {
1840 status = -EPERM;
1841 }
1842
1843 break;
1844 case EWRK3_GET_CSR:
1845 tmp->addr[0] = inb(EWRK3_CSR);
1846 ioc->len = 1;
1847 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1848 status = -EFAULT;
1849 break;
1850 case EWRK3_SET_CSR:
1851 if (capable(CAP_NET_ADMIN)) {
1852 if (copy_from_user(tmp->addr, ioc->data, 1)) {
1853 status = -EFAULT;
1854 break;
1855 }
1856 outb(tmp->addr[0], EWRK3_CSR);
1857 } else {
1858 status = -EPERM;
1859 }
1860
1861 break;
1862 case EWRK3_GET_EEPROM:
1863 if (capable(CAP_NET_ADMIN)) {
1864 for (i = 0; i < (EEPROM_MAX >> 1); i++) {
1865 tmp->val[i] = (short) Read_EEPROM(iobase, i);
1866 }
1867 i = EEPROM_MAX;
1868 tmp->addr[i++] = inb(EWRK3_CMR);
1869 for (j = 0; j < ETH_ALEN; j++) {
1870 tmp->addr[i++] = inb(EWRK3_PAR0 + j);
1871 }
1872 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1873 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1874 status = -EFAULT;
1875 } else {
1876 status = -EPERM;
1877 }
1878
1879 break;
1880 case EWRK3_SET_EEPROM:
1881 if (capable(CAP_NET_ADMIN)) {
1882 if (copy_from_user(tmp->addr, ioc->data, EEPROM_MAX)) {
1883 status = -EFAULT;
1884 break;
1885 }
1886 for (i = 0; i < (EEPROM_MAX >> 1); i++) {
1887 Write_EEPROM(tmp->val[i], iobase, i);
1888 }
1889 } else {
1890 status = -EPERM;
1891 }
1892
1893 break;
1894 case EWRK3_GET_CMR:
1895 tmp->addr[0] = inb(EWRK3_CMR);
1896 ioc->len = 1;
1897 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1898 status = -EFAULT;
1899 break;
1900 case EWRK3_SET_TX_CUT_THRU:
1901 if (capable(CAP_NET_ADMIN)) {
1902 lp->txc = 1;
1903 } else {
1904 status = -EPERM;
1905 }
1906
1907 break;
1908 case EWRK3_CLR_TX_CUT_THRU:
1909 if (capable(CAP_NET_ADMIN)) {
1910 lp->txc = 0;
1911 } else {
1912 status = -EPERM;
1913 }
1914
1915 break;
1916 default:
1917 status = -EOPNOTSUPP;
1918 }
1919 kfree(tmp);
1920 return status;
1921}
1922
1923#ifdef MODULE
1924static struct net_device *ewrk3_devs[MAX_NUM_EWRK3S];
1925static int ndevs;
1926static int io[MAX_NUM_EWRK3S+1] = { 0x300, 0, };
1927
1928
1929module_param_array(io, int, NULL, 0);
1930module_param_array(irq, int, NULL, 0);
1931MODULE_PARM_DESC(io, "EtherWORKS 3 I/O base address(es)");
1932MODULE_PARM_DESC(irq, "EtherWORKS 3 IRQ number(s)");
1933
1934static __exit void ewrk3_exit_module(void)
1935{
1936 int i;
1937
1938 for( i=0; i<ndevs; i++ ) {
1939 struct net_device *dev = ewrk3_devs[i];
1940 struct ewrk3_private *lp = netdev_priv(dev);
1941 ewrk3_devs[i] = NULL;
1942 unregister_netdev(dev);
1943 release_region(dev->base_addr, EWRK3_TOTAL_SIZE);
1944 iounmap(lp->shmem);
1945 free_netdev(dev);
1946 }
1947}
1948
1949static __init int ewrk3_init_module(void)
1950{
1951 int i=0;
1952
1953 while( io[i] && irq[i] ) {
1954 struct net_device *dev
1955 = alloc_etherdev(sizeof(struct ewrk3_private));
1956
1957 if (!dev)
1958 break;
1959
1960 if (ewrk3_probe1(dev, io[i], irq[i]) != 0) {
1961 free_netdev(dev);
1962 break;
1963 }
1964
1965 ewrk3_devs[ndevs++] = dev;
1966 i++;
1967 }
1968
1969 return ndevs ? 0 : -EIO;
1970}
1971
1972
1973
1974module_exit(ewrk3_exit_module);
1975module_init(ewrk3_init_module);
1976#endif
1977MODULE_LICENSE("GPL");
1978