1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2009 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#ifndef _E1000_82575_H_ 29#define _E1000_82575_H_ 30 31extern void igb_shutdown_serdes_link_82575(struct e1000_hw *hw); 32extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); 33 34#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ 35 (ID_LED_DEF1_DEF2 << 8) | \ 36 (ID_LED_DEF1_DEF2 << 4) | \ 37 (ID_LED_OFF1_ON2)) 38 39#define E1000_RAR_ENTRIES_82575 16 40#define E1000_RAR_ENTRIES_82576 24 41 42/* SRRCTL bit definitions */ 43#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 44#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 45#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 46#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 47#define E1000_SRRCTL_DROP_EN 0x80000000 48 49#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 50#define E1000_MRQC_ENABLE_VMDQ 0x00000003 51#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 52#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 53#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 54#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 55 56#define E1000_EICR_TX_QUEUE ( \ 57 E1000_EICR_TX_QUEUE0 | \ 58 E1000_EICR_TX_QUEUE1 | \ 59 E1000_EICR_TX_QUEUE2 | \ 60 E1000_EICR_TX_QUEUE3) 61 62#define E1000_EICR_RX_QUEUE ( \ 63 E1000_EICR_RX_QUEUE0 | \ 64 E1000_EICR_RX_QUEUE1 | \ 65 E1000_EICR_RX_QUEUE2 | \ 66 E1000_EICR_RX_QUEUE3) 67 68/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 69 70/* Receive Descriptor - Advanced */ 71union e1000_adv_rx_desc { 72 struct { 73 __le64 pkt_addr; /* Packet buffer address */ 74 __le64 hdr_addr; /* Header buffer address */ 75 } read; 76 struct { 77 struct { 78 struct { 79 __le16 pkt_info; /* RSS type, Packet type */ 80 __le16 hdr_info; /* Split Header, 81 * header buffer length */ 82 } lo_dword; 83 union { 84 __le32 rss; /* RSS Hash */ 85 struct { 86 __le16 ip_id; /* IP id */ 87 __le16 csum; /* Packet Checksum */ 88 } csum_ip; 89 } hi_dword; 90 } lower; 91 struct { 92 __le32 status_error; /* ext status/error */ 93 __le16 length; /* Packet length */ 94 __le16 vlan; /* VLAN tag */ 95 } upper; 96 } wb; /* writeback */ 97}; 98 99#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 100#define E1000_RXDADV_HDRBUFLEN_SHIFT 5 101 102/* Transmit Descriptor - Advanced */ 103union e1000_adv_tx_desc { 104 struct { 105 __le64 buffer_addr; /* Address of descriptor's data buf */ 106 __le32 cmd_type_len; 107 __le32 olinfo_status; 108 } read; 109 struct { 110 __le64 rsvd; /* Reserved */ 111 __le32 nxtseq_seed; 112 __le32 status; 113 } wb; 114}; 115 116/* Adv Transmit Descriptor Config Masks */ 117#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ 118#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 119#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 120#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 121#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 122#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 123#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 124#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 125 126/* Context descriptors */ 127struct e1000_adv_tx_context_desc { 128 __le32 vlan_macip_lens; 129 __le32 seqnum_seed; 130 __le32 type_tucmd_mlhl; 131 __le32 mss_l4len_idx; 132}; 133 134#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 135#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 136#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 137#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */ 138/* IPSec Encrypt Enable for ESP */ 139#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 140#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 141/* Adv ctxt IPSec SA IDX mask */ 142/* Adv ctxt IPSec ESP len mask */ 143 144/* Additional Transmit Descriptor Control definitions */ 145#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 146/* Tx Queue Arbitration Priority 0=low, 1=high */ 147 148/* Additional Receive Descriptor Control definitions */ 149#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 150 151/* Direct Cache Access (DCA) definitions */ 152#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */ 153#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 154 155#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 156#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 157#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 158#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 159 160#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 161#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 162#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 163 164/* Additional DCA related definitions, note change in position of CPUID */ 165#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 166#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 167#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */ 168#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */ 169 170#define MAX_NUM_VFS 8 171 172#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ 173 174/* Easy defines for setting default pool, would normally be left a zero */ 175#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 176#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 177 178/* Other useful VMD_CTL register defines */ 179#define E1000_VT_CTL_IGNORE_MAC (1 << 28) 180#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) 181#define E1000_VT_CTL_VM_REPL_EN (1 << 30) 182 183/* Per VM Offload register setup */ 184#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 185#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 186#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 187#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 188#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 189#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 190#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 191#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 192#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 193#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 194 195#define E1000_VLVF_ARRAY_SIZE 32 196#define E1000_VLVF_VLANID_MASK 0x00000FFF 197#define E1000_VLVF_POOLSEL_SHIFT 12 198#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 199#define E1000_VLVF_LVLAN 0x00100000 200#define E1000_VLVF_VLANID_ENABLE 0x80000000 201 202#define E1000_IOVCTL 0x05BBC 203#define E1000_IOVCTL_REUSE_VFQ 0x00000001 204 205#define ALL_QUEUES 0xFFFF 206 207void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool); 208void igb_vmdq_set_replication_pf(struct e1000_hw *, bool); 209 210#endif 211