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26
27
28#include <linux/if_ether.h>
29#include <linux/delay.h>
30
31#include "e1000_mac.h"
32#include "e1000_phy.h"
33
34static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
35static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
36 u16 *phy_ctrl);
37static s32 igb_wait_autoneg(struct e1000_hw *hw);
38
39
40static const u16 e1000_m88_cable_length_table[] =
41 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
42
43static const u16 e1000_igp_2_cable_length_table[] =
44 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
45 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
46 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
47 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
48 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
49 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
50 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
51 104, 109, 114, 118, 121, 124};
52#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
53 (sizeof(e1000_igp_2_cable_length_table) / \
54 sizeof(e1000_igp_2_cable_length_table[0]))
55
56
57
58
59
60
61
62
63
64s32 igb_check_reset_block(struct e1000_hw *hw)
65{
66 u32 manc;
67
68 manc = rd32(E1000_MANC);
69
70 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
71 E1000_BLK_PHY_RESET : 0;
72}
73
74
75
76
77
78
79
80
81s32 igb_get_phy_id(struct e1000_hw *hw)
82{
83 struct e1000_phy_info *phy = &hw->phy;
84 s32 ret_val = 0;
85 u16 phy_id;
86
87 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
88 if (ret_val)
89 goto out;
90
91 phy->id = (u32)(phy_id << 16);
92 udelay(20);
93 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
94 if (ret_val)
95 goto out;
96
97 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
98 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
99
100out:
101 return ret_val;
102}
103
104
105
106
107
108
109
110static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
111{
112 s32 ret_val;
113
114 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
115 if (ret_val)
116 goto out;
117
118 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
119
120out:
121 return ret_val;
122}
123
124
125
126
127
128
129
130
131
132
133static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
134{
135 struct e1000_phy_info *phy = &hw->phy;
136 u32 i, mdic = 0;
137 s32 ret_val = 0;
138
139 if (offset > MAX_PHY_REG_ADDRESS) {
140 hw_dbg("PHY Address %d is out of range\n", offset);
141 ret_val = -E1000_ERR_PARAM;
142 goto out;
143 }
144
145
146
147
148
149
150 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
151 (phy->addr << E1000_MDIC_PHY_SHIFT) |
152 (E1000_MDIC_OP_READ));
153
154 wr32(E1000_MDIC, mdic);
155
156
157
158
159
160
161 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
162 udelay(50);
163 mdic = rd32(E1000_MDIC);
164 if (mdic & E1000_MDIC_READY)
165 break;
166 }
167 if (!(mdic & E1000_MDIC_READY)) {
168 hw_dbg("MDI Read did not complete\n");
169 ret_val = -E1000_ERR_PHY;
170 goto out;
171 }
172 if (mdic & E1000_MDIC_ERROR) {
173 hw_dbg("MDI Error\n");
174 ret_val = -E1000_ERR_PHY;
175 goto out;
176 }
177 *data = (u16) mdic;
178
179out:
180 return ret_val;
181}
182
183
184
185
186
187
188
189
190
191static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
192{
193 struct e1000_phy_info *phy = &hw->phy;
194 u32 i, mdic = 0;
195 s32 ret_val = 0;
196
197 if (offset > MAX_PHY_REG_ADDRESS) {
198 hw_dbg("PHY Address %d is out of range\n", offset);
199 ret_val = -E1000_ERR_PARAM;
200 goto out;
201 }
202
203
204
205
206
207
208 mdic = (((u32)data) |
209 (offset << E1000_MDIC_REG_SHIFT) |
210 (phy->addr << E1000_MDIC_PHY_SHIFT) |
211 (E1000_MDIC_OP_WRITE));
212
213 wr32(E1000_MDIC, mdic);
214
215
216
217
218
219
220 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
221 udelay(50);
222 mdic = rd32(E1000_MDIC);
223 if (mdic & E1000_MDIC_READY)
224 break;
225 }
226 if (!(mdic & E1000_MDIC_READY)) {
227 hw_dbg("MDI Write did not complete\n");
228 ret_val = -E1000_ERR_PHY;
229 goto out;
230 }
231 if (mdic & E1000_MDIC_ERROR) {
232 hw_dbg("MDI Error\n");
233 ret_val = -E1000_ERR_PHY;
234 goto out;
235 }
236
237out:
238 return ret_val;
239}
240
241
242
243
244
245
246
247
248
249
250
251s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
252{
253 s32 ret_val = 0;
254
255 if (!(hw->phy.ops.acquire))
256 goto out;
257
258 ret_val = hw->phy.ops.acquire(hw);
259 if (ret_val)
260 goto out;
261
262 if (offset > MAX_PHY_MULTI_PAGE_REG) {
263 ret_val = igb_write_phy_reg_mdic(hw,
264 IGP01E1000_PHY_PAGE_SELECT,
265 (u16)offset);
266 if (ret_val) {
267 hw->phy.ops.release(hw);
268 goto out;
269 }
270 }
271
272 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
273 data);
274
275 hw->phy.ops.release(hw);
276
277out:
278 return ret_val;
279}
280
281
282
283
284
285
286
287
288
289
290s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
291{
292 s32 ret_val = 0;
293
294 if (!(hw->phy.ops.acquire))
295 goto out;
296
297 ret_val = hw->phy.ops.acquire(hw);
298 if (ret_val)
299 goto out;
300
301 if (offset > MAX_PHY_MULTI_PAGE_REG) {
302 ret_val = igb_write_phy_reg_mdic(hw,
303 IGP01E1000_PHY_PAGE_SELECT,
304 (u16)offset);
305 if (ret_val) {
306 hw->phy.ops.release(hw);
307 goto out;
308 }
309 }
310
311 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
312 data);
313
314 hw->phy.ops.release(hw);
315
316out:
317 return ret_val;
318}
319
320
321
322
323
324
325
326
327s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
328{
329 struct e1000_phy_info *phy = &hw->phy;
330 s32 ret_val;
331 u16 phy_data;
332
333 if (phy->reset_disable) {
334 ret_val = 0;
335 goto out;
336 }
337
338
339 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
340 if (ret_val)
341 goto out;
342
343 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
344
345
346
347
348
349
350
351
352
353 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
354
355 switch (phy->mdix) {
356 case 1:
357 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
358 break;
359 case 2:
360 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
361 break;
362 case 3:
363 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
364 break;
365 case 0:
366 default:
367 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
368 break;
369 }
370
371
372
373
374
375
376
377
378 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
379 if (phy->disable_polarity_correction == 1)
380 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
381
382 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
383 if (ret_val)
384 goto out;
385
386 if (phy->revision < E1000_REVISION_4) {
387
388
389
390
391 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
392 &phy_data);
393 if (ret_val)
394 goto out;
395
396 phy_data |= M88E1000_EPSCR_TX_CLK_25;
397
398 if ((phy->revision == E1000_REVISION_2) &&
399 (phy->id == M88E1111_I_PHY_ID)) {
400
401 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
402 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
403 } else {
404
405 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
406 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
407 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
408 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
409 }
410 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
411 phy_data);
412 if (ret_val)
413 goto out;
414 }
415
416
417 ret_val = igb_phy_sw_reset(hw);
418 if (ret_val) {
419 hw_dbg("Error committing the PHY changes\n");
420 goto out;
421 }
422
423out:
424 return ret_val;
425}
426
427
428
429
430
431
432
433
434s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
435{
436 struct e1000_phy_info *phy = &hw->phy;
437 s32 ret_val;
438 u16 data;
439
440 if (phy->reset_disable) {
441 ret_val = 0;
442 goto out;
443 }
444
445 ret_val = phy->ops.reset(hw);
446 if (ret_val) {
447 hw_dbg("Error resetting the PHY.\n");
448 goto out;
449 }
450
451
452
453
454
455 msleep(100);
456
457
458
459
460
461 if (phy->type == e1000_phy_igp) {
462
463 if (phy->ops.set_d3_lplu_state)
464 ret_val = phy->ops.set_d3_lplu_state(hw, false);
465 if (ret_val) {
466 hw_dbg("Error Disabling LPLU D3\n");
467 goto out;
468 }
469 }
470
471
472 ret_val = phy->ops.set_d0_lplu_state(hw, false);
473 if (ret_val) {
474 hw_dbg("Error Disabling LPLU D0\n");
475 goto out;
476 }
477
478 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
479 if (ret_val)
480 goto out;
481
482 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
483
484 switch (phy->mdix) {
485 case 1:
486 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
487 break;
488 case 2:
489 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
490 break;
491 case 0:
492 default:
493 data |= IGP01E1000_PSCR_AUTO_MDIX;
494 break;
495 }
496 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
497 if (ret_val)
498 goto out;
499
500
501 if (hw->mac.autoneg) {
502
503
504
505
506
507 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
508
509 ret_val = phy->ops.read_reg(hw,
510 IGP01E1000_PHY_PORT_CONFIG,
511 &data);
512 if (ret_val)
513 goto out;
514
515 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
516 ret_val = phy->ops.write_reg(hw,
517 IGP01E1000_PHY_PORT_CONFIG,
518 data);
519 if (ret_val)
520 goto out;
521
522
523 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
524 if (ret_val)
525 goto out;
526
527 data &= ~CR_1000T_MS_ENABLE;
528 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
529 if (ret_val)
530 goto out;
531 }
532
533 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
534 if (ret_val)
535 goto out;
536
537
538 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
539 ((data & CR_1000T_MS_VALUE) ?
540 e1000_ms_force_master :
541 e1000_ms_force_slave) :
542 e1000_ms_auto;
543
544 switch (phy->ms_type) {
545 case e1000_ms_force_master:
546 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
547 break;
548 case e1000_ms_force_slave:
549 data |= CR_1000T_MS_ENABLE;
550 data &= ~(CR_1000T_MS_VALUE);
551 break;
552 case e1000_ms_auto:
553 data &= ~CR_1000T_MS_ENABLE;
554 default:
555 break;
556 }
557 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
558 if (ret_val)
559 goto out;
560 }
561
562out:
563 return ret_val;
564}
565
566
567
568
569
570
571
572
573
574
575s32 igb_copper_link_autoneg(struct e1000_hw *hw)
576{
577 struct e1000_phy_info *phy = &hw->phy;
578 s32 ret_val;
579 u16 phy_ctrl;
580
581
582
583
584
585 phy->autoneg_advertised &= phy->autoneg_mask;
586
587
588
589
590
591 if (phy->autoneg_advertised == 0)
592 phy->autoneg_advertised = phy->autoneg_mask;
593
594 hw_dbg("Reconfiguring auto-neg advertisement params\n");
595 ret_val = igb_phy_setup_autoneg(hw);
596 if (ret_val) {
597 hw_dbg("Error Setting up Auto-Negotiation\n");
598 goto out;
599 }
600 hw_dbg("Restarting Auto-Neg\n");
601
602
603
604
605
606 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
607 if (ret_val)
608 goto out;
609
610 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
611 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
612 if (ret_val)
613 goto out;
614
615
616
617
618
619 if (phy->autoneg_wait_to_complete) {
620 ret_val = igb_wait_autoneg(hw);
621 if (ret_val) {
622 hw_dbg("Error while waiting for "
623 "autoneg to complete\n");
624 goto out;
625 }
626 }
627
628 hw->mac.get_link_status = true;
629
630out:
631 return ret_val;
632}
633
634
635
636
637
638
639
640
641
642
643static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
644{
645 struct e1000_phy_info *phy = &hw->phy;
646 s32 ret_val;
647 u16 mii_autoneg_adv_reg;
648 u16 mii_1000t_ctrl_reg = 0;
649
650 phy->autoneg_advertised &= phy->autoneg_mask;
651
652
653 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
654 if (ret_val)
655 goto out;
656
657 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
658
659 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
660 &mii_1000t_ctrl_reg);
661 if (ret_val)
662 goto out;
663 }
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
679 NWAY_AR_100TX_HD_CAPS |
680 NWAY_AR_10T_FD_CAPS |
681 NWAY_AR_10T_HD_CAPS);
682 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
683
684 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
685
686
687 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
688 hw_dbg("Advertise 10mb Half duplex\n");
689 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
690 }
691
692
693 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
694 hw_dbg("Advertise 10mb Full duplex\n");
695 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
696 }
697
698
699 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
700 hw_dbg("Advertise 100mb Half duplex\n");
701 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
702 }
703
704
705 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
706 hw_dbg("Advertise 100mb Full duplex\n");
707 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
708 }
709
710
711 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
712 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
713
714
715 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
716 hw_dbg("Advertise 1000mb Full duplex\n");
717 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
718 }
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738 switch (hw->fc.current_mode) {
739 case e1000_fc_none:
740
741
742
743
744 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
745 break;
746 case e1000_fc_rx_pause:
747
748
749
750
751
752
753
754
755
756
757 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
758 break;
759 case e1000_fc_tx_pause:
760
761
762
763
764 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
765 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
766 break;
767 case e1000_fc_full:
768
769
770
771
772 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
773 break;
774 default:
775 hw_dbg("Flow control param set incorrectly\n");
776 ret_val = -E1000_ERR_CONFIG;
777 goto out;
778 }
779
780 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
781 if (ret_val)
782 goto out;
783
784 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
785
786 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
787 ret_val = phy->ops.write_reg(hw,
788 PHY_1000T_CTRL,
789 mii_1000t_ctrl_reg);
790 if (ret_val)
791 goto out;
792 }
793
794out:
795 return ret_val;
796}
797
798
799
800
801
802
803
804
805
806s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
807{
808 struct e1000_phy_info *phy = &hw->phy;
809 s32 ret_val;
810 u16 phy_data;
811 bool link;
812
813 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
814 if (ret_val)
815 goto out;
816
817 igb_phy_force_speed_duplex_setup(hw, &phy_data);
818
819 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
820 if (ret_val)
821 goto out;
822
823
824
825
826
827 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
828 if (ret_val)
829 goto out;
830
831 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
832 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
833
834 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
835 if (ret_val)
836 goto out;
837
838 hw_dbg("IGP PSCR: %X\n", phy_data);
839
840 udelay(1);
841
842 if (phy->autoneg_wait_to_complete) {
843 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
844
845 ret_val = igb_phy_has_link(hw,
846 PHY_FORCE_LIMIT,
847 100000,
848 &link);
849 if (ret_val)
850 goto out;
851
852 if (!link)
853 hw_dbg("Link taking longer than expected.\n");
854
855
856 ret_val = igb_phy_has_link(hw,
857 PHY_FORCE_LIMIT,
858 100000,
859 &link);
860 if (ret_val)
861 goto out;
862 }
863
864out:
865 return ret_val;
866}
867
868
869
870
871
872
873
874
875
876
877
878s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
879{
880 struct e1000_phy_info *phy = &hw->phy;
881 s32 ret_val;
882 u16 phy_data;
883 bool link;
884
885
886
887
888
889 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
890 if (ret_val)
891 goto out;
892
893 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
894 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
895 if (ret_val)
896 goto out;
897
898 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
899
900 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
901 if (ret_val)
902 goto out;
903
904 igb_phy_force_speed_duplex_setup(hw, &phy_data);
905
906
907 phy_data |= MII_CR_RESET;
908
909 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
910 if (ret_val)
911 goto out;
912
913 udelay(1);
914
915 if (phy->autoneg_wait_to_complete) {
916 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
917
918 ret_val = igb_phy_has_link(hw,
919 PHY_FORCE_LIMIT,
920 100000,
921 &link);
922 if (ret_val)
923 goto out;
924
925 if (!link) {
926
927
928
929
930 ret_val = phy->ops.write_reg(hw,
931 M88E1000_PHY_PAGE_SELECT,
932 0x001d);
933 if (ret_val)
934 goto out;
935 ret_val = igb_phy_reset_dsp(hw);
936 if (ret_val)
937 goto out;
938 }
939
940
941 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
942 100000, &link);
943 if (ret_val)
944 goto out;
945 }
946
947 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
948 if (ret_val)
949 goto out;
950
951
952
953
954
955
956 phy_data |= M88E1000_EPSCR_TX_CLK_25;
957 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
958 if (ret_val)
959 goto out;
960
961
962
963
964
965 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
966 if (ret_val)
967 goto out;
968
969 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
970 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
971
972out:
973 return ret_val;
974}
975
976
977
978
979
980
981
982
983
984
985
986
987
988static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
989 u16 *phy_ctrl)
990{
991 struct e1000_mac_info *mac = &hw->mac;
992 u32 ctrl;
993
994
995 hw->fc.current_mode = e1000_fc_none;
996
997
998 ctrl = rd32(E1000_CTRL);
999 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1000 ctrl &= ~E1000_CTRL_SPD_SEL;
1001
1002
1003 ctrl &= ~E1000_CTRL_ASDE;
1004
1005
1006 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1007
1008
1009 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1010 ctrl &= ~E1000_CTRL_FD;
1011 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1012 hw_dbg("Half Duplex\n");
1013 } else {
1014 ctrl |= E1000_CTRL_FD;
1015 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1016 hw_dbg("Full Duplex\n");
1017 }
1018
1019
1020 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1021 ctrl |= E1000_CTRL_SPD_100;
1022 *phy_ctrl |= MII_CR_SPEED_100;
1023 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1024 hw_dbg("Forcing 100mb\n");
1025 } else {
1026 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1027 *phy_ctrl |= MII_CR_SPEED_10;
1028 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1029 hw_dbg("Forcing 10mb\n");
1030 }
1031
1032 igb_config_collision_dist(hw);
1033
1034 wr32(E1000_CTRL, ctrl);
1035}
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1052{
1053 struct e1000_phy_info *phy = &hw->phy;
1054 s32 ret_val;
1055 u16 data;
1056
1057 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1058 if (ret_val)
1059 goto out;
1060
1061 if (!active) {
1062 data &= ~IGP02E1000_PM_D3_LPLU;
1063 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1064 data);
1065 if (ret_val)
1066 goto out;
1067
1068
1069
1070
1071
1072
1073 if (phy->smart_speed == e1000_smart_speed_on) {
1074 ret_val = phy->ops.read_reg(hw,
1075 IGP01E1000_PHY_PORT_CONFIG,
1076 &data);
1077 if (ret_val)
1078 goto out;
1079
1080 data |= IGP01E1000_PSCFR_SMART_SPEED;
1081 ret_val = phy->ops.write_reg(hw,
1082 IGP01E1000_PHY_PORT_CONFIG,
1083 data);
1084 if (ret_val)
1085 goto out;
1086 } else if (phy->smart_speed == e1000_smart_speed_off) {
1087 ret_val = phy->ops.read_reg(hw,
1088 IGP01E1000_PHY_PORT_CONFIG,
1089 &data);
1090 if (ret_val)
1091 goto out;
1092
1093 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1094 ret_val = phy->ops.write_reg(hw,
1095 IGP01E1000_PHY_PORT_CONFIG,
1096 data);
1097 if (ret_val)
1098 goto out;
1099 }
1100 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1101 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1102 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1103 data |= IGP02E1000_PM_D3_LPLU;
1104 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1105 data);
1106 if (ret_val)
1107 goto out;
1108
1109
1110 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1111 &data);
1112 if (ret_val)
1113 goto out;
1114
1115 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1116 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1117 data);
1118 }
1119
1120out:
1121 return ret_val;
1122}
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132s32 igb_check_downshift(struct e1000_hw *hw)
1133{
1134 struct e1000_phy_info *phy = &hw->phy;
1135 s32 ret_val;
1136 u16 phy_data, offset, mask;
1137
1138 switch (phy->type) {
1139 case e1000_phy_m88:
1140 case e1000_phy_gg82563:
1141 offset = M88E1000_PHY_SPEC_STATUS;
1142 mask = M88E1000_PSSR_DOWNSHIFT;
1143 break;
1144 case e1000_phy_igp_2:
1145 case e1000_phy_igp:
1146 case e1000_phy_igp_3:
1147 offset = IGP01E1000_PHY_LINK_HEALTH;
1148 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1149 break;
1150 default:
1151
1152 phy->speed_downgraded = false;
1153 ret_val = 0;
1154 goto out;
1155 }
1156
1157 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1158
1159 if (!ret_val)
1160 phy->speed_downgraded = (phy_data & mask) ? true : false;
1161
1162out:
1163 return ret_val;
1164}
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174static s32 igb_check_polarity_m88(struct e1000_hw *hw)
1175{
1176 struct e1000_phy_info *phy = &hw->phy;
1177 s32 ret_val;
1178 u16 data;
1179
1180 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1181
1182 if (!ret_val)
1183 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1184 ? e1000_rev_polarity_reversed
1185 : e1000_rev_polarity_normal;
1186
1187 return ret_val;
1188}
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1200{
1201 struct e1000_phy_info *phy = &hw->phy;
1202 s32 ret_val;
1203 u16 data, offset, mask;
1204
1205
1206
1207
1208
1209 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1210 if (ret_val)
1211 goto out;
1212
1213 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1214 IGP01E1000_PSSR_SPEED_1000MBPS) {
1215 offset = IGP01E1000_PHY_PCS_INIT_REG;
1216 mask = IGP01E1000_PHY_POLARITY_MASK;
1217 } else {
1218
1219
1220
1221
1222 offset = IGP01E1000_PHY_PORT_STATUS;
1223 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1224 }
1225
1226 ret_val = phy->ops.read_reg(hw, offset, &data);
1227
1228 if (!ret_val)
1229 phy->cable_polarity = (data & mask)
1230 ? e1000_rev_polarity_reversed
1231 : e1000_rev_polarity_normal;
1232
1233out:
1234 return ret_val;
1235}
1236
1237
1238
1239
1240
1241
1242
1243
1244static s32 igb_wait_autoneg(struct e1000_hw *hw)
1245{
1246 s32 ret_val = 0;
1247 u16 i, phy_status;
1248
1249
1250 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1251 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1252 if (ret_val)
1253 break;
1254 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1255 if (ret_val)
1256 break;
1257 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1258 break;
1259 msleep(100);
1260 }
1261
1262
1263
1264
1265
1266 return ret_val;
1267}
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1279 u32 usec_interval, bool *success)
1280{
1281 s32 ret_val = 0;
1282 u16 i, phy_status;
1283
1284 for (i = 0; i < iterations; i++) {
1285
1286
1287
1288
1289
1290 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1291 if (ret_val)
1292 break;
1293 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1294 if (ret_val)
1295 break;
1296 if (phy_status & MII_SR_LINK_STATUS)
1297 break;
1298 if (usec_interval >= 1000)
1299 mdelay(usec_interval/1000);
1300 else
1301 udelay(usec_interval);
1302 }
1303
1304 *success = (i < iterations) ? true : false;
1305
1306 return ret_val;
1307}
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1325{
1326 struct e1000_phy_info *phy = &hw->phy;
1327 s32 ret_val;
1328 u16 phy_data, index;
1329
1330 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1331 if (ret_val)
1332 goto out;
1333
1334 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1335 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1336 phy->min_cable_length = e1000_m88_cable_length_table[index];
1337 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1338
1339 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1340
1341out:
1342 return ret_val;
1343}
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1357{
1358 struct e1000_phy_info *phy = &hw->phy;
1359 s32 ret_val = 0;
1360 u16 phy_data, i, agc_value = 0;
1361 u16 cur_agc_index, max_agc_index = 0;
1362 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1363 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1364 {IGP02E1000_PHY_AGC_A,
1365 IGP02E1000_PHY_AGC_B,
1366 IGP02E1000_PHY_AGC_C,
1367 IGP02E1000_PHY_AGC_D};
1368
1369
1370 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1371 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1372 if (ret_val)
1373 goto out;
1374
1375
1376
1377
1378
1379
1380
1381 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1382 IGP02E1000_AGC_LENGTH_MASK;
1383
1384
1385 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1386 (cur_agc_index == 0)) {
1387 ret_val = -E1000_ERR_PHY;
1388 goto out;
1389 }
1390
1391
1392 if (e1000_igp_2_cable_length_table[min_agc_index] >
1393 e1000_igp_2_cable_length_table[cur_agc_index])
1394 min_agc_index = cur_agc_index;
1395 if (e1000_igp_2_cable_length_table[max_agc_index] <
1396 e1000_igp_2_cable_length_table[cur_agc_index])
1397 max_agc_index = cur_agc_index;
1398
1399 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1400 }
1401
1402 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1403 e1000_igp_2_cable_length_table[max_agc_index]);
1404 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1405
1406
1407 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1408 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1409 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1410
1411 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1412
1413out:
1414 return ret_val;
1415}
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1428{
1429 struct e1000_phy_info *phy = &hw->phy;
1430 s32 ret_val;
1431 u16 phy_data;
1432 bool link;
1433
1434 if (phy->media_type != e1000_media_type_copper) {
1435 hw_dbg("Phy info is only valid for copper media\n");
1436 ret_val = -E1000_ERR_CONFIG;
1437 goto out;
1438 }
1439
1440 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1441 if (ret_val)
1442 goto out;
1443
1444 if (!link) {
1445 hw_dbg("Phy info is only valid if link is up\n");
1446 ret_val = -E1000_ERR_CONFIG;
1447 goto out;
1448 }
1449
1450 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1451 if (ret_val)
1452 goto out;
1453
1454 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1455 ? true : false;
1456
1457 ret_val = igb_check_polarity_m88(hw);
1458 if (ret_val)
1459 goto out;
1460
1461 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1462 if (ret_val)
1463 goto out;
1464
1465 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1466
1467 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1468 ret_val = phy->ops.get_cable_length(hw);
1469 if (ret_val)
1470 goto out;
1471
1472 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1473 if (ret_val)
1474 goto out;
1475
1476 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1477 ? e1000_1000t_rx_status_ok
1478 : e1000_1000t_rx_status_not_ok;
1479
1480 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1481 ? e1000_1000t_rx_status_ok
1482 : e1000_1000t_rx_status_not_ok;
1483 } else {
1484
1485 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1486 phy->local_rx = e1000_1000t_rx_status_undefined;
1487 phy->remote_rx = e1000_1000t_rx_status_undefined;
1488 }
1489
1490out:
1491 return ret_val;
1492}
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1504{
1505 struct e1000_phy_info *phy = &hw->phy;
1506 s32 ret_val;
1507 u16 data;
1508 bool link;
1509
1510 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1511 if (ret_val)
1512 goto out;
1513
1514 if (!link) {
1515 hw_dbg("Phy info is only valid if link is up\n");
1516 ret_val = -E1000_ERR_CONFIG;
1517 goto out;
1518 }
1519
1520 phy->polarity_correction = true;
1521
1522 ret_val = igb_check_polarity_igp(hw);
1523 if (ret_val)
1524 goto out;
1525
1526 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1527 if (ret_val)
1528 goto out;
1529
1530 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
1531
1532 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1533 IGP01E1000_PSSR_SPEED_1000MBPS) {
1534 ret_val = phy->ops.get_cable_length(hw);
1535 if (ret_val)
1536 goto out;
1537
1538 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
1539 if (ret_val)
1540 goto out;
1541
1542 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1543 ? e1000_1000t_rx_status_ok
1544 : e1000_1000t_rx_status_not_ok;
1545
1546 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1547 ? e1000_1000t_rx_status_ok
1548 : e1000_1000t_rx_status_not_ok;
1549 } else {
1550 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1551 phy->local_rx = e1000_1000t_rx_status_undefined;
1552 phy->remote_rx = e1000_1000t_rx_status_undefined;
1553 }
1554
1555out:
1556 return ret_val;
1557}
1558
1559
1560
1561
1562
1563
1564
1565
1566s32 igb_phy_sw_reset(struct e1000_hw *hw)
1567{
1568 s32 ret_val = 0;
1569 u16 phy_ctrl;
1570
1571 if (!(hw->phy.ops.read_reg))
1572 goto out;
1573
1574 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1575 if (ret_val)
1576 goto out;
1577
1578 phy_ctrl |= MII_CR_RESET;
1579 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1580 if (ret_val)
1581 goto out;
1582
1583 udelay(1);
1584
1585out:
1586 return ret_val;
1587}
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598s32 igb_phy_hw_reset(struct e1000_hw *hw)
1599{
1600 struct e1000_phy_info *phy = &hw->phy;
1601 s32 ret_val;
1602 u32 ctrl;
1603
1604 ret_val = igb_check_reset_block(hw);
1605 if (ret_val) {
1606 ret_val = 0;
1607 goto out;
1608 }
1609
1610 ret_val = phy->ops.acquire(hw);
1611 if (ret_val)
1612 goto out;
1613
1614 ctrl = rd32(E1000_CTRL);
1615 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
1616 wrfl();
1617
1618 udelay(phy->reset_delay_us);
1619
1620 wr32(E1000_CTRL, ctrl);
1621 wrfl();
1622
1623 udelay(150);
1624
1625 phy->ops.release(hw);
1626
1627 ret_val = phy->ops.get_cfg_done(hw);
1628
1629out:
1630 return ret_val;
1631}
1632
1633
1634
1635
1636
1637
1638
1639s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
1640{
1641 hw_dbg("Running IGP 3 PHY init script\n");
1642
1643
1644
1645 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
1646
1647 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
1648
1649 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
1650
1651 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
1652
1653 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
1654
1655 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
1656
1657 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
1658
1659 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
1660
1661 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
1662
1663 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
1664
1665 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1666
1667 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
1668
1669 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
1670
1671 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
1672
1673 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
1674
1675 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
1676
1677 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
1678
1679 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
1680
1681 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
1682
1683 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
1684
1685 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
1686
1687 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
1688
1689 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
1690
1691 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
1692
1693 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
1694
1695 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
1696
1697
1698
1699
1700 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
1701
1702 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
1703
1704
1705
1706
1707 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
1708
1709 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
1710
1711 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
1712
1713 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
1714
1715 return 0;
1716}
1717
1718