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30#define IOC3_NAME "ioc3-eth"
31#define IOC3_VERSION "2.6.3-4"
32
33#include <linux/init.h>
34#include <linux/delay.h>
35#include <linux/kernel.h>
36#include <linux/mm.h>
37#include <linux/errno.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/crc32.h>
41#include <linux/mii.h>
42#include <linux/in.h>
43#include <linux/ip.h>
44#include <linux/tcp.h>
45#include <linux/udp.h>
46#include <linux/dma-mapping.h>
47
48#ifdef CONFIG_SERIAL_8250
49#include <linux/serial_core.h>
50#include <linux/serial_8250.h>
51#include <linux/serial_reg.h>
52#endif
53
54#include <linux/netdevice.h>
55#include <linux/etherdevice.h>
56#include <linux/ethtool.h>
57#include <linux/skbuff.h>
58#include <net/ip.h>
59
60#include <asm/byteorder.h>
61#include <asm/io.h>
62#include <asm/pgtable.h>
63#include <asm/uaccess.h>
64#include <asm/sn/types.h>
65#include <asm/sn/ioc3.h>
66#include <asm/pci/bridge.h>
67
68
69
70
71
72#define RX_BUFFS 64
73
74#define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21)
75#define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21)
76
77
78struct ioc3_private {
79 struct ioc3 *regs;
80 unsigned long *rxr;
81 struct ioc3_etxd *txr;
82 struct sk_buff *rx_skbs[512];
83 struct sk_buff *tx_skbs[128];
84 struct net_device_stats stats;
85 int rx_ci;
86 int rx_pi;
87 int tx_ci;
88 int tx_pi;
89 int txqlen;
90 u32 emcr, ehar_h, ehar_l;
91 spinlock_t ioc3_lock;
92 struct mii_if_info mii;
93 unsigned long flags;
94#define IOC3_FLAG_RX_CHECKSUMS 1
95
96 struct pci_dev *pdev;
97
98
99 struct timer_list ioc3_timer;
100};
101
102static inline struct net_device *priv_netdev(struct ioc3_private *dev)
103{
104 return (void *)dev - ((sizeof(struct net_device) + 31) & ~31);
105}
106
107static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
108static void ioc3_set_multicast_list(struct net_device *dev);
109static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
110static void ioc3_timeout(struct net_device *dev);
111static inline unsigned int ioc3_hash(const unsigned char *addr);
112static inline void ioc3_stop(struct ioc3_private *ip);
113static void ioc3_init(struct net_device *dev);
114
115static const char ioc3_str[] = "IOC3 Ethernet";
116static const struct ethtool_ops ioc3_ethtool_ops;
117
118
119
120#define IOC3_CACHELINE 128UL
121
122static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
123{
124 return (~addr + 1) & (IOC3_CACHELINE - 1UL);
125}
126
127static inline struct sk_buff * ioc3_alloc_skb(unsigned long length,
128 unsigned int gfp_mask)
129{
130 struct sk_buff *skb;
131
132 skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
133 if (likely(skb)) {
134 int offset = aligned_rx_skb_addr((unsigned long) skb->data);
135 if (offset)
136 skb_reserve(skb, offset);
137 }
138
139 return skb;
140}
141
142static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
143{
144#ifdef CONFIG_SGI_IP27
145 vdev <<= 57;
146
147 return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
148 ((unsigned long)ptr & TO_PHYS_MASK);
149#else
150 return virt_to_bus(ptr);
151#endif
152}
153
154
155
156#define RX_OFFSET 10
157#define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
158
159
160#define BARRIER() \
161 __asm__("sync" ::: "memory")
162
163
164#define IOC3_SIZE 0x100000
165
166
167
168
169
170
171
172
173#define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
174#define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
175#define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
176#define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
177#define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
178#define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
179#define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
180#define ioc3_r_eier() be32_to_cpu(ioc3->eier)
181#define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
182#define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
183#define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
184#define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
185#define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
186#define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
187#define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
188#define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
189#define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
190#define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
191#define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
192#define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
193#define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
194#define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
195#define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
196#define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
197#define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
198#define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
199#define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
200#define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
201#define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
202#define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
203#define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
204#define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
205#define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
206#define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
207#define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
208#define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
209#define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
210#define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
211#define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
212#define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
213#define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
214#define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
215#define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
216#define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
217#define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
218#define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
219#define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
220#define ioc3_r_micr() be32_to_cpu(ioc3->micr)
221#define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
222#define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
223#define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
224#define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
225#define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
226
227static inline u32 mcr_pack(u32 pulse, u32 sample)
228{
229 return (pulse << 10) | (sample << 2);
230}
231
232static int nic_wait(struct ioc3 *ioc3)
233{
234 u32 mcr;
235
236 do {
237 mcr = ioc3_r_mcr();
238 } while (!(mcr & 2));
239
240 return mcr & 1;
241}
242
243static int nic_reset(struct ioc3 *ioc3)
244{
245 int presence;
246
247 ioc3_w_mcr(mcr_pack(500, 65));
248 presence = nic_wait(ioc3);
249
250 ioc3_w_mcr(mcr_pack(0, 500));
251 nic_wait(ioc3);
252
253 return presence;
254}
255
256static inline int nic_read_bit(struct ioc3 *ioc3)
257{
258 int result;
259
260 ioc3_w_mcr(mcr_pack(6, 13));
261 result = nic_wait(ioc3);
262 ioc3_w_mcr(mcr_pack(0, 100));
263 nic_wait(ioc3);
264
265 return result;
266}
267
268static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
269{
270 if (bit)
271 ioc3_w_mcr(mcr_pack(6, 110));
272 else
273 ioc3_w_mcr(mcr_pack(80, 30));
274
275 nic_wait(ioc3);
276}
277
278
279
280
281static u32 nic_read_byte(struct ioc3 *ioc3)
282{
283 u32 result = 0;
284 int i;
285
286 for (i = 0; i < 8; i++)
287 result = (result >> 1) | (nic_read_bit(ioc3) << 7);
288
289 return result;
290}
291
292
293
294
295static void nic_write_byte(struct ioc3 *ioc3, int byte)
296{
297 int i, bit;
298
299 for (i = 8; i; i--) {
300 bit = byte & 1;
301 byte >>= 1;
302
303 nic_write_bit(ioc3, bit);
304 }
305}
306
307static u64 nic_find(struct ioc3 *ioc3, int *last)
308{
309 int a, b, index, disc;
310 u64 address = 0;
311
312 nic_reset(ioc3);
313
314 nic_write_byte(ioc3, 0xf0);
315
316
317 for (index = 0, disc = 0; index < 64; index++) {
318 a = nic_read_bit(ioc3);
319 b = nic_read_bit(ioc3);
320
321 if (a && b) {
322 printk("NIC search failed (not fatal).\n");
323 *last = 0;
324 return 0;
325 }
326
327 if (!a && !b) {
328 if (index == *last) {
329 address |= 1UL << index;
330 } else if (index > *last) {
331 address &= ~(1UL << index);
332 disc = index;
333 } else if ((address & (1UL << index)) == 0)
334 disc = index;
335 nic_write_bit(ioc3, address & (1UL << index));
336 continue;
337 } else {
338 if (a)
339 address |= 1UL << index;
340 else
341 address &= ~(1UL << index);
342 nic_write_bit(ioc3, a);
343 continue;
344 }
345 }
346
347 *last = disc;
348
349 return address;
350}
351
352static int nic_init(struct ioc3 *ioc3)
353{
354 const char *unknown = "unknown";
355 const char *type = unknown;
356 u8 crc;
357 u8 serial[6];
358 int save = 0, i;
359
360 while (1) {
361 u64 reg;
362 reg = nic_find(ioc3, &save);
363
364 switch (reg & 0xff) {
365 case 0x91:
366 type = "DS1981U";
367 break;
368 default:
369 if (save == 0) {
370
371 return -1;
372 }
373 continue;
374 }
375
376 nic_reset(ioc3);
377
378
379 nic_write_byte(ioc3, 0x55);
380 for (i = 0; i < 8; i++)
381 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
382
383 reg >>= 8;
384 for (i = 0; i < 6; i++) {
385 serial[i] = reg & 0xff;
386 reg >>= 8;
387 }
388 crc = reg & 0xff;
389 break;
390 }
391
392 printk("Found %s NIC", type);
393 if (type != unknown)
394 printk (" registration number %pM, CRC %02x", serial, crc);
395 printk(".\n");
396
397 return 0;
398}
399
400
401
402
403
404static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
405{
406 struct ioc3 *ioc3 = ip->regs;
407 u8 nic[14];
408 int tries = 2;
409 int i;
410
411 ioc3_w_gpcr_s(1 << 21);
412
413 while (tries--) {
414 if (!nic_init(ioc3))
415 break;
416 udelay(500);
417 }
418
419 if (tries < 0) {
420 printk("Failed to read MAC address\n");
421 return;
422 }
423
424
425 nic_write_byte(ioc3, 0xf0);
426 nic_write_byte(ioc3, 0x00);
427 nic_write_byte(ioc3, 0x00);
428
429 for (i = 13; i >= 0; i--)
430 nic[i] = nic_read_byte(ioc3);
431
432 for (i = 2; i < 8; i++)
433 priv_netdev(ip)->dev_addr[i - 2] = nic[i];
434}
435
436
437
438
439
440
441static void ioc3_get_eaddr(struct ioc3_private *ip)
442{
443 ioc3_get_eaddr_nic(ip);
444
445 printk("Ethernet address is %pM.\n", priv_netdev(ip)->dev_addr);
446}
447
448static void __ioc3_set_mac_address(struct net_device *dev)
449{
450 struct ioc3_private *ip = netdev_priv(dev);
451 struct ioc3 *ioc3 = ip->regs;
452
453 ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]);
454 ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
455 (dev->dev_addr[1] << 8) | dev->dev_addr[0]);
456}
457
458static int ioc3_set_mac_address(struct net_device *dev, void *addr)
459{
460 struct ioc3_private *ip = netdev_priv(dev);
461 struct sockaddr *sa = addr;
462
463 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
464
465 spin_lock_irq(&ip->ioc3_lock);
466 __ioc3_set_mac_address(dev);
467 spin_unlock_irq(&ip->ioc3_lock);
468
469 return 0;
470}
471
472
473
474
475
476static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
477{
478 struct ioc3_private *ip = netdev_priv(dev);
479 struct ioc3 *ioc3 = ip->regs;
480
481 while (ioc3_r_micr() & MICR_BUSY);
482 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
483 while (ioc3_r_micr() & MICR_BUSY);
484
485 return ioc3_r_midr_r() & MIDR_DATA_MASK;
486}
487
488static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
489{
490 struct ioc3_private *ip = netdev_priv(dev);
491 struct ioc3 *ioc3 = ip->regs;
492
493 while (ioc3_r_micr() & MICR_BUSY);
494 ioc3_w_midr_w(data);
495 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg);
496 while (ioc3_r_micr() & MICR_BUSY);
497}
498
499static int ioc3_mii_init(struct ioc3_private *ip);
500
501static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
502{
503 struct ioc3_private *ip = netdev_priv(dev);
504 struct ioc3 *ioc3 = ip->regs;
505
506 ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
507 return &ip->stats;
508}
509
510static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
511{
512 struct ethhdr *eh = eth_hdr(skb);
513 uint32_t csum, ehsum;
514 unsigned int proto;
515 struct iphdr *ih;
516 uint16_t *ew;
517 unsigned char *cp;
518
519
520
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524
525
526
527
528
529
530
531
532
533 if (eh->h_proto != htons(ETH_P_IP))
534 return;
535
536 ih = (struct iphdr *) ((char *)eh + ETH_HLEN);
537 if (ih->frag_off & htons(IP_MF | IP_OFFSET))
538 return;
539
540 proto = ih->protocol;
541 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
542 return;
543
544
545 csum = hwsum +
546 (ih->tot_len - (ih->ihl << 2)) +
547 htons((uint16_t)ih->protocol) +
548 (ih->saddr >> 16) + (ih->saddr & 0xffff) +
549 (ih->daddr >> 16) + (ih->daddr & 0xffff);
550
551
552 ew = (uint16_t *) eh;
553 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
554
555 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
556 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
557
558 csum += 0xffff ^ ehsum;
559
560
561
562 cp = (char *)eh + len;
563 if (len & 1) {
564 csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]);
565 csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]);
566 } else {
567 csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]);
568 csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]);
569 }
570
571 csum = (csum & 0xffff) + (csum >> 16);
572 csum = (csum & 0xffff) + (csum >> 16);
573
574 if (csum == 0xffff)
575 skb->ip_summed = CHECKSUM_UNNECESSARY;
576}
577
578static inline void ioc3_rx(struct ioc3_private *ip)
579{
580 struct sk_buff *skb, *new_skb;
581 struct ioc3 *ioc3 = ip->regs;
582 int rx_entry, n_entry, len;
583 struct ioc3_erxbuf *rxb;
584 unsigned long *rxr;
585 u32 w0, err;
586
587 rxr = (unsigned long *) ip->rxr;
588 rx_entry = ip->rx_ci;
589 n_entry = ip->rx_pi;
590
591 skb = ip->rx_skbs[rx_entry];
592 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
593 w0 = be32_to_cpu(rxb->w0);
594
595 while (w0 & ERXBUF_V) {
596 err = be32_to_cpu(rxb->err);
597 if (err & ERXBUF_GOODPKT) {
598 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
599 skb_trim(skb, len);
600 skb->protocol = eth_type_trans(skb, priv_netdev(ip));
601
602 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
603 if (!new_skb) {
604
605
606 ip->stats.rx_dropped++;
607 new_skb = skb;
608 goto next;
609 }
610
611 if (likely(ip->flags & IOC3_FLAG_RX_CHECKSUMS))
612 ioc3_tcpudp_checksum(skb,
613 w0 & ERXBUF_IPCKSUM_MASK, len);
614
615 netif_rx(skb);
616
617 ip->rx_skbs[rx_entry] = NULL;
618
619
620 skb_put(new_skb, (1664 + RX_OFFSET));
621 rxb = (struct ioc3_erxbuf *) new_skb->data;
622 skb_reserve(new_skb, RX_OFFSET);
623
624 ip->stats.rx_packets++;
625 ip->stats.rx_bytes += len;
626 } else {
627
628
629
630 new_skb = skb;
631 ip->stats.rx_errors++;
632 }
633 if (err & ERXBUF_CRCERR)
634 ip->stats.rx_crc_errors++;
635 if (err & ERXBUF_FRAMERR)
636 ip->stats.rx_frame_errors++;
637next:
638 ip->rx_skbs[n_entry] = new_skb;
639 rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
640 rxb->w0 = 0;
641 n_entry = (n_entry + 1) & 511;
642
643
644 rx_entry = (rx_entry + 1) & 511;
645 skb = ip->rx_skbs[rx_entry];
646 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
647 w0 = be32_to_cpu(rxb->w0);
648 }
649 ioc3_w_erpir((n_entry << 3) | ERPIR_ARM);
650 ip->rx_pi = n_entry;
651 ip->rx_ci = rx_entry;
652}
653
654static inline void ioc3_tx(struct ioc3_private *ip)
655{
656 unsigned long packets, bytes;
657 struct ioc3 *ioc3 = ip->regs;
658 int tx_entry, o_entry;
659 struct sk_buff *skb;
660 u32 etcir;
661
662 spin_lock(&ip->ioc3_lock);
663 etcir = ioc3_r_etcir();
664
665 tx_entry = (etcir >> 7) & 127;
666 o_entry = ip->tx_ci;
667 packets = 0;
668 bytes = 0;
669
670 while (o_entry != tx_entry) {
671 packets++;
672 skb = ip->tx_skbs[o_entry];
673 bytes += skb->len;
674 dev_kfree_skb_irq(skb);
675 ip->tx_skbs[o_entry] = NULL;
676
677 o_entry = (o_entry + 1) & 127;
678
679 etcir = ioc3_r_etcir();
680 tx_entry = (etcir >> 7) & 127;
681 }
682
683 ip->stats.tx_packets += packets;
684 ip->stats.tx_bytes += bytes;
685 ip->txqlen -= packets;
686
687 if (ip->txqlen < 128)
688 netif_wake_queue(priv_netdev(ip));
689
690 ip->tx_ci = o_entry;
691 spin_unlock(&ip->ioc3_lock);
692}
693
694
695
696
697
698
699
700
701static void ioc3_error(struct ioc3_private *ip, u32 eisr)
702{
703 struct net_device *dev = priv_netdev(ip);
704 unsigned char *iface = dev->name;
705
706 spin_lock(&ip->ioc3_lock);
707
708 if (eisr & EISR_RXOFLO)
709 printk(KERN_ERR "%s: RX overflow.\n", iface);
710 if (eisr & EISR_RXBUFOFLO)
711 printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
712 if (eisr & EISR_RXMEMERR)
713 printk(KERN_ERR "%s: RX PCI error.\n", iface);
714 if (eisr & EISR_RXPARERR)
715 printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
716 if (eisr & EISR_TXBUFUFLO)
717 printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
718 if (eisr & EISR_TXMEMERR)
719 printk(KERN_ERR "%s: TX PCI error.\n", iface);
720
721 ioc3_stop(ip);
722 ioc3_init(dev);
723 ioc3_mii_init(ip);
724
725 netif_wake_queue(dev);
726
727 spin_unlock(&ip->ioc3_lock);
728}
729
730
731
732static irqreturn_t ioc3_interrupt(int irq, void *_dev)
733{
734 struct net_device *dev = (struct net_device *)_dev;
735 struct ioc3_private *ip = netdev_priv(dev);
736 struct ioc3 *ioc3 = ip->regs;
737 const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
738 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
739 EISR_TXEXPLICIT | EISR_TXMEMERR;
740 u32 eisr;
741
742 eisr = ioc3_r_eisr() & enabled;
743
744 ioc3_w_eisr(eisr);
745 (void) ioc3_r_eisr();
746
747 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
748 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
749 ioc3_error(ip, eisr);
750 if (eisr & EISR_RXTIMERINT)
751 ioc3_rx(ip);
752 if (eisr & EISR_TXEXPLICIT)
753 ioc3_tx(ip);
754
755 return IRQ_HANDLED;
756}
757
758static inline void ioc3_setup_duplex(struct ioc3_private *ip)
759{
760 struct ioc3 *ioc3 = ip->regs;
761
762 if (ip->mii.full_duplex) {
763 ioc3_w_etcsr(ETCSR_FD);
764 ip->emcr |= EMCR_DUPLEX;
765 } else {
766 ioc3_w_etcsr(ETCSR_HD);
767 ip->emcr &= ~EMCR_DUPLEX;
768 }
769 ioc3_w_emcr(ip->emcr);
770}
771
772static void ioc3_timer(unsigned long data)
773{
774 struct ioc3_private *ip = (struct ioc3_private *) data;
775
776
777 mii_check_media(&ip->mii, 1, 0);
778 ioc3_setup_duplex(ip);
779
780 ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10);
781 add_timer(&ip->ioc3_timer);
782}
783
784
785
786
787
788
789
790
791
792static int ioc3_mii_init(struct ioc3_private *ip)
793{
794 struct net_device *dev = priv_netdev(ip);
795 int i, found = 0, res = 0;
796 int ioc3_phy_workaround = 1;
797 u16 word;
798
799 for (i = 0; i < 32; i++) {
800 word = ioc3_mdio_read(dev, i, MII_PHYSID1);
801
802 if (word != 0xffff && word != 0x0000) {
803 found = 1;
804 break;
805 }
806 }
807
808 if (!found) {
809 if (ioc3_phy_workaround)
810 i = 31;
811 else {
812 ip->mii.phy_id = -1;
813 res = -ENODEV;
814 goto out;
815 }
816 }
817
818 ip->mii.phy_id = i;
819
820out:
821 return res;
822}
823
824static void ioc3_mii_start(struct ioc3_private *ip)
825{
826 ip->ioc3_timer.expires = jiffies + (12 * HZ)/10;
827 ip->ioc3_timer.data = (unsigned long) ip;
828 ip->ioc3_timer.function = &ioc3_timer;
829 add_timer(&ip->ioc3_timer);
830}
831
832static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)
833{
834 struct sk_buff *skb;
835 int i;
836
837 for (i = ip->rx_ci; i & 15; i++) {
838 ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
839 ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
840 }
841 ip->rx_pi &= 511;
842 ip->rx_ci &= 511;
843
844 for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
845 struct ioc3_erxbuf *rxb;
846 skb = ip->rx_skbs[i];
847 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
848 rxb->w0 = 0;
849 }
850}
851
852static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
853{
854 struct sk_buff *skb;
855 int i;
856
857 for (i=0; i < 128; i++) {
858 skb = ip->tx_skbs[i];
859 if (skb) {
860 ip->tx_skbs[i] = NULL;
861 dev_kfree_skb_any(skb);
862 }
863 ip->txr[i].cmd = 0;
864 }
865 ip->tx_pi = 0;
866 ip->tx_ci = 0;
867}
868
869static void ioc3_free_rings(struct ioc3_private *ip)
870{
871 struct sk_buff *skb;
872 int rx_entry, n_entry;
873
874 if (ip->txr) {
875 ioc3_clean_tx_ring(ip);
876 free_pages((unsigned long)ip->txr, 2);
877 ip->txr = NULL;
878 }
879
880 if (ip->rxr) {
881 n_entry = ip->rx_ci;
882 rx_entry = ip->rx_pi;
883
884 while (n_entry != rx_entry) {
885 skb = ip->rx_skbs[n_entry];
886 if (skb)
887 dev_kfree_skb_any(skb);
888
889 n_entry = (n_entry + 1) & 511;
890 }
891 free_page((unsigned long)ip->rxr);
892 ip->rxr = NULL;
893 }
894}
895
896static void ioc3_alloc_rings(struct net_device *dev)
897{
898 struct ioc3_private *ip = netdev_priv(dev);
899 struct ioc3_erxbuf *rxb;
900 unsigned long *rxr;
901 int i;
902
903 if (ip->rxr == NULL) {
904
905 ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
906 rxr = (unsigned long *) ip->rxr;
907 if (!rxr)
908 printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
909
910
911
912
913 for (i = 0; i < RX_BUFFS; i++) {
914 struct sk_buff *skb;
915
916 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
917 if (!skb) {
918 show_free_areas();
919 continue;
920 }
921
922 ip->rx_skbs[i] = skb;
923
924
925 skb_put(skb, (1664 + RX_OFFSET));
926 rxb = (struct ioc3_erxbuf *) skb->data;
927 rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
928 skb_reserve(skb, RX_OFFSET);
929 }
930 ip->rx_ci = 0;
931 ip->rx_pi = RX_BUFFS;
932 }
933
934 if (ip->txr == NULL) {
935
936 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
937 if (!ip->txr)
938 printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
939 ip->tx_pi = 0;
940 ip->tx_ci = 0;
941 }
942}
943
944static void ioc3_init_rings(struct net_device *dev)
945{
946 struct ioc3_private *ip = netdev_priv(dev);
947 struct ioc3 *ioc3 = ip->regs;
948 unsigned long ring;
949
950 ioc3_free_rings(ip);
951 ioc3_alloc_rings(dev);
952
953 ioc3_clean_rx_ring(ip);
954 ioc3_clean_tx_ring(ip);
955
956
957 ring = ioc3_map(ip->rxr, 0);
958 ioc3_w_erbr_h(ring >> 32);
959 ioc3_w_erbr_l(ring & 0xffffffff);
960 ioc3_w_ercir(ip->rx_ci << 3);
961 ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM);
962
963 ring = ioc3_map(ip->txr, 0);
964
965 ip->txqlen = 0;
966
967
968 ioc3_w_etbr_h(ring >> 32);
969 ioc3_w_etbr_l(ring & 0xffffffff);
970 ioc3_w_etpir(ip->tx_pi << 7);
971 ioc3_w_etcir(ip->tx_ci << 7);
972 (void) ioc3_r_etcir();
973}
974
975static inline void ioc3_ssram_disc(struct ioc3_private *ip)
976{
977 struct ioc3 *ioc3 = ip->regs;
978 volatile u32 *ssram0 = &ioc3->ssram[0x0000];
979 volatile u32 *ssram1 = &ioc3->ssram[0x4000];
980 unsigned int pattern = 0x5555;
981
982
983 ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR));
984
985 *ssram0 = pattern;
986 *ssram1 = ~pattern & IOC3_SSRAM_DM;
987
988 if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
989 (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
990
991 ip->emcr = EMCR_RAMPAR;
992 ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
993 } else
994 ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
995}
996
997static void ioc3_init(struct net_device *dev)
998{
999 struct ioc3_private *ip = netdev_priv(dev);
1000 struct ioc3 *ioc3 = ip->regs;
1001
1002 del_timer_sync(&ip->ioc3_timer);
1003
1004 ioc3_w_emcr(EMCR_RST);
1005 (void) ioc3_r_emcr();
1006 udelay(4);
1007 ioc3_w_emcr(0);
1008 (void) ioc3_r_emcr();
1009
1010
1011#ifdef CONFIG_SGI_IP27
1012 ioc3_w_erbar(PCI64_ATTR_BAR >> 32);
1013#else
1014 ioc3_w_erbar(0);
1015#endif
1016 (void) ioc3_r_etcdc();
1017 ioc3_w_ercsr(15);
1018 ioc3_w_ertr(0);
1019 __ioc3_set_mac_address(dev);
1020 ioc3_w_ehar_h(ip->ehar_h);
1021 ioc3_w_ehar_l(ip->ehar_l);
1022 ioc3_w_ersr(42);
1023
1024 ioc3_init_rings(dev);
1025
1026 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
1027 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
1028 ioc3_w_emcr(ip->emcr);
1029 ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
1030 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
1031 EISR_TXEXPLICIT | EISR_TXMEMERR);
1032 (void) ioc3_r_eier();
1033}
1034
1035static inline void ioc3_stop(struct ioc3_private *ip)
1036{
1037 struct ioc3 *ioc3 = ip->regs;
1038
1039 ioc3_w_emcr(0);
1040 ioc3_w_eier(0);
1041 (void) ioc3_r_eier();
1042}
1043
1044static int ioc3_open(struct net_device *dev)
1045{
1046 struct ioc3_private *ip = netdev_priv(dev);
1047
1048 if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
1049 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
1050
1051 return -EAGAIN;
1052 }
1053
1054 ip->ehar_h = 0;
1055 ip->ehar_l = 0;
1056 ioc3_init(dev);
1057 ioc3_mii_start(ip);
1058
1059 netif_start_queue(dev);
1060 return 0;
1061}
1062
1063static int ioc3_close(struct net_device *dev)
1064{
1065 struct ioc3_private *ip = netdev_priv(dev);
1066
1067 del_timer_sync(&ip->ioc3_timer);
1068
1069 netif_stop_queue(dev);
1070
1071 ioc3_stop(ip);
1072 free_irq(dev->irq, dev);
1073
1074 ioc3_free_rings(ip);
1075 return 0;
1076}
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot)
1090{
1091 struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0));
1092 int ret = 0;
1093
1094 if (dev) {
1095 if (dev->vendor == PCI_VENDOR_ID_SGI &&
1096 dev->device == PCI_DEVICE_ID_SGI_IOC3)
1097 ret = 1;
1098 pci_dev_put(dev);
1099 }
1100
1101 return ret;
1102}
1103
1104static int ioc3_is_menet(struct pci_dev *pdev)
1105{
1106 return pdev->bus->parent == NULL &&
1107 ioc3_adjacent_is_ioc3(pdev, 0) &&
1108 ioc3_adjacent_is_ioc3(pdev, 1) &&
1109 ioc3_adjacent_is_ioc3(pdev, 2);
1110}
1111
1112#ifdef CONFIG_SERIAL_8250
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146static void __devinit ioc3_8250_register(struct ioc3_uartregs __iomem *uart)
1147{
1148#define COSMISC_CONSTANT 6
1149
1150 struct uart_port port = {
1151 .irq = 0,
1152 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
1153 .iotype = UPIO_MEM,
1154 .regshift = 0,
1155 .uartclk = (22000000 << 1) / COSMISC_CONSTANT,
1156
1157 .membase = (unsigned char __iomem *) uart,
1158 .mapbase = (unsigned long) uart,
1159 };
1160 unsigned char lcr;
1161
1162 lcr = uart->iu_lcr;
1163 uart->iu_lcr = lcr | UART_LCR_DLAB;
1164 uart->iu_scr = COSMISC_CONSTANT,
1165 uart->iu_lcr = lcr;
1166 uart->iu_lcr;
1167 serial8250_register_port(&port);
1168}
1169
1170static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1171{
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1182 return;
1183
1184
1185
1186
1187
1188 ioc3->gpcr_s = GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL;
1189 ioc3->gpcr_s;
1190 ioc3->gppr_6 = 0;
1191 ioc3->gppr_6;
1192 ioc3->gppr_7 = 0;
1193 ioc3->gppr_7;
1194 ioc3->sscr_a = ioc3->sscr_a & ~SSCR_DMA_EN;
1195 ioc3->sscr_a;
1196 ioc3->sscr_b = ioc3->sscr_b & ~SSCR_DMA_EN;
1197 ioc3->sscr_b;
1198
1199 ioc3->sio_iec &= ~ (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL |
1200 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER |
1201 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS |
1202 SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR);
1203 ioc3->sio_iec |= SIO_IR_SA_INT;
1204 ioc3->sscr_a = 0;
1205 ioc3->sio_iec &= ~ (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL |
1206 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER |
1207 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS |
1208 SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR);
1209 ioc3->sio_iec |= SIO_IR_SB_INT;
1210 ioc3->sscr_b = 0;
1211
1212 ioc3_8250_register(&ioc3->sregs.uarta);
1213 ioc3_8250_register(&ioc3->sregs.uartb);
1214}
1215#endif
1216
1217static const struct net_device_ops ioc3_netdev_ops = {
1218 .ndo_open = ioc3_open,
1219 .ndo_stop = ioc3_close,
1220 .ndo_start_xmit = ioc3_start_xmit,
1221 .ndo_tx_timeout = ioc3_timeout,
1222 .ndo_get_stats = ioc3_get_stats,
1223 .ndo_set_multicast_list = ioc3_set_multicast_list,
1224 .ndo_do_ioctl = ioc3_ioctl,
1225 .ndo_validate_addr = eth_validate_addr,
1226 .ndo_set_mac_address = ioc3_set_mac_address,
1227 .ndo_change_mtu = eth_change_mtu,
1228};
1229
1230static int __devinit ioc3_probe(struct pci_dev *pdev,
1231 const struct pci_device_id *ent)
1232{
1233 unsigned int sw_physid1, sw_physid2;
1234 struct net_device *dev = NULL;
1235 struct ioc3_private *ip;
1236 struct ioc3 *ioc3;
1237 unsigned long ioc3_base, ioc3_size;
1238 u32 vendor, model, rev;
1239 int err, pci_using_dac;
1240
1241
1242 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1243 if (!err) {
1244 pci_using_dac = 1;
1245 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1246 if (err < 0) {
1247 printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
1248 "for consistent allocations\n", pci_name(pdev));
1249 goto out;
1250 }
1251 } else {
1252 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1253 if (err) {
1254 printk(KERN_ERR "%s: No usable DMA configuration, "
1255 "aborting.\n", pci_name(pdev));
1256 goto out;
1257 }
1258 pci_using_dac = 0;
1259 }
1260
1261 if (pci_enable_device(pdev))
1262 return -ENODEV;
1263
1264 dev = alloc_etherdev(sizeof(struct ioc3_private));
1265 if (!dev) {
1266 err = -ENOMEM;
1267 goto out_disable;
1268 }
1269
1270 if (pci_using_dac)
1271 dev->features |= NETIF_F_HIGHDMA;
1272
1273 err = pci_request_regions(pdev, "ioc3");
1274 if (err)
1275 goto out_free;
1276
1277 SET_NETDEV_DEV(dev, &pdev->dev);
1278
1279 ip = netdev_priv(dev);
1280
1281 dev->irq = pdev->irq;
1282
1283 ioc3_base = pci_resource_start(pdev, 0);
1284 ioc3_size = pci_resource_len(pdev, 0);
1285 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
1286 if (!ioc3) {
1287 printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
1288 pci_name(pdev));
1289 err = -ENOMEM;
1290 goto out_res;
1291 }
1292 ip->regs = ioc3;
1293
1294#ifdef CONFIG_SERIAL_8250
1295 ioc3_serial_probe(pdev, ioc3);
1296#endif
1297
1298 spin_lock_init(&ip->ioc3_lock);
1299 init_timer(&ip->ioc3_timer);
1300
1301 ioc3_stop(ip);
1302 ioc3_init(dev);
1303
1304 ip->pdev = pdev;
1305
1306 ip->mii.phy_id_mask = 0x1f;
1307 ip->mii.reg_num_mask = 0x1f;
1308 ip->mii.dev = dev;
1309 ip->mii.mdio_read = ioc3_mdio_read;
1310 ip->mii.mdio_write = ioc3_mdio_write;
1311
1312 ioc3_mii_init(ip);
1313
1314 if (ip->mii.phy_id == -1) {
1315 printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1316 pci_name(pdev));
1317 err = -ENODEV;
1318 goto out_stop;
1319 }
1320
1321 ioc3_mii_start(ip);
1322 ioc3_ssram_disc(ip);
1323 ioc3_get_eaddr(ip);
1324
1325
1326 dev->watchdog_timeo = 5 * HZ;
1327 dev->netdev_ops = &ioc3_netdev_ops;
1328 dev->ethtool_ops = &ioc3_ethtool_ops;
1329 dev->features = NETIF_F_IP_CSUM;
1330
1331 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1332 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
1333
1334 err = register_netdev(dev);
1335 if (err)
1336 goto out_stop;
1337
1338 mii_check_media(&ip->mii, 1, 1);
1339 ioc3_setup_duplex(ip);
1340
1341 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
1342 model = (sw_physid2 >> 4) & 0x3f;
1343 rev = sw_physid2 & 0xf;
1344 printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
1345 "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
1346 printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
1347 ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1348
1349 return 0;
1350
1351out_stop:
1352 ioc3_stop(ip);
1353 del_timer_sync(&ip->ioc3_timer);
1354 ioc3_free_rings(ip);
1355out_res:
1356 pci_release_regions(pdev);
1357out_free:
1358 free_netdev(dev);
1359out_disable:
1360
1361
1362
1363
1364out:
1365 return err;
1366}
1367
1368static void __devexit ioc3_remove_one (struct pci_dev *pdev)
1369{
1370 struct net_device *dev = pci_get_drvdata(pdev);
1371 struct ioc3_private *ip = netdev_priv(dev);
1372 struct ioc3 *ioc3 = ip->regs;
1373
1374 unregister_netdev(dev);
1375 del_timer_sync(&ip->ioc3_timer);
1376
1377 iounmap(ioc3);
1378 pci_release_regions(pdev);
1379 free_netdev(dev);
1380
1381
1382
1383
1384}
1385
1386static struct pci_device_id ioc3_pci_tbl[] = {
1387 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1388 { 0 }
1389};
1390MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1391
1392static struct pci_driver ioc3_driver = {
1393 .name = "ioc3-eth",
1394 .id_table = ioc3_pci_tbl,
1395 .probe = ioc3_probe,
1396 .remove = __devexit_p(ioc3_remove_one),
1397};
1398
1399static int __init ioc3_init_module(void)
1400{
1401 return pci_register_driver(&ioc3_driver);
1402}
1403
1404static void __exit ioc3_cleanup_module(void)
1405{
1406 pci_unregister_driver(&ioc3_driver);
1407}
1408
1409static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1410{
1411 unsigned long data;
1412 struct ioc3_private *ip = netdev_priv(dev);
1413 struct ioc3 *ioc3 = ip->regs;
1414 unsigned int len;
1415 struct ioc3_etxd *desc;
1416 uint32_t w0 = 0;
1417 int produce;
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1428 const struct iphdr *ih = ip_hdr(skb);
1429 const int proto = ntohs(ih->protocol);
1430 unsigned int csoff;
1431 uint32_t csum, ehsum;
1432 uint16_t *eh;
1433
1434
1435
1436 eh = (uint16_t *) skb->data;
1437
1438
1439 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1440
1441
1442 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1443 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1444
1445
1446
1447 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1448 ih->tot_len - (ih->ihl << 2),
1449 proto, 0xffff ^ ehsum);
1450
1451 csum = (csum & 0xffff) + (csum >> 16);
1452 csum = (csum & 0xffff) + (csum >> 16);
1453
1454 csoff = ETH_HLEN + (ih->ihl << 2);
1455 if (proto == IPPROTO_UDP) {
1456 csoff += offsetof(struct udphdr, check);
1457 udp_hdr(skb)->check = csum;
1458 }
1459 if (proto == IPPROTO_TCP) {
1460 csoff += offsetof(struct tcphdr, check);
1461 tcp_hdr(skb)->check = csum;
1462 }
1463
1464 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
1465 }
1466
1467 spin_lock_irq(&ip->ioc3_lock);
1468
1469 data = (unsigned long) skb->data;
1470 len = skb->len;
1471
1472 produce = ip->tx_pi;
1473 desc = &ip->txr[produce];
1474
1475 if (len <= 104) {
1476
1477 skb_copy_from_linear_data(skb, desc->data, skb->len);
1478 if (len < ETH_ZLEN) {
1479
1480 memset(desc->data + len, 0, ETH_ZLEN - len);
1481 len = ETH_ZLEN;
1482 }
1483 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
1484 desc->bufcnt = cpu_to_be32(len);
1485 } else if ((data ^ (data + len - 1)) & 0x4000) {
1486 unsigned long b2 = (data | 0x3fffUL) + 1UL;
1487 unsigned long s1 = b2 - data;
1488 unsigned long s2 = data + len - b2;
1489
1490 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
1491 ETXD_B1V | ETXD_B2V | w0);
1492 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
1493 (s2 << ETXD_B2CNT_SHIFT));
1494 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1495 desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
1496 } else {
1497
1498 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
1499 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1500 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1501 }
1502
1503 BARRIER();
1504
1505 dev->trans_start = jiffies;
1506 ip->tx_skbs[produce] = skb;
1507 produce = (produce + 1) & 127;
1508 ip->tx_pi = produce;
1509 ioc3_w_etpir(produce << 7);
1510
1511 ip->txqlen++;
1512
1513 if (ip->txqlen >= 127)
1514 netif_stop_queue(dev);
1515
1516 spin_unlock_irq(&ip->ioc3_lock);
1517
1518 return NETDEV_TX_OK;
1519}
1520
1521static void ioc3_timeout(struct net_device *dev)
1522{
1523 struct ioc3_private *ip = netdev_priv(dev);
1524
1525 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
1526
1527 spin_lock_irq(&ip->ioc3_lock);
1528
1529 ioc3_stop(ip);
1530 ioc3_init(dev);
1531 ioc3_mii_init(ip);
1532 ioc3_mii_start(ip);
1533
1534 spin_unlock_irq(&ip->ioc3_lock);
1535
1536 netif_wake_queue(dev);
1537}
1538
1539
1540
1541
1542
1543
1544static inline unsigned int ioc3_hash(const unsigned char *addr)
1545{
1546 unsigned int temp = 0;
1547 u32 crc;
1548 int bits;
1549
1550 crc = ether_crc_le(ETH_ALEN, addr);
1551
1552 crc &= 0x3f;
1553 for (bits = 6; --bits >= 0; ) {
1554 temp <<= 1;
1555 temp |= (crc & 0x1);
1556 crc >>= 1;
1557 }
1558
1559 return temp;
1560}
1561
1562static void ioc3_get_drvinfo (struct net_device *dev,
1563 struct ethtool_drvinfo *info)
1564{
1565 struct ioc3_private *ip = netdev_priv(dev);
1566
1567 strcpy (info->driver, IOC3_NAME);
1568 strcpy (info->version, IOC3_VERSION);
1569 strcpy (info->bus_info, pci_name(ip->pdev));
1570}
1571
1572static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1573{
1574 struct ioc3_private *ip = netdev_priv(dev);
1575 int rc;
1576
1577 spin_lock_irq(&ip->ioc3_lock);
1578 rc = mii_ethtool_gset(&ip->mii, cmd);
1579 spin_unlock_irq(&ip->ioc3_lock);
1580
1581 return rc;
1582}
1583
1584static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1585{
1586 struct ioc3_private *ip = netdev_priv(dev);
1587 int rc;
1588
1589 spin_lock_irq(&ip->ioc3_lock);
1590 rc = mii_ethtool_sset(&ip->mii, cmd);
1591 spin_unlock_irq(&ip->ioc3_lock);
1592
1593 return rc;
1594}
1595
1596static int ioc3_nway_reset(struct net_device *dev)
1597{
1598 struct ioc3_private *ip = netdev_priv(dev);
1599 int rc;
1600
1601 spin_lock_irq(&ip->ioc3_lock);
1602 rc = mii_nway_restart(&ip->mii);
1603 spin_unlock_irq(&ip->ioc3_lock);
1604
1605 return rc;
1606}
1607
1608static u32 ioc3_get_link(struct net_device *dev)
1609{
1610 struct ioc3_private *ip = netdev_priv(dev);
1611 int rc;
1612
1613 spin_lock_irq(&ip->ioc3_lock);
1614 rc = mii_link_ok(&ip->mii);
1615 spin_unlock_irq(&ip->ioc3_lock);
1616
1617 return rc;
1618}
1619
1620static u32 ioc3_get_rx_csum(struct net_device *dev)
1621{
1622 struct ioc3_private *ip = netdev_priv(dev);
1623
1624 return ip->flags & IOC3_FLAG_RX_CHECKSUMS;
1625}
1626
1627static int ioc3_set_rx_csum(struct net_device *dev, u32 data)
1628{
1629 struct ioc3_private *ip = netdev_priv(dev);
1630
1631 spin_lock_bh(&ip->ioc3_lock);
1632 if (data)
1633 ip->flags |= IOC3_FLAG_RX_CHECKSUMS;
1634 else
1635 ip->flags &= ~IOC3_FLAG_RX_CHECKSUMS;
1636 spin_unlock_bh(&ip->ioc3_lock);
1637
1638 return 0;
1639}
1640
1641static const struct ethtool_ops ioc3_ethtool_ops = {
1642 .get_drvinfo = ioc3_get_drvinfo,
1643 .get_settings = ioc3_get_settings,
1644 .set_settings = ioc3_set_settings,
1645 .nway_reset = ioc3_nway_reset,
1646 .get_link = ioc3_get_link,
1647 .get_rx_csum = ioc3_get_rx_csum,
1648 .set_rx_csum = ioc3_set_rx_csum,
1649 .get_tx_csum = ethtool_op_get_tx_csum,
1650 .set_tx_csum = ethtool_op_set_tx_csum
1651};
1652
1653static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1654{
1655 struct ioc3_private *ip = netdev_priv(dev);
1656 int rc;
1657
1658 spin_lock_irq(&ip->ioc3_lock);
1659 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
1660 spin_unlock_irq(&ip->ioc3_lock);
1661
1662 return rc;
1663}
1664
1665static void ioc3_set_multicast_list(struct net_device *dev)
1666{
1667 struct dev_mc_list *dmi = dev->mc_list;
1668 struct ioc3_private *ip = netdev_priv(dev);
1669 struct ioc3 *ioc3 = ip->regs;
1670 u64 ehar = 0;
1671 int i;
1672
1673 netif_stop_queue(dev);
1674
1675 if (dev->flags & IFF_PROMISC) {
1676 ip->emcr |= EMCR_PROMISC;
1677 ioc3_w_emcr(ip->emcr);
1678 (void) ioc3_r_emcr();
1679 } else {
1680 ip->emcr &= ~EMCR_PROMISC;
1681 ioc3_w_emcr(ip->emcr);
1682 (void) ioc3_r_emcr();
1683
1684 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1685
1686
1687
1688 ip->ehar_h = 0xffffffff;
1689 ip->ehar_l = 0xffffffff;
1690 } else {
1691 for (i = 0; i < dev->mc_count; i++) {
1692 char *addr = dmi->dmi_addr;
1693 dmi = dmi->next;
1694
1695 if (!(*addr & 1))
1696 continue;
1697
1698 ehar |= (1UL << ioc3_hash(addr));
1699 }
1700 ip->ehar_h = ehar >> 32;
1701 ip->ehar_l = ehar & 0xffffffff;
1702 }
1703 ioc3_w_ehar_h(ip->ehar_h);
1704 ioc3_w_ehar_l(ip->ehar_l);
1705 }
1706
1707 netif_wake_queue(dev);
1708}
1709
1710MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1711MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1712MODULE_LICENSE("GPL");
1713
1714module_init(ioc3_init_module);
1715module_exit(ioc3_cleanup_module);
1716