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30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/string.h>
33#include <linux/timer.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/init.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/delay.h>
46#include <linux/rtnetlink.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/bitops.h>
50#include <linux/prefetch.h>
51#include <asm/processor.h>
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#define DRV_NAME "natsemi"
57#define DRV_VERSION "2.1"
58#define DRV_RELDATE "Sept 11, 2006"
59
60#define RX_OFFSET 2
61
62
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64
65
66
67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72static int debug = -1;
73
74static int mtu;
75
76
77
78static const int multicast_filter_limit = 100;
79
80
81
82static int rx_copybreak;
83
84static int dspcfg_workaround = 1;
85
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89
90
91#define MAX_UNITS 8
92static int options[MAX_UNITS];
93static int full_duplex[MAX_UNITS];
94
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100
101
102#define TX_RING_SIZE 16
103#define TX_QUEUE_LEN 10
104#define RX_RING_SIZE 32
105
106
107
108#define TX_TIMEOUT (2*HZ)
109
110#define NATSEMI_HW_TIMEOUT 400
111#define NATSEMI_TIMER_FREQ 5*HZ
112#define NATSEMI_PG0_NREGS 64
113#define NATSEMI_RFDR_NREGS 8
114#define NATSEMI_PG1_NREGS 4
115#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
116 NATSEMI_PG1_NREGS)
117#define NATSEMI_REGS_VER 1
118#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
119
120
121
122
123
124#define NATSEMI_HEADERS 22
125#define NATSEMI_PADDING 16
126#define NATSEMI_LONGPKT 1518
127#define NATSEMI_RX_LIMIT 2046
128
129
130static const char version[] __devinitconst =
131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 " originally by Donald Becker <becker@scyld.com>\n"
134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
135
136MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138MODULE_LICENSE("GPL");
139
140module_param(mtu, int, 0);
141module_param(debug, int, 0);
142module_param(rx_copybreak, int, 0);
143module_param(dspcfg_workaround, int, 1);
144module_param_array(options, int, NULL, 0);
145module_param_array(full_duplex, int, NULL, 0);
146MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147MODULE_PARM_DESC(debug, "DP8381x default debug level");
148MODULE_PARM_DESC(rx_copybreak,
149 "DP8381x copy breakpoint for copy-only-tiny-frames");
150MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
151MODULE_PARM_DESC(options,
152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
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227
228#define PHYID_AM79C874 0x0022561b
229
230enum {
231 MII_MCTRL = 0x15,
232 MII_FX_SEL = 0x0001,
233 MII_EN_SCRM = 0x0004,
234};
235
236enum {
237 NATSEMI_FLAG_IGNORE_PHY = 0x1,
238};
239
240
241static struct {
242 const char *name;
243 unsigned long flags;
244 unsigned int eeprom_size;
245} natsemi_pci_info[] __devinitdata = {
246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
247 { "NatSemi DP8381[56]", 0, 24 },
248};
249
250static struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
253 { }
254};
255MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
256
257
258
259
260
261
262enum register_offsets {
263 ChipCmd = 0x00,
264 ChipConfig = 0x04,
265 EECtrl = 0x08,
266 PCIBusCfg = 0x0C,
267 IntrStatus = 0x10,
268 IntrMask = 0x14,
269 IntrEnable = 0x18,
270 IntrHoldoff = 0x1C,
271 TxRingPtr = 0x20,
272 TxConfig = 0x24,
273 RxRingPtr = 0x30,
274 RxConfig = 0x34,
275 ClkRun = 0x3C,
276 WOLCmd = 0x40,
277 PauseCmd = 0x44,
278 RxFilterAddr = 0x48,
279 RxFilterData = 0x4C,
280 BootRomAddr = 0x50,
281 BootRomData = 0x54,
282 SiliconRev = 0x58,
283 StatsCtrl = 0x5C,
284 StatsData = 0x60,
285 RxPktErrs = 0x60,
286 RxMissed = 0x68,
287 RxCRCErrs = 0x64,
288 BasicControl = 0x80,
289 BasicStatus = 0x84,
290 AnegAdv = 0x90,
291 AnegPeer = 0x94,
292 PhyStatus = 0xC0,
293 MIntrCtrl = 0xC4,
294 MIntrStatus = 0xC8,
295 PhyCtrl = 0xE4,
296
297
298
299 PGSEL = 0xCC,
300 PMDCSR = 0xE4,
301 TSTDAT = 0xFC,
302 DSPCFG = 0xF4,
303 SDCFG = 0xF8
304};
305
306#define PMDCSR_VAL 0x189c
307#define TSTDAT_VAL 0x0
308#define DSPCFG_VAL 0x5040
309#define SDCFG_VAL 0x008c
310#define DSPCFG_LOCK 0x20
311#define DSPCFG_COEF 0x1000
312#define TSTDAT_FIXED 0xe8
313
314
315enum pci_register_offsets {
316 PCIPM = 0x44,
317};
318
319enum ChipCmd_bits {
320 ChipReset = 0x100,
321 RxReset = 0x20,
322 TxReset = 0x10,
323 RxOff = 0x08,
324 RxOn = 0x04,
325 TxOff = 0x02,
326 TxOn = 0x01,
327};
328
329enum ChipConfig_bits {
330 CfgPhyDis = 0x200,
331 CfgPhyRst = 0x400,
332 CfgExtPhy = 0x1000,
333 CfgAnegEnable = 0x2000,
334 CfgAneg100 = 0x4000,
335 CfgAnegFull = 0x8000,
336 CfgAnegDone = 0x8000000,
337 CfgFullDuplex = 0x20000000,
338 CfgSpeed100 = 0x40000000,
339 CfgLink = 0x80000000,
340};
341
342enum EECtrl_bits {
343 EE_ShiftClk = 0x04,
344 EE_DataIn = 0x01,
345 EE_ChipSelect = 0x08,
346 EE_DataOut = 0x02,
347 MII_Data = 0x10,
348 MII_Write = 0x20,
349 MII_ShiftClk = 0x40,
350};
351
352enum PCIBusCfg_bits {
353 EepromReload = 0x4,
354};
355
356
357enum IntrStatus_bits {
358 IntrRxDone = 0x0001,
359 IntrRxIntr = 0x0002,
360 IntrRxErr = 0x0004,
361 IntrRxEarly = 0x0008,
362 IntrRxIdle = 0x0010,
363 IntrRxOverrun = 0x0020,
364 IntrTxDone = 0x0040,
365 IntrTxIntr = 0x0080,
366 IntrTxErr = 0x0100,
367 IntrTxIdle = 0x0200,
368 IntrTxUnderrun = 0x0400,
369 StatsMax = 0x0800,
370 SWInt = 0x1000,
371 WOLPkt = 0x2000,
372 LinkChange = 0x4000,
373 IntrHighBits = 0x8000,
374 RxStatusFIFOOver = 0x10000,
375 IntrPCIErr = 0xf00000,
376 RxResetDone = 0x1000000,
377 TxResetDone = 0x2000000,
378 IntrAbnormalSummary = 0xCD20,
379};
380
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389
390#define DEFAULT_INTR 0x00f1cd65
391
392enum TxConfig_bits {
393 TxDrthMask = 0x3f,
394 TxFlthMask = 0x3f00,
395 TxMxdmaMask = 0x700000,
396 TxMxdma_512 = 0x0,
397 TxMxdma_4 = 0x100000,
398 TxMxdma_8 = 0x200000,
399 TxMxdma_16 = 0x300000,
400 TxMxdma_32 = 0x400000,
401 TxMxdma_64 = 0x500000,
402 TxMxdma_128 = 0x600000,
403 TxMxdma_256 = 0x700000,
404 TxCollRetry = 0x800000,
405 TxAutoPad = 0x10000000,
406 TxMacLoop = 0x20000000,
407 TxHeartIgn = 0x40000000,
408 TxCarrierIgn = 0x80000000
409};
410
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420
421
422#define TX_FLTH_VAL ((512/32) << 8)
423#define TX_DRTH_VAL_START (64/32)
424#define TX_DRTH_VAL_INC 2
425#define TX_DRTH_VAL_LIMIT (1472/32)
426
427enum RxConfig_bits {
428 RxDrthMask = 0x3e,
429 RxMxdmaMask = 0x700000,
430 RxMxdma_512 = 0x0,
431 RxMxdma_4 = 0x100000,
432 RxMxdma_8 = 0x200000,
433 RxMxdma_16 = 0x300000,
434 RxMxdma_32 = 0x400000,
435 RxMxdma_64 = 0x500000,
436 RxMxdma_128 = 0x600000,
437 RxMxdma_256 = 0x700000,
438 RxAcceptLong = 0x8000000,
439 RxAcceptTx = 0x10000000,
440 RxAcceptRunt = 0x40000000,
441 RxAcceptErr = 0x80000000
442};
443#define RX_DRTH_VAL (128/8)
444
445enum ClkRun_bits {
446 PMEEnable = 0x100,
447 PMEStatus = 0x8000,
448};
449
450enum WolCmd_bits {
451 WakePhy = 0x1,
452 WakeUnicast = 0x2,
453 WakeMulticast = 0x4,
454 WakeBroadcast = 0x8,
455 WakeArp = 0x10,
456 WakePMatch0 = 0x20,
457 WakePMatch1 = 0x40,
458 WakePMatch2 = 0x80,
459 WakePMatch3 = 0x100,
460 WakeMagic = 0x200,
461 WakeMagicSecure = 0x400,
462 SecureHack = 0x100000,
463 WokePhy = 0x400000,
464 WokeUnicast = 0x800000,
465 WokeMulticast = 0x1000000,
466 WokeBroadcast = 0x2000000,
467 WokeArp = 0x4000000,
468 WokePMatch0 = 0x8000000,
469 WokePMatch1 = 0x10000000,
470 WokePMatch2 = 0x20000000,
471 WokePMatch3 = 0x40000000,
472 WokeMagic = 0x80000000,
473 WakeOptsSummary = 0x7ff
474};
475
476enum RxFilterAddr_bits {
477 RFCRAddressMask = 0x3ff,
478 AcceptMulticast = 0x00200000,
479 AcceptMyPhys = 0x08000000,
480 AcceptAllPhys = 0x10000000,
481 AcceptAllMulticast = 0x20000000,
482 AcceptBroadcast = 0x40000000,
483 RxFilterEnable = 0x80000000
484};
485
486enum StatsCtrl_bits {
487 StatsWarn = 0x1,
488 StatsFreeze = 0x2,
489 StatsClear = 0x4,
490 StatsStrobe = 0x8,
491};
492
493enum MIntrCtrl_bits {
494 MICRIntEn = 0x2,
495};
496
497enum PhyCtrl_bits {
498 PhyAddrMask = 0x1f,
499};
500
501#define PHY_ADDR_NONE 32
502#define PHY_ADDR_INTERNAL 1
503
504
505#define SRR_DP83815_C 0x0302
506#define SRR_DP83815_D 0x0403
507#define SRR_DP83816_A4 0x0504
508#define SRR_DP83816_A5 0x0505
509
510
511
512
513struct netdev_desc {
514 __le32 next_desc;
515 __le32 cmd_status;
516 __le32 addr;
517 __le32 software_use;
518};
519
520
521enum desc_status_bits {
522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
523 DescNoCRC=0x10000000, DescPktOK=0x08000000,
524 DescSizeMask=0xfff,
525
526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
530
531 DescRxAbort=0x04000000, DescRxOver=0x02000000,
532 DescRxDest=0x01800000, DescRxLong=0x00400000,
533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
534 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
535 DescRxLoop=0x00020000, DesRxColl=0x00010000,
536};
537
538struct netdev_private {
539
540 dma_addr_t ring_dma;
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543
544 struct sk_buff *rx_skbuff[RX_RING_SIZE];
545 dma_addr_t rx_dma[RX_RING_SIZE];
546
547 struct sk_buff *tx_skbuff[TX_RING_SIZE];
548 dma_addr_t tx_dma[TX_RING_SIZE];
549 struct net_device *dev;
550 struct napi_struct napi;
551 struct net_device_stats stats;
552
553 struct timer_list timer;
554
555 struct pci_dev *pci_dev;
556 struct netdev_desc *rx_head_desc;
557
558 unsigned int cur_rx, dirty_rx;
559 unsigned int cur_tx, dirty_tx;
560
561 unsigned int rx_buf_sz;
562 int oom;
563
564 u32 intr_status;
565
566 int hands_off;
567
568 int ignore_phy;
569
570 int mii;
571 int phy_addr_external;
572 unsigned int full_duplex;
573
574 u32 cur_rx_mode;
575 u32 rx_filter[16];
576
577 u32 tx_config, rx_config;
578
579 u32 SavedClkRun;
580
581 u32 srr;
582
583 u16 dspcfg;
584 int dspcfg_workaround;
585
586 u16 speed;
587 u8 duplex;
588 u8 autoneg;
589
590 u16 advertising;
591 unsigned int iosize;
592 spinlock_t lock;
593 u32 msg_enable;
594
595 int eeprom_size;
596};
597
598static void move_int_phy(struct net_device *dev, int addr);
599static int eeprom_read(void __iomem *ioaddr, int location);
600static int mdio_read(struct net_device *dev, int reg);
601static void mdio_write(struct net_device *dev, int reg, u16 data);
602static void init_phy_fixup(struct net_device *dev);
603static int miiport_read(struct net_device *dev, int phy_id, int reg);
604static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
605static int find_mii(struct net_device *dev);
606static void natsemi_reset(struct net_device *dev);
607static void natsemi_reload_eeprom(struct net_device *dev);
608static void natsemi_stop_rxtx(struct net_device *dev);
609static int netdev_open(struct net_device *dev);
610static void do_cable_magic(struct net_device *dev);
611static void undo_cable_magic(struct net_device *dev);
612static void check_link(struct net_device *dev);
613static void netdev_timer(unsigned long data);
614static void dump_ring(struct net_device *dev);
615static void ns_tx_timeout(struct net_device *dev);
616static int alloc_ring(struct net_device *dev);
617static void refill_rx(struct net_device *dev);
618static void init_ring(struct net_device *dev);
619static void drain_tx(struct net_device *dev);
620static void drain_ring(struct net_device *dev);
621static void free_ring(struct net_device *dev);
622static void reinit_ring(struct net_device *dev);
623static void init_registers(struct net_device *dev);
624static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
625static irqreturn_t intr_handler(int irq, void *dev_instance);
626static void netdev_error(struct net_device *dev, int intr_status);
627static int natsemi_poll(struct napi_struct *napi, int budget);
628static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
629static void netdev_tx_done(struct net_device *dev);
630static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
631#ifdef CONFIG_NET_POLL_CONTROLLER
632static void natsemi_poll_controller(struct net_device *dev);
633#endif
634static void __set_rx_mode(struct net_device *dev);
635static void set_rx_mode(struct net_device *dev);
636static void __get_stats(struct net_device *dev);
637static struct net_device_stats *get_stats(struct net_device *dev);
638static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
639static int netdev_set_wol(struct net_device *dev, u32 newval);
640static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
641static int netdev_set_sopass(struct net_device *dev, u8 *newval);
642static int netdev_get_sopass(struct net_device *dev, u8 *data);
643static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
644static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
645static void enable_wol_mode(struct net_device *dev, int enable_intr);
646static int netdev_close(struct net_device *dev);
647static int netdev_get_regs(struct net_device *dev, u8 *buf);
648static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
649static const struct ethtool_ops ethtool_ops;
650
651#define NATSEMI_ATTR(_name) \
652static ssize_t natsemi_show_##_name(struct device *dev, \
653 struct device_attribute *attr, char *buf); \
654 static ssize_t natsemi_set_##_name(struct device *dev, \
655 struct device_attribute *attr, \
656 const char *buf, size_t count); \
657 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
658
659#define NATSEMI_CREATE_FILE(_dev, _name) \
660 device_create_file(&_dev->dev, &dev_attr_##_name)
661#define NATSEMI_REMOVE_FILE(_dev, _name) \
662 device_remove_file(&_dev->dev, &dev_attr_##_name)
663
664NATSEMI_ATTR(dspcfg_workaround);
665
666static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
667 struct device_attribute *attr,
668 char *buf)
669{
670 struct netdev_private *np = netdev_priv(to_net_dev(dev));
671
672 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
673}
674
675static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
676 struct device_attribute *attr,
677 const char *buf, size_t count)
678{
679 struct netdev_private *np = netdev_priv(to_net_dev(dev));
680 int new_setting;
681 unsigned long flags;
682
683
684 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
685 new_setting = 1;
686 else if (!strncmp("off", buf, count - 1)
687 || !strncmp("0", buf, count - 1))
688 new_setting = 0;
689 else
690 return count;
691
692 spin_lock_irqsave(&np->lock, flags);
693
694 np->dspcfg_workaround = new_setting;
695
696 spin_unlock_irqrestore(&np->lock, flags);
697
698 return count;
699}
700
701static inline void __iomem *ns_ioaddr(struct net_device *dev)
702{
703 return (void __iomem *) dev->base_addr;
704}
705
706static inline void natsemi_irq_enable(struct net_device *dev)
707{
708 writel(1, ns_ioaddr(dev) + IntrEnable);
709 readl(ns_ioaddr(dev) + IntrEnable);
710}
711
712static inline void natsemi_irq_disable(struct net_device *dev)
713{
714 writel(0, ns_ioaddr(dev) + IntrEnable);
715 readl(ns_ioaddr(dev) + IntrEnable);
716}
717
718static void move_int_phy(struct net_device *dev, int addr)
719{
720 struct netdev_private *np = netdev_priv(dev);
721 void __iomem *ioaddr = ns_ioaddr(dev);
722 int target = 31;
723
724
725
726
727
728
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731
732
733
734 if (target == addr)
735 target--;
736 if (target == np->phy_addr_external)
737 target--;
738 writew(target, ioaddr + PhyCtrl);
739 readw(ioaddr + PhyCtrl);
740 udelay(1);
741}
742
743static void __devinit natsemi_init_media (struct net_device *dev)
744{
745 struct netdev_private *np = netdev_priv(dev);
746 u32 tmp;
747
748 if (np->ignore_phy)
749 netif_carrier_on(dev);
750 else
751 netif_carrier_off(dev);
752
753
754 tmp = mdio_read(dev, MII_BMCR);
755 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
756 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
757 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
758 np->advertising= mdio_read(dev, MII_ADVERTISE);
759
760 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
761 && netif_msg_probe(np)) {
762 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
763 "10%s %s duplex.\n",
764 pci_name(np->pci_dev),
765 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
766 "enabled, advertise" : "disabled, force",
767 (np->advertising &
768 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
769 "0" : "",
770 (np->advertising &
771 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
772 "full" : "half");
773 }
774 if (netif_msg_probe(np))
775 printk(KERN_INFO
776 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
777 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
778 np->advertising);
779
780}
781
782static const struct net_device_ops natsemi_netdev_ops = {
783 .ndo_open = netdev_open,
784 .ndo_stop = netdev_close,
785 .ndo_start_xmit = start_tx,
786 .ndo_get_stats = get_stats,
787 .ndo_set_multicast_list = set_rx_mode,
788 .ndo_change_mtu = natsemi_change_mtu,
789 .ndo_do_ioctl = netdev_ioctl,
790 .ndo_tx_timeout = ns_tx_timeout,
791 .ndo_set_mac_address = eth_mac_addr,
792 .ndo_validate_addr = eth_validate_addr,
793#ifdef CONFIG_NET_POLL_CONTROLLER
794 .ndo_poll_controller = natsemi_poll_controller,
795#endif
796};
797
798static int __devinit natsemi_probe1 (struct pci_dev *pdev,
799 const struct pci_device_id *ent)
800{
801 struct net_device *dev;
802 struct netdev_private *np;
803 int i, option, irq, chip_idx = ent->driver_data;
804 static int find_cnt = -1;
805 resource_size_t iostart;
806 unsigned long iosize;
807 void __iomem *ioaddr;
808 const int pcibar = 1;
809 int prev_eedata;
810 u32 tmp;
811
812
813#ifndef MODULE
814 static int printed_version;
815 if (!printed_version++)
816 printk(version);
817#endif
818
819 i = pci_enable_device(pdev);
820 if (i) return i;
821
822
823
824
825
826 pci_read_config_dword(pdev, PCIPM, &tmp);
827 if (tmp & PCI_PM_CTRL_STATE_MASK) {
828
829 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
830 pci_write_config_dword(pdev, PCIPM, newtmp);
831 }
832
833 find_cnt++;
834 iostart = pci_resource_start(pdev, pcibar);
835 iosize = pci_resource_len(pdev, pcibar);
836 irq = pdev->irq;
837
838 pci_set_master(pdev);
839
840 dev = alloc_etherdev(sizeof (struct netdev_private));
841 if (!dev)
842 return -ENOMEM;
843 SET_NETDEV_DEV(dev, &pdev->dev);
844
845 i = pci_request_regions(pdev, DRV_NAME);
846 if (i)
847 goto err_pci_request_regions;
848
849 ioaddr = ioremap(iostart, iosize);
850 if (!ioaddr) {
851 i = -ENOMEM;
852 goto err_ioremap;
853 }
854
855
856 prev_eedata = eeprom_read(ioaddr, 6);
857 for (i = 0; i < 3; i++) {
858 int eedata = eeprom_read(ioaddr, i + 7);
859 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
860 dev->dev_addr[i*2+1] = eedata >> 7;
861 prev_eedata = eedata;
862 }
863
864 dev->base_addr = (unsigned long __force) ioaddr;
865 dev->irq = irq;
866
867 np = netdev_priv(dev);
868 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
869 np->dev = dev;
870
871 np->pci_dev = pdev;
872 pci_set_drvdata(pdev, dev);
873 np->iosize = iosize;
874 spin_lock_init(&np->lock);
875 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
876 np->hands_off = 0;
877 np->intr_status = 0;
878 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
879 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
880 np->ignore_phy = 1;
881 else
882 np->ignore_phy = 0;
883 np->dspcfg_workaround = dspcfg_workaround;
884
885
886
887
888
889
890
891
892
893
894 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
895 dev->if_port = PORT_MII;
896 else
897 dev->if_port = PORT_TP;
898
899 natsemi_reload_eeprom(dev);
900 natsemi_reset(dev);
901
902 if (dev->if_port != PORT_TP) {
903 np->phy_addr_external = find_mii(dev);
904
905
906 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
907 dev->if_port = PORT_TP;
908 np->phy_addr_external = PHY_ADDR_INTERNAL;
909 }
910 } else {
911 np->phy_addr_external = PHY_ADDR_INTERNAL;
912 }
913
914 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
915 if (dev->mem_start)
916 option = dev->mem_start;
917
918
919 if (option) {
920 if (option & 0x200)
921 np->full_duplex = 1;
922 if (option & 15)
923 printk(KERN_INFO
924 "natsemi %s: ignoring user supplied media type %d",
925 pci_name(np->pci_dev), option & 15);
926 }
927 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
928 np->full_duplex = 1;
929
930 dev->netdev_ops = &natsemi_netdev_ops;
931 dev->watchdog_timeo = TX_TIMEOUT;
932
933 SET_ETHTOOL_OPS(dev, ðtool_ops);
934
935 if (mtu)
936 dev->mtu = mtu;
937
938 natsemi_init_media(dev);
939
940
941 np->srr = readl(ioaddr + SiliconRev);
942 if (netif_msg_hw(np))
943 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
944 pci_name(np->pci_dev), np->srr);
945
946 i = register_netdev(dev);
947 if (i)
948 goto err_register_netdev;
949
950 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
951 goto err_create_file;
952
953 if (netif_msg_drv(np)) {
954 printk(KERN_INFO "natsemi %s: %s at %#08llx "
955 "(%s), %pM, IRQ %d",
956 dev->name, natsemi_pci_info[chip_idx].name,
957 (unsigned long long)iostart, pci_name(np->pci_dev),
958 dev->dev_addr, irq);
959 if (dev->if_port == PORT_TP)
960 printk(", port TP.\n");
961 else if (np->ignore_phy)
962 printk(", port MII, ignoring PHY\n");
963 else
964 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
965 }
966 return 0;
967
968 err_create_file:
969 unregister_netdev(dev);
970
971 err_register_netdev:
972 iounmap(ioaddr);
973
974 err_ioremap:
975 pci_release_regions(pdev);
976 pci_set_drvdata(pdev, NULL);
977
978 err_pci_request_regions:
979 free_netdev(dev);
980 return i;
981}
982
983
984
985
986
987
988
989
990
991
992
993
994#define eeprom_delay(ee_addr) readl(ee_addr)
995
996#define EE_Write0 (EE_ChipSelect)
997#define EE_Write1 (EE_ChipSelect | EE_DataIn)
998
999
1000enum EEPROM_Cmds {
1001 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1002};
1003
1004static int eeprom_read(void __iomem *addr, int location)
1005{
1006 int i;
1007 int retval = 0;
1008 void __iomem *ee_addr = addr + EECtrl;
1009 int read_cmd = location | EE_ReadCmd;
1010
1011 writel(EE_Write0, ee_addr);
1012
1013
1014 for (i = 10; i >= 0; i--) {
1015 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1016 writel(dataval, ee_addr);
1017 eeprom_delay(ee_addr);
1018 writel(dataval | EE_ShiftClk, ee_addr);
1019 eeprom_delay(ee_addr);
1020 }
1021 writel(EE_ChipSelect, ee_addr);
1022 eeprom_delay(ee_addr);
1023
1024 for (i = 0; i < 16; i++) {
1025 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1026 eeprom_delay(ee_addr);
1027 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1028 writel(EE_ChipSelect, ee_addr);
1029 eeprom_delay(ee_addr);
1030 }
1031
1032
1033 writel(EE_Write0, ee_addr);
1034 writel(0, ee_addr);
1035 return retval;
1036}
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1048
1049static int mii_getbit (struct net_device *dev)
1050{
1051 int data;
1052 void __iomem *ioaddr = ns_ioaddr(dev);
1053
1054 writel(MII_ShiftClk, ioaddr + EECtrl);
1055 data = readl(ioaddr + EECtrl);
1056 writel(0, ioaddr + EECtrl);
1057 mii_delay(ioaddr);
1058 return (data & MII_Data)? 1 : 0;
1059}
1060
1061static void mii_send_bits (struct net_device *dev, u32 data, int len)
1062{
1063 u32 i;
1064 void __iomem *ioaddr = ns_ioaddr(dev);
1065
1066 for (i = (1 << (len-1)); i; i >>= 1)
1067 {
1068 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1069 writel(mdio_val, ioaddr + EECtrl);
1070 mii_delay(ioaddr);
1071 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1072 mii_delay(ioaddr);
1073 }
1074 writel(0, ioaddr + EECtrl);
1075 mii_delay(ioaddr);
1076}
1077
1078static int miiport_read(struct net_device *dev, int phy_id, int reg)
1079{
1080 u32 cmd;
1081 int i;
1082 u32 retval = 0;
1083
1084
1085 mii_send_bits (dev, 0xffffffff, 32);
1086
1087
1088 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1089 mii_send_bits (dev, cmd, 14);
1090
1091 if (mii_getbit (dev))
1092 return 0;
1093
1094 for (i = 0; i < 16; i++) {
1095 retval <<= 1;
1096 retval |= mii_getbit (dev);
1097 }
1098
1099 mii_getbit (dev);
1100 return retval;
1101}
1102
1103static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1104{
1105 u32 cmd;
1106
1107
1108 mii_send_bits (dev, 0xffffffff, 32);
1109
1110
1111 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1112 mii_send_bits (dev, cmd, 32);
1113
1114 mii_getbit (dev);
1115}
1116
1117static int mdio_read(struct net_device *dev, int reg)
1118{
1119 struct netdev_private *np = netdev_priv(dev);
1120 void __iomem *ioaddr = ns_ioaddr(dev);
1121
1122
1123
1124
1125
1126 if (dev->if_port == PORT_TP)
1127 return readw(ioaddr+BasicControl+(reg<<2));
1128 else
1129 return miiport_read(dev, np->phy_addr_external, reg);
1130}
1131
1132static void mdio_write(struct net_device *dev, int reg, u16 data)
1133{
1134 struct netdev_private *np = netdev_priv(dev);
1135 void __iomem *ioaddr = ns_ioaddr(dev);
1136
1137
1138 if (dev->if_port == PORT_TP)
1139 writew(data, ioaddr+BasicControl+(reg<<2));
1140 else
1141 miiport_write(dev, np->phy_addr_external, reg, data);
1142}
1143
1144static void init_phy_fixup(struct net_device *dev)
1145{
1146 struct netdev_private *np = netdev_priv(dev);
1147 void __iomem *ioaddr = ns_ioaddr(dev);
1148 int i;
1149 u32 cfg;
1150 u16 tmp;
1151
1152
1153 tmp = mdio_read(dev, MII_BMCR);
1154 if (np->autoneg == AUTONEG_ENABLE) {
1155
1156 if ((tmp & BMCR_ANENABLE) == 0
1157 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1158 {
1159
1160 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1161 mdio_write(dev, MII_ADVERTISE, np->advertising);
1162 }
1163 } else {
1164
1165 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1166 if (np->speed == SPEED_100)
1167 tmp |= BMCR_SPEED100;
1168 if (np->duplex == DUPLEX_FULL)
1169 tmp |= BMCR_FULLDPLX;
1170
1171
1172
1173
1174
1175
1176
1177 }
1178 mdio_write(dev, MII_BMCR, tmp);
1179 readl(ioaddr + ChipConfig);
1180 udelay(1);
1181
1182
1183 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1184 + mdio_read(dev, MII_PHYSID2);
1185
1186
1187 switch (np->mii) {
1188 case PHYID_AM79C874:
1189
1190 tmp = mdio_read(dev, MII_MCTRL);
1191 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1192 if (dev->if_port == PORT_FIBRE)
1193 tmp |= MII_FX_SEL;
1194 else
1195 tmp |= MII_EN_SCRM;
1196 mdio_write(dev, MII_MCTRL, tmp);
1197 break;
1198 default:
1199 break;
1200 }
1201 cfg = readl(ioaddr + ChipConfig);
1202 if (cfg & CfgExtPhy)
1203 return;
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1217
1218 int dspcfg;
1219 writew(1, ioaddr + PGSEL);
1220 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1221 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1222 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1223 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1224 writew(np->dspcfg, ioaddr + DSPCFG);
1225 writew(SDCFG_VAL, ioaddr + SDCFG);
1226 writew(0, ioaddr + PGSEL);
1227 readl(ioaddr + ChipConfig);
1228 udelay(10);
1229
1230 writew(1, ioaddr + PGSEL);
1231 dspcfg = readw(ioaddr + DSPCFG);
1232 writew(0, ioaddr + PGSEL);
1233 if (np->dspcfg == dspcfg)
1234 break;
1235 }
1236
1237 if (netif_msg_link(np)) {
1238 if (i==NATSEMI_HW_TIMEOUT) {
1239 printk(KERN_INFO
1240 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1241 dev->name, i*10);
1242 } else {
1243 printk(KERN_INFO
1244 "%s: DSPCFG accepted after %d usec.\n",
1245 dev->name, i*10);
1246 }
1247 }
1248
1249
1250
1251
1252
1253 readw(ioaddr + MIntrStatus);
1254 writew(MICRIntEn, ioaddr + MIntrCtrl);
1255}
1256
1257static int switch_port_external(struct net_device *dev)
1258{
1259 struct netdev_private *np = netdev_priv(dev);
1260 void __iomem *ioaddr = ns_ioaddr(dev);
1261 u32 cfg;
1262
1263 cfg = readl(ioaddr + ChipConfig);
1264 if (cfg & CfgExtPhy)
1265 return 0;
1266
1267 if (netif_msg_link(np)) {
1268 printk(KERN_INFO "%s: switching to external transceiver.\n",
1269 dev->name);
1270 }
1271
1272
1273 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1274 readl(ioaddr + ChipConfig);
1275 udelay(1);
1276
1277
1278
1279
1280
1281
1282
1283
1284 move_int_phy(dev, np->phy_addr_external);
1285 init_phy_fixup(dev);
1286
1287 return 1;
1288}
1289
1290static int switch_port_internal(struct net_device *dev)
1291{
1292 struct netdev_private *np = netdev_priv(dev);
1293 void __iomem *ioaddr = ns_ioaddr(dev);
1294 int i;
1295 u32 cfg;
1296 u16 bmcr;
1297
1298 cfg = readl(ioaddr + ChipConfig);
1299 if (!(cfg &CfgExtPhy))
1300 return 0;
1301
1302 if (netif_msg_link(np)) {
1303 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1304 dev->name);
1305 }
1306
1307 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1308 writel(cfg, ioaddr + ChipConfig);
1309 readl(ioaddr + ChipConfig);
1310 udelay(1);
1311
1312
1313 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1314 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1315 readl(ioaddr + ChipConfig);
1316 udelay(10);
1317 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1318 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1319 if (!(bmcr & BMCR_RESET))
1320 break;
1321 udelay(10);
1322 }
1323 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1324 printk(KERN_INFO
1325 "%s: phy reset did not complete in %d usec.\n",
1326 dev->name, i*10);
1327 }
1328
1329 init_phy_fixup(dev);
1330
1331 return 1;
1332}
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342static int find_mii(struct net_device *dev)
1343{
1344 struct netdev_private *np = netdev_priv(dev);
1345 int tmp;
1346 int i;
1347 int did_switch;
1348
1349
1350 did_switch = switch_port_external(dev);
1351
1352
1353
1354
1355
1356
1357
1358 for (i = 1; i <= 31; i++) {
1359 move_int_phy(dev, i);
1360 tmp = miiport_read(dev, i, MII_BMSR);
1361 if (tmp != 0xffff && tmp != 0x0000) {
1362
1363 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1364 + mdio_read(dev, MII_PHYSID2);
1365 if (netif_msg_probe(np)) {
1366 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1367 pci_name(np->pci_dev), np->mii, i);
1368 }
1369 break;
1370 }
1371 }
1372
1373 if (did_switch)
1374 switch_port_internal(dev);
1375 return i;
1376}
1377
1378
1379#define CFG_RESET_SAVE 0xfde000
1380
1381#define WCSR_RESET_SAVE 0x61f
1382
1383#define RFCR_RESET_SAVE 0xf8500000;
1384
1385static void natsemi_reset(struct net_device *dev)
1386{
1387 int i;
1388 u32 cfg;
1389 u32 wcsr;
1390 u32 rfcr;
1391 u16 pmatch[3];
1392 u16 sopass[3];
1393 struct netdev_private *np = netdev_priv(dev);
1394 void __iomem *ioaddr = ns_ioaddr(dev);
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1406
1407 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1408
1409 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1410
1411 for (i = 0; i < 3; i++) {
1412 writel(i*2, ioaddr + RxFilterAddr);
1413 pmatch[i] = readw(ioaddr + RxFilterData);
1414 }
1415
1416 for (i = 0; i < 3; i++) {
1417 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1418 sopass[i] = readw(ioaddr + RxFilterData);
1419 }
1420
1421
1422 writel(ChipReset, ioaddr + ChipCmd);
1423 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1424 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1425 break;
1426 udelay(5);
1427 }
1428 if (i==NATSEMI_HW_TIMEOUT) {
1429 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1430 dev->name, i*5);
1431 } else if (netif_msg_hw(np)) {
1432 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1433 dev->name, i*5);
1434 }
1435
1436
1437 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1438
1439 if (dev->if_port == PORT_TP)
1440 cfg &= ~(CfgExtPhy | CfgPhyDis);
1441 else
1442 cfg |= (CfgExtPhy | CfgPhyDis);
1443 writel(cfg, ioaddr + ChipConfig);
1444
1445 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1446 writel(wcsr, ioaddr + WOLCmd);
1447
1448 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1449
1450 for (i = 0; i < 3; i++) {
1451 writel(i*2, ioaddr + RxFilterAddr);
1452 writew(pmatch[i], ioaddr + RxFilterData);
1453 }
1454 for (i = 0; i < 3; i++) {
1455 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1456 writew(sopass[i], ioaddr + RxFilterData);
1457 }
1458
1459 writel(rfcr, ioaddr + RxFilterAddr);
1460}
1461
1462static void reset_rx(struct net_device *dev)
1463{
1464 int i;
1465 struct netdev_private *np = netdev_priv(dev);
1466 void __iomem *ioaddr = ns_ioaddr(dev);
1467
1468 np->intr_status &= ~RxResetDone;
1469
1470 writel(RxReset, ioaddr + ChipCmd);
1471
1472 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1473 np->intr_status |= readl(ioaddr + IntrStatus);
1474 if (np->intr_status & RxResetDone)
1475 break;
1476 udelay(15);
1477 }
1478 if (i==NATSEMI_HW_TIMEOUT) {
1479 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1480 dev->name, i*15);
1481 } else if (netif_msg_hw(np)) {
1482 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1483 dev->name, i*15);
1484 }
1485}
1486
1487static void natsemi_reload_eeprom(struct net_device *dev)
1488{
1489 struct netdev_private *np = netdev_priv(dev);
1490 void __iomem *ioaddr = ns_ioaddr(dev);
1491 int i;
1492
1493 writel(EepromReload, ioaddr + PCIBusCfg);
1494 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1495 udelay(50);
1496 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1497 break;
1498 }
1499 if (i==NATSEMI_HW_TIMEOUT) {
1500 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1501 pci_name(np->pci_dev), i*50);
1502 } else if (netif_msg_hw(np)) {
1503 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1504 pci_name(np->pci_dev), i*50);
1505 }
1506}
1507
1508static void natsemi_stop_rxtx(struct net_device *dev)
1509{
1510 void __iomem * ioaddr = ns_ioaddr(dev);
1511 struct netdev_private *np = netdev_priv(dev);
1512 int i;
1513
1514 writel(RxOff | TxOff, ioaddr + ChipCmd);
1515 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1516 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1517 break;
1518 udelay(5);
1519 }
1520 if (i==NATSEMI_HW_TIMEOUT) {
1521 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1522 dev->name, i*5);
1523 } else if (netif_msg_hw(np)) {
1524 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1525 dev->name, i*5);
1526 }
1527}
1528
1529static int netdev_open(struct net_device *dev)
1530{
1531 struct netdev_private *np = netdev_priv(dev);
1532 void __iomem * ioaddr = ns_ioaddr(dev);
1533 int i;
1534
1535
1536 natsemi_reset(dev);
1537
1538 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
1539 if (i) return i;
1540
1541 if (netif_msg_ifup(np))
1542 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1543 dev->name, dev->irq);
1544 i = alloc_ring(dev);
1545 if (i < 0) {
1546 free_irq(dev->irq, dev);
1547 return i;
1548 }
1549 napi_enable(&np->napi);
1550
1551 init_ring(dev);
1552 spin_lock_irq(&np->lock);
1553 init_registers(dev);
1554
1555 for (i = 0; i < 3; i++) {
1556 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1557
1558 writel(i*2, ioaddr + RxFilterAddr);
1559 writew(mac, ioaddr + RxFilterData);
1560 }
1561 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1562 spin_unlock_irq(&np->lock);
1563
1564 netif_start_queue(dev);
1565
1566 if (netif_msg_ifup(np))
1567 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1568 dev->name, (int)readl(ioaddr + ChipCmd));
1569
1570
1571 init_timer(&np->timer);
1572 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1573 np->timer.data = (unsigned long)dev;
1574 np->timer.function = &netdev_timer;
1575 add_timer(&np->timer);
1576
1577 return 0;
1578}
1579
1580static void do_cable_magic(struct net_device *dev)
1581{
1582 struct netdev_private *np = netdev_priv(dev);
1583 void __iomem *ioaddr = ns_ioaddr(dev);
1584
1585 if (dev->if_port != PORT_TP)
1586 return;
1587
1588 if (np->srr >= SRR_DP83816_A5)
1589 return;
1590
1591
1592
1593
1594
1595
1596
1597 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1598 u16 data;
1599
1600 writew(1, ioaddr + PGSEL);
1601
1602
1603
1604
1605 data = readw(ioaddr + TSTDAT) & 0xff;
1606
1607
1608
1609
1610 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1611 np = netdev_priv(dev);
1612
1613
1614 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1615
1616 data = readw(ioaddr + DSPCFG);
1617 np->dspcfg = data | DSPCFG_LOCK;
1618 writew(np->dspcfg, ioaddr + DSPCFG);
1619 }
1620 writew(0, ioaddr + PGSEL);
1621 }
1622}
1623
1624static void undo_cable_magic(struct net_device *dev)
1625{
1626 u16 data;
1627 struct netdev_private *np = netdev_priv(dev);
1628 void __iomem * ioaddr = ns_ioaddr(dev);
1629
1630 if (dev->if_port != PORT_TP)
1631 return;
1632
1633 if (np->srr >= SRR_DP83816_A5)
1634 return;
1635
1636 writew(1, ioaddr + PGSEL);
1637
1638 data = readw(ioaddr + DSPCFG);
1639 np->dspcfg = data & ~DSPCFG_LOCK;
1640 writew(np->dspcfg, ioaddr + DSPCFG);
1641 writew(0, ioaddr + PGSEL);
1642}
1643
1644static void check_link(struct net_device *dev)
1645{
1646 struct netdev_private *np = netdev_priv(dev);
1647 void __iomem * ioaddr = ns_ioaddr(dev);
1648 int duplex = np->duplex;
1649 u16 bmsr;
1650
1651
1652 if (np->ignore_phy)
1653 goto propagate_state;
1654
1655
1656
1657
1658
1659 mdio_read(dev, MII_BMSR);
1660 bmsr = mdio_read(dev, MII_BMSR);
1661
1662 if (!(bmsr & BMSR_LSTATUS)) {
1663 if (netif_carrier_ok(dev)) {
1664 if (netif_msg_link(np))
1665 printk(KERN_NOTICE "%s: link down.\n",
1666 dev->name);
1667 netif_carrier_off(dev);
1668 undo_cable_magic(dev);
1669 }
1670 return;
1671 }
1672 if (!netif_carrier_ok(dev)) {
1673 if (netif_msg_link(np))
1674 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1675 netif_carrier_on(dev);
1676 do_cable_magic(dev);
1677 }
1678
1679 duplex = np->full_duplex;
1680 if (!duplex) {
1681 if (bmsr & BMSR_ANEGCOMPLETE) {
1682 int tmp = mii_nway_result(
1683 np->advertising & mdio_read(dev, MII_LPA));
1684 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1685 duplex = 1;
1686 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1687 duplex = 1;
1688 }
1689
1690propagate_state:
1691
1692 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1693 if (netif_msg_link(np))
1694 printk(KERN_INFO
1695 "%s: Setting %s-duplex based on negotiated "
1696 "link capability.\n", dev->name,
1697 duplex ? "full" : "half");
1698 if (duplex) {
1699 np->rx_config |= RxAcceptTx;
1700 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1701 } else {
1702 np->rx_config &= ~RxAcceptTx;
1703 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1704 }
1705 writel(np->tx_config, ioaddr + TxConfig);
1706 writel(np->rx_config, ioaddr + RxConfig);
1707 }
1708}
1709
1710static void init_registers(struct net_device *dev)
1711{
1712 struct netdev_private *np = netdev_priv(dev);
1713 void __iomem * ioaddr = ns_ioaddr(dev);
1714
1715 init_phy_fixup(dev);
1716
1717
1718 readl(ioaddr + IntrStatus);
1719
1720 writel(np->ring_dma, ioaddr + RxRingPtr);
1721 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1722 ioaddr + TxRingPtr);
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1739 TX_FLTH_VAL | TX_DRTH_VAL_START;
1740 writel(np->tx_config, ioaddr + TxConfig);
1741
1742
1743
1744
1745 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1746
1747 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1748 np->rx_config |= RxAcceptLong;
1749
1750 writel(np->rx_config, ioaddr + RxConfig);
1751
1752
1753
1754
1755
1756
1757
1758 np->SavedClkRun = readl(ioaddr + ClkRun);
1759 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1760 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1761 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1762 dev->name, readl(ioaddr + WOLCmd));
1763 }
1764
1765 check_link(dev);
1766 __set_rx_mode(dev);
1767
1768
1769 writel(DEFAULT_INTR, ioaddr + IntrMask);
1770 natsemi_irq_enable(dev);
1771
1772 writel(RxOn | TxOn, ioaddr + ChipCmd);
1773 writel(StatsClear, ioaddr + StatsCtrl);
1774}
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789static void netdev_timer(unsigned long data)
1790{
1791 struct net_device *dev = (struct net_device *)data;
1792 struct netdev_private *np = netdev_priv(dev);
1793 void __iomem * ioaddr = ns_ioaddr(dev);
1794 int next_tick = NATSEMI_TIMER_FREQ;
1795
1796 if (netif_msg_timer(np)) {
1797
1798
1799
1800 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1801 dev->name);
1802 }
1803
1804 if (dev->if_port == PORT_TP) {
1805 u16 dspcfg;
1806
1807 spin_lock_irq(&np->lock);
1808
1809 writew(1, ioaddr+PGSEL);
1810 dspcfg = readw(ioaddr+DSPCFG);
1811 writew(0, ioaddr+PGSEL);
1812 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1813 if (!netif_queue_stopped(dev)) {
1814 spin_unlock_irq(&np->lock);
1815 if (netif_msg_drv(np))
1816 printk(KERN_NOTICE "%s: possible phy reset: "
1817 "re-initializing\n", dev->name);
1818 disable_irq(dev->irq);
1819 spin_lock_irq(&np->lock);
1820 natsemi_stop_rxtx(dev);
1821 dump_ring(dev);
1822 reinit_ring(dev);
1823 init_registers(dev);
1824 spin_unlock_irq(&np->lock);
1825 enable_irq(dev->irq);
1826 } else {
1827
1828 next_tick = HZ;
1829 spin_unlock_irq(&np->lock);
1830 }
1831 } else {
1832
1833 check_link(dev);
1834 spin_unlock_irq(&np->lock);
1835 }
1836 } else {
1837 spin_lock_irq(&np->lock);
1838 check_link(dev);
1839 spin_unlock_irq(&np->lock);
1840 }
1841 if (np->oom) {
1842 disable_irq(dev->irq);
1843 np->oom = 0;
1844 refill_rx(dev);
1845 enable_irq(dev->irq);
1846 if (!np->oom) {
1847 writel(RxOn, ioaddr + ChipCmd);
1848 } else {
1849 next_tick = 1;
1850 }
1851 }
1852
1853 if (next_tick > 1)
1854 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1855 else
1856 mod_timer(&np->timer, jiffies + next_tick);
1857}
1858
1859static void dump_ring(struct net_device *dev)
1860{
1861 struct netdev_private *np = netdev_priv(dev);
1862
1863 if (netif_msg_pktdata(np)) {
1864 int i;
1865 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1866 for (i = 0; i < TX_RING_SIZE; i++) {
1867 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1868 i, np->tx_ring[i].next_desc,
1869 np->tx_ring[i].cmd_status,
1870 np->tx_ring[i].addr);
1871 }
1872 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1873 for (i = 0; i < RX_RING_SIZE; i++) {
1874 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1875 i, np->rx_ring[i].next_desc,
1876 np->rx_ring[i].cmd_status,
1877 np->rx_ring[i].addr);
1878 }
1879 }
1880}
1881
1882static void ns_tx_timeout(struct net_device *dev)
1883{
1884 struct netdev_private *np = netdev_priv(dev);
1885 void __iomem * ioaddr = ns_ioaddr(dev);
1886
1887 disable_irq(dev->irq);
1888 spin_lock_irq(&np->lock);
1889 if (!np->hands_off) {
1890 if (netif_msg_tx_err(np))
1891 printk(KERN_WARNING
1892 "%s: Transmit timed out, status %#08x,"
1893 " resetting...\n",
1894 dev->name, readl(ioaddr + IntrStatus));
1895 dump_ring(dev);
1896
1897 natsemi_reset(dev);
1898 reinit_ring(dev);
1899 init_registers(dev);
1900 } else {
1901 printk(KERN_WARNING
1902 "%s: tx_timeout while in hands_off state?\n",
1903 dev->name);
1904 }
1905 spin_unlock_irq(&np->lock);
1906 enable_irq(dev->irq);
1907
1908 dev->trans_start = jiffies;
1909 np->stats.tx_errors++;
1910 netif_wake_queue(dev);
1911}
1912
1913static int alloc_ring(struct net_device *dev)
1914{
1915 struct netdev_private *np = netdev_priv(dev);
1916 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1917 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1918 &np->ring_dma);
1919 if (!np->rx_ring)
1920 return -ENOMEM;
1921 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1922 return 0;
1923}
1924
1925static void refill_rx(struct net_device *dev)
1926{
1927 struct netdev_private *np = netdev_priv(dev);
1928
1929
1930 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1931 struct sk_buff *skb;
1932 int entry = np->dirty_rx % RX_RING_SIZE;
1933 if (np->rx_skbuff[entry] == NULL) {
1934 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1935 skb = dev_alloc_skb(buflen);
1936 np->rx_skbuff[entry] = skb;
1937 if (skb == NULL)
1938 break;
1939 skb->dev = dev;
1940 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1941 skb->data, buflen, PCI_DMA_FROMDEVICE);
1942 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1943 }
1944 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1945 }
1946 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1947 if (netif_msg_rx_err(np))
1948 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1949 np->oom = 1;
1950 }
1951}
1952
1953static void set_bufsize(struct net_device *dev)
1954{
1955 struct netdev_private *np = netdev_priv(dev);
1956 if (dev->mtu <= ETH_DATA_LEN)
1957 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1958 else
1959 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1960}
1961
1962
1963static void init_ring(struct net_device *dev)
1964{
1965 struct netdev_private *np = netdev_priv(dev);
1966 int i;
1967
1968
1969 np->dirty_tx = np->cur_tx = 0;
1970 for (i = 0; i < TX_RING_SIZE; i++) {
1971 np->tx_skbuff[i] = NULL;
1972 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1973 +sizeof(struct netdev_desc)
1974 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1975 np->tx_ring[i].cmd_status = 0;
1976 }
1977
1978
1979 np->dirty_rx = 0;
1980 np->cur_rx = RX_RING_SIZE;
1981 np->oom = 0;
1982 set_bufsize(dev);
1983
1984 np->rx_head_desc = &np->rx_ring[0];
1985
1986
1987
1988
1989
1990 for (i = 0; i < RX_RING_SIZE; i++) {
1991 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1992 +sizeof(struct netdev_desc)
1993 *((i+1)%RX_RING_SIZE));
1994 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1995 np->rx_skbuff[i] = NULL;
1996 }
1997 refill_rx(dev);
1998 dump_ring(dev);
1999}
2000
2001static void drain_tx(struct net_device *dev)
2002{
2003 struct netdev_private *np = netdev_priv(dev);
2004 int i;
2005
2006 for (i = 0; i < TX_RING_SIZE; i++) {
2007 if (np->tx_skbuff[i]) {
2008 pci_unmap_single(np->pci_dev,
2009 np->tx_dma[i], np->tx_skbuff[i]->len,
2010 PCI_DMA_TODEVICE);
2011 dev_kfree_skb(np->tx_skbuff[i]);
2012 np->stats.tx_dropped++;
2013 }
2014 np->tx_skbuff[i] = NULL;
2015 }
2016}
2017
2018static void drain_rx(struct net_device *dev)
2019{
2020 struct netdev_private *np = netdev_priv(dev);
2021 unsigned int buflen = np->rx_buf_sz;
2022 int i;
2023
2024
2025 for (i = 0; i < RX_RING_SIZE; i++) {
2026 np->rx_ring[i].cmd_status = 0;
2027 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0);
2028 if (np->rx_skbuff[i]) {
2029 pci_unmap_single(np->pci_dev,
2030 np->rx_dma[i], buflen,
2031 PCI_DMA_FROMDEVICE);
2032 dev_kfree_skb(np->rx_skbuff[i]);
2033 }
2034 np->rx_skbuff[i] = NULL;
2035 }
2036}
2037
2038static void drain_ring(struct net_device *dev)
2039{
2040 drain_rx(dev);
2041 drain_tx(dev);
2042}
2043
2044static void free_ring(struct net_device *dev)
2045{
2046 struct netdev_private *np = netdev_priv(dev);
2047 pci_free_consistent(np->pci_dev,
2048 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2049 np->rx_ring, np->ring_dma);
2050}
2051
2052static void reinit_rx(struct net_device *dev)
2053{
2054 struct netdev_private *np = netdev_priv(dev);
2055 int i;
2056
2057
2058 np->dirty_rx = 0;
2059 np->cur_rx = RX_RING_SIZE;
2060 np->rx_head_desc = &np->rx_ring[0];
2061
2062 for (i = 0; i < RX_RING_SIZE; i++)
2063 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2064
2065 refill_rx(dev);
2066}
2067
2068static void reinit_ring(struct net_device *dev)
2069{
2070 struct netdev_private *np = netdev_priv(dev);
2071 int i;
2072
2073
2074 drain_tx(dev);
2075 np->dirty_tx = np->cur_tx = 0;
2076 for (i=0;i<TX_RING_SIZE;i++)
2077 np->tx_ring[i].cmd_status = 0;
2078
2079 reinit_rx(dev);
2080}
2081
2082static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
2083{
2084 struct netdev_private *np = netdev_priv(dev);
2085 void __iomem * ioaddr = ns_ioaddr(dev);
2086 unsigned entry;
2087 unsigned long flags;
2088
2089
2090
2091
2092
2093 entry = np->cur_tx % TX_RING_SIZE;
2094
2095 np->tx_skbuff[entry] = skb;
2096 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2097 skb->data,skb->len, PCI_DMA_TODEVICE);
2098
2099 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2100
2101 spin_lock_irqsave(&np->lock, flags);
2102
2103 if (!np->hands_off) {
2104 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2105
2106
2107 wmb();
2108 np->cur_tx++;
2109 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2110 netdev_tx_done(dev);
2111 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2112 netif_stop_queue(dev);
2113 }
2114
2115 writel(TxOn, ioaddr + ChipCmd);
2116 } else {
2117 dev_kfree_skb_irq(skb);
2118 np->stats.tx_dropped++;
2119 }
2120 spin_unlock_irqrestore(&np->lock, flags);
2121
2122 dev->trans_start = jiffies;
2123
2124 if (netif_msg_tx_queued(np)) {
2125 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2126 dev->name, np->cur_tx, entry);
2127 }
2128 return NETDEV_TX_OK;
2129}
2130
2131static void netdev_tx_done(struct net_device *dev)
2132{
2133 struct netdev_private *np = netdev_priv(dev);
2134
2135 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2136 int entry = np->dirty_tx % TX_RING_SIZE;
2137 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2138 break;
2139 if (netif_msg_tx_done(np))
2140 printk(KERN_DEBUG
2141 "%s: tx frame #%d finished, status %#08x.\n",
2142 dev->name, np->dirty_tx,
2143 le32_to_cpu(np->tx_ring[entry].cmd_status));
2144 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2145 np->stats.tx_packets++;
2146 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2147 } else {
2148 int tx_status =
2149 le32_to_cpu(np->tx_ring[entry].cmd_status);
2150 if (tx_status & (DescTxAbort|DescTxExcColl))
2151 np->stats.tx_aborted_errors++;
2152 if (tx_status & DescTxFIFO)
2153 np->stats.tx_fifo_errors++;
2154 if (tx_status & DescTxCarrier)
2155 np->stats.tx_carrier_errors++;
2156 if (tx_status & DescTxOOWCol)
2157 np->stats.tx_window_errors++;
2158 np->stats.tx_errors++;
2159 }
2160 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2161 np->tx_skbuff[entry]->len,
2162 PCI_DMA_TODEVICE);
2163
2164 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2165 np->tx_skbuff[entry] = NULL;
2166 }
2167 if (netif_queue_stopped(dev)
2168 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2169
2170 netif_wake_queue(dev);
2171 }
2172}
2173
2174
2175
2176static irqreturn_t intr_handler(int irq, void *dev_instance)
2177{
2178 struct net_device *dev = dev_instance;
2179 struct netdev_private *np = netdev_priv(dev);
2180 void __iomem * ioaddr = ns_ioaddr(dev);
2181
2182
2183
2184
2185 if (np->hands_off || !readl(ioaddr + IntrEnable))
2186 return IRQ_NONE;
2187
2188 np->intr_status = readl(ioaddr + IntrStatus);
2189
2190 if (!np->intr_status)
2191 return IRQ_NONE;
2192
2193 if (netif_msg_intr(np))
2194 printk(KERN_DEBUG
2195 "%s: Interrupt, status %#08x, mask %#08x.\n",
2196 dev->name, np->intr_status,
2197 readl(ioaddr + IntrMask));
2198
2199 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2200
2201 if (napi_schedule_prep(&np->napi)) {
2202
2203 natsemi_irq_disable(dev);
2204 __napi_schedule(&np->napi);
2205 } else
2206 printk(KERN_WARNING
2207 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2208 dev->name, np->intr_status,
2209 readl(ioaddr + IntrMask));
2210
2211 return IRQ_HANDLED;
2212}
2213
2214
2215
2216
2217static int natsemi_poll(struct napi_struct *napi, int budget)
2218{
2219 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2220 struct net_device *dev = np->dev;
2221 void __iomem * ioaddr = ns_ioaddr(dev);
2222 int work_done = 0;
2223
2224 do {
2225 if (netif_msg_intr(np))
2226 printk(KERN_DEBUG
2227 "%s: Poll, status %#08x, mask %#08x.\n",
2228 dev->name, np->intr_status,
2229 readl(ioaddr + IntrMask));
2230
2231
2232
2233 if (np->intr_status &
2234 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2235 IntrRxErr | IntrRxOverrun)) {
2236 netdev_rx(dev, &work_done, budget);
2237 }
2238
2239 if (np->intr_status &
2240 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2241 spin_lock(&np->lock);
2242 netdev_tx_done(dev);
2243 spin_unlock(&np->lock);
2244 }
2245
2246
2247 if (np->intr_status & IntrAbnormalSummary)
2248 netdev_error(dev, np->intr_status);
2249
2250 if (work_done >= budget)
2251 return work_done;
2252
2253 np->intr_status = readl(ioaddr + IntrStatus);
2254 } while (np->intr_status);
2255
2256 napi_complete(napi);
2257
2258
2259
2260 spin_lock(&np->lock);
2261 if (!np->hands_off)
2262 natsemi_irq_enable(dev);
2263 spin_unlock(&np->lock);
2264
2265 return work_done;
2266}
2267
2268
2269
2270static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
2271{
2272 struct netdev_private *np = netdev_priv(dev);
2273 int entry = np->cur_rx % RX_RING_SIZE;
2274 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2275 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2276 unsigned int buflen = np->rx_buf_sz;
2277 void __iomem * ioaddr = ns_ioaddr(dev);
2278
2279
2280 while (desc_status < 0) {
2281 int pkt_len;
2282 if (netif_msg_rx_status(np))
2283 printk(KERN_DEBUG
2284 " netdev_rx() entry %d status was %#08x.\n",
2285 entry, desc_status);
2286 if (--boguscnt < 0)
2287 break;
2288
2289 if (*work_done >= work_to_do)
2290 break;
2291
2292 (*work_done)++;
2293
2294 pkt_len = (desc_status & DescSizeMask) - 4;
2295 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2296 if (desc_status & DescMore) {
2297 unsigned long flags;
2298
2299 if (netif_msg_rx_err(np))
2300 printk(KERN_WARNING
2301 "%s: Oversized(?) Ethernet "
2302 "frame spanned multiple "
2303 "buffers, entry %#08x "
2304 "status %#08x.\n", dev->name,
2305 np->cur_rx, desc_status);
2306 np->stats.rx_length_errors++;
2307
2308
2309
2310
2311
2312
2313 spin_lock_irqsave(&np->lock, flags);
2314 reset_rx(dev);
2315 reinit_rx(dev);
2316 writel(np->ring_dma, ioaddr + RxRingPtr);
2317 check_link(dev);
2318 spin_unlock_irqrestore(&np->lock, flags);
2319
2320
2321
2322 break;
2323
2324 } else {
2325
2326 np->stats.rx_errors++;
2327 if (desc_status & (DescRxAbort|DescRxOver))
2328 np->stats.rx_over_errors++;
2329 if (desc_status & (DescRxLong|DescRxRunt))
2330 np->stats.rx_length_errors++;
2331 if (desc_status & (DescRxInvalid|DescRxAlign))
2332 np->stats.rx_frame_errors++;
2333 if (desc_status & DescRxCRC)
2334 np->stats.rx_crc_errors++;
2335 }
2336 } else if (pkt_len > np->rx_buf_sz) {
2337
2338
2339
2340
2341 } else {
2342 struct sk_buff *skb;
2343
2344
2345
2346 if (pkt_len < rx_copybreak
2347 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2348
2349 skb_reserve(skb, RX_OFFSET);
2350 pci_dma_sync_single_for_cpu(np->pci_dev,
2351 np->rx_dma[entry],
2352 buflen,
2353 PCI_DMA_FROMDEVICE);
2354 skb_copy_to_linear_data(skb,
2355 np->rx_skbuff[entry]->data, pkt_len);
2356 skb_put(skb, pkt_len);
2357 pci_dma_sync_single_for_device(np->pci_dev,
2358 np->rx_dma[entry],
2359 buflen,
2360 PCI_DMA_FROMDEVICE);
2361 } else {
2362 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2363 buflen, PCI_DMA_FROMDEVICE);
2364 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2365 np->rx_skbuff[entry] = NULL;
2366 }
2367 skb->protocol = eth_type_trans(skb, dev);
2368 netif_receive_skb(skb);
2369 np->stats.rx_packets++;
2370 np->stats.rx_bytes += pkt_len;
2371 }
2372 entry = (++np->cur_rx) % RX_RING_SIZE;
2373 np->rx_head_desc = &np->rx_ring[entry];
2374 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2375 }
2376 refill_rx(dev);
2377
2378
2379 if (np->oom)
2380 mod_timer(&np->timer, jiffies + 1);
2381 else
2382 writel(RxOn, ioaddr + ChipCmd);
2383}
2384
2385static void netdev_error(struct net_device *dev, int intr_status)
2386{
2387 struct netdev_private *np = netdev_priv(dev);
2388 void __iomem * ioaddr = ns_ioaddr(dev);
2389
2390 spin_lock(&np->lock);
2391 if (intr_status & LinkChange) {
2392 u16 lpa = mdio_read(dev, MII_LPA);
2393 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2394 && netif_msg_link(np)) {
2395 printk(KERN_INFO
2396 "%s: Autonegotiation advertising"
2397 " %#04x partner %#04x.\n", dev->name,
2398 np->advertising, lpa);
2399 }
2400
2401
2402 readw(ioaddr + MIntrStatus);
2403 check_link(dev);
2404 }
2405 if (intr_status & StatsMax) {
2406 __get_stats(dev);
2407 }
2408 if (intr_status & IntrTxUnderrun) {
2409 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2410 np->tx_config += TX_DRTH_VAL_INC;
2411 if (netif_msg_tx_err(np))
2412 printk(KERN_NOTICE
2413 "%s: increased tx threshold, txcfg %#08x.\n",
2414 dev->name, np->tx_config);
2415 } else {
2416 if (netif_msg_tx_err(np))
2417 printk(KERN_NOTICE
2418 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2419 dev->name, np->tx_config);
2420 }
2421 writel(np->tx_config, ioaddr + TxConfig);
2422 }
2423 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2424 int wol_status = readl(ioaddr + WOLCmd);
2425 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2426 dev->name, wol_status);
2427 }
2428 if (intr_status & RxStatusFIFOOver) {
2429 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2430 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2431 dev->name);
2432 }
2433 np->stats.rx_fifo_errors++;
2434 np->stats.rx_errors++;
2435 }
2436
2437 if (intr_status & IntrPCIErr) {
2438 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2439 intr_status & IntrPCIErr);
2440 np->stats.tx_fifo_errors++;
2441 np->stats.tx_errors++;
2442 np->stats.rx_fifo_errors++;
2443 np->stats.rx_errors++;
2444 }
2445 spin_unlock(&np->lock);
2446}
2447
2448static void __get_stats(struct net_device *dev)
2449{
2450 void __iomem * ioaddr = ns_ioaddr(dev);
2451 struct netdev_private *np = netdev_priv(dev);
2452
2453
2454 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2455 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2456}
2457
2458static struct net_device_stats *get_stats(struct net_device *dev)
2459{
2460 struct netdev_private *np = netdev_priv(dev);
2461
2462
2463 spin_lock_irq(&np->lock);
2464 if (netif_running(dev) && !np->hands_off)
2465 __get_stats(dev);
2466 spin_unlock_irq(&np->lock);
2467
2468 return &np->stats;
2469}
2470
2471#ifdef CONFIG_NET_POLL_CONTROLLER
2472static void natsemi_poll_controller(struct net_device *dev)
2473{
2474 disable_irq(dev->irq);
2475 intr_handler(dev->irq, dev);
2476 enable_irq(dev->irq);
2477}
2478#endif
2479
2480#define HASH_TABLE 0x200
2481static void __set_rx_mode(struct net_device *dev)
2482{
2483 void __iomem * ioaddr = ns_ioaddr(dev);
2484 struct netdev_private *np = netdev_priv(dev);
2485 u8 mc_filter[64];
2486 u32 rx_mode;
2487
2488 if (dev->flags & IFF_PROMISC) {
2489 rx_mode = RxFilterEnable | AcceptBroadcast
2490 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2491 } else if ((dev->mc_count > multicast_filter_limit)
2492 || (dev->flags & IFF_ALLMULTI)) {
2493 rx_mode = RxFilterEnable | AcceptBroadcast
2494 | AcceptAllMulticast | AcceptMyPhys;
2495 } else {
2496 struct dev_mc_list *mclist;
2497 int i;
2498 memset(mc_filter, 0, sizeof(mc_filter));
2499 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2500 i++, mclist = mclist->next) {
2501 int b = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2502 mc_filter[b/8] |= (1 << (b & 0x07));
2503 }
2504 rx_mode = RxFilterEnable | AcceptBroadcast
2505 | AcceptMulticast | AcceptMyPhys;
2506 for (i = 0; i < 64; i += 2) {
2507 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2508 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2509 ioaddr + RxFilterData);
2510 }
2511 }
2512 writel(rx_mode, ioaddr + RxFilterAddr);
2513 np->cur_rx_mode = rx_mode;
2514}
2515
2516static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2517{
2518 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2519 return -EINVAL;
2520
2521 dev->mtu = new_mtu;
2522
2523
2524 if (netif_running(dev)) {
2525 struct netdev_private *np = netdev_priv(dev);
2526 void __iomem * ioaddr = ns_ioaddr(dev);
2527
2528 disable_irq(dev->irq);
2529 spin_lock(&np->lock);
2530
2531 natsemi_stop_rxtx(dev);
2532
2533 drain_rx(dev);
2534
2535 set_bufsize(dev);
2536 reinit_rx(dev);
2537 writel(np->ring_dma, ioaddr + RxRingPtr);
2538
2539 writel(RxOn | TxOn, ioaddr + ChipCmd);
2540 spin_unlock(&np->lock);
2541 enable_irq(dev->irq);
2542 }
2543 return 0;
2544}
2545
2546static void set_rx_mode(struct net_device *dev)
2547{
2548 struct netdev_private *np = netdev_priv(dev);
2549 spin_lock_irq(&np->lock);
2550 if (!np->hands_off)
2551 __set_rx_mode(dev);
2552 spin_unlock_irq(&np->lock);
2553}
2554
2555static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2556{
2557 struct netdev_private *np = netdev_priv(dev);
2558 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2559 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2560 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2561}
2562
2563static int get_regs_len(struct net_device *dev)
2564{
2565 return NATSEMI_REGS_SIZE;
2566}
2567
2568static int get_eeprom_len(struct net_device *dev)
2569{
2570 struct netdev_private *np = netdev_priv(dev);
2571 return np->eeprom_size;
2572}
2573
2574static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2575{
2576 struct netdev_private *np = netdev_priv(dev);
2577 spin_lock_irq(&np->lock);
2578 netdev_get_ecmd(dev, ecmd);
2579 spin_unlock_irq(&np->lock);
2580 return 0;
2581}
2582
2583static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2584{
2585 struct netdev_private *np = netdev_priv(dev);
2586 int res;
2587 spin_lock_irq(&np->lock);
2588 res = netdev_set_ecmd(dev, ecmd);
2589 spin_unlock_irq(&np->lock);
2590 return res;
2591}
2592
2593static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2594{
2595 struct netdev_private *np = netdev_priv(dev);
2596 spin_lock_irq(&np->lock);
2597 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2598 netdev_get_sopass(dev, wol->sopass);
2599 spin_unlock_irq(&np->lock);
2600}
2601
2602static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2603{
2604 struct netdev_private *np = netdev_priv(dev);
2605 int res;
2606 spin_lock_irq(&np->lock);
2607 netdev_set_wol(dev, wol->wolopts);
2608 res = netdev_set_sopass(dev, wol->sopass);
2609 spin_unlock_irq(&np->lock);
2610 return res;
2611}
2612
2613static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2614{
2615 struct netdev_private *np = netdev_priv(dev);
2616 regs->version = NATSEMI_REGS_VER;
2617 spin_lock_irq(&np->lock);
2618 netdev_get_regs(dev, buf);
2619 spin_unlock_irq(&np->lock);
2620}
2621
2622static u32 get_msglevel(struct net_device *dev)
2623{
2624 struct netdev_private *np = netdev_priv(dev);
2625 return np->msg_enable;
2626}
2627
2628static void set_msglevel(struct net_device *dev, u32 val)
2629{
2630 struct netdev_private *np = netdev_priv(dev);
2631 np->msg_enable = val;
2632}
2633
2634static int nway_reset(struct net_device *dev)
2635{
2636 int tmp;
2637 int r = -EINVAL;
2638
2639 tmp = mdio_read(dev, MII_BMCR);
2640 if (tmp & BMCR_ANENABLE) {
2641 tmp |= (BMCR_ANRESTART);
2642 mdio_write(dev, MII_BMCR, tmp);
2643 r = 0;
2644 }
2645 return r;
2646}
2647
2648static u32 get_link(struct net_device *dev)
2649{
2650
2651 mdio_read(dev, MII_BMSR);
2652 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2653}
2654
2655static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2656{
2657 struct netdev_private *np = netdev_priv(dev);
2658 u8 *eebuf;
2659 int res;
2660
2661 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2662 if (!eebuf)
2663 return -ENOMEM;
2664
2665 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2666 spin_lock_irq(&np->lock);
2667 res = netdev_get_eeprom(dev, eebuf);
2668 spin_unlock_irq(&np->lock);
2669 if (!res)
2670 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2671 kfree(eebuf);
2672 return res;
2673}
2674
2675static const struct ethtool_ops ethtool_ops = {
2676 .get_drvinfo = get_drvinfo,
2677 .get_regs_len = get_regs_len,
2678 .get_eeprom_len = get_eeprom_len,
2679 .get_settings = get_settings,
2680 .set_settings = set_settings,
2681 .get_wol = get_wol,
2682 .set_wol = set_wol,
2683 .get_regs = get_regs,
2684 .get_msglevel = get_msglevel,
2685 .set_msglevel = set_msglevel,
2686 .nway_reset = nway_reset,
2687 .get_link = get_link,
2688 .get_eeprom = get_eeprom,
2689};
2690
2691static int netdev_set_wol(struct net_device *dev, u32 newval)
2692{
2693 struct netdev_private *np = netdev_priv(dev);
2694 void __iomem * ioaddr = ns_ioaddr(dev);
2695 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2696
2697
2698 if (newval & WAKE_PHY)
2699 data |= WakePhy;
2700 if (newval & WAKE_UCAST)
2701 data |= WakeUnicast;
2702 if (newval & WAKE_MCAST)
2703 data |= WakeMulticast;
2704 if (newval & WAKE_BCAST)
2705 data |= WakeBroadcast;
2706 if (newval & WAKE_ARP)
2707 data |= WakeArp;
2708 if (newval & WAKE_MAGIC)
2709 data |= WakeMagic;
2710 if (np->srr >= SRR_DP83815_D) {
2711 if (newval & WAKE_MAGICSECURE) {
2712 data |= WakeMagicSecure;
2713 }
2714 }
2715
2716 writel(data, ioaddr + WOLCmd);
2717
2718 return 0;
2719}
2720
2721static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2722{
2723 struct netdev_private *np = netdev_priv(dev);
2724 void __iomem * ioaddr = ns_ioaddr(dev);
2725 u32 regval = readl(ioaddr + WOLCmd);
2726
2727 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2728 | WAKE_ARP | WAKE_MAGIC);
2729
2730 if (np->srr >= SRR_DP83815_D) {
2731
2732 *supported |= WAKE_MAGICSECURE;
2733 }
2734 *cur = 0;
2735
2736
2737 if (regval & WakePhy)
2738 *cur |= WAKE_PHY;
2739 if (regval & WakeUnicast)
2740 *cur |= WAKE_UCAST;
2741 if (regval & WakeMulticast)
2742 *cur |= WAKE_MCAST;
2743 if (regval & WakeBroadcast)
2744 *cur |= WAKE_BCAST;
2745 if (regval & WakeArp)
2746 *cur |= WAKE_ARP;
2747 if (regval & WakeMagic)
2748 *cur |= WAKE_MAGIC;
2749 if (regval & WakeMagicSecure) {
2750
2751 *cur |= WAKE_MAGICSECURE;
2752 }
2753
2754 return 0;
2755}
2756
2757static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2758{
2759 struct netdev_private *np = netdev_priv(dev);
2760 void __iomem * ioaddr = ns_ioaddr(dev);
2761 u16 *sval = (u16 *)newval;
2762 u32 addr;
2763
2764 if (np->srr < SRR_DP83815_D) {
2765 return 0;
2766 }
2767
2768
2769 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2770 addr &= ~RxFilterEnable;
2771 writel(addr, ioaddr + RxFilterAddr);
2772
2773
2774 writel(addr | 0xa, ioaddr + RxFilterAddr);
2775 writew(sval[0], ioaddr + RxFilterData);
2776
2777 writel(addr | 0xc, ioaddr + RxFilterAddr);
2778 writew(sval[1], ioaddr + RxFilterData);
2779
2780 writel(addr | 0xe, ioaddr + RxFilterAddr);
2781 writew(sval[2], ioaddr + RxFilterData);
2782
2783
2784 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2785
2786 return 0;
2787}
2788
2789static int netdev_get_sopass(struct net_device *dev, u8 *data)
2790{
2791 struct netdev_private *np = netdev_priv(dev);
2792 void __iomem * ioaddr = ns_ioaddr(dev);
2793 u16 *sval = (u16 *)data;
2794 u32 addr;
2795
2796 if (np->srr < SRR_DP83815_D) {
2797 sval[0] = sval[1] = sval[2] = 0;
2798 return 0;
2799 }
2800
2801
2802 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2803
2804 writel(addr | 0xa, ioaddr + RxFilterAddr);
2805 sval[0] = readw(ioaddr + RxFilterData);
2806
2807 writel(addr | 0xc, ioaddr + RxFilterAddr);
2808 sval[1] = readw(ioaddr + RxFilterData);
2809
2810 writel(addr | 0xe, ioaddr + RxFilterAddr);
2811 sval[2] = readw(ioaddr + RxFilterData);
2812
2813 writel(addr, ioaddr + RxFilterAddr);
2814
2815 return 0;
2816}
2817
2818static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2819{
2820 struct netdev_private *np = netdev_priv(dev);
2821 u32 tmp;
2822
2823 ecmd->port = dev->if_port;
2824 ecmd->speed = np->speed;
2825 ecmd->duplex = np->duplex;
2826 ecmd->autoneg = np->autoneg;
2827 ecmd->advertising = 0;
2828 if (np->advertising & ADVERTISE_10HALF)
2829 ecmd->advertising |= ADVERTISED_10baseT_Half;
2830 if (np->advertising & ADVERTISE_10FULL)
2831 ecmd->advertising |= ADVERTISED_10baseT_Full;
2832 if (np->advertising & ADVERTISE_100HALF)
2833 ecmd->advertising |= ADVERTISED_100baseT_Half;
2834 if (np->advertising & ADVERTISE_100FULL)
2835 ecmd->advertising |= ADVERTISED_100baseT_Full;
2836 ecmd->supported = (SUPPORTED_Autoneg |
2837 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2838 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2839 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2840 ecmd->phy_address = np->phy_addr_external;
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860 switch (ecmd->port) {
2861 default:
2862 case PORT_TP:
2863 ecmd->advertising |= ADVERTISED_TP;
2864 ecmd->transceiver = XCVR_INTERNAL;
2865 break;
2866 case PORT_MII:
2867 ecmd->advertising |= ADVERTISED_MII;
2868 ecmd->transceiver = XCVR_EXTERNAL;
2869 break;
2870 case PORT_FIBRE:
2871 ecmd->advertising |= ADVERTISED_FIBRE;
2872 ecmd->transceiver = XCVR_EXTERNAL;
2873 break;
2874 }
2875
2876
2877 if (ecmd->autoneg == AUTONEG_ENABLE) {
2878 ecmd->advertising |= ADVERTISED_Autoneg;
2879 tmp = mii_nway_result(
2880 np->advertising & mdio_read(dev, MII_LPA));
2881 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2882 ecmd->speed = SPEED_100;
2883 else
2884 ecmd->speed = SPEED_10;
2885 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2886 ecmd->duplex = DUPLEX_FULL;
2887 else
2888 ecmd->duplex = DUPLEX_HALF;
2889 }
2890
2891
2892
2893 return 0;
2894}
2895
2896static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2897{
2898 struct netdev_private *np = netdev_priv(dev);
2899
2900 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2901 return -EINVAL;
2902 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2903 return -EINVAL;
2904 if (ecmd->autoneg == AUTONEG_ENABLE) {
2905 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2906 ADVERTISED_10baseT_Full |
2907 ADVERTISED_100baseT_Half |
2908 ADVERTISED_100baseT_Full)) == 0) {
2909 return -EINVAL;
2910 }
2911 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2912 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2913 return -EINVAL;
2914 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2915 return -EINVAL;
2916 } else {
2917 return -EINVAL;
2918 }
2919
2920
2921
2922
2923
2924
2925 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2926 ecmd->port == PORT_TP))
2927 return -EINVAL;
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945 dev->if_port = ecmd->port;
2946 np->autoneg = ecmd->autoneg;
2947 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2948 if (np->autoneg == AUTONEG_ENABLE) {
2949
2950 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2951 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2952 np->advertising |= ADVERTISE_10HALF;
2953 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2954 np->advertising |= ADVERTISE_10FULL;
2955 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2956 np->advertising |= ADVERTISE_100HALF;
2957 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2958 np->advertising |= ADVERTISE_100FULL;
2959 } else {
2960 np->speed = ecmd->speed;
2961 np->duplex = ecmd->duplex;
2962
2963 if (np->duplex == DUPLEX_HALF)
2964 np->full_duplex = 0;
2965 }
2966
2967
2968 if (ecmd->port == PORT_TP)
2969 switch_port_internal(dev);
2970 else
2971 switch_port_external(dev);
2972
2973
2974 init_phy_fixup(dev);
2975 check_link(dev);
2976 return 0;
2977}
2978
2979static int netdev_get_regs(struct net_device *dev, u8 *buf)
2980{
2981 int i;
2982 int j;
2983 u32 rfcr;
2984 u32 *rbuf = (u32 *)buf;
2985 void __iomem * ioaddr = ns_ioaddr(dev);
2986
2987
2988 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2989 rbuf[i] = readl(ioaddr + i*4);
2990 }
2991
2992
2993 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2994 rbuf[i] = mdio_read(dev, i & 0x1f);
2995
2996
2997 writew(1, ioaddr + PGSEL);
2998 rbuf[i++] = readw(ioaddr + PMDCSR);
2999 rbuf[i++] = readw(ioaddr + TSTDAT);
3000 rbuf[i++] = readw(ioaddr + DSPCFG);
3001 rbuf[i++] = readw(ioaddr + SDCFG);
3002 writew(0, ioaddr + PGSEL);
3003
3004
3005 rfcr = readl(ioaddr + RxFilterAddr);
3006 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3007 writel(j*2, ioaddr + RxFilterAddr);
3008 rbuf[i++] = readw(ioaddr + RxFilterData);
3009 }
3010 writel(rfcr, ioaddr + RxFilterAddr);
3011
3012
3013 if (rbuf[4] & rbuf[5]) {
3014 printk(KERN_WARNING
3015 "%s: shoot, we dropped an interrupt (%#08x)\n",
3016 dev->name, rbuf[4] & rbuf[5]);
3017 }
3018
3019 return 0;
3020}
3021
3022#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3023 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3024 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3025 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3026 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3027 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3028 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3029 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3030
3031static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3032{
3033 int i;
3034 u16 *ebuf = (u16 *)buf;
3035 void __iomem * ioaddr = ns_ioaddr(dev);
3036 struct netdev_private *np = netdev_priv(dev);
3037
3038
3039 for (i = 0; i < np->eeprom_size/2; i++) {
3040 ebuf[i] = eeprom_read(ioaddr, i);
3041
3042
3043
3044 ebuf[i] = SWAP_BITS(ebuf[i]);
3045 }
3046 return 0;
3047}
3048
3049static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3050{
3051 struct mii_ioctl_data *data = if_mii(rq);
3052 struct netdev_private *np = netdev_priv(dev);
3053
3054 switch(cmd) {
3055 case SIOCGMIIPHY:
3056 data->phy_id = np->phy_addr_external;
3057
3058
3059 case SIOCGMIIREG:
3060
3061
3062
3063
3064 if (dev->if_port == PORT_TP) {
3065 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3066 data->val_out = mdio_read(dev,
3067 data->reg_num & 0x1f);
3068 else
3069 data->val_out = 0;
3070 } else {
3071 move_int_phy(dev, data->phy_id & 0x1f);
3072 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3073 data->reg_num & 0x1f);
3074 }
3075 return 0;
3076
3077 case SIOCSMIIREG:
3078 if (dev->if_port == PORT_TP) {
3079 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3080 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3081 np->advertising = data->val_in;
3082 mdio_write(dev, data->reg_num & 0x1f,
3083 data->val_in);
3084 }
3085 } else {
3086 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3087 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3088 np->advertising = data->val_in;
3089 }
3090 move_int_phy(dev, data->phy_id & 0x1f);
3091 miiport_write(dev, data->phy_id & 0x1f,
3092 data->reg_num & 0x1f,
3093 data->val_in);
3094 }
3095 return 0;
3096 default:
3097 return -EOPNOTSUPP;
3098 }
3099}
3100
3101static void enable_wol_mode(struct net_device *dev, int enable_intr)
3102{
3103 void __iomem * ioaddr = ns_ioaddr(dev);
3104 struct netdev_private *np = netdev_priv(dev);
3105
3106 if (netif_msg_wol(np))
3107 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3108 dev->name);
3109
3110
3111
3112
3113
3114 writel(0, ioaddr + RxRingPtr);
3115
3116
3117 readl(ioaddr + WOLCmd);
3118
3119
3120 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3121
3122
3123 writel(RxOn, ioaddr + ChipCmd);
3124
3125 if (enable_intr) {
3126
3127
3128
3129 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3130 natsemi_irq_enable(dev);
3131 }
3132}
3133
3134static int netdev_close(struct net_device *dev)
3135{
3136 void __iomem * ioaddr = ns_ioaddr(dev);
3137 struct netdev_private *np = netdev_priv(dev);
3138
3139 if (netif_msg_ifdown(np))
3140 printk(KERN_DEBUG
3141 "%s: Shutting down ethercard, status was %#04x.\n",
3142 dev->name, (int)readl(ioaddr + ChipCmd));
3143 if (netif_msg_pktdata(np))
3144 printk(KERN_DEBUG
3145 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3146 dev->name, np->cur_tx, np->dirty_tx,
3147 np->cur_rx, np->dirty_rx);
3148
3149 napi_disable(&np->napi);
3150
3151
3152
3153
3154
3155
3156
3157
3158 del_timer_sync(&np->timer);
3159 disable_irq(dev->irq);
3160 spin_lock_irq(&np->lock);
3161 natsemi_irq_disable(dev);
3162 np->hands_off = 1;
3163 spin_unlock_irq(&np->lock);
3164 enable_irq(dev->irq);
3165
3166 free_irq(dev->irq, dev);
3167
3168
3169
3170
3171
3172 spin_lock_irq(&np->lock);
3173 np->hands_off = 0;
3174 readl(ioaddr + IntrMask);
3175 readw(ioaddr + MIntrStatus);
3176
3177
3178 writel(StatsFreeze, ioaddr + StatsCtrl);
3179
3180
3181 natsemi_stop_rxtx(dev);
3182
3183 __get_stats(dev);
3184 spin_unlock_irq(&np->lock);
3185
3186
3187 netif_carrier_off(dev);
3188 netif_stop_queue(dev);
3189
3190 dump_ring(dev);
3191 drain_ring(dev);
3192 free_ring(dev);
3193
3194 {
3195 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3196 if (wol) {
3197
3198
3199
3200 enable_wol_mode(dev, 0);
3201 } else {
3202
3203 writel(np->SavedClkRun, ioaddr + ClkRun);
3204 }
3205 }
3206 return 0;
3207}
3208
3209
3210static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3211{
3212 struct net_device *dev = pci_get_drvdata(pdev);
3213 void __iomem * ioaddr = ns_ioaddr(dev);
3214
3215 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
3216 unregister_netdev (dev);
3217 pci_release_regions (pdev);
3218 iounmap(ioaddr);
3219 free_netdev (dev);
3220 pci_set_drvdata(pdev, NULL);
3221}
3222
3223#ifdef CONFIG_PM
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3252{
3253 struct net_device *dev = pci_get_drvdata (pdev);
3254 struct netdev_private *np = netdev_priv(dev);
3255 void __iomem * ioaddr = ns_ioaddr(dev);
3256
3257 rtnl_lock();
3258 if (netif_running (dev)) {
3259 del_timer_sync(&np->timer);
3260
3261 disable_irq(dev->irq);
3262 spin_lock_irq(&np->lock);
3263
3264 natsemi_irq_disable(dev);
3265 np->hands_off = 1;
3266 natsemi_stop_rxtx(dev);
3267 netif_stop_queue(dev);
3268
3269 spin_unlock_irq(&np->lock);
3270 enable_irq(dev->irq);
3271
3272 napi_disable(&np->napi);
3273
3274
3275 __get_stats(dev);
3276
3277
3278 drain_ring(dev);
3279 {
3280 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3281
3282 if (wol) {
3283
3284
3285
3286
3287 enable_wol_mode(dev, 0);
3288 } else {
3289
3290 writel(np->SavedClkRun, ioaddr + ClkRun);
3291 }
3292 }
3293 }
3294 netif_device_detach(dev);
3295 rtnl_unlock();
3296 return 0;
3297}
3298
3299
3300static int natsemi_resume (struct pci_dev *pdev)
3301{
3302 struct net_device *dev = pci_get_drvdata (pdev);
3303 struct netdev_private *np = netdev_priv(dev);
3304 int ret = 0;
3305
3306 rtnl_lock();
3307 if (netif_device_present(dev))
3308 goto out;
3309 if (netif_running(dev)) {
3310 BUG_ON(!np->hands_off);
3311 ret = pci_enable_device(pdev);
3312 if (ret < 0) {
3313 dev_err(&pdev->dev,
3314 "pci_enable_device() failed: %d\n", ret);
3315 goto out;
3316 }
3317
3318
3319 napi_enable(&np->napi);
3320
3321 natsemi_reset(dev);
3322 init_ring(dev);
3323 disable_irq(dev->irq);
3324 spin_lock_irq(&np->lock);
3325 np->hands_off = 0;
3326 init_registers(dev);
3327 netif_device_attach(dev);
3328 spin_unlock_irq(&np->lock);
3329 enable_irq(dev->irq);
3330
3331 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
3332 }
3333 netif_device_attach(dev);
3334out:
3335 rtnl_unlock();
3336 return ret;
3337}
3338
3339#endif
3340
3341static struct pci_driver natsemi_driver = {
3342 .name = DRV_NAME,
3343 .id_table = natsemi_pci_tbl,
3344 .probe = natsemi_probe1,
3345 .remove = __devexit_p(natsemi_remove1),
3346#ifdef CONFIG_PM
3347 .suspend = natsemi_suspend,
3348 .resume = natsemi_resume,
3349#endif
3350};
3351
3352static int __init natsemi_init_mod (void)
3353{
3354
3355#ifdef MODULE
3356 printk(version);
3357#endif
3358
3359 return pci_register_driver(&natsemi_driver);
3360}
3361
3362static void __exit natsemi_exit_mod (void)
3363{
3364 pci_unregister_driver (&natsemi_driver);
3365}
3366
3367module_init(natsemi_init_mod);
3368module_exit(natsemi_exit_mod);
3369
3370