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26#ifndef _NETXEN_NIC_H_
27#define _NETXEN_NIC_H_
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/ioport.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/ip.h>
37#include <linux/in.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/firmware.h>
41
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/timer.h>
45
46#include <linux/vmalloc.h>
47
48#include <asm/io.h>
49#include <asm/byteorder.h>
50
51#include "netxen_nic_hdr.h"
52#include "netxen_nic_hw.h"
53
54#define _NETXEN_NIC_LINUX_MAJOR 4
55#define _NETXEN_NIC_LINUX_MINOR 0
56#define _NETXEN_NIC_LINUX_SUBVERSION 50
57#define NETXEN_NIC_LINUX_VERSIONID "4.0.50"
58
59#define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
60#define _major(v) (((v) >> 24) & 0xff)
61#define _minor(v) (((v) >> 16) & 0xff)
62#define _build(v) ((v) & 0xffff)
63
64
65
66
67
68
69#define NETXEN_DECODE_VERSION(v) \
70 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71
72#define NETXEN_NUM_FLASH_SECTORS (64)
73#define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
74#define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
75 * NETXEN_FLASH_SECTOR_SIZE)
76
77#define PHAN_VENDOR_ID 0x4040
78
79#define RCV_DESC_RINGSIZE(rds_ring) \
80 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
81#define RCV_BUFF_RINGSIZE(rds_ring) \
82 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
83#define STATUS_DESC_RINGSIZE(sds_ring) \
84 (sizeof(struct status_desc) * (sds_ring)->num_desc)
85#define TX_BUFF_RINGSIZE(tx_ring) \
86 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
87#define TX_DESC_RINGSIZE(tx_ring) \
88 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
89
90#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
91
92#define NETXEN_RCV_PRODUCER_OFFSET 0
93#define NETXEN_RCV_PEG_DB_ID 2
94#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
95#define FLASH_SUCCESS 0
96
97#define ADDR_IN_WINDOW1(off) \
98 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
99
100
101
102
103
104#define NETXEN_CRB_NORMAL(reg) \
105 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
106
107#define NETXEN_CRB_NORMALIZE(adapter, reg) \
108 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
109
110#define DB_NORMALIZE(adapter, off) \
111 (adapter->ahw.db_base + (off))
112
113#define NX_P2_C0 0x24
114#define NX_P2_C1 0x25
115#define NX_P3_A0 0x30
116#define NX_P3_A2 0x30
117#define NX_P3_B0 0x40
118#define NX_P3_B1 0x41
119#define NX_P3_B2 0x42
120
121#define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
122#define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
123
124#define FIRST_PAGE_GROUP_START 0
125#define FIRST_PAGE_GROUP_END 0x100000
126
127#define SECOND_PAGE_GROUP_START 0x6000000
128#define SECOND_PAGE_GROUP_END 0x68BC000
129
130#define THIRD_PAGE_GROUP_START 0x70E4000
131#define THIRD_PAGE_GROUP_END 0x8000000
132
133#define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
134#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
135#define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
136
137#define P2_MAX_MTU (8000)
138#define P3_MAX_MTU (9600)
139#define NX_ETHERMTU 1500
140#define NX_MAX_ETHERHDR 32
141
142#define NX_P2_RX_BUF_MAX_LEN 1760
143#define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
144#define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
145#define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
146#define NX_CT_DEFAULT_RX_BUF_LEN 2048
147#define NX_LRO_BUFFER_EXTRA 2048
148
149#define NX_RX_LRO_BUFFER_LENGTH (8060)
150
151
152
153
154#define MAX_RING_CTX 1
155
156
157#define TX_ETHER_PKT 0x01
158#define TX_TCP_PKT 0x02
159#define TX_UDP_PKT 0x03
160#define TX_IP_PKT 0x04
161#define TX_TCP_LSO 0x05
162#define TX_TCP_LSO6 0x06
163#define TX_IPSEC 0x07
164#define TX_IPSEC_CMD 0x0a
165#define TX_TCPV6_PKT 0x0b
166#define TX_UDPV6_PKT 0x0c
167
168
169#define NETXEN_CONTROL_OP 0x10
170#define PEGNET_REQUEST 0x11
171
172#define MAX_NUM_CARDS 4
173
174#define MAX_BUFFERS_PER_CMD 32
175#define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
176#define NX_MAX_TX_TIMEOUTS 2
177
178
179
180
181
182#define PHAN_INITIALIZE_START 0xff00
183#define PHAN_INITIALIZE_FAILED 0xffff
184#define PHAN_INITIALIZE_COMPLETE 0xff01
185
186
187#define PHAN_INITIALIZE_ACK 0xf00f
188
189#define NUM_RCV_DESC_RINGS 3
190#define NUM_STS_DESC_RINGS 4
191
192#define RCV_RING_NORMAL 0
193#define RCV_RING_JUMBO 1
194#define RCV_RING_LRO 2
195
196#define MIN_CMD_DESCRIPTORS 64
197#define MIN_RCV_DESCRIPTORS 64
198#define MIN_JUMBO_DESCRIPTORS 32
199
200#define MAX_CMD_DESCRIPTORS 1024
201#define MAX_RCV_DESCRIPTORS_1G 4096
202#define MAX_RCV_DESCRIPTORS_10G 8192
203#define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
204#define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
205#define MAX_LRO_RCV_DESCRIPTORS 8
206
207#define DEFAULT_RCV_DESCRIPTORS_1G 2048
208#define DEFAULT_RCV_DESCRIPTORS_10G 4096
209
210#define NETXEN_CTX_SIGNATURE 0xdee0
211#define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
212#define NETXEN_CTX_RESET 0xbad0
213#define NETXEN_CTX_D3_RESET 0xacc0
214#define NETXEN_RCV_PRODUCER(ringid) (ringid)
215
216#define PHAN_PEG_RCV_INITIALIZED 0xff01
217#define PHAN_PEG_RCV_START_INITIALIZE 0xff00
218
219#define get_next_index(index, length) \
220 (((index) + 1) & ((length) - 1))
221
222#define get_index_range(index,length,count) \
223 (((index) + (count)) & ((length) - 1))
224
225#define MPORT_SINGLE_FUNCTION_MODE 0x1111
226#define MPORT_MULTI_FUNCTION_MODE 0x2222
227
228#define NX_MAX_PCI_FUNC 8
229
230
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238
239
240typedef u32 netxen_ctx_msg;
241
242#define netxen_set_msg_peg_id(config_word, val) \
243 ((config_word) &= ~3, (config_word) |= val & 3)
244#define netxen_set_msg_privid(config_word) \
245 ((config_word) |= 1 << 2)
246#define netxen_set_msg_count(config_word, val) \
247 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
248#define netxen_set_msg_ctxid(config_word, val) \
249 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
250#define netxen_set_msg_opcode(config_word, val) \
251 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
252
253struct netxen_rcv_ring {
254 __le64 addr;
255 __le32 size;
256 __le32 rsrvd;
257};
258
259struct netxen_sts_ring {
260 __le64 addr;
261 __le32 size;
262 __le16 msi_index;
263 __le16 rsvd;
264} ;
265
266struct netxen_ring_ctx {
267
268
269 __le64 cmd_consumer_offset;
270 __le64 cmd_ring_addr;
271 __le32 cmd_ring_size;
272 __le32 rsrvd;
273
274
275 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
276
277 __le64 sts_ring_addr;
278 __le32 sts_ring_size;
279
280 __le32 ctx_id;
281
282 __le64 rsrvd_2[3];
283 __le32 sts_ring_count;
284 __le32 rsrvd_3;
285 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
286
287} __attribute__ ((aligned(64)));
288
289
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296
297
298
299
300#define FLAGS_CHECKSUM_ENABLED 0x01
301#define FLAGS_LSO_ENABLED 0x02
302#define FLAGS_IPSEC_SA_ADD 0x04
303#define FLAGS_IPSEC_SA_DELETE 0x08
304#define FLAGS_VLAN_TAGGED 0x10
305#define FLAGS_VLAN_OOB 0x40
306
307#define netxen_set_tx_vlan_tci(cmd_desc, v) \
308 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
309
310#define netxen_set_cmd_desc_port(cmd_desc, var) \
311 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
312#define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
313 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
314
315#define netxen_set_tx_port(_desc, _port) \
316 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
317
318#define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
319 (_desc)->flags_opcode = \
320 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
321
322#define netxen_set_tx_frags_len(_desc, _frags, _len) \
323 (_desc)->nfrags__length = \
324 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
325
326struct cmd_desc_type0 {
327 u8 tcp_hdr_offset;
328 u8 ip_hdr_offset;
329 __le16 flags_opcode;
330 __le32 nfrags__length;
331
332 __le64 addr_buffer2;
333
334 __le16 reference_handle;
335 __le16 mss;
336 u8 port_ctxid;
337 u8 total_hdr_length;
338 __le16 conn_id;
339
340 __le64 addr_buffer3;
341 __le64 addr_buffer1;
342
343 __le16 buffer_length[4];
344
345 __le64 addr_buffer4;
346
347 __le32 reserved2;
348 __le16 reserved;
349 __le16 vlan_TCI;
350
351} __attribute__ ((aligned(64)));
352
353
354struct rcv_desc {
355 __le16 reference_handle;
356 __le16 reserved;
357 __le32 buffer_length;
358 __le64 addr_buffer;
359};
360
361
362#define NETXEN_NIC_SYN_OFFLOAD 0x03
363#define NETXEN_NIC_RXPKT_DESC 0x04
364#define NETXEN_OLD_RXPKT_DESC 0x3f
365#define NETXEN_NIC_RESPONSE_DESC 0x05
366#define NETXEN_NIC_LRO_DESC 0x12
367
368
369#define STATUS_NEED_CKSUM (1)
370#define STATUS_CKSUM_OK (2)
371
372
373#define STATUS_OWNER_HOST (0x1ULL << 56)
374#define STATUS_OWNER_PHANTOM (0x2ULL << 56)
375
376
377
378
379
380
381#define netxen_get_sts_port(sts_data) \
382 ((sts_data) & 0x0F)
383#define netxen_get_sts_status(sts_data) \
384 (((sts_data) >> 4) & 0x0F)
385#define netxen_get_sts_type(sts_data) \
386 (((sts_data) >> 8) & 0x0F)
387#define netxen_get_sts_totallength(sts_data) \
388 (((sts_data) >> 12) & 0xFFFF)
389#define netxen_get_sts_refhandle(sts_data) \
390 (((sts_data) >> 28) & 0xFFFF)
391#define netxen_get_sts_prot(sts_data) \
392 (((sts_data) >> 44) & 0x0F)
393#define netxen_get_sts_pkt_offset(sts_data) \
394 (((sts_data) >> 48) & 0x1F)
395#define netxen_get_sts_desc_cnt(sts_data) \
396 (((sts_data) >> 53) & 0x7)
397#define netxen_get_sts_opcode(sts_data) \
398 (((sts_data) >> 58) & 0x03F)
399
400#define netxen_get_lro_sts_refhandle(sts_data) \
401 ((sts_data) & 0x0FFFF)
402#define netxen_get_lro_sts_length(sts_data) \
403 (((sts_data) >> 16) & 0x0FFFF)
404#define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
405 (((sts_data) >> 32) & 0x0FF)
406#define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
407 (((sts_data) >> 40) & 0x0FF)
408#define netxen_get_lro_sts_timestamp(sts_data) \
409 (((sts_data) >> 48) & 0x1)
410#define netxen_get_lro_sts_type(sts_data) \
411 (((sts_data) >> 49) & 0x7)
412#define netxen_get_lro_sts_push_flag(sts_data) \
413 (((sts_data) >> 52) & 0x1)
414#define netxen_get_lro_sts_seq_number(sts_data) \
415 ((sts_data) & 0x0FFFFFFFF)
416
417
418struct status_desc {
419 __le64 status_desc_data[2];
420} __attribute__ ((aligned(16)));
421
422
423#define NETXEN_BDINFO_VERSION 1
424
425
426#define NETXEN_BDINFO_MAGIC 0x12345678
427
428
429#define NETXEN_MAX_PORTS 4
430
431#define NETXEN_BRDTYPE_P1_BD 0x0000
432#define NETXEN_BRDTYPE_P1_SB 0x0001
433#define NETXEN_BRDTYPE_P1_SMAX 0x0002
434#define NETXEN_BRDTYPE_P1_SOCK 0x0003
435
436#define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
437#define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
438#define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
439#define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
440#define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
441
442#define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
443#define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
444#define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
445
446#define NETXEN_BRDTYPE_P3_REF_QG 0x0021
447#define NETXEN_BRDTYPE_P3_HMEZ 0x0022
448#define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
449#define NETXEN_BRDTYPE_P3_4_GB 0x0024
450#define NETXEN_BRDTYPE_P3_IMEZ 0x0025
451#define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
452#define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
453#define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
454#define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
455#define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
456#define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
457#define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
458#define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
459#define NETXEN_BRDTYPE_P3_10G_TP 0x0080
460
461
462#define NETXEN_CRBINIT_START 0
463#define NETXEN_BRDCFG_START 0x4000
464#define NETXEN_INITCODE_START 0x6000
465#define NETXEN_BOOTLD_START 0x10000
466#define NETXEN_IMAGE_START 0x43000
467#define NETXEN_SECONDARY_START 0x200000
468#define NETXEN_PXE_START 0x3E0000
469#define NETXEN_USER_START 0x3E8000
470#define NETXEN_FIXED_START 0x3F0000
471#define NETXEN_USER_START_OLD NETXEN_PXE_START
472
473#define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
474#define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
475#define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
476#define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
477#define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
478#define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
479
480#define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
481#define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
482#define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
483
484#define NX_FW_MIN_SIZE (0x3fffff)
485#define NX_P2_MN_ROMIMAGE 0
486#define NX_P3_CT_ROMIMAGE 1
487#define NX_P3_MN_ROMIMAGE 2
488#define NX_FLASH_ROMIMAGE 3
489
490extern char netxen_nic_driver_name[];
491
492
493#define MAX_STATUS_HANDLE (64)
494
495
496
497
498
499struct netxen_skb_frag {
500 u64 dma;
501 u64 length;
502};
503
504struct netxen_recv_crb {
505 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
506 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
507 u32 sw_int_mask[NUM_STS_DESC_RINGS];
508};
509
510
511#define NETXEN_BUFFER_FREE 0
512#define NETXEN_BUFFER_BUSY 1
513
514
515
516
517
518struct netxen_cmd_buffer {
519 struct sk_buff *skb;
520 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
521 u32 frag_count;
522};
523
524
525struct netxen_rx_buffer {
526 struct list_head list;
527 struct sk_buff *skb;
528 u64 dma;
529 u16 ref_handle;
530 u16 state;
531};
532
533
534#define NETXEN_NIC_GBE 0x01
535#define NETXEN_NIC_XGBE 0x02
536
537
538
539
540
541struct netxen_hardware_context {
542 void __iomem *pci_base0;
543 void __iomem *pci_base1;
544 void __iomem *pci_base2;
545 void __iomem *db_base;
546 unsigned long db_len;
547 unsigned long pci_len0;
548
549 int qdr_sn_window;
550 int ddr_mn_window;
551 u32 mn_win_crb;
552 u32 ms_win_crb;
553
554 u8 cut_through;
555 u8 revision_id;
556 u8 pci_func;
557 u8 linkup;
558 u16 port_type;
559 u16 board_type;
560};
561
562#define MINIMUM_ETHERNET_FRAME_SIZE 64
563#define ETHERNET_FCS_SIZE 4
564
565struct netxen_adapter_stats {
566 u64 xmitcalled;
567 u64 xmitfinished;
568 u64 rxdropped;
569 u64 txdropped;
570 u64 csummed;
571 u64 rx_pkts;
572 u64 lro_pkts;
573 u64 rxbytes;
574 u64 txbytes;
575};
576
577
578
579
580
581struct nx_host_rds_ring {
582 u32 producer;
583 u32 num_desc;
584 u32 dma_size;
585 u32 skb_size;
586 u32 flags;
587 void __iomem *crb_rcv_producer;
588 struct rcv_desc *desc_head;
589 struct netxen_rx_buffer *rx_buf_arr;
590 struct list_head free_list;
591 spinlock_t lock;
592 dma_addr_t phys_addr;
593};
594
595struct nx_host_sds_ring {
596 u32 consumer;
597 u32 num_desc;
598 void __iomem *crb_sts_consumer;
599 void __iomem *crb_intr_mask;
600
601 struct status_desc *desc_head;
602 struct netxen_adapter *adapter;
603 struct napi_struct napi;
604 struct list_head free_list[NUM_RCV_DESC_RINGS];
605
606 int irq;
607
608 dma_addr_t phys_addr;
609 char name[IFNAMSIZ+4];
610};
611
612struct nx_host_tx_ring {
613 u32 producer;
614 __le32 *hw_consumer;
615 u32 sw_consumer;
616 void __iomem *crb_cmd_producer;
617 void __iomem *crb_cmd_consumer;
618 u32 num_desc;
619
620 struct netdev_queue *txq;
621
622 struct netxen_cmd_buffer *cmd_buf_arr;
623 struct cmd_desc_type0 *desc_head;
624 dma_addr_t phys_addr;
625};
626
627
628
629
630
631
632
633struct netxen_recv_context {
634 u32 state;
635 u16 context_id;
636 u16 virt_port;
637
638 struct nx_host_rds_ring *rds_rings;
639 struct nx_host_sds_ring *sds_rings;
640
641 struct netxen_ring_ctx *hwctx;
642 dma_addr_t phys_addr;
643};
644
645
646
647#define NX_OS_CRB_RETRY_COUNT 4000
648#define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
649 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
650
651#define NX_CDRP_CLEAR 0x00000000
652#define NX_CDRP_CMD_BIT 0x80000000
653
654
655
656
657
658#define NX_CDRP_FORM_RSP(rsp) (rsp)
659#define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
660
661#define NX_CDRP_RSP_OK 0x00000001
662#define NX_CDRP_RSP_FAIL 0x00000002
663#define NX_CDRP_RSP_TIMEOUT 0x00000003
664
665
666
667
668
669#define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
670#define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
671
672#define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
673#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
674#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
675#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
676#define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
677#define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
678#define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
679#define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
680#define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
681#define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
682#define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
683#define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
684#define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
685#define NX_CDRP_CMD_SET_MTU 0x00000012
686#define NX_CDRP_CMD_READ_PHY 0x00000013
687#define NX_CDRP_CMD_WRITE_PHY 0x00000014
688#define NX_CDRP_CMD_READ_HW_REG 0x00000015
689#define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
690#define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
691#define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
692#define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
693#define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
694#define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
695#define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
696#define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
697#define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
698#define NX_CDRP_CMD_MAX 0x0000001f
699
700#define NX_RCODE_SUCCESS 0
701#define NX_RCODE_NO_HOST_MEM 1
702#define NX_RCODE_NO_HOST_RESOURCE 2
703#define NX_RCODE_NO_CARD_CRB 3
704#define NX_RCODE_NO_CARD_MEM 4
705#define NX_RCODE_NO_CARD_RESOURCE 5
706#define NX_RCODE_INVALID_ARGS 6
707#define NX_RCODE_INVALID_ACTION 7
708#define NX_RCODE_INVALID_STATE 8
709#define NX_RCODE_NOT_SUPPORTED 9
710#define NX_RCODE_NOT_PERMITTED 10
711#define NX_RCODE_NOT_READY 11
712#define NX_RCODE_DOES_NOT_EXIST 12
713#define NX_RCODE_ALREADY_EXISTS 13
714#define NX_RCODE_BAD_SIGNATURE 14
715#define NX_RCODE_CMD_NOT_IMPL 15
716#define NX_RCODE_CMD_INVALID 16
717#define NX_RCODE_TIMEOUT 17
718#define NX_RCODE_CMD_FAILED 18
719#define NX_RCODE_MAX_EXCEEDED 19
720#define NX_RCODE_MAX 20
721
722#define NX_DESTROY_CTX_RESET 0
723#define NX_DESTROY_CTX_D3_RESET 1
724#define NX_DESTROY_CTX_MAX 2
725
726
727
728
729#define NX_CAP_BIT(class, bit) (1 << bit)
730#define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
731#define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
732#define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
733#define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
734#define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
735#define NX_CAP0_LRO NX_CAP_BIT(0, 5)
736#define NX_CAP0_LSO NX_CAP_BIT(0, 6)
737#define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
738#define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
739#define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
740
741
742
743
744#define NX_HOST_CTX_STATE_FREED 0
745#define NX_HOST_CTX_STATE_ALLOCATED 1
746#define NX_HOST_CTX_STATE_ACTIVE 2
747#define NX_HOST_CTX_STATE_DISABLED 3
748#define NX_HOST_CTX_STATE_QUIESCED 4
749#define NX_HOST_CTX_STATE_MAX 5
750
751
752
753
754
755typedef struct {
756 __le64 host_phys_addr;
757 __le32 ring_size;
758 __le16 msi_index;
759 __le16 rsvd;
760} nx_hostrq_sds_ring_t;
761
762typedef struct {
763 __le64 host_phys_addr;
764 __le64 buff_size;
765 __le32 ring_size;
766 __le32 ring_kind;
767} nx_hostrq_rds_ring_t;
768
769typedef struct {
770 __le64 host_rsp_dma_addr;
771 __le32 capabilities[4];
772 __le32 host_int_crb_mode;
773 __le32 host_rds_crb_mode;
774
775 __le32 rds_ring_offset;
776 __le32 sds_ring_offset;
777 __le16 num_rds_rings;
778 __le16 num_sds_rings;
779 __le16 rsvd1;
780 __le16 rsvd2;
781 u8 reserved[128];
782
783
784
785
786 char data[0];
787} nx_hostrq_rx_ctx_t;
788
789typedef struct {
790 __le32 host_producer_crb;
791 __le32 rsvd1;
792} nx_cardrsp_rds_ring_t;
793
794typedef struct {
795 __le32 host_consumer_crb;
796 __le32 interrupt_crb;
797} nx_cardrsp_sds_ring_t;
798
799typedef struct {
800
801 __le32 rds_ring_offset;
802 __le32 sds_ring_offset;
803 __le32 host_ctx_state;
804 __le32 num_fn_per_port;
805 __le16 num_rds_rings;
806 __le16 num_sds_rings;
807 __le16 context_id;
808 u8 phys_port;
809 u8 virt_port;
810 u8 reserved[128];
811
812
813
814
815 char data[0];
816} nx_cardrsp_rx_ctx_t;
817
818#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
819 (sizeof(HOSTRQ_RX) + \
820 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
821 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
822
823#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
824 (sizeof(CARDRSP_RX) + \
825 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
826 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
827
828
829
830
831
832typedef struct {
833 __le64 host_phys_addr;
834 __le32 ring_size;
835 __le32 rsvd;
836} nx_hostrq_cds_ring_t;
837
838typedef struct {
839 __le64 host_rsp_dma_addr;
840 __le64 cmd_cons_dma_addr;
841 __le64 dummy_dma_addr;
842 __le32 capabilities[4];
843 __le32 host_int_crb_mode;
844 __le32 rsvd1;
845 __le16 rsvd2;
846 __le16 interrupt_ctl;
847 __le16 msi_index;
848 __le16 rsvd3;
849 nx_hostrq_cds_ring_t cds_ring;
850 u8 reserved[128];
851} nx_hostrq_tx_ctx_t;
852
853typedef struct {
854 __le32 host_producer_crb;
855 __le32 interrupt_crb;
856} nx_cardrsp_cds_ring_t;
857
858typedef struct {
859 __le32 host_ctx_state;
860 __le16 context_id;
861 u8 phys_port;
862 u8 virt_port;
863 nx_cardrsp_cds_ring_t cds_ring;
864 u8 reserved[128];
865} nx_cardrsp_tx_ctx_t;
866
867#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
868#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
869
870
871
872#define NX_HOST_RDS_CRB_MODE_UNIQUE 0
873#define NX_HOST_RDS_CRB_MODE_SHARED 1
874#define NX_HOST_RDS_CRB_MODE_CUSTOM 2
875#define NX_HOST_RDS_CRB_MODE_MAX 3
876
877#define NX_HOST_INT_CRB_MODE_UNIQUE 0
878#define NX_HOST_INT_CRB_MODE_SHARED 1
879#define NX_HOST_INT_CRB_MODE_NORX 2
880#define NX_HOST_INT_CRB_MODE_NOTX 3
881#define NX_HOST_INT_CRB_MODE_NORXTX 4
882
883
884
885
886#define MC_COUNT_P2 16
887#define MC_COUNT_P3 38
888
889#define NETXEN_MAC_NOOP 0
890#define NETXEN_MAC_ADD 1
891#define NETXEN_MAC_DEL 2
892
893typedef struct nx_mac_list_s {
894 struct list_head list;
895 uint8_t mac_addr[ETH_ALEN+2];
896} nx_mac_list_t;
897
898
899
900
901
902#define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
903#define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
904#define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
905#define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
906
907#define NETXEN_NIC_INTR_DEFAULT 0x04
908
909typedef union {
910 struct {
911 uint16_t rx_packets;
912 uint16_t rx_time_us;
913 uint16_t tx_packets;
914 uint16_t tx_time_us;
915 } data;
916 uint64_t word;
917} nx_nic_intr_coalesce_data_t;
918
919typedef struct {
920 uint16_t stats_time_us;
921 uint16_t rate_sample_time;
922 uint16_t flags;
923 uint16_t rsvd_1;
924 uint32_t low_threshold;
925 uint32_t high_threshold;
926 nx_nic_intr_coalesce_data_t normal;
927 nx_nic_intr_coalesce_data_t low;
928 nx_nic_intr_coalesce_data_t high;
929 nx_nic_intr_coalesce_data_t irq;
930} nx_nic_intr_coalesce_t;
931
932#define NX_HOST_REQUEST 0x13
933#define NX_NIC_REQUEST 0x14
934
935#define NX_MAC_EVENT 0x1
936
937#define NX_IP_UP 2
938#define NX_IP_DOWN 3
939
940
941
942
943#define NX_NIC_H2C_OPCODE_START 0
944#define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
945#define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
946#define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
947#define NX_NIC_H2C_OPCODE_CONFIG_LED 4
948#define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
949#define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
950#define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
951#define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
952#define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
953#define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
954#define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
955#define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
956#define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
957#define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
958#define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
959#define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
960#define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
961#define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
962#define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
963#define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
964#define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
965#define NX_NIC_C2C_OPCODE 22
966#define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
967#define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
968#define NX_NIC_H2C_OPCODE_LAST 25
969
970
971
972
973
974#define NX_NIC_C2H_OPCODE_START 128
975#define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
976#define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
977#define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
978#define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
979#define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
980#define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
981#define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
982#define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
983#define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
984#define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
985#define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
986#define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
987#define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
988#define NX_NIC_C2H_OPCODE_LAST 142
989
990#define VPORT_MISS_MODE_DROP 0
991#define VPORT_MISS_MODE_ACCEPT_ALL 1
992#define VPORT_MISS_MODE_ACCEPT_MULTI 2
993
994#define NX_NIC_LRO_REQUEST_FIRST 0
995#define NX_NIC_LRO_REQUEST_ADD_FLOW 1
996#define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
997#define NX_NIC_LRO_REQUEST_TIMER 3
998#define NX_NIC_LRO_REQUEST_CLEANUP 4
999#define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1000#define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1001#define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1002#define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1003#define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1004#define NX_TOE_LRO_REQUEST_TIMER 10
1005#define NX_NIC_LRO_REQUEST_LAST 11
1006
1007#define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1008#define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1009#define NX_FW_CAPABILITY_PEXQ (1 << 7)
1010#define NX_FW_CAPABILITY_BDG (1 << 8)
1011#define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1012#define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1013
1014
1015#define LINKEVENT_MODULE_NOT_PRESENT 1
1016#define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1017#define LINKEVENT_MODULE_OPTICAL_SRLR 3
1018#define LINKEVENT_MODULE_OPTICAL_LRM 4
1019#define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1020#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1021#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1022#define LINKEVENT_MODULE_TWINAX 8
1023
1024#define LINKSPEED_10GBPS 10000
1025#define LINKSPEED_1GBPS 1000
1026#define LINKSPEED_100MBPS 100
1027#define LINKSPEED_10MBPS 10
1028
1029#define LINKSPEED_ENCODED_10MBPS 0
1030#define LINKSPEED_ENCODED_100MBPS 1
1031#define LINKSPEED_ENCODED_1GBPS 2
1032
1033#define LINKEVENT_AUTONEG_DISABLED 0
1034#define LINKEVENT_AUTONEG_ENABLED 1
1035
1036#define LINKEVENT_HALF_DUPLEX 0
1037#define LINKEVENT_FULL_DUPLEX 1
1038
1039#define LINKEVENT_LINKSPEED_MBPS 0
1040#define LINKEVENT_LINKSPEED_ENCODED 1
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052#define netxen_get_nic_msgtype(msg_hdr) \
1053 ((msg_hdr >> 58) & 0x3F)
1054#define netxen_get_nic_msg_compid(msg_hdr) \
1055 ((msg_hdr >> 40) & 0xFF)
1056#define netxen_get_nic_msg_opcode(msg_hdr) \
1057 ((msg_hdr >> 32) & 0xFF)
1058#define netxen_get_nic_msg_errcode(msg_hdr) \
1059 ((msg_hdr >> 16) & 0xFFFF)
1060
1061typedef struct {
1062 union {
1063 struct {
1064 u64 hdr;
1065 u64 body[7];
1066 };
1067 u64 words[8];
1068 };
1069} nx_fw_msg_t;
1070
1071typedef struct {
1072 __le64 qhdr;
1073 __le64 req_hdr;
1074 __le64 words[6];
1075} nx_nic_req_t;
1076
1077typedef struct {
1078 u8 op;
1079 u8 tag;
1080 u8 mac_addr[6];
1081} nx_mac_req_t;
1082
1083#define MAX_PENDING_DESC_BLOCK_SIZE 64
1084
1085#define NETXEN_NIC_MSI_ENABLED 0x02
1086#define NETXEN_NIC_MSIX_ENABLED 0x04
1087#define NETXEN_NIC_LRO_ENABLED 0x08
1088#define NETXEN_NIC_BRIDGE_ENABLED 0X10
1089#define NETXEN_IS_MSI_FAMILY(adapter) \
1090 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1091
1092#define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1093#define NETXEN_MSIX_TBL_SPACE 8192
1094#define NETXEN_PCI_REG_MSIX_TBL 0x44
1095
1096#define NETXEN_DB_MAPSIZE_BYTES 0x1000
1097
1098#define NETXEN_NETDEV_WEIGHT 128
1099#define NETXEN_ADAPTER_UP_MAGIC 777
1100#define NETXEN_NIC_PEG_TUNE 0
1101
1102#define __NX_FW_ATTACHED 0
1103#define __NX_DEV_UP 1
1104#define __NX_RESETTING 2
1105
1106struct netxen_dummy_dma {
1107 void *addr;
1108 dma_addr_t phys_addr;
1109};
1110
1111struct netxen_adapter {
1112 struct netxen_hardware_context ahw;
1113
1114 struct net_device *netdev;
1115 struct pci_dev *pdev;
1116 struct list_head mac_list;
1117
1118 u32 curr_window;
1119 u32 crb_win;
1120 rwlock_t adapter_lock;
1121
1122 spinlock_t tx_clean_lock;
1123
1124 u16 num_txd;
1125 u16 num_rxd;
1126 u16 num_jumbo_rxd;
1127 u16 num_lro_rxd;
1128
1129 u8 max_rds_rings;
1130 u8 max_sds_rings;
1131 u8 driver_mismatch;
1132 u8 msix_supported;
1133 u8 rx_csum;
1134 u8 pci_using_dac;
1135 u8 portnum;
1136 u8 physical_port;
1137
1138 u8 mc_enabled;
1139 u8 max_mc_count;
1140 u8 rss_supported;
1141 u8 link_changed;
1142 u8 fw_wait_cnt;
1143 u8 fw_fail_cnt;
1144 u8 tx_timeo_cnt;
1145 u8 need_fw_reset;
1146
1147 u8 has_link_events;
1148 u8 fw_type;
1149 u16 tx_context_id;
1150 u16 mtu;
1151 u16 is_up;
1152
1153 u16 link_speed;
1154 u16 link_duplex;
1155 u16 link_autoneg;
1156 u16 module_type;
1157
1158 u32 capabilities;
1159 u32 flags;
1160 u32 irq;
1161 u32 temp;
1162
1163 u32 int_vec_bit;
1164 u32 heartbit;
1165
1166 u8 mac_addr[ETH_ALEN];
1167
1168 struct netxen_adapter_stats stats;
1169
1170 struct netxen_recv_context recv_ctx;
1171 struct nx_host_tx_ring *tx_ring;
1172
1173 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1174 int (*set_mtu) (struct netxen_adapter *, int);
1175 int (*set_promisc) (struct netxen_adapter *, u32);
1176 void (*set_multi) (struct net_device *);
1177 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1178 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1179 int (*init_port) (struct netxen_adapter *, int);
1180 int (*stop_port) (struct netxen_adapter *);
1181
1182 u32 (*crb_read)(struct netxen_adapter *, ulong);
1183 int (*crb_write)(struct netxen_adapter *, ulong, u32);
1184
1185 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1186 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1187
1188 unsigned long (*pci_set_window)(struct netxen_adapter *,
1189 unsigned long long);
1190
1191 u32 (*io_read)(struct netxen_adapter *, void __iomem *);
1192 void (*io_write)(struct netxen_adapter *, void __iomem *, u32);
1193
1194 void __iomem *tgt_mask_reg;
1195 void __iomem *pci_int_reg;
1196 void __iomem *tgt_status_reg;
1197 void __iomem *crb_int_state_reg;
1198 void __iomem *isr_int_vec;
1199
1200 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1201
1202 struct netxen_dummy_dma dummy_dma;
1203
1204 struct delayed_work fw_work;
1205
1206 struct work_struct tx_timeout_task;
1207
1208 struct net_device_stats net_stats;
1209
1210 nx_nic_intr_coalesce_t coal;
1211
1212 unsigned long state;
1213 u32 resv5;
1214 u32 fw_version;
1215 const struct firmware *fw;
1216};
1217
1218int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
1219int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
1220
1221int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1222int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1223
1224
1225int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1226int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1227
1228int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1229int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1230
1231#define NXRD32(adapter, off) \
1232 (adapter->crb_read(adapter, off))
1233#define NXWR32(adapter, off, val) \
1234 (adapter->crb_write(adapter, off, val))
1235#define NXRDIO(adapter, addr) \
1236 (adapter->io_read(adapter, addr))
1237#define NXWRIO(adapter, addr, val) \
1238 (adapter->io_write(adapter, addr, val))
1239
1240int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1241void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1242
1243#define netxen_rom_lock(a) \
1244 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1245#define netxen_rom_unlock(a) \
1246 netxen_pcie_sem_unlock((a), 2)
1247#define netxen_phy_lock(a) \
1248 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1249#define netxen_phy_unlock(a) \
1250 netxen_pcie_sem_unlock((a), 3)
1251#define netxen_api_lock(a) \
1252 netxen_pcie_sem_lock((a), 5, 0)
1253#define netxen_api_unlock(a) \
1254 netxen_pcie_sem_unlock((a), 5)
1255#define netxen_sw_lock(a) \
1256 netxen_pcie_sem_lock((a), 6, 0)
1257#define netxen_sw_unlock(a) \
1258 netxen_pcie_sem_unlock((a), 6)
1259#define crb_win_lock(a) \
1260 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1261#define crb_win_unlock(a) \
1262 netxen_pcie_sem_unlock((a), 7)
1263
1264int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1265int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1266
1267
1268int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1269void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1270
1271int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1272int netxen_load_firmware(struct netxen_adapter *adapter);
1273int netxen_need_fw_reset(struct netxen_adapter *adapter);
1274void netxen_request_firmware(struct netxen_adapter *adapter);
1275void netxen_release_firmware(struct netxen_adapter *adapter);
1276int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1277
1278int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1279int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1280 u8 *bytes, size_t size);
1281int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1282 u8 *bytes, size_t size);
1283int netxen_flash_unlock(struct netxen_adapter *adapter);
1284int netxen_backup_crbinit(struct netxen_adapter *adapter);
1285int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1286int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1287void netxen_halt_pegs(struct netxen_adapter *adapter);
1288
1289int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1290
1291int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1292void netxen_free_sw_resources(struct netxen_adapter *adapter);
1293
1294void netxen_setup_hwops(struct netxen_adapter *adapter);
1295void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32);
1296
1297int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1298void netxen_free_hw_resources(struct netxen_adapter *adapter);
1299
1300void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1301void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1302
1303int netxen_init_firmware(struct netxen_adapter *adapter);
1304void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1305void netxen_watchdog_task(struct work_struct *work);
1306void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1307 struct nx_host_rds_ring *rds_ring);
1308int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1309int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1310void netxen_p2_nic_set_multi(struct net_device *netdev);
1311void netxen_p3_nic_set_multi(struct net_device *netdev);
1312void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1313int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode);
1314int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1315int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1316int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1317int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1318int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1319void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1320
1321int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1322int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1323int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1324int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1325int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1326
1327int netxen_nic_set_mac(struct net_device *netdev, void *p);
1328struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1329
1330void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1331 struct nx_host_tx_ring *tx_ring);
1332
1333
1334int netxen_nic_reset_context(struct netxen_adapter *);
1335
1336
1337
1338
1339
1340#define NETXEN_MAX_SHORT_NAME 32
1341struct netxen_brdinfo {
1342 int brdtype;
1343 long ports;
1344 char short_name[NETXEN_MAX_SHORT_NAME];
1345};
1346
1347static const struct netxen_brdinfo netxen_boards[] = {
1348 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1349 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1350 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1351 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1352 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1353 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1354 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1355 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1356 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1357 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1358 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1359 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1360 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1361 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1362 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1363 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1364 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1365 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1366 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1367};
1368
1369#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1370
1371static inline void get_brd_name_by_type(u32 type, char *name)
1372{
1373 int i, found = 0;
1374 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1375 if (netxen_boards[i].brdtype == type) {
1376 strcpy(name, netxen_boards[i].short_name);
1377 found = 1;
1378 break;
1379 }
1380
1381 }
1382 if (!found)
1383 name = "Unknown";
1384}
1385
1386static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1387{
1388 smp_mb();
1389 return find_diff_among(tx_ring->producer,
1390 tx_ring->sw_consumer, tx_ring->num_desc);
1391
1392}
1393
1394int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1395int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1396extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1397extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1398 int *valp);
1399
1400extern const struct ethtool_ops netxen_nic_ethtool_ops;
1401
1402#endif
1403