linux/drivers/net/s2io.c
<<
>>
Prefs
   1/************************************************************************
   2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3 * Copyright(c) 2002-2007 Neterion Inc.
   4 *
   5 * This software may be used and distributed according to the terms of
   6 * the GNU General Public License (GPL), incorporated herein by reference.
   7 * Drivers based on or derived from this code fall under the GPL and must
   8 * retain the authorship, copyright and license notice.  This file is not
   9 * a complete program and may only be used when the entire operating
  10 * system is licensed under the GPL.
  11 * See the file COPYING in this distribution for more information.
  12 *
  13 * Credits:
  14 * Jeff Garzik          : For pointing out the improper error condition
  15 *                        check in the s2io_xmit routine and also some
  16 *                        issues in the Tx watch dog function. Also for
  17 *                        patiently answering all those innumerable
  18 *                        questions regaring the 2.6 porting issues.
  19 * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20 *                        macros available only in 2.6 Kernel.
  21 * Francois Romieu      : For pointing out all code part that were
  22 *                        deprecated and also styling related comments.
  23 * Grant Grundler       : For helping me get rid of some Architecture
  24 *                        dependent code.
  25 * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26 *
  27 * The module loadable parameters that are supported by the driver and a brief
  28 * explanation of all the variables.
  29 *
  30 * rx_ring_num : This can be used to program the number of receive rings used
  31 * in the driver.
  32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33 *     This is also an array of size 8.
  34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35 *              values are 1, 2.
  36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38 * Tx descriptors that can be associated with each corresponding FIFO.
  39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40 *     2(MSI_X). Default value is '2(MSI_X)'
  41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
  42 *     Possible values '1' for enable '0' for disable. Default is '0'
  43 * lro_max_pkts: This parameter defines maximum number of packets can be
  44 *     aggregated as a single large packet
  45 * napi: This parameter used to enable/disable NAPI (polling Rx)
  46 *     Possible values '1' for enable and '0' for disable. Default is '1'
  47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  48 *      Possible values '1' for enable and '0' for disable. Default is '0'
  49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  50 *                 Possible values '1' for enable , '0' for disable.
  51 *                 Default is '2' - which means disable in promisc mode
  52 *                 and enable in non-promiscuous mode.
  53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
  54 *      Possible values '1' for enable and '0' for disable. Default is '0'
  55 ************************************************************************/
  56
  57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  58
  59#include <linux/module.h>
  60#include <linux/types.h>
  61#include <linux/errno.h>
  62#include <linux/ioport.h>
  63#include <linux/pci.h>
  64#include <linux/dma-mapping.h>
  65#include <linux/kernel.h>
  66#include <linux/netdevice.h>
  67#include <linux/etherdevice.h>
  68#include <linux/mdio.h>
  69#include <linux/skbuff.h>
  70#include <linux/init.h>
  71#include <linux/delay.h>
  72#include <linux/stddef.h>
  73#include <linux/ioctl.h>
  74#include <linux/timex.h>
  75#include <linux/ethtool.h>
  76#include <linux/workqueue.h>
  77#include <linux/if_vlan.h>
  78#include <linux/ip.h>
  79#include <linux/tcp.h>
  80#include <linux/uaccess.h>
  81#include <linux/io.h>
  82#include <net/tcp.h>
  83
  84#include <asm/system.h>
  85#include <asm/div64.h>
  86#include <asm/irq.h>
  87
  88/* local include */
  89#include "s2io.h"
  90#include "s2io-regs.h"
  91
  92#define DRV_VERSION "2.0.26.25"
  93
  94/* S2io Driver name & version. */
  95static char s2io_driver_name[] = "Neterion";
  96static char s2io_driver_version[] = DRV_VERSION;
  97
  98static int rxd_size[2] = {32, 48};
  99static int rxd_count[2] = {127, 85};
 100
 101static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
 102{
 103        int ret;
 104
 105        ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 106               (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 107
 108        return ret;
 109}
 110
 111/*
 112 * Cards with following subsystem_id have a link state indication
 113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 114 * macro below identifies these cards given the subsystem_id.
 115 */
 116#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid)              \
 117        (dev_type == XFRAME_I_DEVICE) ?                                 \
 118        ((((subid >= 0x600B) && (subid <= 0x600D)) ||                   \
 119          ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 120
 121#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 122                                      ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 123
 124static inline int is_s2io_card_up(const struct s2io_nic *sp)
 125{
 126        return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
 127}
 128
 129/* Ethtool related variables and Macros. */
 130static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
 131        "Register test\t(offline)",
 132        "Eeprom test\t(offline)",
 133        "Link test\t(online)",
 134        "RLDRAM test\t(offline)",
 135        "BIST Test\t(offline)"
 136};
 137
 138static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 139        {"tmac_frms"},
 140        {"tmac_data_octets"},
 141        {"tmac_drop_frms"},
 142        {"tmac_mcst_frms"},
 143        {"tmac_bcst_frms"},
 144        {"tmac_pause_ctrl_frms"},
 145        {"tmac_ttl_octets"},
 146        {"tmac_ucst_frms"},
 147        {"tmac_nucst_frms"},
 148        {"tmac_any_err_frms"},
 149        {"tmac_ttl_less_fb_octets"},
 150        {"tmac_vld_ip_octets"},
 151        {"tmac_vld_ip"},
 152        {"tmac_drop_ip"},
 153        {"tmac_icmp"},
 154        {"tmac_rst_tcp"},
 155        {"tmac_tcp"},
 156        {"tmac_udp"},
 157        {"rmac_vld_frms"},
 158        {"rmac_data_octets"},
 159        {"rmac_fcs_err_frms"},
 160        {"rmac_drop_frms"},
 161        {"rmac_vld_mcst_frms"},
 162        {"rmac_vld_bcst_frms"},
 163        {"rmac_in_rng_len_err_frms"},
 164        {"rmac_out_rng_len_err_frms"},
 165        {"rmac_long_frms"},
 166        {"rmac_pause_ctrl_frms"},
 167        {"rmac_unsup_ctrl_frms"},
 168        {"rmac_ttl_octets"},
 169        {"rmac_accepted_ucst_frms"},
 170        {"rmac_accepted_nucst_frms"},
 171        {"rmac_discarded_frms"},
 172        {"rmac_drop_events"},
 173        {"rmac_ttl_less_fb_octets"},
 174        {"rmac_ttl_frms"},
 175        {"rmac_usized_frms"},
 176        {"rmac_osized_frms"},
 177        {"rmac_frag_frms"},
 178        {"rmac_jabber_frms"},
 179        {"rmac_ttl_64_frms"},
 180        {"rmac_ttl_65_127_frms"},
 181        {"rmac_ttl_128_255_frms"},
 182        {"rmac_ttl_256_511_frms"},
 183        {"rmac_ttl_512_1023_frms"},
 184        {"rmac_ttl_1024_1518_frms"},
 185        {"rmac_ip"},
 186        {"rmac_ip_octets"},
 187        {"rmac_hdr_err_ip"},
 188        {"rmac_drop_ip"},
 189        {"rmac_icmp"},
 190        {"rmac_tcp"},
 191        {"rmac_udp"},
 192        {"rmac_err_drp_udp"},
 193        {"rmac_xgmii_err_sym"},
 194        {"rmac_frms_q0"},
 195        {"rmac_frms_q1"},
 196        {"rmac_frms_q2"},
 197        {"rmac_frms_q3"},
 198        {"rmac_frms_q4"},
 199        {"rmac_frms_q5"},
 200        {"rmac_frms_q6"},
 201        {"rmac_frms_q7"},
 202        {"rmac_full_q0"},
 203        {"rmac_full_q1"},
 204        {"rmac_full_q2"},
 205        {"rmac_full_q3"},
 206        {"rmac_full_q4"},
 207        {"rmac_full_q5"},
 208        {"rmac_full_q6"},
 209        {"rmac_full_q7"},
 210        {"rmac_pause_cnt"},
 211        {"rmac_xgmii_data_err_cnt"},
 212        {"rmac_xgmii_ctrl_err_cnt"},
 213        {"rmac_accepted_ip"},
 214        {"rmac_err_tcp"},
 215        {"rd_req_cnt"},
 216        {"new_rd_req_cnt"},
 217        {"new_rd_req_rtry_cnt"},
 218        {"rd_rtry_cnt"},
 219        {"wr_rtry_rd_ack_cnt"},
 220        {"wr_req_cnt"},
 221        {"new_wr_req_cnt"},
 222        {"new_wr_req_rtry_cnt"},
 223        {"wr_rtry_cnt"},
 224        {"wr_disc_cnt"},
 225        {"rd_rtry_wr_ack_cnt"},
 226        {"txp_wr_cnt"},
 227        {"txd_rd_cnt"},
 228        {"txd_wr_cnt"},
 229        {"rxd_rd_cnt"},
 230        {"rxd_wr_cnt"},
 231        {"txf_rd_cnt"},
 232        {"rxf_wr_cnt"}
 233};
 234
 235static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 236        {"rmac_ttl_1519_4095_frms"},
 237        {"rmac_ttl_4096_8191_frms"},
 238        {"rmac_ttl_8192_max_frms"},
 239        {"rmac_ttl_gt_max_frms"},
 240        {"rmac_osized_alt_frms"},
 241        {"rmac_jabber_alt_frms"},
 242        {"rmac_gt_max_alt_frms"},
 243        {"rmac_vlan_frms"},
 244        {"rmac_len_discard"},
 245        {"rmac_fcs_discard"},
 246        {"rmac_pf_discard"},
 247        {"rmac_da_discard"},
 248        {"rmac_red_discard"},
 249        {"rmac_rts_discard"},
 250        {"rmac_ingm_full_discard"},
 251        {"link_fault_cnt"}
 252};
 253
 254static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 255        {"\n DRIVER STATISTICS"},
 256        {"single_bit_ecc_errs"},
 257        {"double_bit_ecc_errs"},
 258        {"parity_err_cnt"},
 259        {"serious_err_cnt"},
 260        {"soft_reset_cnt"},
 261        {"fifo_full_cnt"},
 262        {"ring_0_full_cnt"},
 263        {"ring_1_full_cnt"},
 264        {"ring_2_full_cnt"},
 265        {"ring_3_full_cnt"},
 266        {"ring_4_full_cnt"},
 267        {"ring_5_full_cnt"},
 268        {"ring_6_full_cnt"},
 269        {"ring_7_full_cnt"},
 270        {"alarm_transceiver_temp_high"},
 271        {"alarm_transceiver_temp_low"},
 272        {"alarm_laser_bias_current_high"},
 273        {"alarm_laser_bias_current_low"},
 274        {"alarm_laser_output_power_high"},
 275        {"alarm_laser_output_power_low"},
 276        {"warn_transceiver_temp_high"},
 277        {"warn_transceiver_temp_low"},
 278        {"warn_laser_bias_current_high"},
 279        {"warn_laser_bias_current_low"},
 280        {"warn_laser_output_power_high"},
 281        {"warn_laser_output_power_low"},
 282        {"lro_aggregated_pkts"},
 283        {"lro_flush_both_count"},
 284        {"lro_out_of_sequence_pkts"},
 285        {"lro_flush_due_to_max_pkts"},
 286        {"lro_avg_aggr_pkts"},
 287        {"mem_alloc_fail_cnt"},
 288        {"pci_map_fail_cnt"},
 289        {"watchdog_timer_cnt"},
 290        {"mem_allocated"},
 291        {"mem_freed"},
 292        {"link_up_cnt"},
 293        {"link_down_cnt"},
 294        {"link_up_time"},
 295        {"link_down_time"},
 296        {"tx_tcode_buf_abort_cnt"},
 297        {"tx_tcode_desc_abort_cnt"},
 298        {"tx_tcode_parity_err_cnt"},
 299        {"tx_tcode_link_loss_cnt"},
 300        {"tx_tcode_list_proc_err_cnt"},
 301        {"rx_tcode_parity_err_cnt"},
 302        {"rx_tcode_abort_cnt"},
 303        {"rx_tcode_parity_abort_cnt"},
 304        {"rx_tcode_rda_fail_cnt"},
 305        {"rx_tcode_unkn_prot_cnt"},
 306        {"rx_tcode_fcs_err_cnt"},
 307        {"rx_tcode_buf_size_err_cnt"},
 308        {"rx_tcode_rxd_corrupt_cnt"},
 309        {"rx_tcode_unkn_err_cnt"},
 310        {"tda_err_cnt"},
 311        {"pfc_err_cnt"},
 312        {"pcc_err_cnt"},
 313        {"tti_err_cnt"},
 314        {"tpa_err_cnt"},
 315        {"sm_err_cnt"},
 316        {"lso_err_cnt"},
 317        {"mac_tmac_err_cnt"},
 318        {"mac_rmac_err_cnt"},
 319        {"xgxs_txgxs_err_cnt"},
 320        {"xgxs_rxgxs_err_cnt"},
 321        {"rc_err_cnt"},
 322        {"prc_pcix_err_cnt"},
 323        {"rpa_err_cnt"},
 324        {"rda_err_cnt"},
 325        {"rti_err_cnt"},
 326        {"mc_err_cnt"}
 327};
 328
 329#define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
 330#define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
 331#define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
 332
 333#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
 334#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
 335
 336#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
 337#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
 338
 339#define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
 340#define S2IO_STRINGS_LEN        (S2IO_TEST_LEN * ETH_GSTRING_LEN)
 341
 342#define S2IO_TIMER_CONF(timer, handle, arg, exp)        \
 343        init_timer(&timer);                             \
 344        timer.function = handle;                        \
 345        timer.data = (unsigned long)arg;                \
 346        mod_timer(&timer, (jiffies + exp))              \
 347
 348/* copy mac addr to def_mac_addr array */
 349static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
 350{
 351        sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
 352        sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
 353        sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
 354        sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
 355        sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
 356        sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
 357}
 358
 359/* Add the vlan */
 360static void s2io_vlan_rx_register(struct net_device *dev,
 361                                  struct vlan_group *grp)
 362{
 363        int i;
 364        struct s2io_nic *nic = netdev_priv(dev);
 365        unsigned long flags[MAX_TX_FIFOS];
 366        struct config_param *config = &nic->config;
 367        struct mac_info *mac_control = &nic->mac_control;
 368
 369        for (i = 0; i < config->tx_fifo_num; i++) {
 370                struct fifo_info *fifo = &mac_control->fifos[i];
 371
 372                spin_lock_irqsave(&fifo->tx_lock, flags[i]);
 373        }
 374
 375        nic->vlgrp = grp;
 376
 377        for (i = config->tx_fifo_num - 1; i >= 0; i--) {
 378                struct fifo_info *fifo = &mac_control->fifos[i];
 379
 380                spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
 381        }
 382}
 383
 384/* Unregister the vlan */
 385static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 386{
 387        int i;
 388        struct s2io_nic *nic = netdev_priv(dev);
 389        unsigned long flags[MAX_TX_FIFOS];
 390        struct config_param *config = &nic->config;
 391        struct mac_info *mac_control = &nic->mac_control;
 392
 393        for (i = 0; i < config->tx_fifo_num; i++) {
 394                struct fifo_info *fifo = &mac_control->fifos[i];
 395
 396                spin_lock_irqsave(&fifo->tx_lock, flags[i]);
 397        }
 398
 399        if (nic->vlgrp)
 400                vlan_group_set_device(nic->vlgrp, vid, NULL);
 401
 402        for (i = config->tx_fifo_num - 1; i >= 0; i--) {
 403                struct fifo_info *fifo = &mac_control->fifos[i];
 404
 405                spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
 406        }
 407}
 408
 409/*
 410 * Constants to be programmed into the Xena's registers, to configure
 411 * the XAUI.
 412 */
 413
 414#define END_SIGN        0x0
 415static const u64 herc_act_dtx_cfg[] = {
 416        /* Set address */
 417        0x8000051536750000ULL, 0x80000515367500E0ULL,
 418        /* Write data */
 419        0x8000051536750004ULL, 0x80000515367500E4ULL,
 420        /* Set address */
 421        0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 422        /* Write data */
 423        0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 424        /* Set address */
 425        0x801205150D440000ULL, 0x801205150D4400E0ULL,
 426        /* Write data */
 427        0x801205150D440004ULL, 0x801205150D4400E4ULL,
 428        /* Set address */
 429        0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 430        /* Write data */
 431        0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 432        /* Done */
 433        END_SIGN
 434};
 435
 436static const u64 xena_dtx_cfg[] = {
 437        /* Set address */
 438        0x8000051500000000ULL, 0x80000515000000E0ULL,
 439        /* Write data */
 440        0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 441        /* Set address */
 442        0x8001051500000000ULL, 0x80010515000000E0ULL,
 443        /* Write data */
 444        0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 445        /* Set address */
 446        0x8002051500000000ULL, 0x80020515000000E0ULL,
 447        /* Write data */
 448        0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 449        END_SIGN
 450};
 451
 452/*
 453 * Constants for Fixing the MacAddress problem seen mostly on
 454 * Alpha machines.
 455 */
 456static const u64 fix_mac[] = {
 457        0x0060000000000000ULL, 0x0060600000000000ULL,
 458        0x0040600000000000ULL, 0x0000600000000000ULL,
 459        0x0020600000000000ULL, 0x0060600000000000ULL,
 460        0x0020600000000000ULL, 0x0060600000000000ULL,
 461        0x0020600000000000ULL, 0x0060600000000000ULL,
 462        0x0020600000000000ULL, 0x0060600000000000ULL,
 463        0x0020600000000000ULL, 0x0060600000000000ULL,
 464        0x0020600000000000ULL, 0x0060600000000000ULL,
 465        0x0020600000000000ULL, 0x0060600000000000ULL,
 466        0x0020600000000000ULL, 0x0060600000000000ULL,
 467        0x0020600000000000ULL, 0x0060600000000000ULL,
 468        0x0020600000000000ULL, 0x0060600000000000ULL,
 469        0x0020600000000000ULL, 0x0000600000000000ULL,
 470        0x0040600000000000ULL, 0x0060600000000000ULL,
 471        END_SIGN
 472};
 473
 474MODULE_LICENSE("GPL");
 475MODULE_VERSION(DRV_VERSION);
 476
 477
 478/* Module Loadable parameters. */
 479S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
 480S2IO_PARM_INT(rx_ring_num, 1);
 481S2IO_PARM_INT(multiq, 0);
 482S2IO_PARM_INT(rx_ring_mode, 1);
 483S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 484S2IO_PARM_INT(rmac_pause_time, 0x100);
 485S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 486S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 487S2IO_PARM_INT(shared_splits, 0);
 488S2IO_PARM_INT(tmac_util_period, 5);
 489S2IO_PARM_INT(rmac_util_period, 5);
 490S2IO_PARM_INT(l3l4hdr_size, 128);
 491/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
 492S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
 493/* Frequency of Rx desc syncs expressed as power of 2 */
 494S2IO_PARM_INT(rxsync_frequency, 3);
 495/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
 496S2IO_PARM_INT(intr_type, 2);
 497/* Large receive offload feature */
 498static unsigned int lro_enable;
 499module_param_named(lro, lro_enable, uint, 0);
 500
 501/* Max pkts to be aggregated by LRO at one time. If not specified,
 502 * aggregation happens until we hit max IP pkt size(64K)
 503 */
 504S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 505S2IO_PARM_INT(indicate_max_pkts, 0);
 506
 507S2IO_PARM_INT(napi, 1);
 508S2IO_PARM_INT(ufo, 0);
 509S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 510
 511static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 512{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 513static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 514{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 515static unsigned int rts_frm_len[MAX_RX_RINGS] =
 516{[0 ...(MAX_RX_RINGS - 1)] = 0 };
 517
 518module_param_array(tx_fifo_len, uint, NULL, 0);
 519module_param_array(rx_ring_sz, uint, NULL, 0);
 520module_param_array(rts_frm_len, uint, NULL, 0);
 521
 522/*
 523 * S2IO device table.
 524 * This table lists all the devices that this driver supports.
 525 */
 526static struct pci_device_id s2io_tbl[] __devinitdata = {
 527        {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 528         PCI_ANY_ID, PCI_ANY_ID},
 529        {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 530         PCI_ANY_ID, PCI_ANY_ID},
 531        {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 532         PCI_ANY_ID, PCI_ANY_ID},
 533        {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 534         PCI_ANY_ID, PCI_ANY_ID},
 535        {0,}
 536};
 537
 538MODULE_DEVICE_TABLE(pci, s2io_tbl);
 539
 540static struct pci_error_handlers s2io_err_handler = {
 541        .error_detected = s2io_io_error_detected,
 542        .slot_reset = s2io_io_slot_reset,
 543        .resume = s2io_io_resume,
 544};
 545
 546static struct pci_driver s2io_driver = {
 547        .name = "S2IO",
 548        .id_table = s2io_tbl,
 549        .probe = s2io_init_nic,
 550        .remove = __devexit_p(s2io_rem_nic),
 551        .err_handler = &s2io_err_handler,
 552};
 553
 554/* A simplifier macro used both by init and free shared_mem Fns(). */
 555#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 556
 557/* netqueue manipulation helper functions */
 558static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
 559{
 560        if (!sp->config.multiq) {
 561                int i;
 562
 563                for (i = 0; i < sp->config.tx_fifo_num; i++)
 564                        sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
 565        }
 566        netif_tx_stop_all_queues(sp->dev);
 567}
 568
 569static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
 570{
 571        if (!sp->config.multiq)
 572                sp->mac_control.fifos[fifo_no].queue_state =
 573                        FIFO_QUEUE_STOP;
 574
 575        netif_tx_stop_all_queues(sp->dev);
 576}
 577
 578static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
 579{
 580        if (!sp->config.multiq) {
 581                int i;
 582
 583                for (i = 0; i < sp->config.tx_fifo_num; i++)
 584                        sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 585        }
 586        netif_tx_start_all_queues(sp->dev);
 587}
 588
 589static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
 590{
 591        if (!sp->config.multiq)
 592                sp->mac_control.fifos[fifo_no].queue_state =
 593                        FIFO_QUEUE_START;
 594
 595        netif_tx_start_all_queues(sp->dev);
 596}
 597
 598static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
 599{
 600        if (!sp->config.multiq) {
 601                int i;
 602
 603                for (i = 0; i < sp->config.tx_fifo_num; i++)
 604                        sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 605        }
 606        netif_tx_wake_all_queues(sp->dev);
 607}
 608
 609static inline void s2io_wake_tx_queue(
 610        struct fifo_info *fifo, int cnt, u8 multiq)
 611{
 612
 613        if (multiq) {
 614                if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
 615                        netif_wake_subqueue(fifo->dev, fifo->fifo_no);
 616        } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
 617                if (netif_queue_stopped(fifo->dev)) {
 618                        fifo->queue_state = FIFO_QUEUE_START;
 619                        netif_wake_queue(fifo->dev);
 620                }
 621        }
 622}
 623
 624/**
 625 * init_shared_mem - Allocation and Initialization of Memory
 626 * @nic: Device private variable.
 627 * Description: The function allocates all the memory areas shared
 628 * between the NIC and the driver. This includes Tx descriptors,
 629 * Rx descriptors and the statistics block.
 630 */
 631
 632static int init_shared_mem(struct s2io_nic *nic)
 633{
 634        u32 size;
 635        void *tmp_v_addr, *tmp_v_addr_next;
 636        dma_addr_t tmp_p_addr, tmp_p_addr_next;
 637        struct RxD_block *pre_rxd_blk = NULL;
 638        int i, j, blk_cnt;
 639        int lst_size, lst_per_page;
 640        struct net_device *dev = nic->dev;
 641        unsigned long tmp;
 642        struct buffAdd *ba;
 643        struct config_param *config = &nic->config;
 644        struct mac_info *mac_control = &nic->mac_control;
 645        unsigned long long mem_allocated = 0;
 646
 647        /* Allocation and initialization of TXDLs in FIFOs */
 648        size = 0;
 649        for (i = 0; i < config->tx_fifo_num; i++) {
 650                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 651
 652                size += tx_cfg->fifo_len;
 653        }
 654        if (size > MAX_AVAILABLE_TXDS) {
 655                DBG_PRINT(ERR_DBG,
 656                          "Too many TxDs requested: %d, max supported: %d\n",
 657                          size, MAX_AVAILABLE_TXDS);
 658                return -EINVAL;
 659        }
 660
 661        size = 0;
 662        for (i = 0; i < config->tx_fifo_num; i++) {
 663                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 664
 665                size = tx_cfg->fifo_len;
 666                /*
 667                 * Legal values are from 2 to 8192
 668                 */
 669                if (size < 2) {
 670                        DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
 671                                  "Valid lengths are 2 through 8192\n",
 672                                  i, size);
 673                        return -EINVAL;
 674                }
 675        }
 676
 677        lst_size = (sizeof(struct TxD) * config->max_txds);
 678        lst_per_page = PAGE_SIZE / lst_size;
 679
 680        for (i = 0; i < config->tx_fifo_num; i++) {
 681                struct fifo_info *fifo = &mac_control->fifos[i];
 682                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 683                int fifo_len = tx_cfg->fifo_len;
 684                int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 685
 686                fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
 687                if (!fifo->list_info) {
 688                        DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
 689                        return -ENOMEM;
 690                }
 691                mem_allocated += list_holder_size;
 692        }
 693        for (i = 0; i < config->tx_fifo_num; i++) {
 694                int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 695                                                lst_per_page);
 696                struct fifo_info *fifo = &mac_control->fifos[i];
 697                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 698
 699                fifo->tx_curr_put_info.offset = 0;
 700                fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
 701                fifo->tx_curr_get_info.offset = 0;
 702                fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
 703                fifo->fifo_no = i;
 704                fifo->nic = nic;
 705                fifo->max_txds = MAX_SKB_FRAGS + 2;
 706                fifo->dev = dev;
 707
 708                for (j = 0; j < page_num; j++) {
 709                        int k = 0;
 710                        dma_addr_t tmp_p;
 711                        void *tmp_v;
 712                        tmp_v = pci_alloc_consistent(nic->pdev,
 713                                                     PAGE_SIZE, &tmp_p);
 714                        if (!tmp_v) {
 715                                DBG_PRINT(INFO_DBG,
 716                                          "pci_alloc_consistent failed for TxDL\n");
 717                                return -ENOMEM;
 718                        }
 719                        /* If we got a zero DMA address(can happen on
 720                         * certain platforms like PPC), reallocate.
 721                         * Store virtual address of page we don't want,
 722                         * to be freed later.
 723                         */
 724                        if (!tmp_p) {
 725                                mac_control->zerodma_virt_addr = tmp_v;
 726                                DBG_PRINT(INIT_DBG,
 727                                          "%s: Zero DMA address for TxDL. "
 728                                          "Virtual address %p\n",
 729                                          dev->name, tmp_v);
 730                                tmp_v = pci_alloc_consistent(nic->pdev,
 731                                                             PAGE_SIZE, &tmp_p);
 732                                if (!tmp_v) {
 733                                        DBG_PRINT(INFO_DBG,
 734                                                  "pci_alloc_consistent failed for TxDL\n");
 735                                        return -ENOMEM;
 736                                }
 737                                mem_allocated += PAGE_SIZE;
 738                        }
 739                        while (k < lst_per_page) {
 740                                int l = (j * lst_per_page) + k;
 741                                if (l == tx_cfg->fifo_len)
 742                                        break;
 743                                fifo->list_info[l].list_virt_addr =
 744                                        tmp_v + (k * lst_size);
 745                                fifo->list_info[l].list_phy_addr =
 746                                        tmp_p + (k * lst_size);
 747                                k++;
 748                        }
 749                }
 750        }
 751
 752        for (i = 0; i < config->tx_fifo_num; i++) {
 753                struct fifo_info *fifo = &mac_control->fifos[i];
 754                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 755
 756                size = tx_cfg->fifo_len;
 757                fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 758                if (!fifo->ufo_in_band_v)
 759                        return -ENOMEM;
 760                mem_allocated += (size * sizeof(u64));
 761        }
 762
 763        /* Allocation and initialization of RXDs in Rings */
 764        size = 0;
 765        for (i = 0; i < config->rx_ring_num; i++) {
 766                struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 767                struct ring_info *ring = &mac_control->rings[i];
 768
 769                if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
 770                        DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
 771                                  "multiple of RxDs per Block\n",
 772                                  dev->name, i);
 773                        return FAILURE;
 774                }
 775                size += rx_cfg->num_rxd;
 776                ring->block_count = rx_cfg->num_rxd /
 777                        (rxd_count[nic->rxd_mode] + 1);
 778                ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
 779        }
 780        if (nic->rxd_mode == RXD_MODE_1)
 781                size = (size * (sizeof(struct RxD1)));
 782        else
 783                size = (size * (sizeof(struct RxD3)));
 784
 785        for (i = 0; i < config->rx_ring_num; i++) {
 786                struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 787                struct ring_info *ring = &mac_control->rings[i];
 788
 789                ring->rx_curr_get_info.block_index = 0;
 790                ring->rx_curr_get_info.offset = 0;
 791                ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
 792                ring->rx_curr_put_info.block_index = 0;
 793                ring->rx_curr_put_info.offset = 0;
 794                ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
 795                ring->nic = nic;
 796                ring->ring_no = i;
 797                ring->lro = lro_enable;
 798
 799                blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
 800                /*  Allocating all the Rx blocks */
 801                for (j = 0; j < blk_cnt; j++) {
 802                        struct rx_block_info *rx_blocks;
 803                        int l;
 804
 805                        rx_blocks = &ring->rx_blocks[j];
 806                        size = SIZE_OF_BLOCK;   /* size is always page size */
 807                        tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 808                                                          &tmp_p_addr);
 809                        if (tmp_v_addr == NULL) {
 810                                /*
 811                                 * In case of failure, free_shared_mem()
 812                                 * is called, which should free any
 813                                 * memory that was alloced till the
 814                                 * failure happened.
 815                                 */
 816                                rx_blocks->block_virt_addr = tmp_v_addr;
 817                                return -ENOMEM;
 818                        }
 819                        mem_allocated += size;
 820                        memset(tmp_v_addr, 0, size);
 821
 822                        size = sizeof(struct rxd_info) *
 823                                rxd_count[nic->rxd_mode];
 824                        rx_blocks->block_virt_addr = tmp_v_addr;
 825                        rx_blocks->block_dma_addr = tmp_p_addr;
 826                        rx_blocks->rxds = kmalloc(size,  GFP_KERNEL);
 827                        if (!rx_blocks->rxds)
 828                                return -ENOMEM;
 829                        mem_allocated += size;
 830                        for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
 831                                rx_blocks->rxds[l].virt_addr =
 832                                        rx_blocks->block_virt_addr +
 833                                        (rxd_size[nic->rxd_mode] * l);
 834                                rx_blocks->rxds[l].dma_addr =
 835                                        rx_blocks->block_dma_addr +
 836                                        (rxd_size[nic->rxd_mode] * l);
 837                        }
 838                }
 839                /* Interlinking all Rx Blocks */
 840                for (j = 0; j < blk_cnt; j++) {
 841                        int next = (j + 1) % blk_cnt;
 842                        tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
 843                        tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
 844                        tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
 845                        tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
 846
 847                        pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
 848                        pre_rxd_blk->reserved_2_pNext_RxD_block =
 849                                (unsigned long)tmp_v_addr_next;
 850                        pre_rxd_blk->pNext_RxD_Blk_physical =
 851                                (u64)tmp_p_addr_next;
 852                }
 853        }
 854        if (nic->rxd_mode == RXD_MODE_3B) {
 855                /*
 856                 * Allocation of Storages for buffer addresses in 2BUFF mode
 857                 * and the buffers as well.
 858                 */
 859                for (i = 0; i < config->rx_ring_num; i++) {
 860                        struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 861                        struct ring_info *ring = &mac_control->rings[i];
 862
 863                        blk_cnt = rx_cfg->num_rxd /
 864                                (rxd_count[nic->rxd_mode] + 1);
 865                        size = sizeof(struct buffAdd *) * blk_cnt;
 866                        ring->ba = kmalloc(size, GFP_KERNEL);
 867                        if (!ring->ba)
 868                                return -ENOMEM;
 869                        mem_allocated += size;
 870                        for (j = 0; j < blk_cnt; j++) {
 871                                int k = 0;
 872
 873                                size = sizeof(struct buffAdd) *
 874                                        (rxd_count[nic->rxd_mode] + 1);
 875                                ring->ba[j] = kmalloc(size, GFP_KERNEL);
 876                                if (!ring->ba[j])
 877                                        return -ENOMEM;
 878                                mem_allocated += size;
 879                                while (k != rxd_count[nic->rxd_mode]) {
 880                                        ba = &ring->ba[j][k];
 881                                        size = BUF0_LEN + ALIGN_SIZE;
 882                                        ba->ba_0_org = kmalloc(size, GFP_KERNEL);
 883                                        if (!ba->ba_0_org)
 884                                                return -ENOMEM;
 885                                        mem_allocated += size;
 886                                        tmp = (unsigned long)ba->ba_0_org;
 887                                        tmp += ALIGN_SIZE;
 888                                        tmp &= ~((unsigned long)ALIGN_SIZE);
 889                                        ba->ba_0 = (void *)tmp;
 890
 891                                        size = BUF1_LEN + ALIGN_SIZE;
 892                                        ba->ba_1_org = kmalloc(size, GFP_KERNEL);
 893                                        if (!ba->ba_1_org)
 894                                                return -ENOMEM;
 895                                        mem_allocated += size;
 896                                        tmp = (unsigned long)ba->ba_1_org;
 897                                        tmp += ALIGN_SIZE;
 898                                        tmp &= ~((unsigned long)ALIGN_SIZE);
 899                                        ba->ba_1 = (void *)tmp;
 900                                        k++;
 901                                }
 902                        }
 903                }
 904        }
 905
 906        /* Allocation and initialization of Statistics block */
 907        size = sizeof(struct stat_block);
 908        mac_control->stats_mem =
 909                pci_alloc_consistent(nic->pdev, size,
 910                                     &mac_control->stats_mem_phy);
 911
 912        if (!mac_control->stats_mem) {
 913                /*
 914                 * In case of failure, free_shared_mem() is called, which
 915                 * should free any memory that was alloced till the
 916                 * failure happened.
 917                 */
 918                return -ENOMEM;
 919        }
 920        mem_allocated += size;
 921        mac_control->stats_mem_sz = size;
 922
 923        tmp_v_addr = mac_control->stats_mem;
 924        mac_control->stats_info = (struct stat_block *)tmp_v_addr;
 925        memset(tmp_v_addr, 0, size);
 926        DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n", dev->name,
 927                  (unsigned long long)tmp_p_addr);
 928        mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 929        return SUCCESS;
 930}
 931
 932/**
 933 * free_shared_mem - Free the allocated Memory
 934 * @nic:  Device private variable.
 935 * Description: This function is to free all memory locations allocated by
 936 * the init_shared_mem() function and return it to the kernel.
 937 */
 938
 939static void free_shared_mem(struct s2io_nic *nic)
 940{
 941        int i, j, blk_cnt, size;
 942        void *tmp_v_addr;
 943        dma_addr_t tmp_p_addr;
 944        int lst_size, lst_per_page;
 945        struct net_device *dev;
 946        int page_num = 0;
 947        struct config_param *config;
 948        struct mac_info *mac_control;
 949        struct stat_block *stats;
 950        struct swStat *swstats;
 951
 952        if (!nic)
 953                return;
 954
 955        dev = nic->dev;
 956
 957        config = &nic->config;
 958        mac_control = &nic->mac_control;
 959        stats = mac_control->stats_info;
 960        swstats = &stats->sw_stat;
 961
 962        lst_size = sizeof(struct TxD) * config->max_txds;
 963        lst_per_page = PAGE_SIZE / lst_size;
 964
 965        for (i = 0; i < config->tx_fifo_num; i++) {
 966                struct fifo_info *fifo = &mac_control->fifos[i];
 967                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 968
 969                page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
 970                for (j = 0; j < page_num; j++) {
 971                        int mem_blks = (j * lst_per_page);
 972                        struct list_info_hold *fli;
 973
 974                        if (!fifo->list_info)
 975                                return;
 976
 977                        fli = &fifo->list_info[mem_blks];
 978                        if (!fli->list_virt_addr)
 979                                break;
 980                        pci_free_consistent(nic->pdev, PAGE_SIZE,
 981                                            fli->list_virt_addr,
 982                                            fli->list_phy_addr);
 983                        swstats->mem_freed += PAGE_SIZE;
 984                }
 985                /* If we got a zero DMA address during allocation,
 986                 * free the page now
 987                 */
 988                if (mac_control->zerodma_virt_addr) {
 989                        pci_free_consistent(nic->pdev, PAGE_SIZE,
 990                                            mac_control->zerodma_virt_addr,
 991                                            (dma_addr_t)0);
 992                        DBG_PRINT(INIT_DBG,
 993                                  "%s: Freeing TxDL with zero DMA address. "
 994                                  "Virtual address %p\n",
 995                                  dev->name, mac_control->zerodma_virt_addr);
 996                        swstats->mem_freed += PAGE_SIZE;
 997                }
 998                kfree(fifo->list_info);
 999                swstats->mem_freed += tx_cfg->fifo_len *
1000                        sizeof(struct list_info_hold);
1001        }
1002
1003        size = SIZE_OF_BLOCK;
1004        for (i = 0; i < config->rx_ring_num; i++) {
1005                struct ring_info *ring = &mac_control->rings[i];
1006
1007                blk_cnt = ring->block_count;
1008                for (j = 0; j < blk_cnt; j++) {
1009                        tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1010                        tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1011                        if (tmp_v_addr == NULL)
1012                                break;
1013                        pci_free_consistent(nic->pdev, size,
1014                                            tmp_v_addr, tmp_p_addr);
1015                        swstats->mem_freed += size;
1016                        kfree(ring->rx_blocks[j].rxds);
1017                        swstats->mem_freed += sizeof(struct rxd_info) *
1018                                rxd_count[nic->rxd_mode];
1019                }
1020        }
1021
1022        if (nic->rxd_mode == RXD_MODE_3B) {
1023                /* Freeing buffer storage addresses in 2BUFF mode. */
1024                for (i = 0; i < config->rx_ring_num; i++) {
1025                        struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1026                        struct ring_info *ring = &mac_control->rings[i];
1027
1028                        blk_cnt = rx_cfg->num_rxd /
1029                                (rxd_count[nic->rxd_mode] + 1);
1030                        for (j = 0; j < blk_cnt; j++) {
1031                                int k = 0;
1032                                if (!ring->ba[j])
1033                                        continue;
1034                                while (k != rxd_count[nic->rxd_mode]) {
1035                                        struct buffAdd *ba = &ring->ba[j][k];
1036                                        kfree(ba->ba_0_org);
1037                                        swstats->mem_freed +=
1038                                                BUF0_LEN + ALIGN_SIZE;
1039                                        kfree(ba->ba_1_org);
1040                                        swstats->mem_freed +=
1041                                                BUF1_LEN + ALIGN_SIZE;
1042                                        k++;
1043                                }
1044                                kfree(ring->ba[j]);
1045                                swstats->mem_freed += sizeof(struct buffAdd) *
1046                                        (rxd_count[nic->rxd_mode] + 1);
1047                        }
1048                        kfree(ring->ba);
1049                        swstats->mem_freed += sizeof(struct buffAdd *) *
1050                                blk_cnt;
1051                }
1052        }
1053
1054        for (i = 0; i < nic->config.tx_fifo_num; i++) {
1055                struct fifo_info *fifo = &mac_control->fifos[i];
1056                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1057
1058                if (fifo->ufo_in_band_v) {
1059                        swstats->mem_freed += tx_cfg->fifo_len *
1060                                sizeof(u64);
1061                        kfree(fifo->ufo_in_band_v);
1062                }
1063        }
1064
1065        if (mac_control->stats_mem) {
1066                swstats->mem_freed += mac_control->stats_mem_sz;
1067                pci_free_consistent(nic->pdev,
1068                                    mac_control->stats_mem_sz,
1069                                    mac_control->stats_mem,
1070                                    mac_control->stats_mem_phy);
1071        }
1072}
1073
1074/**
1075 * s2io_verify_pci_mode -
1076 */
1077
1078static int s2io_verify_pci_mode(struct s2io_nic *nic)
1079{
1080        struct XENA_dev_config __iomem *bar0 = nic->bar0;
1081        register u64 val64 = 0;
1082        int     mode;
1083
1084        val64 = readq(&bar0->pci_mode);
1085        mode = (u8)GET_PCI_MODE(val64);
1086
1087        if (val64 & PCI_MODE_UNKNOWN_MODE)
1088                return -1;      /* Unknown PCI mode */
1089        return mode;
1090}
1091
1092#define NEC_VENID   0x1033
1093#define NEC_DEVID   0x0125
1094static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1095{
1096        struct pci_dev *tdev = NULL;
1097        while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1098                if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1099                        if (tdev->bus == s2io_pdev->bus->parent) {
1100                                pci_dev_put(tdev);
1101                                return 1;
1102                        }
1103                }
1104        }
1105        return 0;
1106}
1107
1108static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1109/**
1110 * s2io_print_pci_mode -
1111 */
1112static int s2io_print_pci_mode(struct s2io_nic *nic)
1113{
1114        struct XENA_dev_config __iomem *bar0 = nic->bar0;
1115        register u64 val64 = 0;
1116        int     mode;
1117        struct config_param *config = &nic->config;
1118        const char *pcimode;
1119
1120        val64 = readq(&bar0->pci_mode);
1121        mode = (u8)GET_PCI_MODE(val64);
1122
1123        if (val64 & PCI_MODE_UNKNOWN_MODE)
1124                return -1;      /* Unknown PCI mode */
1125
1126        config->bus_speed = bus_speed[mode];
1127
1128        if (s2io_on_nec_bridge(nic->pdev)) {
1129                DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1130                          nic->dev->name);
1131                return mode;
1132        }
1133
1134        switch (mode) {
1135        case PCI_MODE_PCI_33:
1136                pcimode = "33MHz PCI bus";
1137                break;
1138        case PCI_MODE_PCI_66:
1139                pcimode = "66MHz PCI bus";
1140                break;
1141        case PCI_MODE_PCIX_M1_66:
1142                pcimode = "66MHz PCIX(M1) bus";
1143                break;
1144        case PCI_MODE_PCIX_M1_100:
1145                pcimode = "100MHz PCIX(M1) bus";
1146                break;
1147        case PCI_MODE_PCIX_M1_133:
1148                pcimode = "133MHz PCIX(M1) bus";
1149                break;
1150        case PCI_MODE_PCIX_M2_66:
1151                pcimode = "133MHz PCIX(M2) bus";
1152                break;
1153        case PCI_MODE_PCIX_M2_100:
1154                pcimode = "200MHz PCIX(M2) bus";
1155                break;
1156        case PCI_MODE_PCIX_M2_133:
1157                pcimode = "266MHz PCIX(M2) bus";
1158                break;
1159        default:
1160                pcimode = "unsupported bus!";
1161                mode = -1;
1162        }
1163
1164        DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1165                  nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1166
1167        return mode;
1168}
1169
1170/**
1171 *  init_tti - Initialization transmit traffic interrupt scheme
1172 *  @nic: device private variable
1173 *  @link: link status (UP/DOWN) used to enable/disable continuous
1174 *  transmit interrupts
1175 *  Description: The function configures transmit traffic interrupts
1176 *  Return Value:  SUCCESS on success and
1177 *  '-1' on failure
1178 */
1179
1180static int init_tti(struct s2io_nic *nic, int link)
1181{
1182        struct XENA_dev_config __iomem *bar0 = nic->bar0;
1183        register u64 val64 = 0;
1184        int i;
1185        struct config_param *config = &nic->config;
1186
1187        for (i = 0; i < config->tx_fifo_num; i++) {
1188                /*
1189                 * TTI Initialization. Default Tx timer gets us about
1190                 * 250 interrupts per sec. Continuous interrupts are enabled
1191                 * by default.
1192                 */
1193                if (nic->device_type == XFRAME_II_DEVICE) {
1194                        int count = (nic->config.bus_speed * 125)/2;
1195                        val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1196                } else
1197                        val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1198
1199                val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1200                        TTI_DATA1_MEM_TX_URNG_B(0x10) |
1201                        TTI_DATA1_MEM_TX_URNG_C(0x30) |
1202                        TTI_DATA1_MEM_TX_TIMER_AC_EN;
1203                if (i == 0)
1204                        if (use_continuous_tx_intrs && (link == LINK_UP))
1205                                val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1206                writeq(val64, &bar0->tti_data1_mem);
1207
1208                if (nic->config.intr_type == MSI_X) {
1209                        val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1210                                TTI_DATA2_MEM_TX_UFC_B(0x100) |
1211                                TTI_DATA2_MEM_TX_UFC_C(0x200) |
1212                                TTI_DATA2_MEM_TX_UFC_D(0x300);
1213                } else {
1214                        if ((nic->config.tx_steering_type ==
1215                             TX_DEFAULT_STEERING) &&
1216                            (config->tx_fifo_num > 1) &&
1217                            (i >= nic->udp_fifo_idx) &&
1218                            (i < (nic->udp_fifo_idx +
1219                                  nic->total_udp_fifos)))
1220                                val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1221                                        TTI_DATA2_MEM_TX_UFC_B(0x80) |
1222                                        TTI_DATA2_MEM_TX_UFC_C(0x100) |
1223                                        TTI_DATA2_MEM_TX_UFC_D(0x120);
1224                        else
1225                                val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1226                                        TTI_DATA2_MEM_TX_UFC_B(0x20) |
1227                                        TTI_DATA2_MEM_TX_UFC_C(0x40) |
1228                                        TTI_DATA2_MEM_TX_UFC_D(0x80);
1229                }
1230
1231                writeq(val64, &bar0->tti_data2_mem);
1232
1233                val64 = TTI_CMD_MEM_WE |
1234                        TTI_CMD_MEM_STROBE_NEW_CMD |
1235                        TTI_CMD_MEM_OFFSET(i);
1236                writeq(val64, &bar0->tti_command_mem);
1237
1238                if (wait_for_cmd_complete(&bar0->tti_command_mem,
1239                                          TTI_CMD_MEM_STROBE_NEW_CMD,
1240                                          S2IO_BIT_RESET) != SUCCESS)
1241                        return FAILURE;
1242        }
1243
1244        return SUCCESS;
1245}
1246
1247/**
1248 *  init_nic - Initialization of hardware
1249 *  @nic: device private variable
1250 *  Description: The function sequentially configures every block
1251 *  of the H/W from their reset values.
1252 *  Return Value:  SUCCESS on success and
1253 *  '-1' on failure (endian settings incorrect).
1254 */
1255
1256static int init_nic(struct s2io_nic *nic)
1257{
1258        struct XENA_dev_config __iomem *bar0 = nic->bar0;
1259        struct net_device *dev = nic->dev;
1260        register u64 val64 = 0;
1261        void __iomem *add;
1262        u32 time;
1263        int i, j;
1264        int dtx_cnt = 0;
1265        unsigned long long mem_share;
1266        int mem_size;
1267        struct config_param *config = &nic->config;
1268        struct mac_info *mac_control = &nic->mac_control;
1269
1270        /* to set the swapper controle on the card */
1271        if (s2io_set_swapper(nic)) {
1272                DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1273                return -EIO;
1274        }
1275
1276        /*
1277         * Herc requires EOI to be removed from reset before XGXS, so..
1278         */
1279        if (nic->device_type & XFRAME_II_DEVICE) {
1280                val64 = 0xA500000000ULL;
1281                writeq(val64, &bar0->sw_reset);
1282                msleep(500);
1283                val64 = readq(&bar0->sw_reset);
1284        }
1285
1286        /* Remove XGXS from reset state */
1287        val64 = 0;
1288        writeq(val64, &bar0->sw_reset);
1289        msleep(500);
1290        val64 = readq(&bar0->sw_reset);
1291
1292        /* Ensure that it's safe to access registers by checking
1293         * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1294         */
1295        if (nic->device_type == XFRAME_II_DEVICE) {
1296                for (i = 0; i < 50; i++) {
1297                        val64 = readq(&bar0->adapter_status);
1298                        if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1299                                break;
1300                        msleep(10);
1301                }
1302                if (i == 50)
1303                        return -ENODEV;
1304        }
1305
1306        /*  Enable Receiving broadcasts */
1307        add = &bar0->mac_cfg;
1308        val64 = readq(&bar0->mac_cfg);
1309        val64 |= MAC_RMAC_BCAST_ENABLE;
1310        writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1311        writel((u32)val64, add);
1312        writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1313        writel((u32) (val64 >> 32), (add + 4));
1314
1315        /* Read registers in all blocks */
1316        val64 = readq(&bar0->mac_int_mask);
1317        val64 = readq(&bar0->mc_int_mask);
1318        val64 = readq(&bar0->xgxs_int_mask);
1319
1320        /*  Set MTU */
1321        val64 = dev->mtu;
1322        writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1323
1324        if (nic->device_type & XFRAME_II_DEVICE) {
1325                while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1326                        SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1327                                          &bar0->dtx_control, UF);
1328                        if (dtx_cnt & 0x1)
1329                                msleep(1); /* Necessary!! */
1330                        dtx_cnt++;
1331                }
1332        } else {
1333                while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1334                        SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1335                                          &bar0->dtx_control, UF);
1336                        val64 = readq(&bar0->dtx_control);
1337                        dtx_cnt++;
1338                }
1339        }
1340
1341        /*  Tx DMA Initialization */
1342        val64 = 0;
1343        writeq(val64, &bar0->tx_fifo_partition_0);
1344        writeq(val64, &bar0->tx_fifo_partition_1);
1345        writeq(val64, &bar0->tx_fifo_partition_2);
1346        writeq(val64, &bar0->tx_fifo_partition_3);
1347
1348        for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1349                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1350
1351                val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1352                        vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1353
1354                if (i == (config->tx_fifo_num - 1)) {
1355                        if (i % 2 == 0)
1356                                i++;
1357                }
1358
1359                switch (i) {
1360                case 1:
1361                        writeq(val64, &bar0->tx_fifo_partition_0);
1362                        val64 = 0;
1363                        j = 0;
1364                        break;
1365                case 3:
1366                        writeq(val64, &bar0->tx_fifo_partition_1);
1367                        val64 = 0;
1368                        j = 0;
1369                        break;
1370                case 5:
1371                        writeq(val64, &bar0->tx_fifo_partition_2);
1372                        val64 = 0;
1373                        j = 0;
1374                        break;
1375                case 7:
1376                        writeq(val64, &bar0->tx_fifo_partition_3);
1377                        val64 = 0;
1378                        j = 0;
1379                        break;
1380                default:
1381                        j++;
1382                        break;
1383                }
1384        }
1385
1386        /*
1387         * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1388         * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1389         */
1390        if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1391                writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1392
1393        val64 = readq(&bar0->tx_fifo_partition_0);
1394        DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1395                  &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1396
1397        /*
1398         * Initialization of Tx_PA_CONFIG register to ignore packet
1399         * integrity checking.
1400         */
1401        val64 = readq(&bar0->tx_pa_cfg);
1402        val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1403                TX_PA_CFG_IGNORE_SNAP_OUI |
1404                TX_PA_CFG_IGNORE_LLC_CTRL |
1405                TX_PA_CFG_IGNORE_L2_ERR;
1406        writeq(val64, &bar0->tx_pa_cfg);
1407
1408        /* Rx DMA intialization. */
1409        val64 = 0;
1410        for (i = 0; i < config->rx_ring_num; i++) {
1411                struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1412
1413                val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1414        }
1415        writeq(val64, &bar0->rx_queue_priority);
1416
1417        /*
1418         * Allocating equal share of memory to all the
1419         * configured Rings.
1420         */
1421        val64 = 0;
1422        if (nic->device_type & XFRAME_II_DEVICE)
1423                mem_size = 32;
1424        else
1425                mem_size = 64;
1426
1427        for (i = 0; i < config->rx_ring_num; i++) {
1428                switch (i) {
1429                case 0:
1430                        mem_share = (mem_size / config->rx_ring_num +
1431                                     mem_size % config->rx_ring_num);
1432                        val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1433                        continue;
1434                case 1:
1435                        mem_share = (mem_size / config->rx_ring_num);
1436                        val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1437                        continue;
1438                case 2:
1439                        mem_share = (mem_size / config->rx_ring_num);
1440                        val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1441                        continue;
1442                case 3:
1443                        mem_share = (mem_size / config->rx_ring_num);
1444                        val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1445                        continue;
1446                case 4:
1447                        mem_share = (mem_size / config->rx_ring_num);
1448                        val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1449                        continue;
1450                case 5:
1451                        mem_share = (mem_size / config->rx_ring_num);
1452                        val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1453                        continue;
1454                case 6:
1455                        mem_share = (mem_size / config->rx_ring_num);
1456                        val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1457                        continue;
1458                case 7:
1459                        mem_share = (mem_size / config->rx_ring_num);
1460                        val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1461                        continue;
1462                }
1463        }
1464        writeq(val64, &bar0->rx_queue_cfg);
1465
1466        /*
1467         * Filling Tx round robin registers
1468         * as per the number of FIFOs for equal scheduling priority
1469         */
1470        switch (config->tx_fifo_num) {
1471        case 1:
1472                val64 = 0x0;
1473                writeq(val64, &bar0->tx_w_round_robin_0);
1474                writeq(val64, &bar0->tx_w_round_robin_1);
1475                writeq(val64, &bar0->tx_w_round_robin_2);
1476                writeq(val64, &bar0->tx_w_round_robin_3);
1477                writeq(val64, &bar0->tx_w_round_robin_4);
1478                break;
1479        case 2:
1480                val64 = 0x0001000100010001ULL;
1481                writeq(val64, &bar0->tx_w_round_robin_0);
1482                writeq(val64, &bar0->tx_w_round_robin_1);
1483                writeq(val64, &bar0->tx_w_round_robin_2);
1484                writeq(val64, &bar0->tx_w_round_robin_3);
1485                val64 = 0x0001000100000000ULL;
1486                writeq(val64, &bar0->tx_w_round_robin_4);
1487                break;
1488        case 3:
1489                val64 = 0x0001020001020001ULL;
1490                writeq(val64, &bar0->tx_w_round_robin_0);
1491                val64 = 0x0200010200010200ULL;
1492                writeq(val64, &bar0->tx_w_round_robin_1);
1493                val64 = 0x0102000102000102ULL;
1494                writeq(val64, &bar0->tx_w_round_robin_2);
1495                val64 = 0x0001020001020001ULL;
1496                writeq(val64, &bar0->tx_w_round_robin_3);
1497                val64 = 0x0200010200000000ULL;
1498                writeq(val64, &bar0->tx_w_round_robin_4);
1499                break;
1500        case 4:
1501                val64 = 0x0001020300010203ULL;
1502                writeq(val64, &bar0->tx_w_round_robin_0);
1503                writeq(val64, &bar0->tx_w_round_robin_1);
1504                writeq(val64, &bar0->tx_w_round_robin_2);
1505                writeq(val64, &bar0->tx_w_round_robin_3);
1506                val64 = 0x0001020300000000ULL;
1507                writeq(val64, &bar0->tx_w_round_robin_4);
1508                break;
1509        case 5:
1510                val64 = 0x0001020304000102ULL;
1511                writeq(val64, &bar0->tx_w_round_robin_0);
1512                val64 = 0x0304000102030400ULL;
1513                writeq(val64, &bar0->tx_w_round_robin_1);
1514                val64 = 0x0102030400010203ULL;
1515                writeq(val64, &bar0->tx_w_round_robin_2);
1516                val64 = 0x0400010203040001ULL;
1517                writeq(val64, &bar0->tx_w_round_robin_3);
1518                val64 = 0x0203040000000000ULL;
1519                writeq(val64, &bar0->tx_w_round_robin_4);
1520                break;
1521        case 6:
1522                val64 = 0x0001020304050001ULL;
1523                writeq(val64, &bar0->tx_w_round_robin_0);
1524                val64 = 0x0203040500010203ULL;
1525                writeq(val64, &bar0->tx_w_round_robin_1);
1526                val64 = 0x0405000102030405ULL;
1527                writeq(val64, &bar0->tx_w_round_robin_2);
1528                val64 = 0x0001020304050001ULL;
1529                writeq(val64, &bar0->tx_w_round_robin_3);
1530                val64 = 0x0203040500000000ULL;
1531                writeq(val64, &bar0->tx_w_round_robin_4);
1532                break;
1533        case 7:
1534                val64 = 0x0001020304050600ULL;
1535                writeq(val64, &bar0->tx_w_round_robin_0);
1536                val64 = 0x0102030405060001ULL;
1537                writeq(val64, &bar0->tx_w_round_robin_1);
1538                val64 = 0x0203040506000102ULL;
1539                writeq(val64, &bar0->tx_w_round_robin_2);
1540                val64 = 0x0304050600010203ULL;
1541                writeq(val64, &bar0->tx_w_round_robin_3);
1542                val64 = 0x0405060000000000ULL;
1543                writeq(val64, &bar0->tx_w_round_robin_4);
1544                break;
1545        case 8:
1546                val64 = 0x0001020304050607ULL;
1547                writeq(val64, &bar0->tx_w_round_robin_0);
1548                writeq(val64, &bar0->tx_w_round_robin_1);
1549                writeq(val64, &bar0->tx_w_round_robin_2);
1550                writeq(val64, &bar0->tx_w_round_robin_3);
1551                val64 = 0x0001020300000000ULL;
1552                writeq(val64, &bar0->tx_w_round_robin_4);
1553                break;
1554        }
1555
1556        /* Enable all configured Tx FIFO partitions */
1557        val64 = readq(&bar0->tx_fifo_partition_0);
1558        val64 |= (TX_FIFO_PARTITION_EN);
1559        writeq(val64, &bar0->tx_fifo_partition_0);
1560
1561        /* Filling the Rx round robin registers as per the
1562         * number of Rings and steering based on QoS with
1563         * equal priority.
1564         */
1565        switch (config->rx_ring_num) {
1566        case 1:
1567                val64 = 0x0;
1568                writeq(val64, &bar0->rx_w_round_robin_0);
1569                writeq(val64, &bar0->rx_w_round_robin_1);
1570                writeq(val64, &bar0->rx_w_round_robin_2);
1571                writeq(val64, &bar0->rx_w_round_robin_3);
1572                writeq(val64, &bar0->rx_w_round_robin_4);
1573
1574                val64 = 0x8080808080808080ULL;
1575                writeq(val64, &bar0->rts_qos_steering);
1576                break;
1577        case 2:
1578                val64 = 0x0001000100010001ULL;
1579                writeq(val64, &bar0->rx_w_round_robin_0);
1580                writeq(val64, &bar0->rx_w_round_robin_1);
1581                writeq(val64, &bar0->rx_w_round_robin_2);
1582                writeq(val64, &bar0->rx_w_round_robin_3);
1583                val64 = 0x0001000100000000ULL;
1584                writeq(val64, &bar0->rx_w_round_robin_4);
1585
1586                val64 = 0x8080808040404040ULL;
1587                writeq(val64, &bar0->rts_qos_steering);
1588                break;
1589        case 3:
1590                val64 = 0x0001020001020001ULL;
1591                writeq(val64, &bar0->rx_w_round_robin_0);
1592                val64 = 0x0200010200010200ULL;
1593                writeq(val64, &bar0->rx_w_round_robin_1);
1594                val64 = 0x0102000102000102ULL;
1595                writeq(val64, &bar0->rx_w_round_robin_2);
1596                val64 = 0x0001020001020001ULL;
1597                writeq(val64, &bar0->rx_w_round_robin_3);
1598                val64 = 0x0200010200000000ULL;
1599                writeq(val64, &bar0->rx_w_round_robin_4);
1600
1601                val64 = 0x8080804040402020ULL;
1602                writeq(val64, &bar0->rts_qos_steering);
1603                break;
1604        case 4:
1605                val64 = 0x0001020300010203ULL;
1606                writeq(val64, &bar0->rx_w_round_robin_0);
1607                writeq(val64, &bar0->rx_w_round_robin_1);
1608                writeq(val64, &bar0->rx_w_round_robin_2);
1609                writeq(val64, &bar0->rx_w_round_robin_3);
1610                val64 = 0x0001020300000000ULL;
1611                writeq(val64, &bar0->rx_w_round_robin_4);
1612
1613                val64 = 0x8080404020201010ULL;
1614                writeq(val64, &bar0->rts_qos_steering);
1615                break;
1616        case 5:
1617                val64 = 0x0001020304000102ULL;
1618                writeq(val64, &bar0->rx_w_round_robin_0);
1619                val64 = 0x0304000102030400ULL;
1620                writeq(val64, &bar0->rx_w_round_robin_1);
1621                val64 = 0x0102030400010203ULL;
1622                writeq(val64, &bar0->rx_w_round_robin_2);
1623                val64 = 0x0400010203040001ULL;
1624                writeq(val64, &bar0->rx_w_round_robin_3);
1625                val64 = 0x0203040000000000ULL;
1626                writeq(val64, &bar0->rx_w_round_robin_4);
1627
1628                val64 = 0x8080404020201008ULL;
1629                writeq(val64, &bar0->rts_qos_steering);
1630                break;
1631        case 6:
1632                val64 = 0x0001020304050001ULL;
1633                writeq(val64, &bar0->rx_w_round_robin_0);
1634                val64 = 0x0203040500010203ULL;
1635                writeq(val64, &bar0->rx_w_round_robin_1);
1636                val64 = 0x0405000102030405ULL;
1637                writeq(val64, &bar0->rx_w_round_robin_2);
1638                val64 = 0x0001020304050001ULL;
1639                writeq(val64, &bar0->rx_w_round_robin_3);
1640                val64 = 0x0203040500000000ULL;
1641                writeq(val64, &bar0->rx_w_round_robin_4);
1642
1643                val64 = 0x8080404020100804ULL;
1644                writeq(val64, &bar0->rts_qos_steering);
1645                break;
1646        case 7:
1647                val64 = 0x0001020304050600ULL;
1648                writeq(val64, &bar0->rx_w_round_robin_0);
1649                val64 = 0x0102030405060001ULL;
1650                writeq(val64, &bar0->rx_w_round_robin_1);
1651                val64 = 0x0203040506000102ULL;
1652                writeq(val64, &bar0->rx_w_round_robin_2);
1653                val64 = 0x0304050600010203ULL;
1654                writeq(val64, &bar0->rx_w_round_robin_3);
1655                val64 = 0x0405060000000000ULL;
1656                writeq(val64, &bar0->rx_w_round_robin_4);
1657
1658                val64 = 0x8080402010080402ULL;
1659                writeq(val64, &bar0->rts_qos_steering);
1660                break;
1661        case 8:
1662                val64 = 0x0001020304050607ULL;
1663                writeq(val64, &bar0->rx_w_round_robin_0);
1664                writeq(val64, &bar0->rx_w_round_robin_1);
1665                writeq(val64, &bar0->rx_w_round_robin_2);
1666                writeq(val64, &bar0->rx_w_round_robin_3);
1667                val64 = 0x0001020300000000ULL;
1668                writeq(val64, &bar0->rx_w_round_robin_4);
1669
1670                val64 = 0x8040201008040201ULL;
1671                writeq(val64, &bar0->rts_qos_steering);
1672                break;
1673        }
1674
1675        /* UDP Fix */
1676        val64 = 0;
1677        for (i = 0; i < 8; i++)
1678                writeq(val64, &bar0->rts_frm_len_n[i]);
1679
1680        /* Set the default rts frame length for the rings configured */
1681        val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1682        for (i = 0 ; i < config->rx_ring_num ; i++)
1683                writeq(val64, &bar0->rts_frm_len_n[i]);
1684
1685        /* Set the frame length for the configured rings
1686         * desired by the user
1687         */
1688        for (i = 0; i < config->rx_ring_num; i++) {
1689                /* If rts_frm_len[i] == 0 then it is assumed that user not
1690                 * specified frame length steering.
1691                 * If the user provides the frame length then program
1692                 * the rts_frm_len register for those values or else
1693                 * leave it as it is.
1694                 */
1695                if (rts_frm_len[i] != 0) {
1696                        writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1697                               &bar0->rts_frm_len_n[i]);
1698                }
1699        }
1700
1701        /* Disable differentiated services steering logic */
1702        for (i = 0; i < 64; i++) {
1703                if (rts_ds_steer(nic, i, 0) == FAILURE) {
1704                        DBG_PRINT(ERR_DBG,
1705                                  "%s: rts_ds_steer failed on codepoint %d\n",
1706                                  dev->name, i);
1707                        return -ENODEV;
1708                }
1709        }
1710
1711        /* Program statistics memory */
1712        writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1713
1714        if (nic->device_type == XFRAME_II_DEVICE) {
1715                val64 = STAT_BC(0x320);
1716                writeq(val64, &bar0->stat_byte_cnt);
1717        }
1718
1719        /*
1720         * Initializing the sampling rate for the device to calculate the
1721         * bandwidth utilization.
1722         */
1723        val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1724                MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1725        writeq(val64, &bar0->mac_link_util);
1726
1727        /*
1728         * Initializing the Transmit and Receive Traffic Interrupt
1729         * Scheme.
1730         */
1731
1732        /* Initialize TTI */
1733        if (SUCCESS != init_tti(nic, nic->last_link_state))
1734                return -ENODEV;
1735
1736        /* RTI Initialization */
1737        if (nic->device_type == XFRAME_II_DEVICE) {
1738                /*
1739                 * Programmed to generate Apprx 500 Intrs per
1740                 * second
1741                 */
1742                int count = (nic->config.bus_speed * 125)/4;
1743                val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1744        } else
1745                val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1746        val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1747                RTI_DATA1_MEM_RX_URNG_B(0x10) |
1748                RTI_DATA1_MEM_RX_URNG_C(0x30) |
1749                RTI_DATA1_MEM_RX_TIMER_AC_EN;
1750
1751        writeq(val64, &bar0->rti_data1_mem);
1752
1753        val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1754                RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1755        if (nic->config.intr_type == MSI_X)
1756                val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1757                          RTI_DATA2_MEM_RX_UFC_D(0x40));
1758        else
1759                val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1760                          RTI_DATA2_MEM_RX_UFC_D(0x80));
1761        writeq(val64, &bar0->rti_data2_mem);
1762
1763        for (i = 0; i < config->rx_ring_num; i++) {
1764                val64 = RTI_CMD_MEM_WE |
1765                        RTI_CMD_MEM_STROBE_NEW_CMD |
1766                        RTI_CMD_MEM_OFFSET(i);
1767                writeq(val64, &bar0->rti_command_mem);
1768
1769                /*
1770                 * Once the operation completes, the Strobe bit of the
1771                 * command register will be reset. We poll for this
1772                 * particular condition. We wait for a maximum of 500ms
1773                 * for the operation to complete, if it's not complete
1774                 * by then we return error.
1775                 */
1776                time = 0;
1777                while (true) {
1778                        val64 = readq(&bar0->rti_command_mem);
1779                        if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1780                                break;
1781
1782                        if (time > 10) {
1783                                DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1784                                          dev->name);
1785                                return -ENODEV;
1786                        }
1787                        time++;
1788                        msleep(50);
1789                }
1790        }
1791
1792        /*
1793         * Initializing proper values as Pause threshold into all
1794         * the 8 Queues on Rx side.
1795         */
1796        writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797        writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1798
1799        /* Disable RMAC PAD STRIPPING */
1800        add = &bar0->mac_cfg;
1801        val64 = readq(&bar0->mac_cfg);
1802        val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803        writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804        writel((u32) (val64), add);
1805        writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806        writel((u32) (val64 >> 32), (add + 4));
1807        val64 = readq(&bar0->mac_cfg);
1808
1809        /* Enable FCS stripping by adapter */
1810        add = &bar0->mac_cfg;
1811        val64 = readq(&bar0->mac_cfg);
1812        val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813        if (nic->device_type == XFRAME_II_DEVICE)
1814                writeq(val64, &bar0->mac_cfg);
1815        else {
1816                writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817                writel((u32) (val64), add);
1818                writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819                writel((u32) (val64 >> 32), (add + 4));
1820        }
1821
1822        /*
1823         * Set the time value to be inserted in the pause frame
1824         * generated by xena.
1825         */
1826        val64 = readq(&bar0->rmac_pause_cfg);
1827        val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828        val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829        writeq(val64, &bar0->rmac_pause_cfg);
1830
1831        /*
1832         * Set the Threshold Limit for Generating the pause frame
1833         * If the amount of data in any Queue exceeds ratio of
1834         * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835         * pause frame is generated
1836         */
1837        val64 = 0;
1838        for (i = 0; i < 4; i++) {
1839                val64 |= (((u64)0xFF00 |
1840                           nic->mac_control.mc_pause_threshold_q0q3)
1841                          << (i * 2 * 8));
1842        }
1843        writeq(val64, &bar0->mc_pause_thresh_q0q3);
1844
1845        val64 = 0;
1846        for (i = 0; i < 4; i++) {
1847                val64 |= (((u64)0xFF00 |
1848                           nic->mac_control.mc_pause_threshold_q4q7)
1849                          << (i * 2 * 8));
1850        }
1851        writeq(val64, &bar0->mc_pause_thresh_q4q7);
1852
1853        /*
1854         * TxDMA will stop Read request if the number of read split has
1855         * exceeded the limit pointed by shared_splits
1856         */
1857        val64 = readq(&bar0->pic_control);
1858        val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1859        writeq(val64, &bar0->pic_control);
1860
1861        if (nic->config.bus_speed == 266) {
1862                writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1863                writeq(0x0, &bar0->read_retry_delay);
1864                writeq(0x0, &bar0->write_retry_delay);
1865        }
1866
1867        /*
1868         * Programming the Herc to split every write transaction
1869         * that does not start on an ADB to reduce disconnects.
1870         */
1871        if (nic->device_type == XFRAME_II_DEVICE) {
1872                val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1873                        MISC_LINK_STABILITY_PRD(3);
1874                writeq(val64, &bar0->misc_control);
1875                val64 = readq(&bar0->pic_control2);
1876                val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1877                writeq(val64, &bar0->pic_control2);
1878        }
1879        if (strstr(nic->product_name, "CX4")) {
1880                val64 = TMAC_AVG_IPG(0x17);
1881                writeq(val64, &bar0->tmac_avg_ipg);
1882        }
1883
1884        return SUCCESS;
1885}
1886#define LINK_UP_DOWN_INTERRUPT          1
1887#define MAC_RMAC_ERR_TIMER              2
1888
1889static int s2io_link_fault_indication(struct s2io_nic *nic)
1890{
1891        if (nic->device_type == XFRAME_II_DEVICE)
1892                return LINK_UP_DOWN_INTERRUPT;
1893        else
1894                return MAC_RMAC_ERR_TIMER;
1895}
1896
1897/**
1898 *  do_s2io_write_bits -  update alarm bits in alarm register
1899 *  @value: alarm bits
1900 *  @flag: interrupt status
1901 *  @addr: address value
1902 *  Description: update alarm bits in alarm register
1903 *  Return Value:
1904 *  NONE.
1905 */
1906static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1907{
1908        u64 temp64;
1909
1910        temp64 = readq(addr);
1911
1912        if (flag == ENABLE_INTRS)
1913                temp64 &= ~((u64)value);
1914        else
1915                temp64 |= ((u64)value);
1916        writeq(temp64, addr);
1917}
1918
1919static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1920{
1921        struct XENA_dev_config __iomem *bar0 = nic->bar0;
1922        register u64 gen_int_mask = 0;
1923        u64 interruptible;
1924
1925        writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1926        if (mask & TX_DMA_INTR) {
1927                gen_int_mask |= TXDMA_INT_M;
1928
1929                do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1930                                   TXDMA_PCC_INT | TXDMA_TTI_INT |
1931                                   TXDMA_LSO_INT | TXDMA_TPA_INT |
1932                                   TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1933
1934                do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1935                                   PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1936                                   PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1937                                   &bar0->pfc_err_mask);
1938
1939                do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1940                                   TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1941                                   TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1942
1943                do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1944                                   PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1945                                   PCC_N_SERR | PCC_6_COF_OV_ERR |
1946                                   PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1947                                   PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1948                                   PCC_TXB_ECC_SG_ERR,
1949                                   flag, &bar0->pcc_err_mask);
1950
1951                do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1952                                   TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1953
1954                do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1955                                   LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1956                                   LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1957                                   flag, &bar0->lso_err_mask);
1958
1959                do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1960                                   flag, &bar0->tpa_err_mask);
1961
1962                do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1963        }
1964
1965        if (mask & TX_MAC_INTR) {
1966                gen_int_mask |= TXMAC_INT_M;
1967                do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1968                                   &bar0->mac_int_mask);
1969                do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1970                                   TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1971                                   TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1972                                   flag, &bar0->mac_tmac_err_mask);
1973        }
1974
1975        if (mask & TX_XGXS_INTR) {
1976                gen_int_mask |= TXXGXS_INT_M;
1977                do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1978                                   &bar0->xgxs_int_mask);
1979                do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1980                                   TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1981                                   flag, &bar0->xgxs_txgxs_err_mask);
1982        }
1983
1984        if (mask & RX_DMA_INTR) {
1985                gen_int_mask |= RXDMA_INT_M;
1986                do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1987                                   RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1988                                   flag, &bar0->rxdma_int_mask);
1989                do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1990                                   RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1991                                   RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1992                                   RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1993                do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1994                                   PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1995                                   PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1996                                   &bar0->prc_pcix_err_mask);
1997                do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1998                                   RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1999                                   &bar0->rpa_err_mask);
2000                do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2001                                   RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2002                                   RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2003                                   RDA_FRM_ECC_SG_ERR |
2004                                   RDA_MISC_ERR|RDA_PCIX_ERR,
2005                                   flag, &bar0->rda_err_mask);
2006                do_s2io_write_bits(RTI_SM_ERR_ALARM |
2007                                   RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2008                                   flag, &bar0->rti_err_mask);
2009        }
2010
2011        if (mask & RX_MAC_INTR) {
2012                gen_int_mask |= RXMAC_INT_M;
2013                do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2014                                   &bar0->mac_int_mask);
2015                interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2016                                 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2017                                 RMAC_DOUBLE_ECC_ERR);
2018                if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2019                        interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2020                do_s2io_write_bits(interruptible,
2021                                   flag, &bar0->mac_rmac_err_mask);
2022        }
2023
2024        if (mask & RX_XGXS_INTR) {
2025                gen_int_mask |= RXXGXS_INT_M;
2026                do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2027                                   &bar0->xgxs_int_mask);
2028                do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2029                                   &bar0->xgxs_rxgxs_err_mask);
2030        }
2031
2032        if (mask & MC_INTR) {
2033                gen_int_mask |= MC_INT_M;
2034                do_s2io_write_bits(MC_INT_MASK_MC_INT,
2035                                   flag, &bar0->mc_int_mask);
2036                do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2037                                   MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038                                   &bar0->mc_err_mask);
2039        }
2040        nic->general_int_mask = gen_int_mask;
2041
2042        /* Remove this line when alarm interrupts are enabled */
2043        nic->general_int_mask = 0;
2044}
2045
2046/**
2047 *  en_dis_able_nic_intrs - Enable or Disable the interrupts
2048 *  @nic: device private variable,
2049 *  @mask: A mask indicating which Intr block must be modified and,
2050 *  @flag: A flag indicating whether to enable or disable the Intrs.
2051 *  Description: This function will either disable or enable the interrupts
2052 *  depending on the flag argument. The mask argument can be used to
2053 *  enable/disable any Intr block.
2054 *  Return Value: NONE.
2055 */
2056
2057static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2058{
2059        struct XENA_dev_config __iomem *bar0 = nic->bar0;
2060        register u64 temp64 = 0, intr_mask = 0;
2061
2062        intr_mask = nic->general_int_mask;
2063
2064        /*  Top level interrupt classification */
2065        /*  PIC Interrupts */
2066        if (mask & TX_PIC_INTR) {
2067                /*  Enable PIC Intrs in the general intr mask register */
2068                intr_mask |= TXPIC_INT_M;
2069                if (flag == ENABLE_INTRS) {
2070                        /*
2071                         * If Hercules adapter enable GPIO otherwise
2072                         * disable all PCIX, Flash, MDIO, IIC and GPIO
2073                         * interrupts for now.
2074                         * TODO
2075                         */
2076                        if (s2io_link_fault_indication(nic) ==
2077                            LINK_UP_DOWN_INTERRUPT) {
2078                                do_s2io_write_bits(PIC_INT_GPIO, flag,
2079                                                   &bar0->pic_int_mask);
2080                                do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2081                                                   &bar0->gpio_int_mask);
2082                        } else
2083                                writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2084                } else if (flag == DISABLE_INTRS) {
2085                        /*
2086                         * Disable PIC Intrs in the general
2087                         * intr mask register
2088                         */
2089                        writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2090                }
2091        }
2092
2093        /*  Tx traffic interrupts */
2094        if (mask & TX_TRAFFIC_INTR) {
2095                intr_mask |= TXTRAFFIC_INT_M;
2096                if (flag == ENABLE_INTRS) {
2097                        /*
2098                         * Enable all the Tx side interrupts
2099                         * writing 0 Enables all 64 TX interrupt levels
2100                         */
2101                        writeq(0x0, &bar0->tx_traffic_mask);
2102                } else if (flag == DISABLE_INTRS) {
2103                        /*
2104                         * Disable Tx Traffic Intrs in the general intr mask
2105                         * register.
2106                         */
2107                        writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2108                }
2109        }
2110
2111        /*  Rx traffic interrupts */
2112        if (mask & RX_TRAFFIC_INTR) {
2113                intr_mask |= RXTRAFFIC_INT_M;
2114                if (flag == ENABLE_INTRS) {
2115                        /* writing 0 Enables all 8 RX interrupt levels */
2116                        writeq(0x0, &bar0->rx_traffic_mask);
2117                } else if (flag == DISABLE_INTRS) {
2118                        /*
2119                         * Disable Rx Traffic Intrs in the general intr mask
2120                         * register.
2121                         */
2122                        writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2123                }
2124        }
2125
2126        temp64 = readq(&bar0->general_int_mask);
2127        if (flag == ENABLE_INTRS)
2128                temp64 &= ~((u64)intr_mask);
2129        else
2130                temp64 = DISABLE_ALL_INTRS;
2131        writeq(temp64, &bar0->general_int_mask);
2132
2133        nic->general_int_mask = readq(&bar0->general_int_mask);
2134}
2135
2136/**
2137 *  verify_pcc_quiescent- Checks for PCC quiescent state
2138 *  Return: 1 If PCC is quiescence
2139 *          0 If PCC is not quiescence
2140 */
2141static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2142{
2143        int ret = 0, herc;
2144        struct XENA_dev_config __iomem *bar0 = sp->bar0;
2145        u64 val64 = readq(&bar0->adapter_status);
2146
2147        herc = (sp->device_type == XFRAME_II_DEVICE);
2148
2149        if (flag == false) {
2150                if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2151                        if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2152                                ret = 1;
2153                } else {
2154                        if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2155                                ret = 1;
2156                }
2157        } else {
2158                if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2159                        if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2160                             ADAPTER_STATUS_RMAC_PCC_IDLE))
2161                                ret = 1;
2162                } else {
2163                        if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2164                             ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2165                                ret = 1;
2166                }
2167        }
2168
2169        return ret;
2170}
2171/**
2172 *  verify_xena_quiescence - Checks whether the H/W is ready
2173 *  Description: Returns whether the H/W is ready to go or not. Depending
2174 *  on whether adapter enable bit was written or not the comparison
2175 *  differs and the calling function passes the input argument flag to
2176 *  indicate this.
2177 *  Return: 1 If xena is quiescence
2178 *          0 If Xena is not quiescence
2179 */
2180
2181static int verify_xena_quiescence(struct s2io_nic *sp)
2182{
2183        int  mode;
2184        struct XENA_dev_config __iomem *bar0 = sp->bar0;
2185        u64 val64 = readq(&bar0->adapter_status);
2186        mode = s2io_verify_pci_mode(sp);
2187
2188        if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2189                DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2190                return 0;
2191        }
2192        if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2193                DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2194                return 0;
2195        }
2196        if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2197                DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2198                return 0;
2199        }
2200        if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2201                DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2202                return 0;
2203        }
2204        if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2205                DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2206                return 0;
2207        }
2208        if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2209                DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2210                return 0;
2211        }
2212        if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2213                DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2214                return 0;
2215        }
2216        if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2217                DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2218                return 0;
2219        }
2220
2221        /*
2222         * In PCI 33 mode, the P_PLL is not used, and therefore,
2223         * the the P_PLL_LOCK bit in the adapter_status register will
2224         * not be asserted.
2225         */
2226        if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2227            sp->device_type == XFRAME_II_DEVICE &&
2228            mode != PCI_MODE_PCI_33) {
2229                DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2230                return 0;
2231        }
2232        if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2233              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2234                DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2235                return 0;
2236        }
2237        return 1;
2238}
2239
2240/**
2241 * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2242 * @sp: Pointer to device specifc structure
2243 * Description :
2244 * New procedure to clear mac address reading  problems on Alpha platforms
2245 *
2246 */
2247
2248static void fix_mac_address(struct s2io_nic *sp)
2249{
2250        struct XENA_dev_config __iomem *bar0 = sp->bar0;
2251        u64 val64;
2252        int i = 0;
2253
2254        while (fix_mac[i] != END_SIGN) {
2255                writeq(fix_mac[i++], &bar0->gpio_control);
2256                udelay(10);
2257                val64 = readq(&bar0->gpio_control);
2258        }
2259}
2260
2261/**
2262 *  start_nic - Turns the device on
2263 *  @nic : device private variable.
2264 *  Description:
2265 *  This function actually turns the device on. Before this  function is
2266 *  called,all Registers are configured from their reset states
2267 *  and shared memory is allocated but the NIC is still quiescent. On
2268 *  calling this function, the device interrupts are cleared and the NIC is
2269 *  literally switched on by writing into the adapter control register.
2270 *  Return Value:
2271 *  SUCCESS on success and -1 on failure.
2272 */
2273
2274static int start_nic(struct s2io_nic *nic)
2275{
2276        struct XENA_dev_config __iomem *bar0 = nic->bar0;
2277        struct net_device *dev = nic->dev;
2278        register u64 val64 = 0;
2279        u16 subid, i;
2280        struct config_param *config = &nic->config;
2281        struct mac_info *mac_control = &nic->mac_control;
2282
2283        /*  PRC Initialization and configuration */
2284        for (i = 0; i < config->rx_ring_num; i++) {
2285                struct ring_info *ring = &mac_control->rings[i];
2286
2287                writeq((u64)ring->rx_blocks[0].block_dma_addr,
2288                       &bar0->prc_rxd0_n[i]);
2289
2290                val64 = readq(&bar0->prc_ctrl_n[i]);
2291                if (nic->rxd_mode == RXD_MODE_1)
2292                        val64 |= PRC_CTRL_RC_ENABLED;
2293                else
2294                        val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2295                if (nic->device_type == XFRAME_II_DEVICE)
2296                        val64 |= PRC_CTRL_GROUP_READS;
2297                val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298                val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2299                writeq(val64, &bar0->prc_ctrl_n[i]);
2300        }
2301
2302        if (nic->rxd_mode == RXD_MODE_3B) {
2303                /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304                val64 = readq(&bar0->rx_pa_cfg);
2305                val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306                writeq(val64, &bar0->rx_pa_cfg);
2307        }
2308
2309        if (vlan_tag_strip == 0) {
2310                val64 = readq(&bar0->rx_pa_cfg);
2311                val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312                writeq(val64, &bar0->rx_pa_cfg);
2313                nic->vlan_strip_flag = 0;
2314        }
2315
2316        /*
2317         * Enabling MC-RLDRAM. After enabling the device, we timeout
2318         * for around 100ms, which is approximately the time required
2319         * for the device to be ready for operation.
2320         */
2321        val64 = readq(&bar0->mc_rldram_mrs);
2322        val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323        SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324        val64 = readq(&bar0->mc_rldram_mrs);
2325
2326        msleep(100);    /* Delay by around 100 ms. */
2327
2328        /* Enabling ECC Protection. */
2329        val64 = readq(&bar0->adapter_control);
2330        val64 &= ~ADAPTER_ECC_EN;
2331        writeq(val64, &bar0->adapter_control);
2332
2333        /*
2334         * Verify if the device is ready to be enabled, if so enable
2335         * it.
2336         */
2337        val64 = readq(&bar0->adapter_status);
2338        if (!verify_xena_quiescence(nic)) {
2339                DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2340                          "Adapter status reads: 0x%llx\n",
2341                          dev->name, (unsigned long long)val64);
2342                return FAILURE;
2343        }
2344
2345        /*
2346         * With some switches, link might be already up at this point.
2347         * Because of this weird behavior, when we enable laser,
2348         * we may not get link. We need to handle this. We cannot
2349         * figure out which switch is misbehaving. So we are forced to
2350         * make a global change.
2351         */
2352
2353        /* Enabling Laser. */
2354        val64 = readq(&bar0->adapter_control);
2355        val64 |= ADAPTER_EOI_TX_ON;
2356        writeq(val64, &bar0->adapter_control);
2357
2358        if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2359                /*
2360                 * Dont see link state interrupts initally on some switches,
2361                 * so directly scheduling the link state task here.
2362                 */
2363                schedule_work(&nic->set_link_task);
2364        }
2365        /* SXE-002: Initialize link and activity LED */
2366        subid = nic->pdev->subsystem_device;
2367        if (((subid & 0xFF) >= 0x07) &&
2368            (nic->device_type == XFRAME_I_DEVICE)) {
2369                val64 = readq(&bar0->gpio_control);
2370                val64 |= 0x0000800000000000ULL;
2371                writeq(val64, &bar0->gpio_control);
2372                val64 = 0x0411040400000000ULL;
2373                writeq(val64, (void __iomem *)bar0 + 0x2700);
2374        }
2375
2376        return SUCCESS;
2377}
2378/**
2379 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2380 */
2381static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2382                                        struct TxD *txdlp, int get_off)
2383{
2384        struct s2io_nic *nic = fifo_data->nic;
2385        struct sk_buff *skb;
2386        struct TxD *txds;
2387        u16 j, frg_cnt;
2388
2389        txds = txdlp;
2390        if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2391                pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2392                                 sizeof(u64), PCI_DMA_TODEVICE);
2393                txds++;
2394        }
2395
2396        skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2397        if (!skb) {
2398                memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2399                return NULL;
2400        }
2401        pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2402                         skb->len - skb->data_len, PCI_DMA_TODEVICE);
2403        frg_cnt = skb_shinfo(skb)->nr_frags;
2404        if (frg_cnt) {
2405                txds++;
2406                for (j = 0; j < frg_cnt; j++, txds++) {
2407                        skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2408                        if (!txds->Buffer_Pointer)
2409                                break;
2410                        pci_unmap_page(nic->pdev,
2411                                       (dma_addr_t)txds->Buffer_Pointer,
2412                                       frag->size, PCI_DMA_TODEVICE);
2413                }
2414        }
2415        memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2416        return skb;
2417}
2418
2419/**
2420 *  free_tx_buffers - Free all queued Tx buffers
2421 *  @nic : device private variable.
2422 *  Description:
2423 *  Free all queued Tx buffers.
2424 *  Return Value: void
2425 */
2426
2427static void free_tx_buffers(struct s2io_nic *nic)
2428{
2429        struct net_device *dev = nic->dev;
2430        struct sk_buff *skb;
2431        struct TxD *txdp;
2432        int i, j;
2433        int cnt = 0;
2434        struct config_param *config = &nic->config;
2435        struct mac_info *mac_control = &nic->mac_control;
2436        struct stat_block *stats = mac_control->stats_info;
2437        struct swStat *swstats = &stats->sw_stat;
2438
2439        for (i = 0; i < config->tx_fifo_num; i++) {
2440                struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2441                struct fifo_info *fifo = &mac_control->fifos[i];
2442                unsigned long flags;
2443
2444                spin_lock_irqsave(&fifo->tx_lock, flags);
2445                for (j = 0; j < tx_cfg->fifo_len; j++) {
2446                        txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2447                        skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2448                        if (skb) {
2449                                swstats->mem_freed += skb->truesize;
2450                                dev_kfree_skb(skb);
2451                                cnt++;
2452                        }
2453                }
2454                DBG_PRINT(INTR_DBG,
2455                          "%s: forcibly freeing %d skbs on FIFO%d\n",
2456                          dev->name, cnt, i);
2457                fifo->tx_curr_get_info.offset = 0;
2458                fifo->tx_curr_put_info.offset = 0;
2459                spin_unlock_irqrestore(&fifo->tx_lock, flags);
2460        }
2461}
2462
2463/**
2464 *   stop_nic -  To stop the nic
2465 *   @nic ; device private variable.
2466 *   Description:
2467 *   This function does exactly the opposite of what the start_nic()
2468 *   function does. This function is called to stop the device.
2469 *   Return Value:
2470 *   void.
2471 */
2472
2473static void stop_nic(struct s2io_nic *nic)
2474{
2475        struct XENA_dev_config __iomem *bar0 = nic->bar0;
2476        register u64 val64 = 0;
2477        u16 interruptible;
2478
2479        /*  Disable all interrupts */
2480        en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2481        interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2482        interruptible |= TX_PIC_INTR;
2483        en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2484
2485        /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486        val64 = readq(&bar0->adapter_control);
2487        val64 &= ~(ADAPTER_CNTL_EN);
2488        writeq(val64, &bar0->adapter_control);
2489}
2490
2491/**
2492 *  fill_rx_buffers - Allocates the Rx side skbs
2493 *  @ring_info: per ring structure
2494 *  @from_card_up: If this is true, we will map the buffer to get
2495 *     the dma address for buf0 and buf1 to give it to the card.
2496 *     Else we will sync the already mapped buffer to give it to the card.
2497 *  Description:
2498 *  The function allocates Rx side skbs and puts the physical
2499 *  address of these buffers into the RxD buffer pointers, so that the NIC
2500 *  can DMA the received frame into these locations.
2501 *  The NIC supports 3 receive modes, viz
2502 *  1. single buffer,
2503 *  2. three buffer and
2504 *  3. Five buffer modes.
2505 *  Each mode defines how many fragments the received frame will be split
2506 *  up into by the NIC. The frame is split into L3 header, L4 Header,
2507 *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508 *  is split into 3 fragments. As of now only single buffer mode is
2509 *  supported.
2510 *   Return Value:
2511 *  SUCCESS on success or an appropriate -ve value on failure.
2512 */
2513static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2514                           int from_card_up)
2515{
2516        struct sk_buff *skb;
2517        struct RxD_t *rxdp;
2518        int off, size, block_no, block_no1;
2519        u32 alloc_tab = 0;
2520        u32 alloc_cnt;
2521        u64 tmp;
2522        struct buffAdd *ba;
2523        struct RxD_t *first_rxdp = NULL;
2524        u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2525        int rxd_index = 0;
2526        struct RxD1 *rxdp1;
2527        struct RxD3 *rxdp3;
2528        struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2529
2530        alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2531
2532        block_no1 = ring->rx_curr_get_info.block_index;
2533        while (alloc_tab < alloc_cnt) {
2534                block_no = ring->rx_curr_put_info.block_index;
2535
2536                off = ring->rx_curr_put_info.offset;
2537
2538                rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2539
2540                rxd_index = off + 1;
2541                if (block_no)
2542                        rxd_index += (block_no * ring->rxd_count);
2543
2544                if ((block_no == block_no1) &&
2545                    (off == ring->rx_curr_get_info.offset) &&
2546                    (rxdp->Host_Control)) {
2547                        DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2548                                  ring->dev->name);
2549                        goto end;
2550                }
2551                if (off && (off == ring->rxd_count)) {
2552                        ring->rx_curr_put_info.block_index++;
2553                        if (ring->rx_curr_put_info.block_index ==
2554                            ring->block_count)
2555                                ring->rx_curr_put_info.block_index = 0;
2556                        block_no = ring->rx_curr_put_info.block_index;
2557                        off = 0;
2558                        ring->rx_curr_put_info.offset = off;
2559                        rxdp = ring->rx_blocks[block_no].block_virt_addr;
2560                        DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2561                                  ring->dev->name, rxdp);
2562
2563                }
2564
2565                if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2566                    ((ring->rxd_mode == RXD_MODE_3B) &&
2567                     (rxdp->Control_2 & s2BIT(0)))) {
2568                        ring->rx_curr_put_info.offset = off;
2569                        goto end;
2570                }
2571                /* calculate size of skb based on ring mode */
2572                size = ring->mtu +
2573                        HEADER_ETHERNET_II_802_3_SIZE +
2574                        HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2575                if (ring->rxd_mode == RXD_MODE_1)
2576                        size += NET_IP_ALIGN;
2577                else
2578                        size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2579
2580                /* allocate skb */
2581                skb = dev_alloc_skb(size);
2582                if (!skb) {
2583                        DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2584                                  ring->dev->name);
2585                        if (first_rxdp) {
2586                                wmb();
2587                                first_rxdp->Control_1 |= RXD_OWN_XENA;
2588                        }
2589                        swstats->mem_alloc_fail_cnt++;
2590
2591                        return -ENOMEM ;
2592                }
2593                swstats->mem_allocated += skb->truesize;
2594
2595                if (ring->rxd_mode == RXD_MODE_1) {
2596                        /* 1 buffer mode - normal operation mode */
2597                        rxdp1 = (struct RxD1 *)rxdp;
2598                        memset(rxdp, 0, sizeof(struct RxD1));
2599                        skb_reserve(skb, NET_IP_ALIGN);
2600                        rxdp1->Buffer0_ptr =
2601                                pci_map_single(ring->pdev, skb->data,
2602                                               size - NET_IP_ALIGN,
2603                                               PCI_DMA_FROMDEVICE);
2604                        if (pci_dma_mapping_error(nic->pdev,
2605                                                  rxdp1->Buffer0_ptr))
2606                                goto pci_map_failed;
2607
2608                        rxdp->Control_2 =
2609                                SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2610                        rxdp->Host_Control = (unsigned long)skb;
2611                } else if (ring->rxd_mode == RXD_MODE_3B) {
2612                        /*
2613                         * 2 buffer mode -
2614                         * 2 buffer mode provides 128
2615                         * byte aligned receive buffers.
2616                         */
2617
2618                        rxdp3 = (struct RxD3 *)rxdp;
2619                        /* save buffer pointers to avoid frequent dma mapping */
2620                        Buffer0_ptr = rxdp3->Buffer0_ptr;
2621                        Buffer1_ptr = rxdp3->Buffer1_ptr;
2622                        memset(rxdp, 0, sizeof(struct RxD3));
2623                        /* restore the buffer pointers for dma sync*/
2624                        rxdp3->Buffer0_ptr = Buffer0_ptr;
2625                        rxdp3->Buffer1_ptr = Buffer1_ptr;
2626
2627                        ba = &ring->ba[block_no][off];
2628                        skb_reserve(skb, BUF0_LEN);
2629                        tmp = (u64)(unsigned long)skb->data;
2630                        tmp += ALIGN_SIZE;
2631                        tmp &= ~ALIGN_SIZE;
2632                        skb->data = (void *) (unsigned long)tmp;
2633                        skb_reset_tail_pointer(skb);
2634
2635                        if (from_card_up) {
2636                                rxdp3->Buffer0_ptr =
2637                                        pci_map_single(ring->pdev, ba->ba_0,
2638                                                       BUF0_LEN,
2639                                                       PCI_DMA_FROMDEVICE);
2640                                if (pci_dma_mapping_error(nic->pdev,
2641                                                          rxdp3->Buffer0_ptr))
2642                                        goto pci_map_failed;
2643                        } else
2644                                pci_dma_sync_single_for_device(ring->pdev,
2645                                                               (dma_addr_t)rxdp3->Buffer0_ptr,
2646                                                               BUF0_LEN,
2647                                                               PCI_DMA_FROMDEVICE);
2648
2649                        rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2650                        if (ring->rxd_mode == RXD_MODE_3B) {
2651                                /* Two buffer mode */
2652
2653                                /*
2654                                 * Buffer2 will have L3/L4 header plus
2655                                 * L4 payload
2656                                 */
2657                                rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2658                                                                    skb->data,
2659                                                                    ring->mtu + 4,
2660                                                                    PCI_DMA_FROMDEVICE);
2661
2662                                if (pci_dma_mapping_error(nic->pdev,
2663                                                          rxdp3->Buffer2_ptr))
2664                                        goto pci_map_failed;
2665
2666                                if (from_card_up) {
2667                                        rxdp3->Buffer1_ptr =
2668                                                pci_map_single(ring->pdev,
2669                                                               ba->ba_1,
2670                                                               BUF1_LEN,
2671                                                               PCI_DMA_FROMDEVICE);
2672
2673                                        if (pci_dma_mapping_error(nic->pdev,
2674                                                                  rxdp3->Buffer1_ptr)) {
2675                                                pci_unmap_single(ring->pdev,
2676                                                                 (dma_addr_t)(unsigned long)
2677                                                                 skb->data,
2678                                                                 ring->mtu + 4,
2679                                                                 PCI_DMA_FROMDEVICE);
2680                                                goto pci_map_failed;
2681                                        }
2682                                }
2683                                rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2684                                rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2685                                        (ring->mtu + 4);
2686                        }
2687                        rxdp->Control_2 |= s2BIT(0);
2688                        rxdp->Host_Control = (unsigned long) (skb);
2689                }
2690                if (alloc_tab & ((1 << rxsync_frequency) - 1))
2691                        rxdp->Control_1 |= RXD_OWN_XENA;
2692                off++;
2693                if (off == (ring->rxd_count + 1))
2694                        off = 0;
2695                ring->rx_curr_put_info.offset = off;
2696
2697                rxdp->Control_2 |= SET_RXD_MARKER;
2698                if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2699                        if (first_rxdp) {
2700                                wmb();
2701                                first_rxdp->Control_1 |= RXD_OWN_XENA;
2702                        }
2703                        first_rxdp = rxdp;
2704                }
2705                ring->rx_bufs_left += 1;
2706                alloc_tab++;
2707        }
2708
2709end:
2710        /* Transfer ownership of first descriptor to adapter just before
2711         * exiting. Before that, use memory barrier so that ownership
2712         * and other fields are seen by adapter correctly.
2713         */
2714        if (first_rxdp) {
2715                wmb();
2716                first_rxdp->Control_1 |= RXD_OWN_XENA;
2717        }
2718
2719        return SUCCESS;
2720
2721pci_map_failed:
2722        swstats->pci_map_fail_cnt++;
2723        swstats->mem_freed += skb->truesize;
2724        dev_kfree_skb_irq(skb);
2725        return -ENOMEM;
2726}
2727
2728static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2729{
2730        struct net_device *dev = sp->dev;
2731        int j;
2732        struct sk_buff *skb;
2733        struct RxD_t *rxdp;
2734        struct buffAdd *ba;
2735        struct RxD1 *rxdp1;
2736        struct RxD3 *rxdp3;
2737        struct mac_info *mac_control = &sp->mac_control;
2738        struct stat_block *stats = mac_control->stats_info;
2739        struct swStat *swstats = &stats->sw_stat;
2740
2741        for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2742                rxdp = mac_control->rings[ring_no].
2743                        rx_blocks[blk].rxds[j].virt_addr;
2744                skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2745                if (!skb)
2746                        continue;
2747                if (sp->rxd_mode == RXD_MODE_1) {
2748                        rxdp1 = (struct RxD1 *)rxdp;
2749                        pci_unmap_single(sp->pdev,
2750                                         (dma_addr_t)rxdp1->Buffer0_ptr,
2751                                         dev->mtu +
2752                                         HEADER_ETHERNET_II_802_3_SIZE +
2753                                         HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2754                                         PCI_DMA_FROMDEVICE);
2755                        memset(rxdp, 0, sizeof(struct RxD1));
2756                } else if (sp->rxd_mode == RXD_MODE_3B) {
2757                        rxdp3 = (struct RxD3 *)rxdp;
2758                        ba = &mac_control->rings[ring_no].ba[blk][j];
2759                        pci_unmap_single(sp->pdev,
2760                                         (dma_addr_t)rxdp3->Buffer0_ptr,
2761                                         BUF0_LEN,
2762                                         PCI_DMA_FROMDEVICE);
2763                        pci_unmap_single(sp->pdev,
2764                                         (dma_addr_t)rxdp3->Buffer1_ptr,
2765                                         BUF1_LEN,
2766                                         PCI_DMA_FROMDEVICE);
2767                        pci_unmap_single(sp->pdev,
2768                                         (dma_addr_t)rxdp3->Buffer2_ptr,
2769                                         dev->mtu + 4,
2770                                         PCI_DMA_FROMDEVICE);
2771                        memset(rxdp, 0, sizeof(struct RxD3));
2772                }
2773                swstats->mem_freed += skb->truesize;
2774                dev_kfree_skb(skb);
2775                mac_control->rings[ring_no].rx_bufs_left -= 1;
2776        }
2777}
2778
2779/**
2780 *  free_rx_buffers - Frees all Rx buffers
2781 *  @sp: device private variable.
2782 *  Description:
2783 *  This function will free all Rx buffers allocated by host.
2784 *  Return Value:
2785 *  NONE.
2786 */
2787
2788static void free_rx_buffers(struct s2io_nic *sp)
2789{
2790        struct net_device *dev = sp->dev;
2791        int i, blk = 0, buf_cnt = 0;
2792        struct config_param *config = &sp->config;
2793        struct mac_info *mac_control = &sp->mac_control;
2794
2795        for (i = 0; i < config->rx_ring_num; i++) {
2796                struct ring_info *ring = &mac_control->rings[i];
2797
2798                for (blk = 0; blk < rx_ring_sz[i]; blk++)
2799                        free_rxd_blk(sp, i, blk);
2800
2801                ring->rx_curr_put_info.block_index = 0;
2802                ring->rx_curr_get_info.block_index = 0;
2803                ring->rx_curr_put_info.offset = 0;
2804                ring->rx_curr_get_info.offset = 0;
2805                ring->rx_bufs_left = 0;
2806                DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2807                          dev->name, buf_cnt, i);
2808        }
2809}
2810
2811static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2812{
2813        if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2814                DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2815                          ring->dev->name);
2816        }
2817        return 0;
2818}
2819
2820/**
2821 * s2io_poll - Rx interrupt handler for NAPI support
2822 * @napi : pointer to the napi structure.
2823 * @budget : The number of packets that were budgeted to be processed
2824 * during  one pass through the 'Poll" function.
2825 * Description:
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2829 * Return value:
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2831 */
2832
2833static int s2io_poll_msix(struct napi_struct *napi, int budget)
2834{
2835        struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836        struct net_device *dev = ring->dev;
2837        int pkts_processed = 0;
2838        u8 __iomem *addr = NULL;
2839        u8 val8 = 0;
2840        struct s2io_nic *nic = netdev_priv(dev);
2841        struct XENA_dev_config __iomem *bar0 = nic->bar0;
2842        int budget_org = budget;
2843
2844        if (unlikely(!is_s2io_card_up(nic)))
2845                return 0;
2846
2847        pkts_processed = rx_intr_handler(ring, budget);
2848        s2io_chk_rx_buffers(nic, ring);
2849
2850        if (pkts_processed < budget_org) {
2851                napi_complete(napi);
2852                /*Re Enable MSI-Rx Vector*/
2853                addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2854                addr += 7 - ring->ring_no;
2855                val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2856                writeb(val8, addr);
2857                val8 = readb(addr);
2858        }
2859        return pkts_processed;
2860}
2861
2862static int s2io_poll_inta(struct napi_struct *napi, int budget)
2863{
2864        struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2865        int pkts_processed = 0;
2866        int ring_pkts_processed, i;
2867        struct XENA_dev_config __iomem *bar0 = nic->bar0;
2868        int budget_org = budget;
2869        struct config_param *config = &nic->config;
2870        struct mac_info *mac_control = &nic->mac_control;
2871
2872        if (unlikely(!is_s2io_card_up(nic)))
2873                return 0;
2874
2875        for (i = 0; i < config->rx_ring_num; i++) {
2876                struct ring_info *ring = &mac_control->rings[i];
2877                ring_pkts_processed = rx_intr_handler(ring, budget);
2878                s2io_chk_rx_buffers(nic, ring);
2879                pkts_processed += ring_pkts_processed;
2880                budget -= ring_pkts_processed;
2881                if (budget <= 0)
2882                        break;
2883        }
2884        if (pkts_processed < budget_org) {
2885                napi_complete(napi);
2886                /* Re enable the Rx interrupts for the ring */
2887                writeq(0, &bar0->rx_traffic_mask);
2888                readl(&bar0->rx_traffic_mask);
2889        }
2890        return pkts_processed;
2891}
2892
2893#ifdef CONFIG_NET_POLL_CONTROLLER
2894/**
2895 * s2io_netpoll - netpoll event handler entry point
2896 * @dev : pointer to the device structure.
2897 * Description:
2898 *      This function will be called by upper layer to check for events on the
2899 * interface in situations where interrupts are disabled. It is used for
2900 * specific in-kernel networking tasks, such as remote consoles and kernel
2901 * debugging over the network (example netdump in RedHat).
2902 */
2903static void s2io_netpoll(struct net_device *dev)
2904{
2905        struct s2io_nic *nic = netdev_priv(dev);
2906        struct XENA_dev_config __iomem *bar0 = nic->bar0;
2907        u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2908        int i;
2909        struct config_param *config = &nic->config;
2910        struct mac_info *mac_control = &nic->mac_control;
2911
2912        if (pci_channel_offline(nic->pdev))
2913                return;
2914
2915        disable_irq(dev->irq);
2916
2917        writeq(val64, &bar0->rx_traffic_int);
2918        writeq(val64, &bar0->tx_traffic_int);
2919
2920        /* we need to free up the transmitted skbufs or else netpoll will
2921         * run out of skbs and will fail and eventually netpoll application such
2922         * as netdump will fail.
2923         */
2924        for (i = 0; i < config->tx_fifo_num; i++)
2925                tx_intr_handler(&mac_control->fifos[i]);
2926
2927        /* check for received packet and indicate up to network */
2928        for (i = 0; i < config->rx_ring_num; i++) {
2929                struct ring_info *ring = &mac_control->rings[i];
2930
2931                rx_intr_handler(ring, 0);
2932        }
2933
2934        for (i = 0; i < config->rx_ring_num; i++) {
2935                struct ring_info *ring = &mac_control->rings[i];
2936
2937                if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2938                        DBG_PRINT(INFO_DBG,
2939                                  "%s: Out of memory in Rx Netpoll!!\n",
2940                                  dev->name);
2941                        break;
2942                }
2943        }
2944        enable_irq(dev->irq);
2945        return;
2946}
2947#endif
2948
2949/**
2950 *  rx_intr_handler - Rx interrupt handler
2951 *  @ring_info: per ring structure.
2952 *  @budget: budget for napi processing.
2953 *  Description:
2954 *  If the interrupt is because of a received frame or if the
2955 *  receive ring contains fresh as yet un-processed frames,this function is
2956 *  called. It picks out the RxD at which place the last Rx processing had
2957 *  stopped and sends the skb to the OSM's Rx handler and then increments
2958 *  the offset.
2959 *  Return Value:
2960 *  No. of napi packets processed.
2961 */
2962static int rx_intr_handler(struct ring_info *ring_data, int budget)
2963{
2964        int get_block, put_block;
2965        struct rx_curr_get_info get_info, put_info;
2966        struct RxD_t *rxdp;
2967        struct sk_buff *skb;
2968        int pkt_cnt = 0, napi_pkts = 0;
2969        int i;
2970        struct RxD1 *rxdp1;
2971        struct RxD3 *rxdp3;
2972
2973        get_info = ring_data->rx_curr_get_info;
2974        get_block = get_info.block_index;
2975        memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2976        put_block = put_info.block_index;
2977        rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2978
2979        while (RXD_IS_UP2DT(rxdp)) {
2980                /*
2981                 * If your are next to put index then it's
2982                 * FIFO full condition
2983                 */
2984                if ((get_block == put_block) &&
2985                    (get_info.offset + 1) == put_info.offset) {
2986                        DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2987                                  ring_data->dev->name);
2988                        break;
2989                }
2990                skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2991                if (skb == NULL) {
2992                        DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2993                                  ring_data->dev->name);
2994                        return 0;
2995                }
2996                if (ring_data->rxd_mode == RXD_MODE_1) {
2997                        rxdp1 = (struct RxD1 *)rxdp;
2998                        pci_unmap_single(ring_data->pdev, (dma_addr_t)
2999                                         rxdp1->Buffer0_ptr,
3000                                         ring_data->mtu +
3001                                         HEADER_ETHERNET_II_802_3_SIZE +
3002                                         HEADER_802_2_SIZE +
3003                                         HEADER_SNAP_SIZE,
3004                                         PCI_DMA_FROMDEVICE);
3005                } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3006                        rxdp3 = (struct RxD3 *)rxdp;
3007                        pci_dma_sync_single_for_cpu(ring_data->pdev,
3008                                                    (dma_addr_t)rxdp3->Buffer0_ptr,
3009                                                    BUF0_LEN,
3010                                                    PCI_DMA_FROMDEVICE);
3011                        pci_unmap_single(ring_data->pdev,
3012                                         (dma_addr_t)rxdp3->Buffer2_ptr,
3013                                         ring_data->mtu + 4,
3014                                         PCI_DMA_FROMDEVICE);
3015                }
3016                prefetch(skb->data);
3017                rx_osm_handler(ring_data, rxdp);
3018                get_info.offset++;
3019                ring_data->rx_curr_get_info.offset = get_info.offset;
3020                rxdp = ring_data->rx_blocks[get_block].
3021                        rxds[get_info.offset].virt_addr;
3022                if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3023                        get_info.offset = 0;
3024                        ring_data->rx_curr_get_info.offset = get_info.offset;
3025                        get_block++;
3026                        if (get_block == ring_data->block_count)
3027                                get_block = 0;
3028                        ring_data->rx_curr_get_info.block_index = get_block;
3029                        rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3030                }
3031
3032                if (ring_data->nic->config.napi) {
3033                        budget--;
3034                        napi_pkts++;
3035                        if (!budget)
3036                                break;
3037                }
3038                pkt_cnt++;
3039                if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3040                        break;
3041        }
3042        if (ring_data->lro) {
3043                /* Clear all LRO sessions before exiting */
3044                for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3045                        struct lro *lro = &ring_data->lro0_n[i];
3046                        if (lro->in_use) {
3047                                update_L3L4_header(ring_data->nic, lro);
3048                                queue_rx_frame(lro->parent, lro->vlan_tag);
3049                                clear_lro_session(lro);
3050                        }
3051                }
3052        }
3053        return napi_pkts;
3054}
3055
3056/**
3057 *  tx_intr_handler - Transmit interrupt handler
3058 *  @nic : device private variable
3059 *  Description:
3060 *  If an interrupt was raised to indicate DMA complete of the
3061 *  Tx packet, this function is called. It identifies the last TxD
3062 *  whose buffer was freed and frees all skbs whose data have already
3063 *  DMA'ed into the NICs internal memory.
3064 *  Return Value:
3065 *  NONE
3066 */
3067
3068static void tx_intr_handler(struct fifo_info *fifo_data)
3069{
3070        struct s2io_nic *nic = fifo_data->nic;
3071        struct tx_curr_get_info get_info, put_info;
3072        struct sk_buff *skb = NULL;
3073        struct TxD *txdlp;
3074        int pkt_cnt = 0;
3075        unsigned long flags = 0;
3076        u8 err_mask;
3077        struct stat_block *stats = nic->mac_control.stats_info;
3078        struct swStat *swstats = &stats->sw_stat;
3079
3080        if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3081                return;
3082
3083        get_info = fifo_data->tx_curr_get_info;
3084        memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3085        txdlp = (struct TxD *)
3086                fifo_data->list_info[get_info.offset].list_virt_addr;
3087        while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3088               (get_info.offset != put_info.offset) &&
3089               (txdlp->Host_Control)) {
3090                /* Check for TxD errors */
3091                if (txdlp->Control_1 & TXD_T_CODE) {
3092                        unsigned long long err;
3093                        err = txdlp->Control_1 & TXD_T_CODE;
3094                        if (err & 0x1) {
3095                                swstats->parity_err_cnt++;
3096                        }
3097
3098                        /* update t_code statistics */
3099                        err_mask = err >> 48;
3100                        switch (err_mask) {
3101                        case 2:
3102                                swstats->tx_buf_abort_cnt++;
3103                                break;
3104
3105                        case 3:
3106                                swstats->tx_desc_abort_cnt++;
3107                                break;
3108
3109                        case 7:
3110                                swstats->tx_parity_err_cnt++;
3111                                break;
3112
3113                        case 10:
3114                                swstats->tx_link_loss_cnt++;
3115                                break;
3116
3117                        case 15:
3118                                swstats->tx_list_proc_err_cnt++;
3119                                break;
3120                        }
3121                }
3122
3123                skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3124                if (skb == NULL) {
3125                        spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3126                        DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3127                                  __func__);
3128                        return;
3129                }
3130                pkt_cnt++;
3131
3132                /* Updating the statistics block */
3133                nic->dev->stats.tx_bytes += skb->len;
3134                swstats->mem_freed += skb->truesize;
3135                dev_kfree_skb_irq(skb);
3136
3137                get_info.offset++;
3138                if (get_info.offset == get_info.fifo_len + 1)
3139                        get_info.offset = 0;
3140                txdlp = (struct TxD *)
3141                        fifo_data->list_info[get_info.offset].list_virt_addr;
3142                fifo_data->tx_curr_get_info.offset = get_info.offset;
3143        }
3144
3145        s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3146
3147        spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3148}
3149
3150/**
3151 *  s2io_mdio_write - Function to write in to MDIO registers
3152 *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3153 *  @addr     : address value
3154 *  @value    : data value
3155 *  @dev      : pointer to net_device structure
3156 *  Description:
3157 *  This function is used to write values to the MDIO registers
3158 *  NONE
3159 */
3160static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3161                            struct net_device *dev)
3162{
3163        u64 val64;
3164        struct s2io_nic *sp = netdev_priv(dev);
3165        struct XENA_dev_config __iomem *bar0 = sp->bar0;
3166
3167        /* address transaction */
3168        val64 = MDIO_MMD_INDX_ADDR(addr) |
3169                MDIO_MMD_DEV_ADDR(mmd_type) |
3170                MDIO_MMS_PRT_ADDR(0x0);
3171        writeq(val64, &bar0->mdio_control);
3172        val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3173        writeq(val64, &bar0->mdio_control);
3174        udelay(100);
3175
3176        /* Data transaction */
3177        val64 = MDIO_MMD_INDX_ADDR(addr) |
3178                MDIO_MMD_DEV_ADDR(mmd_type) |
3179                MDIO_MMS_PRT_ADDR(0x0) |
3180                MDIO_MDIO_DATA(value) |
3181                MDIO_OP(MDIO_OP_WRITE_TRANS);
3182        writeq(val64, &bar0->mdio_control);
3183        val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3184        writeq(val64, &bar0->mdio_control);
3185        udelay(100);
3186
3187        val64 = MDIO_MMD_INDX_ADDR(addr) |
3188                MDIO_MMD_DEV_ADDR(mmd_type) |
3189                MDIO_MMS_PRT_ADDR(0x0) |
3190                MDIO_OP(MDIO_OP_READ_TRANS);
3191        writeq(val64, &bar0->mdio_control);
3192        val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3193        writeq(val64, &bar0->mdio_control);
3194        udelay(100);
3195}
3196
3197/**
3198 *  s2io_mdio_read - Function to write in to MDIO registers
3199 *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3200 *  @addr     : address value
3201 *  @dev      : pointer to net_device structure
3202 *  Description:
3203 *  This function is used to read values to the MDIO registers
3204 *  NONE
3205 */
3206static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3207{
3208        u64 val64 = 0x0;
3209        u64 rval64 = 0x0;
3210        struct s2io_nic *sp = netdev_priv(dev);
3211        struct XENA_dev_config __iomem *bar0 = sp->bar0;
3212
3213        /* address transaction */
3214        val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3215                         | MDIO_MMD_DEV_ADDR(mmd_type)
3216                         | MDIO_MMS_PRT_ADDR(0x0));
3217        writeq(val64, &bar0->mdio_control);
3218        val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3219        writeq(val64, &bar0->mdio_control);
3220        udelay(100);
3221
3222        /* Data transaction */
3223        val64 = MDIO_MMD_INDX_ADDR(addr) |
3224                MDIO_MMD_DEV_ADDR(mmd_type) |
3225                MDIO_MMS_PRT_ADDR(0x0) |
3226                MDIO_OP(MDIO_OP_READ_TRANS);
3227        writeq(val64, &bar0->mdio_control);
3228        val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3229        writeq(val64, &bar0->mdio_control);
3230        udelay(100);
3231
3232        /* Read the value from regs */
3233        rval64 = readq(&bar0->mdio_control);
3234        rval64 = rval64 & 0xFFFF0000;
3235        rval64 = rval64 >> 16;
3236        return rval64;
3237}
3238
3239/**
3240 *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3241 *  @counter      : couter value to be updated
3242 *  @flag         : flag to indicate the status
3243 *  @type         : counter type
3244 *  Description:
3245 *  This function is to check the status of the xpak counters value
3246 *  NONE
3247 */
3248
3249static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3250                                  u16 flag, u16 type)
3251{
3252        u64 mask = 0x3;
3253        u64 val64;
3254        int i;
3255        for (i = 0; i < index; i++)
3256                mask = mask << 0x2;
3257
3258        if (flag > 0) {
3259                *counter = *counter + 1;
3260                val64 = *regs_stat & mask;
3261                val64 = val64 >> (index * 0x2);
3262                val64 = val64 + 1;
3263                if (val64 == 3) {
3264                        switch (type) {
3265                        case 1:
3266                                DBG_PRINT(ERR_DBG,
3267                                          "Take Xframe NIC out of service.\n");
3268                                DBG_PRINT(ERR_DBG,
3269"Excessive temperatures may result in premature transceiver failure.\n");
3270                                break;
3271                        case 2:
3272                                DBG_PRINT(ERR_DBG,
3273                                          "Take Xframe NIC out of service.\n");
3274                                DBG_PRINT(ERR_DBG,
3275"Excessive bias currents may indicate imminent laser diode failure.\n");
3276                                break;
3277                        case 3:
3278                                DBG_PRINT(ERR_DBG,
3279                                          "Take Xframe NIC out of service.\n");
3280                                DBG_PRINT(ERR_DBG,
3281"Excessive laser output power may saturate far-end receiver.\n");
3282                                break;
3283                        default:
3284                                DBG_PRINT(ERR_DBG,
3285                                          "Incorrect XPAK Alarm type\n");
3286                        }
3287                        val64 = 0x0;
3288                }
3289                val64 = val64 << (index * 0x2);
3290                *regs_stat = (*regs_stat & (~mask)) | (val64);
3291
3292        } else {
3293                *regs_stat = *regs_stat & (~mask);
3294        }
3295}
3296
3297/**
3298 *  s2io_updt_xpak_counter - Function to update the xpak counters
3299 *  @dev         : pointer to net_device struct
3300 *  Description:
3301 *  This function is to upate the status of the xpak counters value
3302 *  NONE
3303 */
3304static void s2io_updt_xpak_counter(struct net_device *dev)
3305{
3306        u16 flag  = 0x0;
3307        u16 type  = 0x0;
3308        u16 val16 = 0x0;
3309        u64 val64 = 0x0;
3310        u64 addr  = 0x0;
3311
3312        struct s2io_nic *sp = netdev_priv(dev);
3313        struct stat_block *stats = sp->mac_control.stats_info;
3314        struct xpakStat *xstats = &stats->xpak_stat;
3315
3316        /* Check the communication with the MDIO slave */
3317        addr = MDIO_CTRL1;
3318        val64 = 0x0;
3319        val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3320        if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3321                DBG_PRINT(ERR_DBG,
3322                          "ERR: MDIO slave access failed - Returned %llx\n",
3323                          (unsigned long long)val64);
3324                return;
3325        }
3326
3327        /* Check for the expected value of control reg 1 */
3328        if (val64 != MDIO_CTRL1_SPEED10G) {
3329                DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3330                          "Returned: %llx- Expected: 0x%x\n",
3331                          (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3332                return;
3333        }
3334
3335        /* Loading the DOM register to MDIO register */
3336        addr = 0xA100;
3337        s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3338        val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3339
3340        /* Reading the Alarm flags */
3341        addr = 0xA070;
3342        val64 = 0x0;
3343        val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3344
3345        flag = CHECKBIT(val64, 0x7);
3346        type = 1;
3347        s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3348                              &xstats->xpak_regs_stat,
3349                              0x0, flag, type);
3350
3351        if (CHECKBIT(val64, 0x6))
3352                xstats->alarm_transceiver_temp_low++;
3353
3354        flag = CHECKBIT(val64, 0x3);
3355        type = 2;
3356        s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3357                              &xstats->xpak_regs_stat,
3358                              0x2, flag, type);
3359
3360        if (CHECKBIT(val64, 0x2))
3361                xstats->alarm_laser_bias_current_low++;
3362
3363        flag = CHECKBIT(val64, 0x1);
3364        type = 3;
3365        s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3366                              &xstats->xpak_regs_stat,
3367                              0x4, flag, type);
3368
3369        if (CHECKBIT(val64, 0x0))
3370                xstats->alarm_laser_output_power_low++;
3371
3372        /* Reading the Warning flags */
3373        addr = 0xA074;
3374        val64 = 0x0;
3375        val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3376
3377        if (CHECKBIT(val64, 0x7))
3378                xstats->warn_transceiver_temp_high++;
3379
3380        if (CHECKBIT(val64, 0x6))
3381                xstats->warn_transceiver_temp_low++;
3382
3383        if (CHECKBIT(val64, 0x3))
3384                xstats->warn_laser_bias_current_high++;
3385
3386        if (CHECKBIT(val64, 0x2))
3387                xstats->warn_laser_bias_current_low++;
3388
3389        if (CHECKBIT(val64, 0x1))
3390                xstats->warn_laser_output_power_high++;
3391
3392        if (CHECKBIT(val64, 0x0))
3393                xstats->warn_laser_output_power_low++;
3394}
3395
3396/**
3397 *  wait_for_cmd_complete - waits for a command to complete.
3398 *  @sp : private member of the device structure, which is a pointer to the
3399 *  s2io_nic structure.
3400 *  Description: Function that waits for a command to Write into RMAC
3401 *  ADDR DATA registers to be completed and returns either success or
3402 *  error depending on whether the command was complete or not.
3403 *  Return value:
3404 *   SUCCESS on success and FAILURE on failure.
3405 */
3406
3407static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3408                                 int bit_state)
3409{
3410        int ret = FAILURE, cnt = 0, delay = 1;
3411        u64 val64;
3412
3413        if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3414                return FAILURE;
3415
3416        do {
3417                val64 = readq(addr);
3418                if (bit_state == S2IO_BIT_RESET) {
3419                        if (!(val64 & busy_bit)) {
3420                                ret = SUCCESS;
3421                                break;
3422                        }
3423                } else {
3424                        if (!(val64 & busy_bit)) {
3425                                ret = SUCCESS;
3426                                break;
3427                        }
3428                }
3429
3430                if (in_interrupt())
3431                        mdelay(delay);
3432                else
3433                        msleep(delay);
3434
3435                if (++cnt >= 10)
3436                        delay = 50;
3437        } while (cnt < 20);
3438        return ret;
3439}
3440/*
3441 * check_pci_device_id - Checks if the device id is supported
3442 * @id : device id
3443 * Description: Function to check if the pci device id is supported by driver.
3444 * Return value: Actual device id if supported else PCI_ANY_ID
3445 */
3446static u16 check_pci_device_id(u16 id)
3447{
3448        switch (id) {
3449        case PCI_DEVICE_ID_HERC_WIN:
3450        case PCI_DEVICE_ID_HERC_UNI:
3451                return XFRAME_II_DEVICE;
3452        case PCI_DEVICE_ID_S2IO_UNI:
3453        case PCI_DEVICE_ID_S2IO_WIN:
3454                return XFRAME_I_DEVICE;
3455        default:
3456                return PCI_ANY_ID;
3457        }
3458}
3459
3460/**
3461 *  s2io_reset - Resets the card.
3462 *  @sp : private member of the device structure.
3463 *  Description: Function to Reset the card. This function then also
3464 *  restores the previously saved PCI configuration space registers as
3465 *  the card reset also resets the configuration space.
3466 *  Return value:
3467 *  void.
3468 */
3469
3470static void s2io_reset(struct s2io_nic *sp)
3471{
3472        struct XENA_dev_config __iomem *bar0 = sp->bar0;
3473        u64 val64;
3474        u16 subid, pci_cmd;
3475        int i;
3476        u16 val16;
3477        unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3478        unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3479        struct stat_block *stats;
3480        struct swStat *swstats;
3481
3482        DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3483                  __func__, sp->dev->name);
3484
3485        /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3486        pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3487
3488        val64 = SW_RESET_ALL;
3489        writeq(val64, &bar0->sw_reset);
3490        if (strstr(sp->product_name, "CX4"))
3491                msleep(750);
3492        msleep(250);
3493        for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3494
3495                /* Restore the PCI state saved during initialization. */
3496                pci_restore_state(sp->pdev);
3497                pci_save_state(sp->pdev);
3498                pci_read_config_word(sp->pdev, 0x2, &val16);
3499                if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3500                        break;
3501                msleep(200);
3502        }
3503
3504        if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3505                DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3506
3507        pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3508
3509        s2io_init_pci(sp);
3510
3511        /* Set swapper to enable I/O register access */
3512        s2io_set_swapper(sp);
3513
3514        /* restore mac_addr entries */
3515        do_s2io_restore_unicast_mc(sp);
3516
3517        /* Restore the MSIX table entries from local variables */
3518        restore_xmsi_data(sp);
3519
3520        /* Clear certain PCI/PCI-X fields after reset */
3521        if (sp->device_type == XFRAME_II_DEVICE) {
3522                /* Clear "detected parity error" bit */
3523                pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3524
3525                /* Clearing PCIX Ecc status register */
3526                pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3527
3528                /* Clearing PCI_STATUS error reflected here */
3529                writeq(s2BIT(62), &bar0->txpic_int_reg);
3530        }
3531
3532        /* Reset device statistics maintained by OS */
3533        memset(&sp->stats, 0, sizeof(struct net_device_stats));
3534
3535        stats = sp->mac_control.stats_info;
3536        swstats = &stats->sw_stat;
3537
3538        /* save link up/down time/cnt, reset/memory/watchdog cnt */
3539        up_cnt = swstats->link_up_cnt;
3540        down_cnt = swstats->link_down_cnt;
3541        up_time = swstats->link_up_time;
3542        down_time = swstats->link_down_time;
3543        reset_cnt = swstats->soft_reset_cnt;
3544        mem_alloc_cnt = swstats->mem_allocated;
3545        mem_free_cnt = swstats->mem_freed;
3546        watchdog_cnt = swstats->watchdog_timer_cnt;
3547
3548        memset(stats, 0, sizeof(struct stat_block));
3549
3550        /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3551        swstats->link_up_cnt = up_cnt;
3552        swstats->link_down_cnt = down_cnt;
3553        swstats->link_up_time = up_time;
3554        swstats->link_down_time = down_time;
3555        swstats->soft_reset_cnt = reset_cnt;
3556        swstats->mem_allocated = mem_alloc_cnt;
3557        swstats->mem_freed = mem_free_cnt;
3558        swstats->watchdog_timer_cnt = watchdog_cnt;
3559
3560        /* SXE-002: Configure link and activity LED to turn it off */
3561        subid = sp->pdev->subsystem_device;
3562        if (((subid & 0xFF) >= 0x07) &&
3563            (sp->device_type == XFRAME_I_DEVICE)) {
3564                val64 = readq(&bar0->gpio_control);
3565                val64 |= 0x0000800000000000ULL;
3566                writeq(val64, &bar0->gpio_control);
3567                val64 = 0x0411040400000000ULL;
3568                writeq(val64, (void __iomem *)bar0 + 0x2700);
3569        }
3570
3571        /*
3572         * Clear spurious ECC interrupts that would have occured on
3573         * XFRAME II cards after reset.
3574         */
3575        if (sp->device_type == XFRAME_II_DEVICE) {
3576                val64 = readq(&bar0->pcc_err_reg);
3577                writeq(val64, &bar0->pcc_err_reg);
3578        }
3579
3580        sp->device_enabled_once = false;
3581}
3582
3583/**
3584 *  s2io_set_swapper - to set the swapper controle on the card
3585 *  @sp : private member of the device structure,
3586 *  pointer to the s2io_nic structure.
3587 *  Description: Function to set the swapper control on the card
3588 *  correctly depending on the 'endianness' of the system.
3589 *  Return value:
3590 *  SUCCESS on success and FAILURE on failure.
3591 */
3592
3593static int s2io_set_swapper(struct s2io_nic *sp)
3594{
3595        struct net_device *dev = sp->dev;
3596        struct XENA_dev_config __iomem *bar0 = sp->bar0;
3597        u64 val64, valt, valr;
3598
3599        /*
3600         * Set proper endian settings and verify the same by reading
3601         * the PIF Feed-back register.
3602         */
3603
3604        val64 = readq(&bar0->pif_rd_swapper_fb);
3605        if (val64 != 0x0123456789ABCDEFULL) {
3606                int i = 0;
3607                u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3608                                0x8100008181000081ULL,  /* FE=1, SE=0 */
3609                                0x4200004242000042ULL,  /* FE=0, SE=1 */
3610                                0};                     /* FE=0, SE=0 */
3611
3612                while (i < 4) {
3613                        writeq(value[i], &bar0->swapper_ctrl);
3614                        val64 = readq(&bar0->pif_rd_swapper_fb);
3615                        if (val64 == 0x0123456789ABCDEFULL)
3616                                break;
3617                        i++;
3618                }
3619                if (i == 4) {
3620                        DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3621                                  "feedback read %llx\n",
3622                                  dev->name, (unsigned long long)val64);
3623                        return FAILURE;
3624                }
3625                valr = value[i];
3626        } else {
3627                valr = readq(&bar0->swapper_ctrl);
3628        }
3629
3630        valt = 0x0123456789ABCDEFULL;
3631        writeq(valt, &bar0->xmsi_address);
3632        val64 = readq(&bar0->xmsi_address);
3633
3634        if (val64 != valt) {
3635                int i = 0;
3636                u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3637                                0x0081810000818100ULL,  /* FE=1, SE=0 */
3638                                0x0042420000424200ULL,  /* FE=0, SE=1 */
3639                                0};                     /* FE=0, SE=0 */
3640
3641                while (i < 4) {
3642                        writeq((value[i] | valr), &bar0->swapper_ctrl);
3643                        writeq(valt, &bar0->xmsi_address);
3644                        val64 = readq(&bar0->xmsi_address);
3645                        if (val64 == valt)
3646                                break;
3647                        i++;
3648                }
3649                if (i == 4) {
3650                        unsigned long long x = val64;
3651                        DBG_PRINT(ERR_DBG,
3652                                  "Write failed, Xmsi_addr reads:0x%llx\n", x);
3653                        return FAILURE;
3654                }
3655        }
3656        val64 = readq(&bar0->swapper_ctrl);
3657        val64 &= 0xFFFF000000000000ULL;
3658
3659#ifdef __BIG_ENDIAN
3660        /*
3661         * The device by default set to a big endian format, so a
3662         * big endian driver need not set anything.
3663         */
3664        val64 |= (SWAPPER_CTRL_TXP_FE |
3665                  SWAPPER_CTRL_TXP_SE |
3666                  SWAPPER_CTRL_TXD_R_FE |
3667                  SWAPPER_CTRL_TXD_W_FE |
3668                  SWAPPER_CTRL_TXF_R_FE |
3669                  SWAPPER_CTRL_RXD_R_FE |
3670                  SWAPPER_CTRL_RXD_W_FE |
3671                  SWAPPER_CTRL_RXF_W_FE |
3672                  SWAPPER_CTRL_XMSI_FE |
3673                  SWAPPER_CTRL_STATS_FE |
3674                  SWAPPER_CTRL_STATS_SE);
3675        if (sp->config.intr_type == INTA)
3676                val64 |= SWAPPER_CTRL_XMSI_SE;
3677        writeq(val64, &bar0->swapper_ctrl);
3678#else
3679        /*
3680         * Initially we enable all bits to make it accessible by the
3681         * driver, then we selectively enable only those bits that
3682         * we want to set.
3683         */
3684        val64 |= (SWAPPER_CTRL_TXP_FE |
3685                  SWAPPER_CTRL_TXP_SE |
3686                  SWAPPER_CTRL_TXD_R_FE |
3687                  SWAPPER_CTRL_TXD_R_SE |
3688                  SWAPPER_CTRL_TXD_W_FE |
3689                  SWAPPER_CTRL_TXD_W_SE |
3690                  SWAPPER_CTRL_TXF_R_FE |
3691                  SWAPPER_CTRL_RXD_R_FE |
3692                  SWAPPER_CTRL_RXD_R_SE |
3693                  SWAPPER_CTRL_RXD_W_FE |
3694                  SWAPPER_CTRL_RXD_W_SE |
3695                  SWAPPER_CTRL_RXF_W_FE |
3696                  SWAPPER_CTRL_XMSI_FE |
3697                  SWAPPER_CTRL_STATS_FE |
3698                  SWAPPER_CTRL_STATS_SE);
3699        if (sp->config.intr_type == INTA)
3700                val64 |= SWAPPER_CTRL_XMSI_SE;
3701        writeq(val64, &bar0->swapper_ctrl);
3702#endif
3703        val64 = readq(&bar0->swapper_ctrl);
3704
3705        /*
3706         * Verifying if endian settings are accurate by reading a
3707         * feedback register.
3708         */
3709        val64 = readq(&bar0->pif_rd_swapper_fb);
3710        if (val64 != 0x0123456789ABCDEFULL) {
3711                /* Endian settings are incorrect, calls for another dekko. */
3712                DBG_PRINT(ERR_DBG,
3713                          "%s: Endian settings are wrong, feedback read %llx\n",
3714                          dev->name, (unsigned long long)val64);
3715                return FAILURE;
3716        }
3717
3718        return SUCCESS;
3719}
3720
3721static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3722{
3723        struct XENA_dev_config __iomem *bar0 = nic->bar0;
3724        u64 val64;
3725        int ret = 0, cnt = 0;
3726
3727        do {
3728                val64 = readq(&bar0->xmsi_access);
3729                if (!(val64 & s2BIT(15)))
3730                        break;
3731                mdelay(1);
3732                cnt++;
3733        } while (cnt < 5);
3734        if (cnt == 5) {
3735                DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3736                ret = 1;
3737        }
3738
3739        return ret;
3740}
3741
3742static void restore_xmsi_data(struct s2io_nic *nic)
3743{
3744        struct XENA_dev_config __iomem *bar0 = nic->bar0;
3745        u64 val64;
3746        int i, msix_index;
3747
3748        if (nic->device_type == XFRAME_I_DEVICE)
3749                return;
3750
3751        for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3752                msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3753                writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3754                writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3755                val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3756                writeq(val64, &bar0->xmsi_access);
3757                if (wait_for_msix_trans(nic, msix_index)) {
3758                        DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3759                                  __func__, msix_index);
3760                        continue;
3761                }
3762        }
3763}
3764
3765static void store_xmsi_data(struct s2io_nic *nic)
3766{
3767        struct XENA_dev_config __iomem *bar0 = nic->bar0;
3768        u64 val64, addr, data;
3769        int i, msix_index;
3770
3771        if (nic->device_type == XFRAME_I_DEVICE)
3772                return;
3773
3774        /* Store and display */
3775        for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3776                msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3777                val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3778                writeq(val64, &bar0->xmsi_access);
3779                if (wait_for_msix_trans(nic, msix_index)) {
3780                        DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3781                                  __func__, msix_index);
3782                        continue;
3783                }
3784                addr = readq(&bar0->xmsi_address);
3785                data = readq(&bar0->xmsi_data);
3786                if (addr && data) {
3787                        nic->msix_info[i].addr = addr;
3788                        nic->msix_info[i].data = data;
3789                }
3790        }
3791}
3792
3793static int s2io_enable_msi_x(struct s2io_nic *nic)
3794{
3795        struct XENA_dev_config __iomem *bar0 = nic->bar0;
3796        u64 rx_mat;
3797        u16 msi_control; /* Temp variable */
3798        int ret, i, j, msix_indx = 1;
3799        int size;
3800        struct stat_block *stats = nic->mac_control.stats_info;
3801        struct swStat *swstats = &stats->sw_stat;
3802
3803        size = nic->num_entries * sizeof(struct msix_entry);
3804        nic->entries = kzalloc(size, GFP_KERNEL);
3805        if (!nic->entries) {
3806                DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3807                          __func__);
3808                swstats->mem_alloc_fail_cnt++;
3809                return -ENOMEM;
3810        }
3811        swstats->mem_allocated += size;
3812
3813        size = nic->num_entries * sizeof(struct s2io_msix_entry);
3814        nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3815        if (!nic->s2io_entries) {
3816                DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3817                          __func__);
3818                swstats->mem_alloc_fail_cnt++;
3819                kfree(nic->entries);
3820                swstats->mem_freed
3821                        += (nic->num_entries * sizeof(struct msix_entry));
3822                return -ENOMEM;
3823        }
3824        swstats->mem_allocated += size;
3825
3826        nic->entries[0].entry = 0;
3827        nic->s2io_entries[0].entry = 0;
3828        nic->s2io_entries[0].in_use = MSIX_FLG;
3829        nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3830        nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3831
3832        for (i = 1; i < nic->num_entries; i++) {
3833                nic->entries[i].entry = ((i - 1) * 8) + 1;
3834                nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3835                nic->s2io_entries[i].arg = NULL;
3836                nic->s2io_entries[i].in_use = 0;
3837        }
3838
3839        rx_mat = readq(&bar0->rx_mat);
3840        for (j = 0; j < nic->config.rx_ring_num; j++) {
3841                rx_mat |= RX_MAT_SET(j, msix_indx);
3842                nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3843                nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3844                nic->s2io_entries[j+1].in_use = MSIX_FLG;
3845                msix_indx += 8;
3846        }
3847        writeq(rx_mat, &bar0->rx_mat);
3848        readq(&bar0->rx_mat);
3849
3850        ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3851        /* We fail init if error or we get less vectors than min required */
3852        if (ret) {
3853                DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3854                kfree(nic->entries);
3855                swstats->mem_freed += nic->num_entries *
3856                        sizeof(struct msix_entry);
3857                kfree(nic->s2io_entries);
3858                swstats->mem_freed += nic->num_entries *
3859                        sizeof(struct s2io_msix_entry);
3860                nic->entries = NULL;
3861                nic->s2io_entries = NULL;
3862                return -ENOMEM;
3863        }
3864
3865        /*
3866         * To enable MSI-X, MSI also needs to be enabled, due to a bug
3867         * in the herc NIC. (Temp change, needs to be removed later)
3868         */
3869        pci_read_config_word(nic->pdev, 0x42, &msi_control);
3870        msi_control |= 0x1; /* Enable MSI */
3871        pci_write_config_word(nic->pdev, 0x42, msi_control);
3872
3873        return 0;
3874}
3875
3876/* Handle software interrupt used during MSI(X) test */
3877static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3878{
3879        struct s2io_nic *sp = dev_id;
3880
3881        sp->msi_detected = 1;
3882        wake_up(&sp->msi_wait);
3883
3884        return IRQ_HANDLED;
3885}
3886
3887/* Test interrupt path by forcing a a software IRQ */
3888static int s2io_test_msi(struct s2io_nic *sp)
3889{
3890        struct pci_dev *pdev = sp->pdev;
3891        struct XENA_dev_config __iomem *bar0 = sp->bar0;
3892        int err;
3893        u64 val64, saved64;
3894
3895        err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3896                          sp->name, sp);
3897        if (err) {
3898                DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3899                          sp->dev->name, pci_name(pdev), pdev->irq);
3900                return err;
3901        }
3902
3903        init_waitqueue_head(&sp->msi_wait);
3904        sp->msi_detected = 0;
3905
3906        saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3907        val64 |= SCHED_INT_CTRL_ONE_SHOT;
3908        val64 |= SCHED_INT_CTRL_TIMER_EN;
3909        val64 |= SCHED_INT_CTRL_INT2MSI(1);
3910        writeq(val64, &bar0->scheduled_int_ctrl);
3911
3912        wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3913
3914        if (!sp->msi_detected) {
3915                /* MSI(X) test failed, go back to INTx mode */
3916                DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3917                          "using MSI(X) during test\n",
3918                          sp->dev->name, pci_name(pdev));
3919
3920                err = -EOPNOTSUPP;
3921        }
3922
3923        free_irq(sp->entries[1].vector, sp);
3924
3925        writeq(saved64, &bar0->scheduled_int_ctrl);
3926
3927        return err;
3928}
3929
3930static void remove_msix_isr(struct s2io_nic *sp)
3931{
3932        int i;
3933        u16 msi_control;
3934
3935        for (i = 0; i < sp->num_entries; i++) {
3936                if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3937                        int vector = sp->entries[i].vector;
3938                        void *arg = sp->s2io_entries[i].arg;
3939                        free_irq(vector, arg);
3940                }
3941        }
3942
3943        kfree(sp->entries);
3944        kfree(sp->s2io_entries);
3945        sp->entries = NULL;
3946        sp->s2io_entries = NULL;
3947
3948        pci_read_config_word(sp->pdev, 0x42, &msi_control);
3949        msi_control &= 0xFFFE; /* Disable MSI */
3950        pci_write_config_word(sp->pdev, 0x42, msi_control);
3951
3952        pci_disable_msix(sp->pdev);
3953}
3954
3955static void remove_inta_isr(struct s2io_nic *sp)
3956{
3957        struct net_device *dev = sp->dev;
3958
3959        free_irq(sp->pdev->irq, dev);
3960}
3961
3962/* ********************************************************* *
3963 * Functions defined below concern the OS part of the driver *
3964 * ********************************************************* */
3965
3966/**
3967 *  s2io_open - open entry point of the driver
3968 *  @dev : pointer to the device structure.
3969 *  Description:
3970 *  This function is the open entry point of the driver. It mainly calls a
3971 *  function to allocate Rx buffers and inserts them into the buffer
3972 *  descriptors and then enables the Rx part of the NIC.
3973 *  Return value:
3974 *  0 on success and an appropriate (-)ve integer as defined in errno.h
3975 *   file on failure.
3976 */
3977
3978static int s2io_open(struct net_device *dev)
3979{
3980        struct s2io_nic *sp = netdev_priv(dev);
3981        struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3982        int err = 0;
3983
3984        /*
3985         * Make sure you have link off by default every time
3986         * Nic is initialized
3987         */
3988        netif_carrier_off(dev);
3989        sp->last_link_state = 0;
3990
3991        /* Initialize H/W and enable interrupts */
3992        err = s2io_card_up(sp);
3993        if (err) {
3994                DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3995                          dev->name);
3996                goto hw_init_failed;
3997        }
3998
3999        if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4000                DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4001                s2io_card_down(sp);
4002                err = -ENODEV;
4003                goto hw_init_failed;
4004        }
4005        s2io_start_all_tx_queue(sp);
4006        return 0;
4007
4008hw_init_failed:
4009        if (sp->config.intr_type == MSI_X) {
4010                if (sp->entries) {
4011                        kfree(sp->entries);
4012                        swstats->mem_freed += sp->num_entries *
4013                                sizeof(struct msix_entry);
4014                }
4015                if (sp->s2io_entries) {
4016                        kfree(sp->s2io_entries);
4017                        swstats->mem_freed += sp->num_entries *
4018                                sizeof(struct s2io_msix_entry);
4019                }
4020        }
4021        return err;
4022}
4023
4024/**
4025 *  s2io_close -close entry point of the driver
4026 *  @dev : device pointer.
4027 *  Description:
4028 *  This is the stop entry point of the driver. It needs to undo exactly
4029 *  whatever was done by the open entry point,thus it's usually referred to
4030 *  as the close function.Among other things this function mainly stops the
4031 *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4032 *  Return value:
4033 *  0 on success and an appropriate (-)ve integer as defined in errno.h
4034 *  file on failure.
4035 */
4036
4037static int s2io_close(struct net_device *dev)
4038{
4039        struct s2io_nic *sp = netdev_priv(dev);
4040        struct config_param *config = &sp->config;
4041        u64 tmp64;
4042        int offset;
4043
4044        /* Return if the device is already closed               *
4045         *  Can happen when s2io_card_up failed in change_mtu    *
4046         */
4047        if (!is_s2io_card_up(sp))
4048                return 0;
4049
4050        s2io_stop_all_tx_queue(sp);
4051        /* delete all populated mac entries */
4052        for (offset = 1; offset < config->max_mc_addr; offset++) {
4053                tmp64 = do_s2io_read_unicast_mc(sp, offset);
4054                if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4055                        do_s2io_delete_unicast_mc(sp, tmp64);
4056        }
4057
4058        s2io_card_down(sp);
4059
4060        return 0;
4061}
4062
4063/**
4064 *  s2io_xmit - Tx entry point of te driver
4065 *  @skb : the socket buffer containing the Tx data.
4066 *  @dev : device pointer.
4067 *  Description :
4068 *  This function is the Tx entry point of the driver. S2IO NIC supports
4069 *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4070 *  NOTE: when device cant queue the pkt,just the trans_start variable will
4071 *  not be upadted.
4072 *  Return value:
4073 *  0 on success & 1 on failure.
4074 */
4075
4076static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4077{
4078        struct s2io_nic *sp = netdev_priv(dev);
4079        u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4080        register u64 val64;
4081        struct TxD *txdp;
4082        struct TxFIFO_element __iomem *tx_fifo;
4083        unsigned long flags = 0;
4084        u16 vlan_tag = 0;
4085        struct fifo_info *fifo = NULL;
4086        int do_spin_lock = 1;
4087        int offload_type;
4088        int enable_per_list_interrupt = 0;
4089        struct config_param *config = &sp->config;
4090        struct mac_info *mac_control = &sp->mac_control;
4091        struct stat_block *stats = mac_control->stats_info;
4092        struct swStat *swstats = &stats->sw_stat;
4093
4094        DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4095
4096        if (unlikely(skb->len <= 0)) {
4097                DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4098                dev_kfree_skb_any(skb);
4099                return NETDEV_TX_OK;
4100        }
4101
4102        if (!is_s2io_card_up(sp)) {
4103                DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4104                          dev->name);
4105                dev_kfree_skb(skb);
4106                return NETDEV_TX_OK;
4107        }
4108
4109        queue = 0;
4110        if (sp->vlgrp && vlan_tx_tag_present(skb))
4111                vlan_tag = vlan_tx_tag_get(skb);
4112        if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4113                if (skb->protocol == htons(ETH_P_IP)) {
4114                        struct iphdr *ip;
4115                        struct tcphdr *th;
4116                        ip = ip_hdr(skb);
4117
4118                        if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4119                                th = (struct tcphdr *)(((unsigned char *)ip) +
4120                                                       ip->ihl*4);
4121
4122                                if (ip->protocol == IPPROTO_TCP) {
4123                                        queue_len = sp->total_tcp_fifos;
4124                                        queue = (ntohs(th->source) +
4125                                                 ntohs(th->dest)) &
4126                                                sp->fifo_selector[queue_len - 1];
4127                                        if (queue >= queue_len)
4128                                                queue = queue_len - 1;
4129                                } else if (ip->protocol == IPPROTO_UDP) {
4130                                        queue_len = sp->total_udp_fifos;
4131                                        queue = (ntohs(th->source) +
4132                                                 ntohs(th->dest)) &
4133                                                sp->fifo_selector[queue_len - 1];
4134                                        if (queue >= queue_len)
4135                                                queue = queue_len - 1;
4136                                        queue += sp->udp_fifo_idx;
4137                                        if (skb->len > 1024)
4138                                                enable_per_list_interrupt = 1;
4139                                        do_spin_lock = 0;
4140                                }
4141                        }
4142                }
4143        } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4144                /* get fifo number based on skb->priority value */
4145                queue = config->fifo_mapping
4146                        [skb->priority & (MAX_TX_FIFOS - 1)];
4147        fifo = &mac_control->fifos[queue];
4148
4149        if (do_spin_lock)
4150                spin_lock_irqsave(&fifo->tx_lock, flags);
4151        else {
4152                if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4153                        return NETDEV_TX_LOCKED;
4154        }
4155
4156        if (sp->config.multiq) {
4157                if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4158                        spin_unlock_irqrestore(&fifo->tx_lock, flags);
4159                        return NETDEV_TX_BUSY;
4160                }
4161        } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4162                if (netif_queue_stopped(dev)) {
4163                        spin_unlock_irqrestore(&fifo->tx_lock, flags);
4164                        return NETDEV_TX_BUSY;
4165                }
4166        }
4167
4168        put_off = (u16)fifo->tx_curr_put_info.offset;
4169        get_off = (u16)fifo->tx_curr_get_info.offset;
4170        txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4171
4172        queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4173        /* Avoid "put" pointer going beyond "get" pointer */
4174        if (txdp->Host_Control ||
4175            ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4176                DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4177                s2io_stop_tx_queue(sp, fifo->fifo_no);
4178                dev_kfree_skb(skb);
4179                spin_unlock_irqrestore(&fifo->tx_lock, flags);
4180                return NETDEV_TX_OK;
4181        }
4182
4183        offload_type = s2io_offload_type(skb);
4184        if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4185                txdp->Control_1 |= TXD_TCP_LSO_EN;
4186                txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4187        }
4188        if (skb->ip_summed == CHECKSUM_PARTIAL) {
4189                txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4190                                    TXD_TX_CKO_TCP_EN |
4191                                    TXD_TX_CKO_UDP_EN);
4192        }
4193        txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4194        txdp->Control_1 |= TXD_LIST_OWN_XENA;
4195        txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4196        if (enable_per_list_interrupt)
4197                if (put_off & (queue_len >> 5))
4198                        txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4199        if (vlan_tag) {
4200                txdp->Control_2 |= TXD_VLAN_ENABLE;
4201                txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4202        }
4203
4204        frg_len = skb->len - skb->data_len;
4205        if (offload_type == SKB_GSO_UDP) {
4206                int ufo_size;
4207
4208                ufo_size = s2io_udp_mss(skb);
4209                ufo_size &= ~7;
4210                txdp->Control_1 |= TXD_UFO_EN;
4211                txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4212                txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4213#ifdef __BIG_ENDIAN
4214                /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4215                fifo->ufo_in_band_v[put_off] =
4216                        (__force u64)skb_shinfo(skb)->ip6_frag_id;
4217#else
4218                fifo->ufo_in_band_v[put_off] =
4219                        (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4220#endif
4221                txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4222                txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4223                                                      fifo->ufo_in_band_v,
4224                                                      sizeof(u64),
4225                                                      PCI_DMA_TODEVICE);
4226                if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4227                        goto pci_map_failed;
4228                txdp++;
4229        }
4230
4231        txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4232                                              frg_len, PCI_DMA_TODEVICE);
4233        if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4234                goto pci_map_failed;
4235
4236        txdp->Host_Control = (unsigned long)skb;
4237        txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4238        if (offload_type == SKB_GSO_UDP)
4239                txdp->Control_1 |= TXD_UFO_EN;
4240
4241        frg_cnt = skb_shinfo(skb)->nr_frags;
4242        /* For fragmented SKB. */
4243        for (i = 0; i < frg_cnt; i++) {
4244                skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4245                /* A '0' length fragment will be ignored */
4246                if (!frag->size)
4247                        continue;
4248                txdp++;
4249                txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4250                                                         frag->page_offset,
4251                                                         frag->size,
4252                                                         PCI_DMA_TODEVICE);
4253                txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4254                if (offload_type == SKB_GSO_UDP)
4255                        txdp->Control_1 |= TXD_UFO_EN;
4256        }
4257        txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4258
4259        if (offload_type == SKB_GSO_UDP)
4260                frg_cnt++; /* as Txd0 was used for inband header */
4261
4262        tx_fifo = mac_control->tx_FIFO_start[queue];
4263        val64 = fifo->list_info[put_off].list_phy_addr;
4264        writeq(val64, &tx_fifo->TxDL_Pointer);
4265
4266        val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4267                 TX_FIFO_LAST_LIST);
4268        if (offload_type)
4269                val64 |= TX_FIFO_SPECIAL_FUNC;
4270
4271        writeq(val64, &tx_fifo->List_Control);
4272
4273        mmiowb();
4274
4275        put_off++;
4276        if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4277                put_off = 0;
4278        fifo->tx_curr_put_info.offset = put_off;
4279
4280        /* Avoid "put" pointer going beyond "get" pointer */
4281        if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4282                swstats->fifo_full_cnt++;
4283                DBG_PRINT(TX_DBG,
4284                          "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4285                          put_off, get_off);
4286                s2io_stop_tx_queue(sp, fifo->fifo_no);
4287        }
4288        swstats->mem_allocated += skb->truesize;
4289        spin_unlock_irqrestore(&fifo->tx_lock, flags);
4290
4291        if (sp->config.intr_type == MSI_X)
4292                tx_intr_handler(fifo);
4293
4294        return NETDEV_TX_OK;
4295
4296pci_map_failed:
4297        swstats->pci_map_fail_cnt++;
4298        s2io_stop_tx_queue(sp, fifo->fifo_no);
4299        swstats->mem_freed += skb->truesize;
4300        dev_kfree_skb(skb);
4301        spin_unlock_irqrestore(&fifo->tx_lock, flags);
4302        return NETDEV_TX_OK;
4303}
4304
4305static void
4306s2io_alarm_handle(unsigned long data)
4307{
4308        struct s2io_nic *sp = (struct s2io_nic *)data;
4309        struct net_device *dev = sp->dev;
4310
4311        s2io_handle_errors(dev);
4312        mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4313}
4314
4315static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4316{
4317        struct ring_info *ring = (struct ring_info *)dev_id;
4318        struct s2io_nic *sp = ring->nic;
4319        struct XENA_dev_config __iomem *bar0 = sp->bar0;
4320
4321        if (unlikely(!is_s2io_card_up(sp)))
4322                return IRQ_HANDLED;
4323
4324        if (sp->config.napi) {
4325                u8 __iomem *addr = NULL;
4326                u8 val8 = 0;
4327
4328                addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4329                addr += (7 - ring->ring_no);
4330                val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4331                writeb(val8, addr);
4332                val8 = readb(addr);
4333                napi_schedule(&ring->napi);
4334        } else {
4335                rx_intr_handler(ring, 0);
4336                s2io_chk_rx_buffers(sp, ring);
4337        }
4338
4339        return IRQ_HANDLED;
4340}
4341
4342static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4343{
4344        int i;
4345        struct fifo_info *fifos = (struct fifo_info *)dev_id;
4346        struct s2io_nic *sp = fifos->nic;
4347        struct XENA_dev_config __iomem *bar0 = sp->bar0;
4348        struct config_param *config  = &sp->config;
4349        u64 reason;
4350
4351        if (unlikely(!is_s2io_card_up(sp)))
4352                return IRQ_NONE;
4353
4354        reason = readq(&bar0->general_int_status);
4355        if (unlikely(reason == S2IO_MINUS_ONE))
4356                /* Nothing much can be done. Get out */
4357                return IRQ_HANDLED;
4358
4359        if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4360                writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4361
4362                if (reason & GEN_INTR_TXPIC)
4363                        s2io_txpic_intr_handle(sp);
4364
4365                if (reason & GEN_INTR_TXTRAFFIC)
4366                        writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4367
4368                for (i = 0; i < config->tx_fifo_num; i++)
4369                        tx_intr_handler(&fifos[i]);
4370
4371                writeq(sp->general_int_mask, &bar0->general_int_mask);
4372                readl(&bar0->general_int_status);
4373                return IRQ_HANDLED;
4374        }
4375        /* The interrupt was not raised by us */
4376        return IRQ_NONE;
4377}
4378
4379static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4380{
4381        struct XENA_dev_config __iomem *bar0 = sp->bar0;
4382        u64 val64;
4383
4384        val64 = readq(&bar0->pic_int_status);
4385        if (val64 & PIC_INT_GPIO) {
4386                val64 = readq(&bar0->gpio_int_reg);
4387                if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4388                    (val64 & GPIO_INT_REG_LINK_UP)) {
4389                        /*
4390                         * This is unstable state so clear both up/down
4391                         * interrupt and adapter to re-evaluate the link state.
4392                         */
4393                        val64 |= GPIO_INT_REG_LINK_DOWN;
4394                        val64 |= GPIO_INT_REG_LINK_UP;
4395                        writeq(val64, &bar0->gpio_int_reg);
4396                        val64 = readq(&bar0->gpio_int_mask);
4397                        val64 &= ~(GPIO_INT_MASK_LINK_UP |
4398                                   GPIO_INT_MASK_LINK_DOWN);
4399                        writeq(val64, &bar0->gpio_int_mask);
4400                } else if (val64 & GPIO_INT_REG_LINK_UP) {
4401                        val64 = readq(&bar0->adapter_status);
4402                        /* Enable Adapter */
4403                        val64 = readq(&bar0->adapter_control);
4404                        val64 |= ADAPTER_CNTL_EN;
4405                        writeq(val64, &bar0->adapter_control);
4406                        val64 |= ADAPTER_LED_ON;
4407                        writeq(val64, &bar0->adapter_control);
4408                        if (!sp->device_enabled_once)
4409                                sp->device_enabled_once = 1;
4410
4411                        s2io_link(sp, LINK_UP);
4412                        /*
4413                         * unmask link down interrupt and mask link-up
4414                         * intr
4415                         */
4416                        val64 = readq(&bar0->gpio_int_mask);
4417                        val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4418                        val64 |= GPIO_INT_MASK_LINK_UP;
4419                        writeq(val64, &bar0->gpio_int_mask);
4420
4421                } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4422                        val64 = readq(&bar0->adapter_status);
4423                        s2io_link(sp, LINK_DOWN);
4424                        /* Link is down so unmaks link up interrupt */
4425                        val64 = readq(&bar0->gpio_int_mask);
4426                        val64 &= ~GPIO_INT_MASK_LINK_UP;
4427                        val64 |= GPIO_INT_MASK_LINK_DOWN;
4428                        writeq(val64, &bar0->gpio_int_mask);
4429
4430                        /* turn off LED */
4431                        val64 = readq(&bar0->adapter_control);
4432                        val64 = val64 & (~ADAPTER_LED_ON);
4433                        writeq(val64, &bar0->adapter_control);
4434                }
4435        }
4436        val64 = readq(&bar0->gpio_int_mask);
4437}
4438
4439/**
4440 *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4441 *  @value: alarm bits
4442 *  @addr: address value
4443 *  @cnt: counter variable
4444 *  Description: Check for alarm and increment the counter
4445 *  Return Value:
4446 *  1 - if alarm bit set
4447 *  0 - if alarm bit is not set
4448 */
4449static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4450                                 unsigned long long *cnt)
4451{
4452        u64 val64;
4453        val64 = readq(addr);
4454        if (val64 & value) {
4455                writeq(val64, addr);
4456                (*cnt)++;
4457                return 1;
4458        }
4459        return 0;
4460
4461}
4462
4463/**
4464 *  s2io_handle_errors - Xframe error indication handler
4465 *  @nic: device private variable
4466 *  Description: Handle alarms such as loss of link, single or
4467 *  double ECC errors, critical and serious errors.
4468 *  Return Value:
4469 *  NONE
4470 */
4471static void s2io_handle_errors(void *dev_id)
4472{
4473        struct net_device *dev = (struct net_device *)dev_id;
4474        struct s2io_nic *sp = netdev_priv(dev);
4475        struct XENA_dev_config __iomem *bar0 = sp->bar0;
4476        u64 temp64 = 0, val64 = 0;
4477        int i = 0;
4478
4479        struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4480        struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4481
4482        if (!is_s2io_card_up(sp))
4483                return;
4484
4485        if (pci_channel_offline(sp->pdev))
4486                return;
4487
4488        memset(&sw_stat->ring_full_cnt, 0,
4489               sizeof(sw_stat->ring_full_cnt));
4490
4491        /* Handling the XPAK counters update */
4492        if (stats->xpak_timer_count < 72000) {
4493                /* waiting for an hour */
4494                stats->xpak_timer_count++;
4495        } else {
4496                s2io_updt_xpak_counter(dev);
4497                /* reset the count to zero */
4498                stats->xpak_timer_count = 0;
4499        }
4500
4501        /* Handling link status change error Intr */
4502        if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4503                val64 = readq(&bar0->mac_rmac_err_reg);
4504                writeq(val64, &bar0->mac_rmac_err_reg);
4505                if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4506                        schedule_work(&sp->set_link_task);
4507        }
4508
4509        /* In case of a serious error, the device will be Reset. */
4510        if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4511                                  &sw_stat->serious_err_cnt))
4512                goto reset;
4513
4514        /* Check for data parity error */
4515        if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4516                                  &sw_stat->parity_err_cnt))
4517                goto reset;
4518
4519        /* Check for ring full counter */
4520        if (sp->device_type == XFRAME_II_DEVICE) {
4521                val64 = readq(&bar0->ring_bump_counter1);
4522                for (i = 0; i < 4; i++) {
4523                        temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4524                        temp64 >>= 64 - ((i+1)*16);
4525                        sw_stat->ring_full_cnt[i] += temp64;
4526                }
4527
4528                val64 = readq(&bar0->ring_bump_counter2);
4529                for (i = 0; i < 4; i++) {
4530                        temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4531                        temp64 >>= 64 - ((i+1)*16);
4532                        sw_stat->ring_full_cnt[i+4] += temp64;
4533                }
4534        }
4535
4536        val64 = readq(&bar0->txdma_int_status);
4537        /*check for pfc_err*/
4538        if (val64 & TXDMA_PFC_INT) {
4539                if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4540                                          PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4541                                          PFC_PCIX_ERR,
4542                                          &bar0->pfc_err_reg,
4543                                          &sw_stat->pfc_err_cnt))
4544                        goto reset;
4545                do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4546                                      &bar0->pfc_err_reg,
4547                                      &sw_stat->pfc_err_cnt);
4548        }
4549
4550        /*check for tda_err*/
4551        if (val64 & TXDMA_TDA_INT) {
4552                if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4553                                          TDA_SM0_ERR_ALARM |
4554                                          TDA_SM1_ERR_ALARM,
4555                                          &bar0->tda_err_reg,
4556                                          &sw_stat->tda_err_cnt))
4557                        goto reset;
4558                do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4559                                      &bar0->tda_err_reg,
4560                                      &sw_stat->tda_err_cnt);
4561        }
4562        /*check for pcc_err*/
4563        if (val64 & TXDMA_PCC_INT) {
4564                if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4565                                          PCC_N_SERR | PCC_6_COF_OV_ERR |
4566                                          PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4567                                          PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4568                                          PCC_TXB_ECC_DB_ERR,
4569                                          &bar0->pcc_err_reg,
4570                                          &sw_stat->pcc_err_cnt))
4571                        goto reset;
4572                do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4573                                      &bar0->pcc_err_reg,
4574                                      &sw_stat->pcc_err_cnt);
4575        }
4576
4577        /*check for tti_err*/
4578        if (val64 & TXDMA_TTI_INT) {
4579                if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4580                                          &bar0->tti_err_reg,
4581                                          &sw_stat->tti_err_cnt))
4582                        goto reset;
4583                do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4584                                      &bar0->tti_err_reg,
4585                                      &sw_stat->tti_err_cnt);
4586        }
4587
4588        /*check for lso_err*/
4589        if (val64 & TXDMA_LSO_INT) {
4590                if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4591                                          LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4592                                          &bar0->lso_err_reg,
4593                                          &sw_stat->lso_err_cnt))
4594                        goto reset;
4595                do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4596                                      &bar0->lso_err_reg,
4597                                      &sw_stat->lso_err_cnt);
4598        }
4599
4600        /*check for tpa_err*/
4601        if (val64 & TXDMA_TPA_INT) {
4602                if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4603                                          &bar0->tpa_err_reg,
4604                                          &sw_stat->tpa_err_cnt))
4605                        goto reset;
4606                do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4607                                      &bar0->tpa_err_reg,
4608                                      &sw_stat->tpa_err_cnt);
4609        }
4610
4611        /*check for sm_err*/
4612        if (val64 & TXDMA_SM_INT) {
4613                if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4614                                          &bar0->sm_err_reg,
4615                                          &sw_stat->sm_err_cnt))
4616                        goto reset;
4617        }
4618
4619        val64 = readq(&bar0->mac_int_status);
4620        if (val64 & MAC_INT_STATUS_TMAC_INT) {
4621                if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4622                                          &bar0->mac_tmac_err_reg,
4623                                          &sw_stat->mac_tmac_err_cnt))
4624                        goto reset;
4625                do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4626                                      TMAC_DESC_ECC_SG_ERR |
4627                                      TMAC_DESC_ECC_DB_ERR,
4628                                      &bar0->mac_tmac_err_reg,
4629                                      &sw_stat->mac_tmac_err_cnt);
4630        }
4631
4632        val64 = readq(&bar0->xgxs_int_status);
4633        if (val64 & XGXS_INT_STATUS_TXGXS) {
4634                if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4635                                          &bar0->xgxs_txgxs_err_reg,
4636                                          &sw_stat->xgxs_txgxs_err_cnt))
4637                        goto reset;
4638                do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4639                                      &bar0->xgxs_txgxs_err_reg,
4640                                      &sw_stat->xgxs_txgxs_err_cnt);
4641        }
4642
4643        val64 = readq(&bar0->rxdma_int_status);
4644        if (val64 & RXDMA_INT_RC_INT_M) {
4645                if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4646                                          RC_FTC_ECC_DB_ERR |
4647                                          RC_PRCn_SM_ERR_ALARM |
4648                                          RC_FTC_SM_ERR_ALARM,
4649                                          &bar0->rc_err_reg,
4650                                          &sw_stat->rc_err_cnt))
4651                        goto reset;
4652                do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4653                                      RC_FTC_ECC_SG_ERR |
4654                                      RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4655                                      &sw_stat->rc_err_cnt);
4656                if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4657                                          PRC_PCI_AB_WR_Rn |
4658                                          PRC_PCI_AB_F_WR_Rn,
4659                                          &bar0->prc_pcix_err_reg,
4660                                          &sw_stat->prc_pcix_err_cnt))
4661                        goto reset;
4662                do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4663                                      PRC_PCI_DP_WR_Rn |
4664                                      PRC_PCI_DP_F_WR_Rn,
4665                                      &bar0->prc_pcix_err_reg,
4666                                      &sw_stat->prc_pcix_err_cnt);
4667        }
4668
4669        if (val64 & RXDMA_INT_RPA_INT_M) {
4670                if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4671                                          &bar0->rpa_err_reg,
4672                                          &sw_stat->rpa_err_cnt))
4673                        goto reset;
4674                do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4675                                      &bar0->rpa_err_reg,
4676                                      &sw_stat->rpa_err_cnt);
4677        }
4678
4679        if (val64 & RXDMA_INT_RDA_INT_M) {
4680                if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4681                                          RDA_FRM_ECC_DB_N_AERR |
4682                                          RDA_SM1_ERR_ALARM |
4683                                          RDA_SM0_ERR_ALARM |
4684                                          RDA_RXD_ECC_DB_SERR,
4685                                          &bar0->rda_err_reg,
4686                                          &sw_stat->rda_err_cnt))
4687                        goto reset;
4688                do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4689                                      RDA_FRM_ECC_SG_ERR |
4690                                      RDA_MISC_ERR |
4691                                      RDA_PCIX_ERR,
4692                                      &bar0->rda_err_reg,
4693                                      &sw_stat->rda_err_cnt);
4694        }
4695
4696        if (val64 & RXDMA_INT_RTI_INT_M) {
4697                if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4698                                          &bar0->rti_err_reg,
4699                                          &sw_stat->rti_err_cnt))
4700                        goto reset;
4701                do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4702                                      &bar0->rti_err_reg,
4703                                      &sw_stat->rti_err_cnt);
4704        }
4705
4706        val64 = readq(&bar0->mac_int_status);
4707        if (val64 & MAC_INT_STATUS_RMAC_INT) {
4708                if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4709                                          &bar0->mac_rmac_err_reg,
4710                                          &sw_stat->mac_rmac_err_cnt))
4711                        goto reset;
4712                do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4713                                      RMAC_SINGLE_ECC_ERR |
4714                                      RMAC_DOUBLE_ECC_ERR,
4715                                      &bar0->mac_rmac_err_reg,
4716                                      &sw_stat->mac_rmac_err_cnt);
4717        }
4718
4719        val64 = readq(&bar0->xgxs_int_status);
4720        if (val64 & XGXS_INT_STATUS_RXGXS) {
4721                if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4722                                          &bar0->xgxs_rxgxs_err_reg,
4723                                          &sw_stat->xgxs_rxgxs_err_cnt))
4724                        goto reset;
4725        }
4726
4727        val64 = readq(&bar0->mc_int_status);
4728        if (val64 & MC_INT_STATUS_MC_INT) {
4729                if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4730                                          &bar0->mc_err_reg,
4731                                          &sw_stat->mc_err_cnt))
4732                        goto reset;
4733
4734                /* Handling Ecc errors */
4735                if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4736                        writeq(val64, &bar0->mc_err_reg);
4737                        if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4738                                sw_stat->double_ecc_errs++;
4739                                if (sp->device_type != XFRAME_II_DEVICE) {
4740                                        /*
4741                                         * Reset XframeI only if critical error
4742                                         */
4743                                        if (val64 &
4744                                            (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4745                                             MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4746                                                goto reset;
4747                                }
4748                        } else
4749                                sw_stat->single_ecc_errs++;
4750                }
4751        }
4752        return;
4753
4754reset:
4755        s2io_stop_all_tx_queue(sp);
4756        schedule_work(&sp->rst_timer_task);
4757        sw_stat->soft_reset_cnt++;
4758        return;
4759}
4760
4761/**
4762 *  s2io_isr - ISR handler of the device .
4763 *  @irq: the irq of the device.
4764 *  @dev_id: a void pointer to the dev structure of the NIC.
4765 *  Description:  This function is the ISR handler of the device. It
4766 *  identifies the reason for the interrupt and calls the relevant
4767 *  service routines. As a contongency measure, this ISR allocates the
4768 *  recv buffers, if their numbers are below the panic value which is
4769 *  presently set to 25% of the original number of rcv buffers allocated.
4770 *  Return value:
4771 *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4772 *   IRQ_NONE: will be returned if interrupt is not from our device
4773 */
4774static irqreturn_t s2io_isr(int irq, void *dev_id)
4775{
4776        struct net_device *dev = (struct net_device *)dev_id;
4777        struct s2io_nic *sp = netdev_priv(dev);
4778        struct XENA_dev_config __iomem *bar0 = sp->bar0;
4779        int i;
4780        u64 reason = 0;
4781        struct mac_info *mac_control;
4782        struct config_param *config;
4783
4784        /* Pretend we handled any irq's from a disconnected card */
4785        if (pci_channel_offline(sp->pdev))
4786                return IRQ_NONE;
4787
4788        if (!is_s2io_card_up(sp))
4789                return IRQ_NONE;
4790
4791        config = &sp->config;
4792        mac_control = &sp->mac_control;
4793
4794        /*
4795         * Identify the cause for interrupt and call the appropriate
4796         * interrupt handler. Causes for the interrupt could be;
4797         * 1. Rx of packet.
4798         * 2. Tx complete.
4799         * 3. Link down.
4800         */
4801        reason = readq(&bar0->general_int_status);
4802
4803        if (unlikely(reason == S2IO_MINUS_ONE))
4804                return IRQ_HANDLED;     /* Nothing much can be done. Get out */
4805
4806        if (reason &
4807            (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4808                writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4809
4810                if (config->napi) {
4811                        if (reason & GEN_INTR_RXTRAFFIC) {
4812                                napi_schedule(&sp->napi);
4813                                writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4814                                writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4815                                readl(&bar0->rx_traffic_int);
4816                        }
4817                } else {
4818                        /*
4819                         * rx_traffic_int reg is an R1 register, writing all 1's
4820                         * will ensure that the actual interrupt causing bit
4821                         * get's cleared and hence a read can be avoided.
4822                         */
4823                        if (reason & GEN_INTR_RXTRAFFIC)
4824                                writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4825
4826                        for (i = 0; i < config->rx_ring_num; i++) {
4827                                struct ring_info *ring = &mac_control->rings[i];
4828
4829                                rx_intr_handler(ring, 0);
4830                        }
4831                }
4832
4833                /*
4834                 * tx_traffic_int reg is an R1 register, writing all 1's
4835                 * will ensure that the actual interrupt causing bit get's
4836                 * cleared and hence a read can be avoided.
4837                 */
4838                if (reason & GEN_INTR_TXTRAFFIC)
4839                        writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4840
4841                for (i = 0; i < config->tx_fifo_num; i++)
4842                        tx_intr_handler(&mac_control->fifos[i]);
4843
4844                if (reason & GEN_INTR_TXPIC)
4845                        s2io_txpic_intr_handle(sp);
4846
4847                /*
4848                 * Reallocate the buffers from the interrupt handler itself.
4849                 */
4850                if (!config->napi) {
4851                        for (i = 0; i < config->rx_ring_num; i++) {
4852                                struct ring_info *ring = &mac_control->rings[i];
4853
4854                                s2io_chk_rx_buffers(sp, ring);
4855                        }
4856                }
4857                writeq(sp->general_int_mask, &bar0->general_int_mask);
4858                readl(&bar0->general_int_status);
4859
4860                return IRQ_HANDLED;
4861
4862        } else if (!reason) {
4863                /* The interrupt was not raised by us */
4864                return IRQ_NONE;
4865        }
4866
4867        return IRQ_HANDLED;
4868}
4869
4870/**
4871 * s2io_updt_stats -
4872 */
4873static void s2io_updt_stats(struct s2io_nic *sp)
4874{
4875        struct XENA_dev_config __iomem *bar0 = sp->bar0;
4876        u64 val64;
4877        int cnt = 0;
4878
4879        if (is_s2io_card_up(sp)) {
4880                /* Apprx 30us on a 133 MHz bus */
4881                val64 = SET_UPDT_CLICKS(10) |
4882                        STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4883                writeq(val64, &bar0->stat_cfg);
4884                do {
4885                        udelay(100);
4886                        val64 = readq(&bar0->stat_cfg);
4887                        if (!(val64 & s2BIT(0)))
4888                                break;
4889                        cnt++;
4890                        if (cnt == 5)
4891                                break; /* Updt failed */
4892                } while (1);
4893        }
4894}
4895
4896/**
4897 *  s2io_get_stats - Updates the device statistics structure.
4898 *  @dev : pointer to the device structure.
4899 *  Description:
4900 *  This function updates the device statistics structure in the s2io_nic
4901 *  structure and returns a pointer to the same.
4902 *  Return value:
4903 *  pointer to the updated net_device_stats structure.
4904 */
4905
4906static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4907{
4908        struct s2io_nic *sp = netdev_priv(dev);
4909        struct config_param *config = &sp->config;
4910        struct mac_info *mac_control = &sp->mac_control;
4911        struct stat_block *stats = mac_control->stats_info;
4912        int i;
4913
4914        /* Configure Stats for immediate updt */
4915        s2io_updt_stats(sp);
4916
4917        /* Using sp->stats as a staging area, because reset (due to mtu
4918           change, for example) will clear some hardware counters */
4919        dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
4920                sp->stats.tx_packets;
4921        sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4922
4923        dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
4924                sp->stats.tx_errors;
4925        sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4926
4927        dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
4928                sp->stats.rx_errors;
4929        sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4930
4931        dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
4932                sp->stats.multicast;
4933        sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4934
4935        dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
4936                sp->stats.rx_length_errors;
4937        sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
4938
4939        /* collect per-ring rx_packets and rx_bytes */
4940        dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4941        for (i = 0; i < config->rx_ring_num; i++) {
4942                struct ring_info *ring = &mac_control->rings[i];
4943
4944                dev->stats.rx_packets += ring->rx_packets;
4945                dev->stats.rx_bytes += ring->rx_bytes;
4946        }
4947
4948        return &dev->stats;
4949}
4950
4951/**
4952 *  s2io_set_multicast - entry point for multicast address enable/disable.
4953 *  @dev : pointer to the device structure
4954 *  Description:
4955 *  This function is a driver entry point which gets called by the kernel
4956 *  whenever multicast addresses must be enabled/disabled. This also gets
4957 *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4958 *  determine, if multicast address must be enabled or if promiscuous mode
4959 *  is to be disabled etc.
4960 *  Return value:
4961 *  void.
4962 */
4963
4964static void s2io_set_multicast(struct net_device *dev)
4965{
4966        int i, j, prev_cnt;
4967        struct dev_mc_list *mclist;
4968        struct s2io_nic *sp = netdev_priv(dev);
4969        struct XENA_dev_config __iomem *bar0 = sp->bar0;
4970        u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4971                0xfeffffffffffULL;
4972        u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4973        void __iomem *add;
4974        struct config_param *config = &sp->config;
4975
4976        if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4977                /*  Enable all Multicast addresses */
4978                writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4979                       &bar0->rmac_addr_data0_mem);
4980                writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4981                       &bar0->rmac_addr_data1_mem);
4982                val64 = RMAC_ADDR_CMD_MEM_WE |
4983                        RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4984                        RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4985                writeq(val64, &bar0->rmac_addr_cmd_mem);
4986                /* Wait till command completes */
4987                wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4988                                      RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4989                                      S2IO_BIT_RESET);
4990
4991                sp->m_cast_flg = 1;
4992                sp->all_multi_pos = config->max_mc_addr - 1;
4993        } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4994                /*  Disable all Multicast addresses */
4995                writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4996                       &bar0->rmac_addr_data0_mem);
4997                writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4998                       &bar0->rmac_addr_data1_mem);
4999                val64 = RMAC_ADDR_CMD_MEM_WE |
5000                        RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5001                        RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5002                writeq(val64, &bar0->rmac_addr_cmd_mem);
5003                /* Wait till command completes */
5004                wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5005                                      RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5006                                      S2IO_BIT_RESET);
5007
5008                sp->m_cast_flg = 0;
5009                sp->all_multi_pos = 0;
5010        }
5011
5012        if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5013                /*  Put the NIC into promiscuous mode */
5014                add = &bar0->mac_cfg;
5015                val64 = readq(&bar0->mac_cfg);
5016                val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5017
5018                writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5019                writel((u32)val64, add);
5020                writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5021                writel((u32) (val64 >> 32), (add + 4));
5022
5023                if (vlan_tag_strip != 1) {
5024                        val64 = readq(&bar0->rx_pa_cfg);
5025                        val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5026                        writeq(val64, &bar0->rx_pa_cfg);
5027                        sp->vlan_strip_flag = 0;
5028                }
5029
5030                val64 = readq(&bar0->mac_cfg);
5031                sp->promisc_flg = 1;
5032                DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5033                          dev->name);
5034        } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5035                /*  Remove the NIC from promiscuous mode */
5036                add = &bar0->mac_cfg;
5037                val64 = readq(&bar0->mac_cfg);
5038                val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5039
5040                writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5041                writel((u32)val64, add);
5042                writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5043                writel((u32) (val64 >> 32), (add + 4));
5044
5045                if (vlan_tag_strip != 0) {
5046                        val64 = readq(&bar0->rx_pa_cfg);
5047                        val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5048                        writeq(val64, &bar0->rx_pa_cfg);
5049                        sp->vlan_strip_flag = 1;
5050                }
5051
5052                val64 = readq(&bar0->mac_cfg);
5053                sp->promisc_flg = 0;
5054                DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5055        }
5056
5057        /*  Update individual M_CAST address list */
5058        if ((!sp->m_cast_flg) && dev->mc_count) {
5059                if (dev->mc_count >
5060                    (config->max_mc_addr - config->max_mac_addr)) {
5061                        DBG_PRINT(ERR_DBG,
5062                                  "%s: No more Rx filters can be added - "
5063                                  "please enable ALL_MULTI instead\n",
5064                                  dev->name);
5065                        return;
5066                }
5067
5068                prev_cnt = sp->mc_addr_count;
5069                sp->mc_addr_count = dev->mc_count;
5070
5071                /* Clear out the previous list of Mc in the H/W. */
5072                for (i = 0; i < prev_cnt; i++) {
5073                        writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5074                               &bar0->rmac_addr_data0_mem);
5075                        writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5076                               &bar0->rmac_addr_data1_mem);
5077                        val64 = RMAC_ADDR_CMD_MEM_WE |
5078                                RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5079                                RMAC_ADDR_CMD_MEM_OFFSET
5080                                (config->mc_start_offset + i);
5081                        writeq(val64, &bar0->rmac_addr_cmd_mem);
5082
5083                        /* Wait for command completes */
5084                        if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5085                                                  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5086                                                  S2IO_BIT_RESET)) {
5087                                DBG_PRINT(ERR_DBG,
5088                                          "%s: Adding Multicasts failed\n",
5089                                          dev->name);
5090                                return;
5091                        }
5092                }
5093
5094                /* Create the new Rx filter list and update the same in H/W. */
5095                for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5096                     i++, mclist = mclist->next) {
5097                        memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5098                               ETH_ALEN);
5099                        mac_addr = 0;
5100                        for (j = 0; j < ETH_ALEN; j++) {
5101                                mac_addr |= mclist->dmi_addr[j];
5102                                mac_addr <<= 8;
5103                        }
5104                        mac_addr >>= 8;
5105                        writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5106                               &bar0->rmac_addr_data0_mem);
5107                        writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5108                               &bar0->rmac_addr_data1_mem);
5109                        val64 = RMAC_ADDR_CMD_MEM_WE |
5110                                RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5111                                RMAC_ADDR_CMD_MEM_OFFSET
5112                                (i + config->mc_start_offset);
5113                        writeq(val64, &bar0->rmac_addr_cmd_mem);
5114
5115                        /* Wait for command completes */
5116                        if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5117                                                  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5118                                                  S2IO_BIT_RESET)) {
5119                                DBG_PRINT(ERR_DBG,
5120                                          "%s: Adding Multicasts failed\n",
5121                                          dev->name);
5122                                return;
5123                        }
5124                }
5125        }
5126}
5127
5128/* read from CAM unicast & multicast addresses and store it in
5129 * def_mac_addr structure
5130 */
5131static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5132{
5133        int offset;
5134        u64 mac_addr = 0x0;
5135        struct config_param *config = &sp->config;
5136
5137        /* store unicast & multicast mac addresses */
5138        for (offset = 0; offset < config->max_mc_addr; offset++) {
5139                mac_addr = do_s2io_read_unicast_mc(sp, offset);
5140                /* if read fails disable the entry */
5141                if (mac_addr == FAILURE)
5142                        mac_addr = S2IO_DISABLE_MAC_ENTRY;
5143                do_s2io_copy_mac_addr(sp, offset, mac_addr);
5144        }
5145}
5146
5147/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5148static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5149{
5150        int offset;
5151        struct config_param *config = &sp->config;
5152        /* restore unicast mac address */
5153        for (offset = 0; offset < config->max_mac_addr; offset++)
5154                do_s2io_prog_unicast(sp->dev,
5155                                     sp->def_mac_addr[offset].mac_addr);
5156
5157        /* restore multicast mac address */
5158        for (offset = config->mc_start_offset;
5159             offset < config->max_mc_addr; offset++)
5160                do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5161}
5162
5163/* add a multicast MAC address to CAM */
5164static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5165{
5166        int i;
5167        u64 mac_addr = 0;
5168        struct config_param *config = &sp->config;
5169
5170        for (i = 0; i < ETH_ALEN; i++) {
5171                mac_addr <<= 8;
5172                mac_addr |= addr[i];
5173        }
5174        if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5175                return SUCCESS;
5176
5177        /* check if the multicast mac already preset in CAM */
5178        for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5179                u64 tmp64;
5180                tmp64 = do_s2io_read_unicast_mc(sp, i);
5181                if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5182                        break;
5183
5184                if (tmp64 == mac_addr)
5185                        return SUCCESS;
5186        }
5187        if (i == config->max_mc_addr) {
5188                DBG_PRINT(ERR_DBG,
5189                          "CAM full no space left for multicast MAC\n");
5190                return FAILURE;
5191        }
5192        /* Update the internal structure with this new mac address */
5193        do_s2io_copy_mac_addr(sp, i, mac_addr);
5194
5195        return do_s2io_add_mac(sp, mac_addr, i);
5196}
5197
5198/* add MAC address to CAM */
5199static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5200{
5201        u64 val64;
5202        struct XENA_dev_config __iomem *bar0 = sp->bar0;
5203
5204        writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5205               &bar0->rmac_addr_data0_mem);
5206
5207        val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5208                RMAC_ADDR_CMD_MEM_OFFSET(off);
5209        writeq(val64, &bar0->rmac_addr_cmd_mem);
5210
5211        /* Wait till command completes */
5212        if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5213                                  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5214                                  S2IO_BIT_RESET)) {
5215                DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5216                return FAILURE;
5217        }
5218        return SUCCESS;
5219}
5220/* deletes a specified unicast/multicast mac entry from CAM */
5221static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5222{
5223        int offset;
5224        u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5225        struct config_param *config = &sp->config;
5226
5227        for (offset = 1;
5228             offset < config->max_mc_addr; offset++) {
5229                tmp64 = do_s2io_read_unicast_mc(sp, offset);
5230                if (tmp64 == addr) {
5231                        /* disable the entry by writing  0xffffffffffffULL */
5232                        if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5233                                return FAILURE;
5234                        /* store the new mac list from CAM */
5235                        do_s2io_store_unicast_mc(sp);
5236                        return SUCCESS;
5237                }
5238        }
5239        DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5240                  (unsigned long long)addr);
5241        return FAILURE;
5242}
5243
5244/* read mac entries from CAM */
5245static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5246{
5247        u64 tmp64 = 0xffffffffffff0000ULL, val64;
5248        struct XENA_dev_config __iomem *bar0 = sp->bar0;
5249
5250        /* read mac addr */
5251        val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5252                RMAC_ADDR_CMD_MEM_OFFSET(offset);
5253        writeq(val64, &bar0->rmac_addr_cmd_mem);
5254
5255        /* Wait till command completes */
5256        if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5257                                  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5258                                  S2IO_BIT_RESET)) {
5259                DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5260                return FAILURE;
5261        }
5262        tmp64 = readq(&bar0->rmac_addr_data0_mem);
5263
5264        return tmp64 >> 16;
5265}
5266
5267/**
5268 * s2io_set_mac_addr driver entry point
5269 */
5270
5271static int s2io_set_mac_addr(struct net_device *dev, void *p)
5272{
5273        struct sockaddr *addr = p;
5274
5275        if (!is_valid_ether_addr(addr->sa_data))
5276                return -EINVAL;
5277
5278        memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5279
5280        /* store the MAC address in CAM */
5281        return do_s2io_prog_unicast(dev, dev->dev_addr);
5282}
5283/**
5284 *  do_s2io_prog_unicast - Programs the Xframe mac address
5285 *  @dev : pointer to the device structure.
5286 *  @addr: a uchar pointer to the new mac address which is to be set.
5287 *  Description : This procedure will program the Xframe to receive
5288 *  frames with new Mac Address
5289 *  Return value: SUCCESS on success and an appropriate (-)ve integer
5290 *  as defined in errno.h file on failure.
5291 */
5292
5293static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5294{
5295        struct s2io_nic *sp = netdev_priv(dev);
5296        register u64 mac_addr = 0, perm_addr = 0;
5297        int i;
5298        u64 tmp64;
5299        struct config_param *config = &sp->config;
5300
5301        /*
5302         * Set the new MAC address as the new unicast filter and reflect this
5303         * change on the device address registered with the OS. It will be
5304         * at offset 0.
5305         */
5306        for (i = 0; i < ETH_ALEN; i++) {
5307                mac_addr <<= 8;
5308                mac_addr |= addr[i];
5309                perm_addr <<= 8;
5310                perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5311        }
5312
5313        /* check if the dev_addr is different than perm_addr */
5314        if (mac_addr == perm_addr)
5315                return SUCCESS;
5316
5317        /* check if the mac already preset in CAM */
5318        for (i = 1; i < config->max_mac_addr; i++) {
5319                tmp64 = do_s2io_read_unicast_mc(sp, i);
5320                if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5321                        break;
5322
5323                if (tmp64 == mac_addr) {
5324                        DBG_PRINT(INFO_DBG,
5325                                  "MAC addr:0x%llx already present in CAM\n",
5326                                  (unsigned long long)mac_addr);
5327                        return SUCCESS;
5328                }
5329        }
5330        if (i == config->max_mac_addr) {
5331                DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5332                return FAILURE;
5333        }
5334        /* Update the internal structure with this new mac address */
5335        do_s2io_copy_mac_addr(sp, i, mac_addr);
5336
5337        return do_s2io_add_mac(sp, mac_addr, i);
5338}
5339
5340/**
5341 * s2io_ethtool_sset - Sets different link parameters.
5342 * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
5343 * @info: pointer to the structure with parameters given by ethtool to set
5344 * link information.
5345 * Description:
5346 * The function sets different link parameters provided by the user onto
5347 * the NIC.
5348 * Return value:
5349 * 0 on success.
5350 */
5351
5352static int s2io_ethtool_sset(struct net_device *dev,
5353                             struct ethtool_cmd *info)
5354{
5355        struct s2io_nic *sp = netdev_priv(dev);
5356        if ((info->autoneg == AUTONEG_ENABLE) ||
5357            (info->speed != SPEED_10000) ||
5358            (info->duplex != DUPLEX_FULL))
5359                return -EINVAL;
5360        else {
5361                s2io_close(sp->dev);
5362                s2io_open(sp->dev);
5363        }
5364
5365        return 0;
5366}