LXR linux/drivers/net/smc91x.h

   1/*------------------------------------------------------------------------
   2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
   3 .
   4 . Copyright (C) 1996 by Erik Stahlman
   5 . Copyright (C) 2001 Standard Microsystems Corporation
   6 .      Developed by Simple Network Magic Corporation
   7 . Copyright (C) 2003 Monta Vista Software, Inc.
   8 .      Unified SMC91x driver by Nicolas Pitre
   9 .
  10 . This program is free software; you can redistribute it and/or modify
  11 . it under the terms of the GNU General Public License as published by
  12 . the Free Software Foundation; either version 2 of the License, or
  13 . (at your option) any later version.
  14 .
  15 . This program is distributed in the hope that it will be useful,
  16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 . GNU General Public License for more details.
  19 .
  20 . You should have received a copy of the GNU General Public License
  21 . along with this program; if not, write to the Free Software
  22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23 .
  24 . Information contained in this file was obtained from the LAN91C111
  25 . manual from SMC.  To get a copy, if you really want one, you can find
  26 . information under www.smsc.com.
  27 .
  28 . Authors
  29 .      Erik Stahlman           <erik@vt.edu>
  30 .      Daris A Nevil           <dnevil@snmc.com>
  31 .      Nicolas Pitre           <nico@fluxnic.net>
  32 .
  33 ---------------------------------------------------------------------------*/
  34#ifndef _SMC91X_H_
  35#define _SMC91X_H_
  36
  37#include <linux/smc91x.h>
  38
  39/*
  40 * Define your architecture specific bus configuration parameters here.
  41 */
  42
  43#if defined(CONFIG_ARCH_LUBBOCK) ||\
  44    defined(CONFIG_MACH_MAINSTONE) ||\
  45    defined(CONFIG_MACH_ZYLONITE) ||\
  46    defined(CONFIG_MACH_LITTLETON) ||\
  47    defined(CONFIG_MACH_ZYLONITE2) ||\
  48    defined(CONFIG_ARCH_VIPER) ||\
  49    defined(CONFIG_MACH_STARGATE2)
  50
  51#include <asm/mach-types.h>
  52
  53/* Now the bus width is specified in the platform data
  54 * pretend here to support all I/O access types
  55 */
  56#define SMC_CAN_USE_8BIT        1
  57#define SMC_CAN_USE_16BIT       1
  58#define SMC_CAN_USE_32BIT       1
  59#define SMC_NOWAIT              1
  60
  61#define SMC_IO_SHIFT            (lp->io_shift)
  62
  63#define SMC_inb(a, r)           readb((a) + (r))
  64#define SMC_inw(a, r)           readw((a) + (r))
  65#define SMC_inl(a, r)           readl((a) + (r))
  66#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
  67#define SMC_outl(v, a, r)       writel(v, (a) + (r))
  68#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
  69#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
  70#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
  71#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
  72#define SMC_IRQ_FLAGS           (-1)    /* from resource */
  73
  74/* We actually can't write halfwords properly if not word aligned */
  75static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  76{
  77        if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
  78                unsigned int v = val << 16;
  79                v |= readl(ioaddr + (reg & ~2)) & 0xffff;
  80                writel(v, ioaddr + (reg & ~2));
  81        } else {
  82                writew(val, ioaddr + reg);
  83        }
  84}
  85
  86#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
  87
  88/* We can only do 16-bit reads and writes in the static memory space. */
  89#define SMC_CAN_USE_8BIT        0
  90#define SMC_CAN_USE_16BIT       1
  91#define SMC_CAN_USE_32BIT       0
  92#define SMC_NOWAIT              1
  93
  94#define SMC_IO_SHIFT            0
  95
  96#define SMC_inw(a, r)           in_be16((volatile u16 *)((a) + (r)))
  97#define SMC_outw(v, a, r)       out_be16((volatile u16 *)((a) + (r)), v)
  98#define SMC_insw(a, r, p, l)                                            \
  99        do {                                                            \
 100                unsigned long __port = (a) + (r);                       \
 101                u16 *__p = (u16 *)(p);                                  \
 102                int __l = (l);                                          \
 103                insw(__port, __p, __l);                                 \
 104                while (__l > 0) {                                       \
 105                        *__p = swab16(*__p);                            \
 106                        __p++;                                          \
 107                        __l--;                                          \
 108                }                                                       \
 109        } while (0)
 110#define SMC_outsw(a, r, p, l)                                           \
 111        do {                                                            \
 112                unsigned long __port = (a) + (r);                       \
 113                u16 *__p = (u16 *)(p);                                  \
 114                int __l = (l);                                          \
 115                while (__l > 0) {                                       \
 116                        /* Believe it or not, the swab isn't needed. */ \
 117                        outw( /* swab16 */ (*__p++), __port);           \
 118                        __l--;                                          \
 119                }                                                       \
 120        } while (0)
 121#define SMC_IRQ_FLAGS           (0)
 122
 123#elif defined(CONFIG_SA1100_PLEB)
 124/* We can only do 16-bit reads and writes in the static memory space. */
 125#define SMC_CAN_USE_8BIT        1
 126#define SMC_CAN_USE_16BIT       1
 127#define SMC_CAN_USE_32BIT       0
 128#define SMC_IO_SHIFT            0
 129#define SMC_NOWAIT              1
 130
 131#define SMC_inb(a, r)           readb((a) + (r))
 132#define SMC_insb(a, r, p, l)    readsb((a) + (r), p, (l))
 133#define SMC_inw(a, r)           readw((a) + (r))
 134#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 135#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 136#define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, (l))
 137#define SMC_outw(v, a, r)       writew(v, (a) + (r))
 138#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 139
 140#define SMC_IRQ_FLAGS           (-1)
 141
 142#elif defined(CONFIG_SA1100_ASSABET)
 143
 144#include <mach/neponset.h>
 145
 146/* We can only do 8-bit reads and writes in the static memory space. */
 147#define SMC_CAN_USE_8BIT        1
 148#define SMC_CAN_USE_16BIT       0
 149#define SMC_CAN_USE_32BIT       0
 150#define SMC_NOWAIT              1
 151
 152/* The first two address lines aren't connected... */
 153#define SMC_IO_SHIFT            2
 154
 155#define SMC_inb(a, r)           readb((a) + (r))
 156#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 157#define SMC_insb(a, r, p, l)    readsb((a) + (r), p, (l))
 158#define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, (l))
 159#define SMC_IRQ_FLAGS           (-1)    /* from resource */
 160
 161#elif   defined(CONFIG_MACH_LOGICPD_PXA270) \
 162        || defined(CONFIG_MACH_NOMADIK_8815NHK)
 163
 164#define SMC_CAN_USE_8BIT        0
 165#define SMC_CAN_USE_16BIT       1
 166#define SMC_CAN_USE_32BIT       0
 167#define SMC_IO_SHIFT            0
 168#define SMC_NOWAIT              1
 169
 170#define SMC_inw(a, r)           readw((a) + (r))
 171#define SMC_outw(v, a, r)       writew(v, (a) + (r))
 172#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 173#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 174
 175#elif   defined(CONFIG_ARCH_INNOKOM) || \
 176        defined(CONFIG_ARCH_PXA_IDP) || \
 177        defined(CONFIG_ARCH_RAMSES) || \
 178        defined(CONFIG_ARCH_PCM027)
 179
 180#define SMC_CAN_USE_8BIT        1
 181#define SMC_CAN_USE_16BIT       1
 182#define SMC_CAN_USE_32BIT       1
 183#define SMC_IO_SHIFT            0
 184#define SMC_NOWAIT              1
 185#define SMC_USE_PXA_DMA         1
 186
 187#define SMC_inb(a, r)           readb((a) + (r))
 188#define SMC_inw(a, r)           readw((a) + (r))
 189#define SMC_inl(a, r)           readl((a) + (r))
 190#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 191#define SMC_outl(v, a, r)       writel(v, (a) + (r))
 192#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 193#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 194#define SMC_IRQ_FLAGS           (-1)    /* from resource */
 195
 196/* We actually can't write halfwords properly if not word aligned */
 197static inline void
 198SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 199{
 200        if (reg & 2) {
 201                unsigned int v = val << 16;
 202                v |= readl(ioaddr + (reg & ~2)) & 0xffff;
 203                writel(v, ioaddr + (reg & ~2));
 204        } else {
 205                writew(val, ioaddr + reg);
 206        }
 207}
 208
 209#elif   defined(CONFIG_ARCH_OMAP)
 210
 211/* We can only do 16-bit reads and writes in the static memory space. */
 212#define SMC_CAN_USE_8BIT        0
 213#define SMC_CAN_USE_16BIT       1
 214#define SMC_CAN_USE_32BIT       0
 215#define SMC_IO_SHIFT            0
 216#define SMC_NOWAIT              1
 217
 218#define SMC_inw(a, r)           readw((a) + (r))
 219#define SMC_outw(v, a, r)       writew(v, (a) + (r))
 220#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 221#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 222#define SMC_IRQ_FLAGS           (-1)    /* from resource */
 223
 224#elif   defined(CONFIG_SH_SH4202_MICRODEV)
 225
 226#define SMC_CAN_USE_8BIT        0
 227#define SMC_CAN_USE_16BIT       1
 228#define SMC_CAN_USE_32BIT       0
 229
 230#define SMC_inb(a, r)           inb((a) + (r) - 0xa0000000)
 231#define SMC_inw(a, r)           inw((a) + (r) - 0xa0000000)
 232#define SMC_inl(a, r)           inl((a) + (r) - 0xa0000000)
 233#define SMC_outb(v, a, r)       outb(v, (a) + (r) - 0xa0000000)
 234#define SMC_outw(v, a, r)       outw(v, (a) + (r) - 0xa0000000)
 235#define SMC_outl(v, a, r)       outl(v, (a) + (r) - 0xa0000000)
 236#define SMC_insl(a, r, p, l)    insl((a) + (r) - 0xa0000000, p, l)
 237#define SMC_outsl(a, r, p, l)   outsl((a) + (r) - 0xa0000000, p, l)
 238#define SMC_insw(a, r, p, l)    insw((a) + (r) - 0xa0000000, p, l)
 239#define SMC_outsw(a, r, p, l)   outsw((a) + (r) - 0xa0000000, p, l)
 240
 241#define SMC_IRQ_FLAGS           (0)
 242
 243#elif   defined(CONFIG_M32R)
 244
 245#define SMC_CAN_USE_8BIT        0
 246#define SMC_CAN_USE_16BIT       1
 247#define SMC_CAN_USE_32BIT       0
 248
 249#define SMC_inb(a, r)           inb(((u32)a) + (r))
 250#define SMC_inw(a, r)           inw(((u32)a) + (r))
 251#define SMC_outb(v, a, r)       outb(v, ((u32)a) + (r))
 252#define SMC_outw(v, a, r)       outw(v, ((u32)a) + (r))
 253#define SMC_insw(a, r, p, l)    insw(((u32)a) + (r), p, l)
 254#define SMC_outsw(a, r, p, l)   outsw(((u32)a) + (r), p, l)
 255
 256#define SMC_IRQ_FLAGS           (0)
 257
 258#define RPC_LSA_DEFAULT         RPC_LED_TX_RX
 259#define RPC_LSB_DEFAULT         RPC_LED_100_10
 260
 261#elif   defined(CONFIG_MACH_LPD79520) \
 262     || defined(CONFIG_MACH_LPD7A400) \
 263     || defined(CONFIG_MACH_LPD7A404)
 264
 265/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
 266 * way that the CPU handles chip selects and the way that the SMC chip
 267 * expects the chip select to operate.  Refer to
 268 * Documentation/arm/Sharp-LH/IOBarrier for details.  The read from
 269 * IOBARRIER is a byte, in order that we read the least-common
 270 * denominator.  It would be wasteful to read 32 bits from an 8-bit
 271 * accessible region.
 272 *
 273 * There is no explicit protection against interrupts intervening
 274 * between the writew and the IOBARRIER.  In SMC ISR there is a
 275 * preamble that performs an IOBARRIER in the extremely unlikely event
 276 * that the driver interrupts itself between a writew to the chip an
 277 * the IOBARRIER that follows *and* the cache is large enough that the
 278 * first off-chip access while handing the interrupt is to the SMC
 279 * chip.  Other devices in the same address space as the SMC chip must
 280 * be aware of the potential for trouble and perform a similar
 281 * IOBARRIER on entry to their ISR.
 282 */
 283
 284#include <mach/constants.h>     /* IOBARRIER_VIRT */
 285
 286#define SMC_CAN_USE_8BIT        0
 287#define SMC_CAN_USE_16BIT       1
 288#define SMC_CAN_USE_32BIT       0
 289#define SMC_NOWAIT              0
 290#define LPD7X_IOBARRIER         readb (IOBARRIER_VIRT)
 291
 292#define SMC_inw(a,r)\
 293   ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
 294#define SMC_outw(v,a,r)   ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
 295
 296#define SMC_insw                LPD7_SMC_insw
 297static inline void LPD7_SMC_insw (unsigned char* a, int r,
 298                                  unsigned char* p, int l)
 299{
 300        unsigned short* ps = (unsigned short*) p;
 301        while (l-- > 0) {
 302                *ps++ = readw (a + r);
 303                LPD7X_IOBARRIER;
 304        }
 305}
 306
 307#define SMC_outsw               LPD7_SMC_outsw
 308static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 309                                   unsigned char* p, int l)
 310{
 311        unsigned short* ps = (unsigned short*) p;
 312        while (l-- > 0) {
 313                writew (*ps++, a + r);
 314                LPD7X_IOBARRIER;
 315        }
 316}
 317
 318#define SMC_INTERRUPT_PREAMBLE  LPD7X_IOBARRIER
 319
 320#define RPC_LSA_DEFAULT         RPC_LED_TX_RX
 321#define RPC_LSB_DEFAULT         RPC_LED_100_10
 322
 323#elif   defined(CONFIG_ARCH_VERSATILE)
 324
 325#define SMC_CAN_USE_8BIT        1
 326#define SMC_CAN_USE_16BIT       1
 327#define SMC_CAN_USE_32BIT       1
 328#define SMC_NOWAIT              1
 329
 330#define SMC_inb(a, r)           readb((a) + (r))
 331#define SMC_inw(a, r)           readw((a) + (r))
 332#define SMC_inl(a, r)           readl((a) + (r))
 333#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 334#define SMC_outw(v, a, r)       writew(v, (a) + (r))
 335#define SMC_outl(v, a, r)       writel(v, (a) + (r))
 336#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 337#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 338#define SMC_IRQ_FLAGS           (-1)    /* from resource */
 339
 340#elif defined(CONFIG_MN10300)
 341
 342/*
 343 * MN10300/AM33 configuration
 344 */
 345
 346#include <unit/smc91111.h>
 347
 348#else
 349
 350/*
 351 * Default configuration
 352 */
 353
 354#define SMC_CAN_USE_8BIT        1
 355#define SMC_CAN_USE_16BIT       1
 356#define SMC_CAN_USE_32BIT       1
 357#define SMC_NOWAIT              1
 358
 359#define SMC_IO_SHIFT            (lp->io_shift)
 360
 361#define SMC_inb(a, r)           readb((a) + (r))
 362#define SMC_inw(a, r)           readw((a) + (r))
 363#define SMC_inl(a, r)           readl((a) + (r))
 364#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 365#define SMC_outw(v, a, r)       writew(v, (a) + (r))
 366#define SMC_outl(v, a, r)       writel(v, (a) + (r))
 367#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 368#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 369#define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 370#define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 371
 372#define RPC_LSA_DEFAULT         RPC_LED_100_10
 373#define RPC_LSB_DEFAULT         RPC_LED_TX_RX
 374
 375#endif
 376
 377
 378/* store this information for the driver.. */
 379struct smc_local {
 380        /*
 381         * If I have to wait until memory is available to send a
 382         * packet, I will store the skbuff here, until I get the
 383         * desired memory.  Then, I'll send it out and free it.
 384         */
 385        struct sk_buff *pending_tx_skb;
 386        struct tasklet_struct tx_task;
 387
 388        /* version/revision of the SMC91x chip */
 389        int     version;
 390
 391        /* Contains the current active transmission mode */
 392        int     tcr_cur_mode;
 393
 394        /* Contains the current active receive mode */
 395        int     rcr_cur_mode;
 396
 397        /* Contains the current active receive/phy mode */
 398        int     rpc_cur_mode;
 399        int     ctl_rfduplx;
 400        int     ctl_rspeed;
 401
 402        u32     msg_enable;
 403        u32     phy_type;
 404        struct mii_if_info mii;
 405
 406        /* work queue */
 407        struct work_struct phy_configure;
 408        struct net_device *dev;
 409        int     work_pending;
 410
 411        spinlock_t lock;
 412
 413#ifdef CONFIG_ARCH_PXA
 414        /* DMA needs the physical address of the chip */
 415        u_long physaddr;
 416        struct device *device;
 417#endif
 418        void __iomem *base;
 419        void __iomem *datacs;
 420
 421        /* the low address lines on some platforms aren't connected... */
 422        int     io_shift;
 423
 424        struct smc91x_platdata cfg;
 425};
 426
 427#define SMC_8BIT(p)     ((p)->cfg.flags & SMC91X_USE_8BIT)
 428#define SMC_16BIT(p)    ((p)->cfg.flags & SMC91X_USE_16BIT)
 429#define SMC_32BIT(p)    ((p)->cfg.flags & SMC91X_USE_32BIT)
 430
 431#ifdef CONFIG_ARCH_PXA
 432/*
 433 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
 434 * always happening in irq context so no need to worry about races.  TX is
 435 * different and probably not worth it for that reason, and not as critical
 436 * as RX which can overrun memory and lose packets.
 437 */
 438#include <linux/dma-mapping.h>
 439#include <mach/dma.h>
 440
 441#ifdef SMC_insl
 442#undef SMC_insl
 443#define SMC_insl(a, r, p, l) \
 444        smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
 445static inline void
 446smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 447                 u_char *buf, int len)
 448{
 449        u_long physaddr = lp->physaddr;
 450        dma_addr_t dmabuf;
 451
 452        /* fallback if no DMA available */
 453        if (dma == (unsigned char)-1) {
 454                readsl(ioaddr + reg, buf, len);
 455                return;
 456        }
 457
 458        /* 64 bit alignment is required for memory to memory DMA */
 459        if ((long)buf & 4) {
 460                *((u32 *)buf) = SMC_inl(ioaddr, reg);
 461                buf += 4;
 462                len--;
 463        }
 464
 465        len *= 4;
 466        dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
 467        DCSR(dma) = DCSR_NODESC;
 468        DTADR(dma) = dmabuf;
 469        DSADR(dma) = physaddr + reg;
 470        DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 471                     DCMD_WIDTH4 | (DCMD_LENGTH & len));
 472        DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 473        while (!(DCSR(dma) & DCSR_STOPSTATE))
 474                cpu_relax();
 475        DCSR(dma) = 0;
 476        dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 477}
 478#endif
 479
 480#ifdef SMC_insw
 481#undef SMC_insw
 482#define SMC_insw(a, r, p, l) \
 483        smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
 484static inline void
 485smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 486                 u_char *buf, int len)
 487{
 488        u_long physaddr = lp->physaddr;
 489        dma_addr_t dmabuf;
 490
 491        /* fallback if no DMA available */
 492        if (dma == (unsigned char)-1) {
 493                readsw(ioaddr + reg, buf, len);
 494                return;
 495        }
 496
 497        /* 64 bit alignment is required for memory to memory DMA */
 498        while ((long)buf & 6) {
 499                *((u16 *)buf) = SMC_inw(ioaddr, reg);
 500                buf += 2;
 501                len--;
 502        }
 503
 504        len *= 2;
 505        dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
 506        DCSR(dma) = DCSR_NODESC;
 507        DTADR(dma) = dmabuf;
 508        DSADR(dma) = physaddr + reg;
 509        DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 510                     DCMD_WIDTH2 | (DCMD_LENGTH & len));
 511        DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 512        while (!(DCSR(dma) & DCSR_STOPSTATE))
 513                cpu_relax();
 514        DCSR(dma) = 0;
 515        dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 516}
 517#endif
 518
 519static void
 520smc_pxa_dma_irq(int dma, void *dummy)
 521{
 522        DCSR(dma) = 0;
 523}
 524#endif  /* CONFIG_ARCH_PXA */
 525
 526
 527/*
 528 * Everything a particular hardware setup needs should have been defined
 529 * at this point.  Add stubs for the undefined cases, mainly to avoid
 530 * compilation warnings since they'll be optimized away, or to prevent buggy
 531 * use of them.
 532 */
 533
 534#if ! SMC_CAN_USE_32BIT
 535#define SMC_inl(ioaddr, reg)            ({ BUG(); 0; })
 536#define SMC_outl(x, ioaddr, reg)        BUG()
 537#define SMC_insl(a, r, p, l)            BUG()
 538#define SMC_outsl(a, r, p, l)           BUG()
 539#endif
 540
 541#if !defined(SMC_insl) || !defined(SMC_outsl)
 542#define SMC_insl(a, r, p, l)            BUG()
 543#define SMC_outsl(a, r, p, l)           BUG()
 544#endif
 545
 546#if ! SMC_CAN_USE_16BIT
 547
 548/*
 549 * Any 16-bit access is performed with two 8-bit accesses if the hardware
 550 * can't do it directly. Most registers are 16-bit so those are mandatory.
 551 */
 552#define SMC_outw(x, ioaddr, reg)                                        \
 553        do {                                                            \
 554                unsigned int __val16 = (x);                             \
 555                SMC_outb( __val16, ioaddr, reg );                       \
 556                SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
 557        } while (0)
 558#define SMC_inw(ioaddr, reg)                                            \
 559        ({                                                              \
 560                unsigned int __val16;                                   \
 561                __val16 =  SMC_inb( ioaddr, reg );                      \
 562                __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
 563                __val16;                                                \
 564        })
 565
 566#define SMC_insw(a, r, p, l)            BUG()
 567#define SMC_outsw(a, r, p, l)           BUG()
 568
 569#endif
 570
 571#if !defined(SMC_insw) || !defined(SMC_outsw)
 572#define SMC_insw(a, r, p, l)            BUG()
 573#define SMC_outsw(a, r, p, l)           BUG()
 574#endif
 575
 576#if ! SMC_CAN_USE_8BIT
 577#define SMC_inb(ioaddr, reg)            ({ BUG(); 0; })
 578#define SMC_outb(x, ioaddr, reg)        BUG()
 579#define SMC_insb(a, r, p, l)            BUG()
 580#define SMC_outsb(a, r, p, l)           BUG()
 581#endif
 582
 583#if !defined(SMC_insb) || !defined(SMC_outsb)
 584#define SMC_insb(a, r, p, l)            BUG()
 585#define SMC_outsb(a, r, p, l)           BUG()
 586#endif
 587
 588#ifndef SMC_CAN_USE_DATACS
 589#define SMC_CAN_USE_DATACS      0
 590#endif
 591
 592#ifndef SMC_IO_SHIFT
 593#define SMC_IO_SHIFT    0
 594#endif
 595
 596#ifndef SMC_IRQ_FLAGS
 597#define SMC_IRQ_FLAGS           IRQF_TRIGGER_RISING
 598#endif
 599
 600#ifndef SMC_INTERRUPT_PREAMBLE
 601#define SMC_INTERRUPT_PREAMBLE
 602#endif
 603
 604
 605/* Because of bank switching, the LAN91x uses only 16 I/O ports */
 606#define SMC_IO_EXTENT   (16 << SMC_IO_SHIFT)
 607#define SMC_DATA_EXTENT (4)
 608
 609/*
 610 . Bank Select Register:
 611 .
 612 .              yyyy yyyy 0000 00xx
 613 .              xx              = bank number
 614 .              yyyy yyyy       = 0x33, for identification purposes.
 615*/
 616#define BANK_SELECT             (14 << SMC_IO_SHIFT)
 617
 618
 619// Transmit Control Register
 620/* BANK 0  */
 621#define TCR_REG(lp)     SMC_REG(lp, 0x0000, 0)
 622#define TCR_ENABLE      0x0001  // When 1 we can transmit
 623#define TCR_LOOP        0x0002  // Controls output pin LBK
 624#define TCR_FORCOL      0x0004  // When 1 will force a collision
 625#define TCR_PAD_EN      0x0080  // When 1 will pad tx frames < 64 bytes w/0
 626#define TCR_NOCRC       0x0100  // When 1 will not append CRC to tx frames
 627#define TCR_MON_CSN     0x0400  // When 1 tx monitors carrier
 628#define TCR_FDUPLX      0x0800  // When 1 enables full duplex operation
 629#define TCR_STP_SQET    0x1000  // When 1 stops tx if Signal Quality Error
 630#define TCR_EPH_LOOP    0x2000  // When 1 enables EPH block loopback
 631#define TCR_SWFDUP      0x8000  // When 1 enables Switched Full Duplex mode
 632
 633#define TCR_CLEAR       0       /* do NOTHING */
 634/* the default settings for the TCR register : */
 635#define TCR_DEFAULT     (TCR_ENABLE | TCR_PAD_EN)
 636
 637
 638// EPH Status Register
 639/* BANK 0  */
 640#define EPH_STATUS_REG(lp)      SMC_REG(lp, 0x0002, 0)
 641#define ES_TX_SUC       0x0001  // Last TX was successful
 642#define ES_SNGL_COL     0x0002  // Single collision detected for last tx
 643#define ES_MUL_COL      0x0004  // Multiple collisions detected for last tx
 644#define ES_LTX_MULT     0x0008  // Last tx was a multicast
 645#define ES_16COL        0x0010  // 16 Collisions Reached
 646#define ES_SQET         0x0020  // Signal Quality Error Test
 647#define ES_LTXBRD       0x0040  // Last tx was a broadcast
 648#define ES_TXDEFR       0x0080  // Transmit Deferred
 649#define ES_LATCOL       0x0200  // Late collision detected on last tx
 650#define ES_LOSTCARR     0x0400  // Lost Carrier Sense
 651#define ES_EXC_DEF      0x0800  // Excessive Deferral
 652#define ES_CTR_ROL      0x1000  // Counter Roll Over indication
 653#define ES_LINK_OK      0x4000  // Driven by inverted value of nLNK pin
 654#define ES_TXUNRN       0x8000  // Tx Underrun
 655
 656
 657// Receive Control Register
 658/* BANK 0  */
 659#define RCR_REG(lp)             SMC_REG(lp, 0x0004, 0)
 660#define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
 661#define RCR_PRMS        0x0002  // Enable promiscuous mode
 662#define RCR_ALMUL       0x0004  // When set accepts all multicast frames
 663#define RCR_RXEN        0x0100  // IFF this is set, we can receive packets
 664#define RCR_STRIP_CRC   0x0200  // When set strips CRC from rx packets
 665#define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision
 666#define RCR_FILT_CAR    0x0400  // When set filters leading 12 bit s of carrier
 667#define RCR_SOFTRST     0x8000  // resets the chip
 668
 669/* the normal settings for the RCR register : */
 670#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
 671#define RCR_CLEAR       0x0     // set it to a base state
 672
 673
 674// Counter Register
 675/* BANK 0  */
 676#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
 677
 678
 679// Memory Information Register
 680/* BANK 0  */
 681#define MIR_REG(lp)             SMC_REG(lp, 0x0008, 0)
 682
 683
 684// Receive/Phy Control Register
 685/* BANK 0  */
 686#define RPC_REG(lp)             SMC_REG(lp, 0x000A, 0)
 687#define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
 688#define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
 689#define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
 690#define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
 691#define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
 692
 693#ifndef RPC_LSA_DEFAULT
 694#define RPC_LSA_DEFAULT RPC_LED_100
 695#endif
 696#ifndef RPC_LSB_DEFAULT
 697#define RPC_LSB_DEFAULT RPC_LED_FD
 698#endif
 699
 700#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
 701
 702
 703/* Bank 0 0x0C is reserved */
 704
 705// Bank Select Register
 706/* All Banks */
 707#define BSR_REG         0x000E
 708
 709
 710// Configuration Reg
 711/* BANK 1 */
 712#define CONFIG_REG(lp)  SMC_REG(lp, 0x0000,     1)
 713#define CONFIG_EXT_PHY  0x0200  // 1=external MII, 0=internal Phy
 714#define CONFIG_GPCNTRL  0x0400  // Inverse value drives pin nCNTRL
 715#define CONFIG_NO_WAIT  0x1000  // When 1 no extra wait states on ISA bus
 716#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
 717
 718// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
 719#define CONFIG_DEFAULT  (CONFIG_EPH_POWER_EN)
 720
 721
 722// Base Address Register
 723/* BANK 1 */
 724#define BASE_REG(lp)    SMC_REG(lp, 0x0002, 1)
 725
 726
 727// Individual Address Registers
 728/* BANK 1 */
 729#define ADDR0_REG(lp)   SMC_REG(lp, 0x0004, 1)
 730#define ADDR1_REG(lp)   SMC_REG(lp, 0x0006, 1)
 731#define ADDR2_REG(lp)   SMC_REG(lp, 0x0008, 1)
 732
 733
 734// General Purpose Register
 735/* BANK 1 */
 736#define GP_REG(lp)              SMC_REG(lp, 0x000A, 1)
 737
 738
 739// Control Register
 740/* BANK 1 */
 741#define CTL_REG(lp)             SMC_REG(lp, 0x000C, 1)
 742#define CTL_RCV_BAD     0x4000 // When 1 bad CRC packets are received
 743#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
 744#define CTL_LE_ENABLE   0x0080 // When 1 enables Link Error interrupt
 745#define CTL_CR_ENABLE   0x0040 // When 1 enables Counter Rollover interrupt
 746#define CTL_TE_ENABLE   0x0020 // When 1 enables Transmit Error interrupt
 747#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
 748#define CTL_RELOAD      0x0002 // When set reads EEPROM into registers
 749#define CTL_STORE       0x0001 // When set stores registers into EEPROM
 750
 751
 752// MMU Command Register
 753/* BANK 2 */
 754#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
 755#define MC_BUSY         1       // When 1 the last release has not completed
 756#define MC_NOP          (0<<5)  // No Op
 757#define MC_ALLOC        (1<<5)  // OR with number of 256 byte packets
 758#define MC_RESET        (2<<5)  // Reset MMU to initial state
 759#define MC_REMOVE       (3<<5)  // Remove the current rx packet
 760#define MC_RELEASE      (4<<5)  // Remove and release the current rx packet
 761#define MC_FREEPKT      (5<<5)  // Release packet in PNR register
 762#define MC_ENQUEUE      (6<<5)  // Enqueue the packet for transmit
 763#define MC_RSTTXFIFO    (7<<5)  // Reset the TX FIFOs
 764
 765
 766// Packet Number Register
 767/* BANK 2 */
 768#define PN_REG(lp)              SMC_REG(lp, 0x0002, 2)
 769
 770
 771// Allocation Result Register
 772/* BANK 2 */
 773#define AR_REG(lp)              SMC_REG(lp, 0x0003, 2)
 774#define AR_FAILED       0x80    // Alocation Failed
 775
 776
 777// TX FIFO Ports Register
 778/* BANK 2 */
 779#define TXFIFO_REG(lp)  SMC_REG(lp, 0x0004, 2)
 780#define TXFIFO_TEMPTY   0x80    // TX FIFO Empty
 781
 782// RX FIFO Ports Register
 783/* BANK 2 */
 784#define RXFIFO_REG(lp)  SMC_REG(lp, 0x0005, 2)
 785#define RXFIFO_REMPTY   0x80    // RX FIFO Empty
 786
 787#define FIFO_REG(lp)    SMC_REG(lp, 0x0004, 2)
 788
 789// Pointer Register
 790/* BANK 2 */
 791#define PTR_REG(lp)             SMC_REG(lp, 0x0006, 2)
 792#define PTR_RCV         0x8000 // 1=Receive area, 0=Transmit area
 793#define PTR_AUTOINC     0x4000 // Auto increment the pointer on each access
 794#define PTR_READ        0x2000 // When 1 the operation is a read
 795
 796
 797// Data Register
 798/* BANK 2 */
 799#define DATA_REG(lp)    SMC_REG(lp, 0x0008, 2)
 800
 801
 802// Interrupt Status/Acknowledge Register
 803/* BANK 2 */
 804#define INT_REG(lp)             SMC_REG(lp, 0x000C, 2)
 805
 806
 807// Interrupt Mask Register
 808/* BANK 2 */
 809#define IM_REG(lp)              SMC_REG(lp, 0x000D, 2)
 810#define IM_MDINT        0x80 // PHY MI Register 18 Interrupt
 811#define IM_ERCV_INT     0x40 // Early Receive Interrupt
 812#define IM_EPH_INT      0x20 // Set by Ethernet Protocol Handler section
 813#define IM_RX_OVRN_INT  0x10 // Set by Receiver Overruns
 814#define IM_ALLOC_INT    0x08 // Set when allocation request is completed
 815#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
 816#define IM_TX_INT       0x02 // Transmit Interrupt
 817#define IM_RCV_INT      0x01 // Receive Interrupt
 818
 819
 820// Multicast Table Registers
 821/* BANK 3 */
 822#define MCAST_REG1(lp)  SMC_REG(lp, 0x0000, 3)
 823#define MCAST_REG2(lp)  SMC_REG(lp, 0x0002, 3)
 824#define MCAST_REG3(lp)  SMC_REG(lp, 0x0004, 3)
 825#define MCAST_REG4(lp)  SMC_REG(lp, 0x0006, 3)
 826
 827
 828// Management Interface Register (MII)
 829/* BANK 3 */
 830#define MII_REG(lp)             SMC_REG(lp, 0x0008, 3)
 831#define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
 832#define MII_MDOE        0x0008 // MII Output Enable
 833#define MII_MCLK        0x0004 // MII Clock, pin MDCLK
 834#define MII_MDI         0x0002 // MII Input, pin MDI
 835#define MII_MDO         0x0001 // MII Output, pin MDO
 836
 837
 838// Revision Register
 839/* BANK 3 */
 840/* ( hi: chip id   low: rev # ) */
 841#define REV_REG(lp)             SMC_REG(lp, 0x000A, 3)
 842
 843
 844// Early RCV Register
 845/* BANK 3 */
 846/* this is NOT on SMC9192 */
 847#define ERCV_REG(lp)    SMC_REG(lp, 0x000C, 3)
 848#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
 849#define ERCV_THRESHOLD  0x001F // ERCV Threshold Mask
 850
 851
 852// External Register
 853/* BANK 7 */
 854#define EXT_REG(lp)             SMC_REG(lp, 0x0000, 7)
 855
 856
 857#define CHIP_9192       3
 858#define CHIP_9194       4
 859#define CHIP_9195       5
 860#define CHIP_9196       6
 861#define CHIP_91100      7
 862#define CHIP_91100FD    8
 863#define CHIP_91111FD    9
 864
 865static const char * chip_ids[ 16 ] =  {
 866        NULL, NULL, NULL,
 867        /* 3 */ "SMC91C90/91C92",
 868        /* 4 */ "SMC91C94",
 869        /* 5 */ "SMC91C95",
 870        /* 6 */ "SMC91C96",
 871        /* 7 */ "SMC91C100",
 872        /* 8 */ "SMC91C100FD",
 873        /* 9 */ "SMC91C11xFD",
 874        NULL, NULL, NULL,
 875        NULL, NULL, NULL};
 876
 877
 878/*
 879 . Receive status bits
 880*/
 881#define RS_ALGNERR      0x8000
 882#define RS_BRODCAST     0x4000
 883#define RS_BADCRC       0x2000
 884#define RS_ODDFRAME     0x1000
 885#define RS_TOOLONG      0x0800
 886#define RS_TOOSHORT     0x0400
 887#define RS_MULTICAST    0x0001
 888#define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
 889
 890
 891/*
 892 * PHY IDs
 893 *  LAN83C183 == LAN91C111 Internal PHY
 894 */
 895#define PHY_LAN83C183   0x0016f840
 896#define PHY_LAN83C180   0x02821c50
 897
 898/*
 899 * PHY Register Addresses (LAN91C111 Internal PHY)
 900 *
 901 * Generic PHY registers can be found in <linux/mii.h>
 902 *
 903 * These phy registers are specific to our on-board phy.
 904 */
 905
 906// PHY Configuration Register 1
 907#define PHY_CFG1_REG            0x10
 908#define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
 909#define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
 910#define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
 911#define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
 912#define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
 913#define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
 914#define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
 915#define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
 916#define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
 917#define PHY_CFG1_TLVL_MASK      0x003C
 918#define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
 919
 920
 921// PHY Configuration Register 2
 922#define PHY_CFG2_REG            0x11
 923#define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
 924#define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
 925#define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
 926#define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
 927
 928// PHY Status Output (and Interrupt status) Register
 929#define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
 930#define PHY_INT_INT             0x8000  // 1=bits have changed since last read
 931#define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
 932#define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
 933#define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
 934#define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
 935#define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
 936#define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
 937#define PHY_INT_JAB             0x0100  // 1=Jabber detected
 938#define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
 939#define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
 940
 941// PHY Interrupt/Status Mask Register
 942#define PHY_MASK_REG            0x13    // Interrupt Mask
 943// Uses the same bit definitions as PHY_INT_REG
 944
 945
 946/*
 947 * SMC91C96 ethernet config and status registers.
 948 * These are in the "attribute" space.
 949 */
 950#define ECOR                    0x8000
 951#define ECOR_RESET              0x80
 952#define ECOR_LEVEL_IRQ          0x40
 953#define ECOR_WR_ATTRIB          0x04
 954#define ECOR_ENABLE             0x01
 955
 956#define ECSR                    0x8002
 957#define ECSR_IOIS8              0x20
 958#define ECSR_PWRDWN             0x04
 959#define ECSR_INT                0x02
 960
 961#define ATTRIB_SIZE             ((64*1024) << SMC_IO_SHIFT)
 962
 963
 964/*
 965 * Macros to abstract register access according to the data bus
 966 * capabilities.  Please use those and not the in/out primitives.
 967 * Note: the following macros do *not* select the bank -- this must
 968 * be done separately as needed in the main code.  The SMC_REG() macro
 969 * only uses the bank argument for debugging purposes (when enabled).
 970 *
 971 * Note: despite inline functions being safer, everything leading to this
 972 * should preferably be macros to let BUG() display the line number in
 973 * the core source code since we're interested in the top call site
 974 * not in any inline function location.
 975 */
 976
 977#if SMC_DEBUG > 0
 978#define SMC_REG(lp, reg, bank)                                  \
 979        ({                                                              \
 980                int __b = SMC_CURRENT_BANK(lp);                 \
 981                if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {       \
 982                        printk( "%s: bank reg screwed (0x%04x)\n",      \
 983                                CARDNAME, __b );                        \
 984                        BUG();                                          \
 985                }                                                       \
 986                reg<<SMC_IO_SHIFT;                                      \
 987        })
 988#else
 989#define SMC_REG(lp, reg, bank)  (reg<<SMC_IO_SHIFT)
 990#endif
 991
 992/*
 993 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
 994 * aligned to a 32 bit boundary.  I tell you that does exist!
 995 * Fortunately the affected register accesses can be easily worked around
 996 * since we can write zeroes to the preceeding 16 bits without adverse
 997 * effects and use a 32-bit access.
 998 *
 999 * Enforce it on any 32-bit capable setup for now.
1000 */

1001#define SMC_MUST_ALIGN_WRITE(lp)        SMC_32BIT(lp)
1002
1003#define SMC_GET_PN(lp)                                          \
1004        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, PN_REG(lp))) \
1005                                : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1006
1007#define SMC_SET_PN(lp, x)                                               \
1008        do {                                                            \
1009                if (SMC_MUST_ALIGN_WRITE(lp))                           \
1010                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));   \
1011                else if (SMC_8BIT(lp))                          \
1012                        SMC_outb(x, ioaddr, PN_REG(lp));                \
1013                else                                                    \
1014                        SMC_outw(x, ioaddr, PN_REG(lp));                \
1015        } while (0)
1016
1017#define SMC_GET_AR(lp)                                          \
1018        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, AR_REG(lp))) \
1019                                : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1020
1021#define SMC_GET_TXFIFO(lp)                                              \
1022        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, TXFIFO_REG(lp)))     \
1023                                : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1024
1025#define SMC_GET_RXFIFO(lp)                                              \
1026        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, RXFIFO_REG(lp)))     \
1027                                : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1028
1029#define SMC_GET_INT(lp)                                         \
1030        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, INT_REG(lp)))        \
1031                                : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1032
1033#define SMC_ACK_INT(lp, x)                                              \
1034        do {                                                            \
1035                if (SMC_8BIT(lp))                                       \
1036                        SMC_outb(x, ioaddr, INT_REG(lp));               \
1037                else {                                                  \
1038                        unsigned long __flags;                          \
1039                        int __mask;                                     \
1040                        local_irq_save(__flags);                        \
1041                        __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1042                        SMC_outw(__mask | (x), ioaddr, INT_REG(lp));    \
1043                        local_irq_restore(__flags);                     \
1044                }                                                       \
1045        } while (0)
1046
1047#define SMC_GET_INT_MASK(lp)                                            \
1048        (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, IM_REG(lp))) \
1049                                : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1050
1051#define SMC_SET_INT_MASK(lp, x)                                 \
1052        do {                                                            \
1053                if (SMC_8BIT(lp))                                       \
1054                        SMC_outb(x, ioaddr, IM_REG(lp));                \
1055                else                                                    \
1056                        SMC_outw((x) << 8, ioaddr, INT_REG(lp));        \
1057        } while (0)
1058
1059#define SMC_CURRENT_BANK(lp)    SMC_inw(ioaddr, BANK_SELECT)
1060
1061#define SMC_SELECT_BANK(lp, x)                                  \
1062        do {                                                            \
1063                if (SMC_MUST_ALIGN_WRITE(lp))                           \
1064                        SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);    \
1065                else                                                    \
1066                        SMC_outw(x, ioaddr, BANK_SELECT);               \
1067        } while (0)
1068
1069#define SMC_GET_BASE(lp)                SMC_inw(ioaddr, BASE_REG(lp))
1070
1071#define SMC_SET_BASE(lp, x)             SMC_outw(x, ioaddr, BASE_REG(lp))
1072
1073#define SMC_GET_CONFIG(lp)      SMC_inw(ioaddr, CONFIG_REG(lp))
1074
1075#define SMC_SET_CONFIG(lp, x)   SMC_outw(x, ioaddr, CONFIG_REG(lp))
1076
1077#define SMC_GET_COUNTER(lp)     SMC_inw(ioaddr, COUNTER_REG(lp))
1078
1079#define SMC_GET_CTL(lp)         SMC_inw(ioaddr, CTL_REG(lp))
1080
1081#define SMC_SET_CTL(lp, x)              SMC_outw(x, ioaddr, CTL_REG(lp))
1082
1083#define SMC_GET_MII(lp)         SMC_inw(ioaddr, MII_REG(lp))
1084
1085#define SMC_GET_GP(lp)          SMC_inw(ioaddr, GP_REG(lp))
1086
1087#define SMC_SET_GP(lp, x)                                               \
1088        do {                                                            \
1089                if (SMC_MUST_ALIGN_WRITE(lp))                           \
1090                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));   \
1091                else                                                    \
1092                        SMC_outw(x, ioaddr, GP_REG(lp));                \
1093        } while (0)
1094
1095#define SMC_SET_MII(lp, x)              SMC_outw(x, ioaddr, MII_REG(lp))
1096
1097#define SMC_GET_MIR(lp)         SMC_inw(ioaddr, MIR_REG(lp))
1098
1099#define SMC_SET_MIR(lp, x)              SMC_outw(x, ioaddr, MIR_REG(lp))
1100
1101#define SMC_GET_MMU_CMD(lp)     SMC_inw(ioaddr, MMU_CMD_REG(lp))
1102
1103#define SMC_SET_MMU_CMD(lp, x)  SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1104
1105#define SMC_GET_FIFO(lp)                SMC_inw(ioaddr, FIFO_REG(lp))
1106
1107#define SMC_GET_PTR(lp)         SMC_inw(ioaddr, PTR_REG(lp))
1108
1109#define SMC_SET_PTR(lp, x)                                              \
1110        do {                                                            \
1111                if (SMC_MUST_ALIGN_WRITE(lp))                           \
1112                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));   \
1113                else                                                    \
1114                        SMC_outw(x, ioaddr, PTR_REG(lp));               \
1115        } while (0)
1116
1117#define SMC_GET_EPH_STATUS(lp)  SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1118
1119#define SMC_GET_RCR(lp)         SMC_inw(ioaddr, RCR_REG(lp))
1120
1121#define SMC_SET_RCR(lp, x)              SMC_outw(x, ioaddr, RCR_REG(lp))
1122
1123#define SMC_GET_REV(lp)         SMC_inw(ioaddr, REV_REG(lp))
1124
1125#define SMC_GET_RPC(lp)         SMC_inw(ioaddr, RPC_REG(lp))
1126
1127#define SMC_SET_RPC(lp, x)                                              \
1128        do {                                                            \
1129                if (SMC_MUST_ALIGN_WRITE(lp))                           \
1130                        SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));   \
1131                else                                                    \
1132                        SMC_outw(x, ioaddr, RPC_REG(lp));               \
1133        } while (0)
1134
1135#define SMC_GET_TCR(lp)         SMC_inw(ioaddr, TCR_REG(lp))
1136
1137#define SMC_SET_TCR(lp, x)              SMC_outw(x, ioaddr, TCR_REG(lp))
1138
1139#ifndef SMC_GET_MAC_ADDR
1140#define SMC_GET_MAC_ADDR(lp, addr)                                      \
1141        do {                                                            \
1142                unsigned int __v;                                       \
1143                __v = SMC_inw(ioaddr, ADDR0_REG(lp));                   \
1144                addr[0] = __v; addr[1] = __v >> 8;                      \
1145                __v = SMC_inw(ioaddr, ADDR1_REG(lp));                   \
1146                addr[2] = __v; addr[3] = __v >> 8;                      \
1147                __v = SMC_inw(ioaddr, ADDR2_REG(lp));                   \
1148                addr[4] = __v; addr[5] = __v >> 8;                      \
1149        } while (0)
1150#endif
1151
1152#define SMC_SET_MAC_ADDR(lp, addr)                                      \
1153        do {                                                            \
1154                SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1155                SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1156                SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1157        } while (0)
1158
1159#define SMC_SET_MCAST(lp, x)                                            \
1160        do {                                                            \
1161                const unsigned char *mt = (x);                          \
1162                SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1163                SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1164                SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1165                SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1166        } while (0)
1167
1168#define SMC_PUT_PKT_HDR(lp, status, length)                             \
1169        do {                                                            \
1170                if (SMC_32BIT(lp))                                      \
1171                        SMC_outl((status) | (length)<<16, ioaddr,       \
1172                                 DATA_REG(lp));                 \
1173                else {                                                  \
1174                        SMC_outw(status, ioaddr, DATA_REG(lp)); \
1175                        SMC_outw(length, ioaddr, DATA_REG(lp)); \
1176                }                                                       \
1177        } while (0)
1178
1179#define SMC_GET_PKT_HDR(lp, status, length)                             \
1180        do {                                                            \
1181                if (SMC_32BIT(lp)) {                            \
1182                        unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1183                        (status) = __val & 0xffff;                      \
1184                        (length) = __val >> 16;                         \
1185                } else {                                                \
1186                        (status) = SMC_inw(ioaddr, DATA_REG(lp));       \
1187                        (length) = SMC_inw(ioaddr, DATA_REG(lp));       \
1188                }                                                       \
1189        } while (0)
1190
1191#define SMC_PUSH_DATA(lp, p, l)                                 \
1192        do {                                                            \
1193                if (SMC_32BIT(lp)) {                            \
1194                        void *__ptr = (p);                              \
1195                        int __len = (l);                                \
1196                        void __iomem *__ioaddr = ioaddr;                \
1197                        if (__len >= 2 && (unsigned long)__ptr & 2) {   \
1198                                __len -= 2;                             \
1199                                SMC_outw(*(u16 *)__ptr, ioaddr,         \
1200                                        DATA_REG(lp));          \
1201                                __ptr += 2;                             \
1202                        }                                               \
1203                        if (SMC_CAN_USE_DATACS && lp->datacs)           \
1204                                __ioaddr = lp->datacs;                  \
1205                        SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1206                        if (__len & 2) {                                \
1207                                __ptr += (__len & ~3);                  \
1208                                SMC_outw(*((u16 *)__ptr), ioaddr,       \
1209                                         DATA_REG(lp));         \
1210                        }                                               \
1211                } else if (SMC_16BIT(lp))                               \
1212                        SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);   \
1213                else if (SMC_8BIT(lp))                          \
1214                        SMC_outsb(ioaddr, DATA_REG(lp), p, l);  \
1215        } while (0)
1216
1217#define SMC_PULL_DATA(lp, p, l)                                 \
1218        do {                                                            \
1219                if (SMC_32BIT(lp)) {                            \
1220                        void *__ptr = (p);                              \
1221                        int __len = (l);                                \
1222                        void __iomem *__ioaddr = ioaddr;                \
1223                        if ((unsigned long)__ptr & 2) {                 \
1224                                /*                                      \
1225                                 * We want 32bit alignment here.        \
1226                                 * Since some buses perform a full      \
1227                                 * 32bit fetch even for 16bit data      \
1228                                 * we can't use SMC_inw() here.         \
1229                                 * Back both source (on-chip) and       \
1230                                 * destination pointers of 2 bytes.     \
1231                                 * This is possible since the call to   \
1232                                 * SMC_GET_PKT_HDR() already advanced   \
1233                                 * the source pointer of 4 bytes, and   \
1234                                 * the skb_reserve(skb, 2) advanced     \
1235                                 * the destination pointer of 2 bytes.  \
1236                                 */                                     \
1237                                __ptr -= 2;                             \
1238                                __len += 2;                             \
1239                                SMC_SET_PTR(lp,                 \
1240                                        2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1241                        }                                               \
1242                        if (SMC_CAN_USE_DATACS && lp->datacs)           \
1243                                __ioaddr = lp->datacs;                  \
1244                        __len += 2;                                     \
1245                        SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1246                } else if (SMC_16BIT(lp))                               \
1247                        SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);    \
1248                else if (SMC_8BIT(lp))                          \
1249                        SMC_insb(ioaddr, DATA_REG(lp), p, l);           \
1250        } while (0)
1251
1252#endif  /* _SMC91X_H_ */
1253