linux/drivers/net/tulip/de4x5.c
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   1/*  de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
   2             ethernet driver for Linux.
   3
   4    Copyright 1994, 1995 Digital Equipment Corporation.
   5
   6    Testing resources for this driver have been made available
   7    in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
   8
   9    The author may be reached at davies@maniac.ultranet.com.
  10
  11    This program is free software; you can redistribute  it and/or modify it
  12    under  the terms of  the GNU General  Public License as published by the
  13    Free Software Foundation;  either version 2 of the  License, or (at your
  14    option) any later version.
  15
  16    THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
  17    WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  18    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  19    NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
  20    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21    NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  22    USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23    ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  24    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25    THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26
  27    You should have received a copy of the  GNU General Public License along
  28    with this program; if not, write  to the Free Software Foundation, Inc.,
  29    675 Mass Ave, Cambridge, MA 02139, USA.
  30
  31    Originally,   this  driver  was    written  for the  Digital   Equipment
  32    Corporation series of EtherWORKS ethernet cards:
  33
  34        DE425 TP/COAX EISA
  35        DE434 TP PCI
  36        DE435 TP/COAX/AUI PCI
  37        DE450 TP/COAX/AUI PCI
  38        DE500 10/100 PCI Fasternet
  39
  40    but it  will  now attempt  to  support all  cards which   conform to the
  41    Digital Semiconductor   SROM   Specification.    The  driver   currently
  42    recognises the following chips:
  43
  44        DC21040  (no SROM)
  45        DC21041[A]
  46        DC21140[A]
  47        DC21142
  48        DC21143
  49
  50    So far the driver is known to work with the following cards:
  51
  52        KINGSTON
  53        Linksys
  54        ZNYX342
  55        SMC8432
  56        SMC9332 (w/new SROM)
  57        ZNYX31[45]
  58        ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
  59
  60    The driver has been tested on a relatively busy network using the DE425,
  61    DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
  62    16M of data to a DECstation 5000/200 as follows:
  63
  64                TCP           UDP
  65             TX     RX     TX     RX
  66    DE425   1030k  997k   1170k  1128k
  67    DE434   1063k  995k   1170k  1125k
  68    DE435   1063k  995k   1170k  1125k
  69    DE500   1063k  998k   1170k  1125k  in 10Mb/s mode
  70
  71    All  values are typical (in   kBytes/sec) from a  sample  of 4 for  each
  72    measurement. Their error is +/-20k on a quiet (private) network and also
  73    depend on what load the CPU has.
  74
  75    =========================================================================
  76    This driver  has been written substantially  from  scratch, although its
  77    inheritance of style and stack interface from 'ewrk3.c' and in turn from
  78    Donald Becker's 'lance.c' should be obvious. With the module autoload of
  79    every  usable DECchip board,  I  pinched Donald's 'next_module' field to
  80    link my modules together.
  81
  82    Upto 15 EISA cards can be supported under this driver, limited primarily
  83    by the available IRQ lines.  I have  checked different configurations of
  84    multiple depca, EtherWORKS 3 cards and de4x5 cards and  have not found a
  85    problem yet (provided you have at least depca.c v0.38) ...
  86
  87    PCI support has been added  to allow the driver  to work with the DE434,
  88    DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
  89    to the differences in the EISA and PCI CSR address offsets from the base
  90    address.
  91
  92    The ability to load this  driver as a loadable  module has been included
  93    and used extensively  during the driver development  (to save those long
  94    reboot sequences).  Loadable module support  under PCI and EISA has been
  95    achieved by letting the driver autoprobe as if it were compiled into the
  96    kernel. Do make sure  you're not sharing  interrupts with anything  that
  97    cannot accommodate  interrupt  sharing!
  98
  99    To utilise this ability, you have to do 8 things:
 100
 101    0) have a copy of the loadable modules code installed on your system.
 102    1) copy de4x5.c from the  /linux/drivers/net directory to your favourite
 103    temporary directory.
 104    2) for fixed  autoprobes (not  recommended),  edit the source code  near
 105    line 5594 to reflect the I/O address  you're using, or assign these when
 106    loading by:
 107
 108                   insmod de4x5 io=0xghh           where g = bus number
 109                                                        hh = device number
 110
 111       NB: autoprobing for modules is now supported by default. You may just
 112           use:
 113
 114                   insmod de4x5
 115
 116           to load all available boards. For a specific board, still use
 117           the 'io=?' above.
 118    3) compile  de4x5.c, but include -DMODULE in  the command line to ensure
 119    that the correct bits are compiled (see end of source code).
 120    4) if you are wanting to add a new  card, goto 5. Otherwise, recompile a
 121    kernel with the de4x5 configuration turned off and reboot.
 122    5) insmod de4x5 [io=0xghh]
 123    6) run the net startup bits for your new eth?? interface(s) manually
 124    (usually /etc/rc.inet[12] at boot time).
 125    7) enjoy!
 126
 127    To unload a module, turn off the associated interface(s)
 128    'ifconfig eth?? down' then 'rmmod de4x5'.
 129
 130    Automedia detection is included so that in  principal you can disconnect
 131    from, e.g.  TP, reconnect  to BNC  and  things will still work  (after a
 132    pause whilst the   driver figures out   where its media went).  My tests
 133    using ping showed that it appears to work....
 134
 135    By  default,  the driver will  now   autodetect any  DECchip based card.
 136    Should you have a need to restrict the driver to DIGITAL only cards, you
 137    can compile with a  DEC_ONLY define, or if  loading as a module, use the
 138    'dec_only=1'  parameter.
 139
 140    I've changed the timing routines to  use the kernel timer and scheduling
 141    functions  so that the  hangs  and other assorted problems that occurred
 142    while autosensing the  media  should be gone.  A  bonus  for the DC21040
 143    auto  media sense algorithm is  that it can now  use one that is more in
 144    line with the  rest (the DC21040  chip doesn't  have a hardware  timer).
 145    The downside is the 1 'jiffies' (10ms) resolution.
 146
 147    IEEE 802.3u MII interface code has  been added in anticipation that some
 148    products may use it in the future.
 149
 150    The SMC9332 card  has a non-compliant SROM  which needs fixing -  I have
 151    patched this  driver to detect it  because the SROM format used complies
 152    to a previous DEC-STD format.
 153
 154    I have removed the buffer copies needed for receive on Intels.  I cannot
 155    remove them for   Alphas since  the  Tulip hardware   only does longword
 156    aligned  DMA transfers  and  the  Alphas get   alignment traps with  non
 157    longword aligned data copies (which makes them really slow). No comment.
 158
 159    I  have added SROM decoding  routines to make this  driver work with any
 160    card that  supports the Digital  Semiconductor SROM spec. This will help
 161    all  cards running the dc2114x  series chips in particular.  Cards using
 162    the dc2104x  chips should run correctly with  the basic  driver.  I'm in
 163    debt to <mjacob@feral.com> for the  testing and feedback that helped get
 164    this feature working.  So far we have  tested KINGSTON, SMC8432, SMC9332
 165    (with the latest SROM complying  with the SROM spec  V3: their first was
 166    broken), ZNYX342  and  LinkSys. ZYNX314 (dual  21041  MAC) and  ZNYX 315
 167    (quad 21041 MAC)  cards also  appear  to work despite their  incorrectly
 168    wired IRQs.
 169
 170    I have added a temporary fix for interrupt problems when some SCSI cards
 171    share the same interrupt as the DECchip based  cards. The problem occurs
 172    because  the SCSI card wants to  grab the interrupt  as a fast interrupt
 173    (runs the   service routine with interrupts turned   off) vs.  this card
 174    which really needs to run the service routine with interrupts turned on.
 175    This driver will  now   add the interrupt service   routine  as  a  fast
 176    interrupt if it   is bounced from the   slow interrupt.  THIS IS NOT   A
 177    RECOMMENDED WAY TO RUN THE DRIVER  and has been done  for a limited time
 178    until  people   sort  out their  compatibility    issues and the  kernel
 179    interrupt  service code  is  fixed.   YOU  SHOULD SEPARATE OUT  THE FAST
 180    INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
 181    run on the same interrupt. PCMCIA/CardBus is another can of worms...
 182
 183    Finally, I think  I have really  fixed  the module  loading problem with
 184    more than one DECchip based  card.  As a  side effect, I don't mess with
 185    the  device structure any  more which means that  if more than 1 card in
 186    2.0.x is    installed (4  in   2.1.x),  the  user   will have   to  edit
 187    linux/drivers/net/Space.c  to make room for  them. Hence, module loading
 188    is  the preferred way to use   this driver, since  it  doesn't have this
 189    limitation.
 190
 191    Where SROM media  detection is used and  full duplex is specified in the
 192    SROM,  the feature is  ignored unless  lp->params.fdx  is set at compile
 193    time  OR during  a   module load  (insmod  de4x5   args='eth??:fdx' [see
 194    below]).  This is because there  is no way  to automatically detect full
 195    duplex   links  except through   autonegotiation.    When I  include the
 196    autonegotiation feature in  the SROM autoconf  code, this detection will
 197    occur automatically for that case.
 198
 199    Command  line arguments are  now  allowed, similar  to passing arguments
 200    through LILO. This will allow a per adapter board  set up of full duplex
 201    and media. The only lexical constraints  are: the board name (dev->name)
 202    appears in the list before its  parameters.  The list of parameters ends
 203    either at the end of the parameter list or with another board name.  The
 204    following parameters are allowed:
 205
 206            fdx        for full duplex
 207            autosense  to set the media/speed; with the following
 208                       sub-parameters:
 209                       TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
 210
 211    Case sensitivity is important  for  the sub-parameters. They *must*   be
 212    upper case. Examples:
 213
 214        insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
 215
 216    For a compiled in driver, at or above line 548, place e.g.
 217        #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
 218
 219    Yes,  I know full duplex isn't  permissible on BNC  or AUI; they're just
 220    examples. By default, full duplex is turned off and  AUTO is the default
 221    autosense setting.  In reality, I expect only  the full duplex option to
 222    be used. Note the use of single quotes in the two examples above and the
 223    lack of commas to separate items. ALSO, you must get the requested media
 224    correct in relation to what the adapter SROM says it has. There's no way
 225    to  determine this in  advance other than by  trial and error and common
 226    sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
 227
 228    Changed the bus probing.  EISA used to be  done first,  followed by PCI.
 229    Most people probably don't even know  what a de425 is today and the EISA
 230    probe has messed  up some SCSI cards  in the past,  so now PCI is always
 231    probed  first  followed by  EISA if  a) the architecture allows EISA and
 232    either  b) there have been no PCI cards detected or  c) an EISA probe is
 233    forced by  the user.  To force  a probe  include  "force_eisa"  in  your
 234    insmod "args" line;  for built-in kernels either change the driver to do
 235    this  automatically  or include  #define DE4X5_FORCE_EISA  on or  before
 236    line 1040 in the driver.
 237
 238    TO DO:
 239    ------
 240
 241    Revision History
 242    ----------------
 243
 244    Version   Date        Description
 245
 246      0.1     17-Nov-94   Initial writing. ALPHA code release.
 247      0.2     13-Jan-95   Added PCI support for DE435's.
 248      0.21    19-Jan-95   Added auto media detection.
 249      0.22    10-Feb-95   Fix interrupt handler call <chris@cosy.sbg.ac.at>.
 250                          Fix recognition bug reported by <bkm@star.rl.ac.uk>.
 251                          Add request/release_region code.
 252                          Add loadable modules support for PCI.
 253                          Clean up loadable modules support.
 254      0.23    28-Feb-95   Added DC21041 and DC21140 support.
 255                          Fix missed frame counter value and initialisation.
 256                          Fixed EISA probe.
 257      0.24    11-Apr-95   Change delay routine to use <linux/udelay>.
 258                          Change TX_BUFFS_AVAIL macro.
 259                          Change media autodetection to allow manual setting.
 260                          Completed DE500 (DC21140) support.
 261      0.241   18-Apr-95   Interim release without DE500 Autosense Algorithm.
 262      0.242   10-May-95   Minor changes.
 263      0.30    12-Jun-95   Timer fix for DC21140.
 264                          Portability changes.
 265                          Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
 266                          Add DE500 semi automatic autosense.
 267                          Add Link Fail interrupt TP failure detection.
 268                          Add timer based link change detection.
 269                          Plugged a memory leak in de4x5_queue_pkt().
 270      0.31    13-Jun-95   Fixed PCI stuff for 1.3.1.
 271      0.32    26-Jun-95   Added verify_area() calls in de4x5_ioctl() from a
 272                          suggestion by <heiko@colossus.escape.de>.
 273      0.33     8-Aug-95   Add shared interrupt support (not released yet).
 274      0.331   21-Aug-95   Fix de4x5_open() with fast CPUs.
 275                          Fix de4x5_interrupt().
 276                          Fix dc21140_autoconf() mess.
 277                          No shared interrupt support.
 278      0.332   11-Sep-95   Added MII management interface routines.
 279      0.40     5-Mar-96   Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
 280                          Add kernel timer code (h/w is too flaky).
 281                          Add MII based PHY autosense.
 282                          Add new multicasting code.
 283                          Add new autosense algorithms for media/mode
 284                          selection using kernel scheduling/timing.
 285                          Re-formatted.
 286                          Made changes suggested by <jeff@router.patch.net>:
 287                            Change driver to detect all DECchip based cards
 288                            with DEC_ONLY restriction a special case.
 289                            Changed driver to autoprobe as a module. No irq
 290                            checking is done now - assume BIOS is good!
 291                          Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
 292      0.41    21-Mar-96   Don't check for get_hw_addr checksum unless DEC card
 293                          only <niles@axp745gsfc.nasa.gov>
 294                          Fix for multiple PCI cards reported by <jos@xos.nl>
 295                          Duh, put the IRQF_SHARED flag into request_interrupt().
 296                          Fix SMC ethernet address in enet_det[].
 297                          Print chip name instead of "UNKNOWN" during boot.
 298      0.42    26-Apr-96   Fix MII write TA bit error.
 299                          Fix bug in dc21040 and dc21041 autosense code.
 300                          Remove buffer copies on receive for Intels.
 301                          Change sk_buff handling during media disconnects to
 302                           eliminate DUP packets.
 303                          Add dynamic TX thresholding.
 304                          Change all chips to use perfect multicast filtering.
 305                          Fix alloc_device() bug <jari@markkus2.fimr.fi>
 306      0.43   21-Jun-96    Fix unconnected media TX retry bug.
 307                          Add Accton to the list of broken cards.
 308                          Fix TX under-run bug for non DC21140 chips.
 309                          Fix boot command probe bug in alloc_device() as
 310                           reported by <koen.gadeyne@barco.com> and
 311                           <orava@nether.tky.hut.fi>.
 312                          Add cache locks to prevent a race condition as
 313                           reported by <csd@microplex.com> and
 314                           <baba@beckman.uiuc.edu>.
 315                          Upgraded alloc_device() code.
 316      0.431  28-Jun-96    Fix potential bug in queue_pkt() from discussion
 317                          with <csd@microplex.com>
 318      0.44   13-Aug-96    Fix RX overflow bug in 2114[023] chips.
 319                          Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
 320                          and <michael@compurex.com>.
 321      0.441   9-Sep-96    Change dc21041_autoconf() to probe quiet BNC media
 322                           with a loopback packet.
 323      0.442   9-Sep-96    Include AUI in dc21041 media printout. Bug reported
 324                           by <bhat@mundook.cs.mu.OZ.AU>
 325      0.45    8-Dec-96    Include endian functions for PPC use, from work
 326                           by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
 327      0.451  28-Dec-96    Added fix to allow autoprobe for modules after
 328                           suggestion from <mjacob@feral.com>.
 329      0.5    30-Jan-97    Added SROM decoding functions.
 330                          Updated debug flags.
 331                          Fix sleep/wakeup calls for PCI cards, bug reported
 332                           by <cross@gweep.lkg.dec.com>.
 333                          Added multi-MAC, one SROM feature from discussion
 334                           with <mjacob@feral.com>.
 335                          Added full module autoprobe capability.
 336                          Added attempt to use an SMC9332 with broken SROM.
 337                          Added fix for ZYNX multi-mac cards that didn't
 338                           get their IRQs wired correctly.
 339      0.51   13-Feb-97    Added endian fixes for the SROM accesses from
 340                           <paubert@iram.es>
 341                          Fix init_connection() to remove extra device reset.
 342                          Fix MAC/PHY reset ordering in dc21140m_autoconf().
 343                          Fix initialisation problem with lp->timeout in
 344                           typeX_infoblock() from <paubert@iram.es>.
 345                          Fix MII PHY reset problem from work done by
 346                           <paubert@iram.es>.
 347      0.52   26-Apr-97    Some changes may not credit the right people -
 348                           a disk crash meant I lost some mail.
 349                          Change RX interrupt routine to drop rather than
 350                           defer packets to avoid hang reported by
 351                           <g.thomas@opengroup.org>.
 352                          Fix srom_exec() to return for COMPACT and type 1
 353                           infoblocks.
 354                          Added DC21142 and DC21143 functions.
 355                          Added byte counters from <phil@tazenda.demon.co.uk>
 356                          Added IRQF_DISABLED temporary fix from
 357                           <mjacob@feral.com>.
 358      0.53   12-Nov-97    Fix the *_probe() to include 'eth??' name during
 359                           module load: bug reported by
 360                           <Piete.Brooks@cl.cam.ac.uk>
 361                          Fix multi-MAC, one SROM, to work with 2114x chips:
 362                           bug reported by <cmetz@inner.net>.
 363                          Make above search independent of BIOS device scan
 364                           direction.
 365                          Completed DC2114[23] autosense functions.
 366      0.531  21-Dec-97    Fix DE500-XA 100Mb/s bug reported by
 367                           <robin@intercore.com
 368                          Fix type1_infoblock() bug introduced in 0.53, from
 369                           problem reports by
 370                           <parmee@postecss.ncrfran.france.ncr.com> and
 371                           <jo@ice.dillingen.baynet.de>.
 372                          Added argument list to set up each board from either
 373                           a module's command line or a compiled in #define.
 374                          Added generic MII PHY functionality to deal with
 375                           newer PHY chips.
 376                          Fix the mess in 2.1.67.
 377      0.532   5-Jan-98    Fix bug in mii_get_phy() reported by
 378                           <redhat@cococo.net>.
 379                          Fix bug in pci_probe() for 64 bit systems reported
 380                           by <belliott@accessone.com>.
 381      0.533   9-Jan-98    Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
 382      0.534  24-Jan-98    Fix last (?) endian bug from <geert@linux-m68k.org>
 383      0.535  21-Feb-98    Fix Ethernet Address PROM reset bug for DC21040.
 384      0.536  21-Mar-98    Change pci_probe() to use the pci_dev structure.
 385                          **Incompatible with 2.0.x from here.**
 386      0.540   5-Jul-98    Atomicize assertion of dev->interrupt for SMP
 387                           from <lma@varesearch.com>
 388                          Add TP, AUI and BNC cases to 21140m_autoconf() for
 389                           case where a 21140 under SROM control uses, e.g. AUI
 390                           from problem report by <delchini@lpnp09.in2p3.fr>
 391                          Add MII parallel detection to 2114x_autoconf() for
 392                           case where no autonegotiation partner exists from
 393                           problem report by <mlapsley@ndirect.co.uk>.
 394                          Add ability to force connection type directly even
 395                           when using SROM control from problem report by
 396                           <earl@exis.net>.
 397                          Updated the PCI interface to conform with the latest
 398                           version. I hope nothing is broken...
 399                          Add TX done interrupt modification from suggestion
 400                           by <Austin.Donnelly@cl.cam.ac.uk>.
 401                          Fix is_anc_capable() bug reported by
 402                           <Austin.Donnelly@cl.cam.ac.uk>.
 403                          Fix type[13]_infoblock() bug: during MII search, PHY
 404                           lp->rst not run because lp->ibn not initialised -
 405                           from report & fix by <paubert@iram.es>.
 406                          Fix probe bug with EISA & PCI cards present from
 407                           report by <eirik@netcom.com>.
 408      0.541  24-Aug-98    Fix compiler problems associated with i386-string
 409                           ops from multiple bug reports and temporary fix
 410                           from <paubert@iram.es>.
 411                          Fix pci_probe() to correctly emulate the old
 412                           pcibios_find_class() function.
 413                          Add an_exception() for old ZYNX346 and fix compile
 414                           warning on PPC & SPARC, from <ecd@skynet.be>.
 415                          Fix lastPCI to correctly work with compiled in
 416                           kernels and modules from bug report by
 417                           <Zlatko.Calusic@CARNet.hr> et al.
 418      0.542  15-Sep-98    Fix dc2114x_autoconf() to stop multiple messages
 419                           when media is unconnected.
 420                          Change dev->interrupt to lp->interrupt to ensure
 421                           alignment for Alpha's and avoid their unaligned
 422                           access traps. This flag is merely for log messages:
 423                           should do something more definitive though...
 424      0.543  30-Dec-98    Add SMP spin locking.
 425      0.544   8-May-99    Fix for buggy SROM in Motorola embedded boards using
 426                           a 21143 by <mmporter@home.com>.
 427                          Change PCI/EISA bus probing order.
 428      0.545  28-Nov-99    Further Moto SROM bug fix from
 429                           <mporter@eng.mcd.mot.com>
 430                          Remove double checking for DEBUG_RX in de4x5_dbg_rx()
 431                           from report by <geert@linux-m68k.org>
 432      0.546  22-Feb-01    Fixes Alpha XP1000 oops.  The srom_search function
 433                           was causing a page fault when initializing the
 434                           variable 'pb', on a non de4x5 PCI device, in this
 435                           case a PCI bridge (DEC chip 21152). The value of
 436                           'pb' is now only initialized if a de4x5 chip is
 437                           present.
 438                           <france@handhelds.org>
 439      0.547  08-Nov-01    Use library crc32 functions by <Matt_Domsch@dell.com>
 440      0.548  30-Aug-03    Big 2.6 cleanup. Ported to PCI/EISA probing and
 441                           generic DMA APIs. Fixed DE425 support on Alpha.
 442                           <maz@wild-wind.fr.eu.org>
 443    =========================================================================
 444*/
 445
 446#include <linux/module.h>
 447#include <linux/kernel.h>
 448#include <linux/string.h>
 449#include <linux/interrupt.h>
 450#include <linux/ptrace.h>
 451#include <linux/errno.h>
 452#include <linux/ioport.h>
 453#include <linux/slab.h>
 454#include <linux/pci.h>
 455#include <linux/eisa.h>
 456#include <linux/delay.h>
 457#include <linux/init.h>
 458#include <linux/spinlock.h>
 459#include <linux/crc32.h>
 460#include <linux/netdevice.h>
 461#include <linux/etherdevice.h>
 462#include <linux/skbuff.h>
 463#include <linux/time.h>
 464#include <linux/types.h>
 465#include <linux/unistd.h>
 466#include <linux/ctype.h>
 467#include <linux/dma-mapping.h>
 468#include <linux/moduleparam.h>
 469#include <linux/bitops.h>
 470
 471#include <asm/io.h>
 472#include <asm/dma.h>
 473#include <asm/byteorder.h>
 474#include <asm/unaligned.h>
 475#include <asm/uaccess.h>
 476#ifdef CONFIG_PPC_PMAC
 477#include <asm/machdep.h>
 478#endif /* CONFIG_PPC_PMAC */
 479
 480#include "de4x5.h"
 481
 482static const char version[] __devinitconst =
 483        KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
 484
 485#define c_char const char
 486
 487/*
 488** MII Information
 489*/
 490struct phy_table {
 491    int reset;              /* Hard reset required?                         */
 492    int id;                 /* IEEE OUI                                     */
 493    int ta;                 /* One cycle TA time - 802.3u is confusing here */
 494    struct {                /* Non autonegotiation (parallel) speed det.    */
 495        int reg;
 496        int mask;
 497        int value;
 498    } spd;
 499};
 500
 501struct mii_phy {
 502    int reset;              /* Hard reset required?                      */
 503    int id;                 /* IEEE OUI                                  */
 504    int ta;                 /* One cycle TA time                         */
 505    struct {                /* Non autonegotiation (parallel) speed det. */
 506        int reg;
 507        int mask;
 508        int value;
 509    } spd;
 510    int addr;               /* MII address for the PHY                   */
 511    u_char  *gep;           /* Start of GEP sequence block in SROM       */
 512    u_char  *rst;           /* Start of reset sequence in SROM           */
 513    u_int mc;               /* Media Capabilities                        */
 514    u_int ana;              /* NWay Advertisement                        */
 515    u_int fdx;              /* Full DupleX capabilities for each media   */
 516    u_int ttm;              /* Transmit Threshold Mode for each media    */
 517    u_int mci;              /* 21142 MII Connector Interrupt info        */
 518};
 519
 520#define DE4X5_MAX_PHY 8     /* Allow upto 8 attached PHY devices per board */
 521
 522struct sia_phy {
 523    u_char mc;              /* Media Code                                */
 524    u_char ext;             /* csr13-15 valid when set                   */
 525    int csr13;              /* SIA Connectivity Register                 */
 526    int csr14;              /* SIA TX/RX Register                        */
 527    int csr15;              /* SIA General Register                      */
 528    int gepc;               /* SIA GEP Control Information               */
 529    int gep;                /* SIA GEP Data                              */
 530};
 531
 532/*
 533** Define the know universe of PHY devices that can be
 534** recognised by this driver.
 535*/
 536static struct phy_table phy_info[] = {
 537    {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}},       /* National TX      */
 538    {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}},       /* Broadcom T4      */
 539    {0, SEEQ_T4    , 1, {0x12, 0x10, 0x10}},       /* SEEQ T4          */
 540    {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}},       /* Cypress T4       */
 541    {0, 0x7810     , 1, {0x14, 0x0800, 0x0800}}    /* Level One LTX970 */
 542};
 543
 544/*
 545** These GENERIC values assumes that the PHY devices follow 802.3u and
 546** allow parallel detection to set the link partner ability register.
 547** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
 548*/
 549#define GENERIC_REG   0x05      /* Autoneg. Link Partner Advertisement Reg. */
 550#define GENERIC_MASK  MII_ANLPA_100M /* All 100Mb/s Technologies            */
 551#define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4       */
 552
 553/*
 554** Define special SROM detection cases
 555*/
 556static c_char enet_det[][ETH_ALEN] = {
 557    {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
 558    {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
 559};
 560
 561#define SMC    1
 562#define ACCTON 2
 563
 564/*
 565** SROM Repair definitions. If a broken SROM is detected a card may
 566** use this information to help figure out what to do. This is a
 567** "stab in the dark" and so far for SMC9332's only.
 568*/
 569static c_char srom_repair_info[][100] = {
 570    {0x00,0x1e,0x00,0x00,0x00,0x08,             /* SMC9332 */
 571     0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
 572     0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
 573     0x00,0x18,}
 574};
 575
 576
 577#ifdef DE4X5_DEBUG
 578static int de4x5_debug = DE4X5_DEBUG;
 579#else
 580/*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
 581static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
 582#endif
 583
 584/*
 585** Allow per adapter set up. For modules this is simply a command line
 586** parameter, e.g.:
 587** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
 588**
 589** For a compiled in driver, place e.g.
 590**     #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
 591** here
 592*/
 593#ifdef DE4X5_PARM
 594static char *args = DE4X5_PARM;
 595#else
 596static char *args;
 597#endif
 598
 599struct parameters {
 600    bool fdx;
 601    int autosense;
 602};
 603
 604#define DE4X5_AUTOSENSE_MS 250      /* msec autosense tick (DE500) */
 605
 606#define DE4X5_NDA 0xffe0            /* No Device (I/O) Address */
 607
 608/*
 609** Ethernet PROM defines
 610*/
 611#define PROBE_LENGTH    32
 612#define ETH_PROM_SIG    0xAA5500FFUL
 613
 614/*
 615** Ethernet Info
 616*/
 617#define PKT_BUF_SZ      1536            /* Buffer size for each Tx/Rx buffer */
 618#define IEEE802_3_SZ    1518            /* Packet + CRC */
 619#define MAX_PKT_SZ      1514            /* Maximum ethernet packet length */
 620#define MAX_DAT_SZ      1500            /* Maximum ethernet data length */
 621#define MIN_DAT_SZ      1               /* Minimum ethernet data length */
 622#define PKT_HDR_LEN     14              /* Addresses and data length info */
 623#define FAKE_FRAME_LEN  (MAX_PKT_SZ + 1)
 624#define QUEUE_PKT_TIMEOUT (3*HZ)        /* 3 second timeout */
 625
 626
 627/*
 628** EISA bus defines
 629*/
 630#define DE4X5_EISA_IO_PORTS   0x0c00    /* I/O port base address, slot 0 */
 631#define DE4X5_EISA_TOTAL_SIZE 0x100     /* I/O address extent */
 632
 633#define EISA_ALLOWED_IRQ_LIST  {5, 9, 10, 11}
 634
 635#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
 636#define DE4X5_NAME_LENGTH 8
 637
 638static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
 639
 640/*
 641** Ethernet PROM defines for DC21040
 642*/
 643#define PROBE_LENGTH    32
 644#define ETH_PROM_SIG    0xAA5500FFUL
 645
 646/*
 647** PCI Bus defines
 648*/
 649#define PCI_MAX_BUS_NUM      8
 650#define DE4X5_PCI_TOTAL_SIZE 0x80       /* I/O address extent */
 651#define DE4X5_CLASS_CODE     0x00020000 /* Network controller, Ethernet */
 652
 653/*
 654** Memory Alignment. Each descriptor is 4 longwords long. To force a
 655** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
 656** DESC_ALIGN. ALIGN aligns the start address of the private memory area
 657** and hence the RX descriptor ring's first entry.
 658*/
 659#define DE4X5_ALIGN4      ((u_long)4 - 1)     /* 1 longword align */
 660#define DE4X5_ALIGN8      ((u_long)8 - 1)     /* 2 longword align */
 661#define DE4X5_ALIGN16     ((u_long)16 - 1)    /* 4 longword align */
 662#define DE4X5_ALIGN32     ((u_long)32 - 1)    /* 8 longword align */
 663#define DE4X5_ALIGN64     ((u_long)64 - 1)    /* 16 longword align */
 664#define DE4X5_ALIGN128    ((u_long)128 - 1)   /* 32 longword align */
 665
 666#define DE4X5_ALIGN         DE4X5_ALIGN32           /* Keep the DC21040 happy... */
 667#define DE4X5_CACHE_ALIGN   CAL_16LONG
 668#define DESC_SKIP_LEN DSL_0             /* Must agree with DESC_ALIGN */
 669/*#define DESC_ALIGN    u32 dummy[4];  / * Must agree with DESC_SKIP_LEN */
 670#define DESC_ALIGN
 671
 672#ifndef DEC_ONLY                        /* See README.de4x5 for using this */
 673static int dec_only;
 674#else
 675static int dec_only = 1;
 676#endif
 677
 678/*
 679** DE4X5 IRQ ENABLE/DISABLE
 680*/
 681#define ENABLE_IRQs { \
 682    imr |= lp->irq_en;\
 683    outl(imr, DE4X5_IMR);               /* Enable the IRQs */\
 684}
 685
 686#define DISABLE_IRQs {\
 687    imr = inl(DE4X5_IMR);\
 688    imr &= ~lp->irq_en;\
 689    outl(imr, DE4X5_IMR);               /* Disable the IRQs */\
 690}
 691
 692#define UNMASK_IRQs {\
 693    imr |= lp->irq_mask;\
 694    outl(imr, DE4X5_IMR);               /* Unmask the IRQs */\
 695}
 696
 697#define MASK_IRQs {\
 698    imr = inl(DE4X5_IMR);\
 699    imr &= ~lp->irq_mask;\
 700    outl(imr, DE4X5_IMR);               /* Mask the IRQs */\
 701}
 702
 703/*
 704** DE4X5 START/STOP
 705*/
 706#define START_DE4X5 {\
 707    omr = inl(DE4X5_OMR);\
 708    omr |= OMR_ST | OMR_SR;\
 709    outl(omr, DE4X5_OMR);               /* Enable the TX and/or RX */\
 710}
 711
 712#define STOP_DE4X5 {\
 713    omr = inl(DE4X5_OMR);\
 714    omr &= ~(OMR_ST|OMR_SR);\
 715    outl(omr, DE4X5_OMR);               /* Disable the TX and/or RX */ \
 716}
 717
 718/*
 719** DE4X5 SIA RESET
 720*/
 721#define RESET_SIA outl(0, DE4X5_SICR);  /* Reset SIA connectivity regs */
 722
 723/*
 724** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
 725*/
 726#define DE4X5_AUTOSENSE_MS  250
 727
 728/*
 729** SROM Structure
 730*/
 731struct de4x5_srom {
 732    char sub_vendor_id[2];
 733    char sub_system_id[2];
 734    char reserved[12];
 735    char id_block_crc;
 736    char reserved2;
 737    char version;
 738    char num_controllers;
 739    char ieee_addr[6];
 740    char info[100];
 741    short chksum;
 742};
 743#define SUB_VENDOR_ID 0x500a
 744
 745/*
 746** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
 747** and have sizes of both a power of 2 and a multiple of 4.
 748** A size of 256 bytes for each buffer could be chosen because over 90% of
 749** all packets in our network are <256 bytes long and 64 longword alignment
 750** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
 751** descriptors are needed for machines with an ALPHA CPU.
 752*/
 753#define NUM_RX_DESC 8                   /* Number of RX descriptors   */
 754#define NUM_TX_DESC 32                  /* Number of TX descriptors   */
 755#define RX_BUFF_SZ  1536                /* Power of 2 for kmalloc and */
 756                                        /* Multiple of 4 for DC21040  */
 757                                        /* Allows 512 byte alignment  */
 758struct de4x5_desc {
 759    volatile __le32 status;
 760    __le32 des1;
 761    __le32 buf;
 762    __le32 next;
 763    DESC_ALIGN
 764};
 765
 766/*
 767** The DE4X5 private structure
 768*/
 769#define DE4X5_PKT_STAT_SZ 16
 770#define DE4X5_PKT_BIN_SZ  128            /* Should be >=100 unless you
 771                                            increase DE4X5_PKT_STAT_SZ */
 772
 773struct pkt_stats {
 774        u_int bins[DE4X5_PKT_STAT_SZ];      /* Private stats counters       */
 775        u_int unicast;
 776        u_int multicast;
 777        u_int broadcast;
 778        u_int excessive_collisions;
 779        u_int tx_underruns;
 780        u_int excessive_underruns;
 781        u_int rx_runt_frames;
 782        u_int rx_collision;
 783        u_int rx_dribble;
 784        u_int rx_overflow;
 785};
 786
 787struct de4x5_private {
 788    char adapter_name[80];                  /* Adapter name                 */
 789    u_long interrupt;                       /* Aligned ISR flag             */
 790    struct de4x5_desc *rx_ring;             /* RX descriptor ring           */
 791    struct de4x5_desc *tx_ring;             /* TX descriptor ring           */
 792    struct sk_buff *tx_skb[NUM_TX_DESC];    /* TX skb for freeing when sent */
 793    struct sk_buff *rx_skb[NUM_RX_DESC];    /* RX skb's                     */
 794    int rx_new, rx_old;                     /* RX descriptor ring pointers  */
 795    int tx_new, tx_old;                     /* TX descriptor ring pointers  */
 796    char setup_frame[SETUP_FRAME_LEN];      /* Holds MCA and PA info.       */
 797    char frame[64];                         /* Min sized packet for loopback*/
 798    spinlock_t lock;                        /* Adapter specific spinlock    */
 799    struct net_device_stats stats;          /* Public stats                 */
 800    struct pkt_stats pktStats;              /* Private stats counters       */
 801    char rxRingSize;
 802    char txRingSize;
 803    int  bus;                               /* EISA or PCI                  */
 804    int  bus_num;                           /* PCI Bus number               */
 805    int  device;                            /* Device number on PCI bus     */
 806    int  state;                             /* Adapter OPENED or CLOSED     */
 807    int  chipset;                           /* DC21040, DC21041 or DC21140  */
 808    s32  irq_mask;                          /* Interrupt Mask (Enable) bits */
 809    s32  irq_en;                            /* Summary interrupt bits       */
 810    int  media;                             /* Media (eg TP), mode (eg 100B)*/
 811    int  c_media;                           /* Remember the last media conn */
 812    bool fdx;                               /* media full duplex flag       */
 813    int  linkOK;                            /* Link is OK                   */
 814    int  autosense;                         /* Allow/disallow autosensing   */
 815    bool tx_enable;                         /* Enable descriptor polling    */
 816    int  setup_f;                           /* Setup frame filtering type   */
 817    int  local_state;                       /* State within a 'media' state */
 818    struct mii_phy phy[DE4X5_MAX_PHY];      /* List of attached PHY devices */
 819    struct sia_phy sia;                     /* SIA PHY Information          */
 820    int  active;                            /* Index to active PHY device   */
 821    int  mii_cnt;                           /* Number of attached PHY's     */
 822    int  timeout;                           /* Scheduling counter           */
 823    struct timer_list timer;                /* Timer info for kernel        */
 824    int tmp;                                /* Temporary global per card    */
 825    struct {
 826        u_long lock;                        /* Lock the cache accesses      */
 827        s32 csr0;                           /* Saved Bus Mode Register      */
 828        s32 csr6;                           /* Saved Operating Mode Reg.    */
 829        s32 csr7;                           /* Saved IRQ Mask Register      */
 830        s32 gep;                            /* Saved General Purpose Reg.   */
 831        s32 gepc;                           /* Control info for GEP         */
 832        s32 csr13;                          /* Saved SIA Connectivity Reg.  */
 833        s32 csr14;                          /* Saved SIA TX/RX Register     */
 834        s32 csr15;                          /* Saved SIA General Register   */
 835        int save_cnt;                       /* Flag if state already saved  */
 836        struct sk_buff_head queue;          /* Save the (re-ordered) skb's  */
 837    } cache;
 838    struct de4x5_srom srom;                 /* A copy of the SROM           */
 839    int cfrv;                               /* Card CFRV copy */
 840    int rx_ovf;                             /* Check for 'RX overflow' tag  */
 841    bool useSROM;                           /* For non-DEC card use SROM    */
 842    bool useMII;                            /* Infoblock using the MII      */
 843    int asBitValid;                         /* Autosense bits in GEP?       */
 844    int asPolarity;                         /* 0 => asserted high           */
 845    int asBit;                              /* Autosense bit number in GEP  */
 846    int defMedium;                          /* SROM default medium          */
 847    int tcount;                             /* Last infoblock number        */
 848    int infoblock_init;                     /* Initialised this infoblock?  */
 849    int infoleaf_offset;                    /* SROM infoleaf for controller */
 850    s32 infoblock_csr6;                     /* csr6 value in SROM infoblock */
 851    int infoblock_media;                    /* infoblock media              */
 852    int (*infoleaf_fn)(struct net_device *);    /* Pointer to infoleaf function */
 853    u_char *rst;                            /* Pointer to Type 5 reset info */
 854    u_char  ibn;                            /* Infoblock number             */
 855    struct parameters params;               /* Command line/ #defined params */
 856    struct device *gendev;                  /* Generic device */
 857    dma_addr_t dma_rings;                   /* DMA handle for rings         */
 858    int dma_size;                           /* Size of the DMA area         */
 859    char *rx_bufs;                          /* rx bufs on alpha, sparc, ... */
 860};
 861
 862/*
 863** To get around certain poxy cards that don't provide an SROM
 864** for the second and more DECchip, I have to key off the first
 865** chip's address. I'll assume there's not a bad SROM iff:
 866**
 867**      o the chipset is the same
 868**      o the bus number is the same and > 0
 869**      o the sum of all the returned hw address bytes is 0 or 0x5fa
 870**
 871** Also have to save the irq for those cards whose hardware designers
 872** can't follow the PCI to PCI Bridge Architecture spec.
 873*/
 874static struct {
 875    int chipset;
 876    int bus;
 877    int irq;
 878    u_char addr[ETH_ALEN];
 879} last = {0,};
 880
 881/*
 882** The transmit ring full condition is described by the tx_old and tx_new
 883** pointers by:
 884**    tx_old            = tx_new    Empty ring
 885**    tx_old            = tx_new+1  Full ring
 886**    tx_old+txRingSize = tx_new+1  Full ring  (wrapped condition)
 887*/
 888#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
 889                        lp->tx_old+lp->txRingSize-lp->tx_new-1:\
 890                        lp->tx_old               -lp->tx_new-1)
 891
 892#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
 893
 894/*
 895** Public Functions
 896*/
 897static int     de4x5_open(struct net_device *dev);
 898static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
 899                                         struct net_device *dev);
 900static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
 901static int     de4x5_close(struct net_device *dev);
 902static struct  net_device_stats *de4x5_get_stats(struct net_device *dev);
 903static void    de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
 904static void    set_multicast_list(struct net_device *dev);
 905static int     de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 906
 907/*
 908** Private functions
 909*/
 910static int     de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
 911static int     de4x5_init(struct net_device *dev);
 912static int     de4x5_sw_reset(struct net_device *dev);
 913static int     de4x5_rx(struct net_device *dev);
 914static int     de4x5_tx(struct net_device *dev);
 915static void    de4x5_ast(struct net_device *dev);
 916static int     de4x5_txur(struct net_device *dev);
 917static int     de4x5_rx_ovfc(struct net_device *dev);
 918
 919static int     autoconf_media(struct net_device *dev);
 920static void    create_packet(struct net_device *dev, char *frame, int len);
 921static void    load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
 922static int     dc21040_autoconf(struct net_device *dev);
 923static int     dc21041_autoconf(struct net_device *dev);
 924static int     dc21140m_autoconf(struct net_device *dev);
 925static int     dc2114x_autoconf(struct net_device *dev);
 926static int     srom_autoconf(struct net_device *dev);
 927static int     de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
 928static int     dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
 929static int     test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
 930static int     test_for_100Mb(struct net_device *dev, int msec);
 931static int     wait_for_link(struct net_device *dev);
 932static int     test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
 933static int     is_spd_100(struct net_device *dev);
 934static int     is_100_up(struct net_device *dev);
 935static int     is_10_up(struct net_device *dev);
 936static int     is_anc_capable(struct net_device *dev);
 937static int     ping_media(struct net_device *dev, int msec);
 938static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
 939static void    de4x5_free_rx_buffs(struct net_device *dev);
 940static void    de4x5_free_tx_buffs(struct net_device *dev);
 941static void    de4x5_save_skbs(struct net_device *dev);
 942static void    de4x5_rst_desc_ring(struct net_device *dev);
 943static void    de4x5_cache_state(struct net_device *dev, int flag);
 944static void    de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
 945static void    de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
 946static struct  sk_buff *de4x5_get_cache(struct net_device *dev);
 947static void    de4x5_setup_intr(struct net_device *dev);
 948static void    de4x5_init_connection(struct net_device *dev);
 949static int     de4x5_reset_phy(struct net_device *dev);
 950static void    reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
 951static int     test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
 952static int     test_tp(struct net_device *dev, s32 msec);
 953static int     EISA_signature(char *name, struct device *device);
 954static int     PCI_signature(char *name, struct de4x5_private *lp);
 955static void    DevicePresent(struct net_device *dev, u_long iobase);
 956static void    enet_addr_rst(u_long aprom_addr);
 957static int     de4x5_bad_srom(struct de4x5_private *lp);
 958static short   srom_rd(u_long address, u_char offset);
 959static void    srom_latch(u_int command, u_long address);
 960static void    srom_command(u_int command, u_long address);
 961static void    srom_address(u_int command, u_long address, u_char offset);
 962static short   srom_data(u_int command, u_long address);
 963/*static void    srom_busy(u_int command, u_long address);*/
 964static void    sendto_srom(u_int command, u_long addr);
 965static int     getfrom_srom(u_long addr);
 966static int     srom_map_media(struct net_device *dev);
 967static int     srom_infoleaf_info(struct net_device *dev);
 968static void    srom_init(struct net_device *dev);
 969static void    srom_exec(struct net_device *dev, u_char *p);
 970static int     mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
 971static void    mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
 972static int     mii_rdata(u_long ioaddr);
 973static void    mii_wdata(int data, int len, u_long ioaddr);
 974static void    mii_ta(u_long rw, u_long ioaddr);
 975static int     mii_swap(int data, int len);
 976static void    mii_address(u_char addr, u_long ioaddr);
 977static void    sendto_mii(u32 command, int data, u_long ioaddr);
 978static int     getfrom_mii(u32 command, u_long ioaddr);
 979static int     mii_get_oui(u_char phyaddr, u_long ioaddr);
 980static int     mii_get_phy(struct net_device *dev);
 981static void    SetMulticastFilter(struct net_device *dev);
 982static int     get_hw_addr(struct net_device *dev);
 983static void    srom_repair(struct net_device *dev, int card);
 984static int     test_bad_enet(struct net_device *dev, int status);
 985static int     an_exception(struct de4x5_private *lp);
 986static char    *build_setup_frame(struct net_device *dev, int mode);
 987static void    disable_ast(struct net_device *dev);
 988static long    de4x5_switch_mac_port(struct net_device *dev);
 989static int     gep_rd(struct net_device *dev);
 990static void    gep_wr(s32 data, struct net_device *dev);
 991static void    yawn(struct net_device *dev, int state);
 992static void    de4x5_parse_params(struct net_device *dev);
 993static void    de4x5_dbg_open(struct net_device *dev);
 994static void    de4x5_dbg_mii(struct net_device *dev, int k);
 995static void    de4x5_dbg_media(struct net_device *dev);
 996static void    de4x5_dbg_srom(struct de4x5_srom *p);
 997static void    de4x5_dbg_rx(struct sk_buff *skb, int len);
 998static int     de4x5_strncmp(char *a, char *b, int n);
 999static int     dc21041_infoleaf(struct net_device *dev);
1000static int     dc21140_infoleaf(struct net_device *dev);
1001static int     dc21142_infoleaf(struct net_device *dev);
1002static int     dc21143_infoleaf(struct net_device *dev);
1003static int     type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1004static int     type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1005static int     type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1006static int     type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1007static int     type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1008static int     type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1009static int     compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1010
1011/*
1012** Note now that module autoprobing is allowed under EISA and PCI. The
1013** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1014** to "do the right thing".
1015*/
1016
1017static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED        */
1018
1019module_param(io, int, 0);
1020module_param(de4x5_debug, int, 0);
1021module_param(dec_only, int, 0);
1022module_param(args, charp, 0);
1023
1024MODULE_PARM_DESC(io, "de4x5 I/O base address");
1025MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1026MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1027MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1028MODULE_LICENSE("GPL");
1029
1030/*
1031** List the SROM infoleaf functions and chipsets
1032*/
1033struct InfoLeaf {
1034    int chipset;
1035    int (*fn)(struct net_device *);
1036};
1037static struct InfoLeaf infoleaf_array[] = {
1038    {DC21041, dc21041_infoleaf},
1039    {DC21140, dc21140_infoleaf},
1040    {DC21142, dc21142_infoleaf},
1041    {DC21143, dc21143_infoleaf}
1042};
1043#define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1044
1045/*
1046** List the SROM info block functions
1047*/
1048static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1049    type0_infoblock,
1050    type1_infoblock,
1051    type2_infoblock,
1052    type3_infoblock,
1053    type4_infoblock,
1054    type5_infoblock,
1055    compact_infoblock
1056};
1057
1058#define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1059
1060/*
1061** Miscellaneous defines...
1062*/
1063#define RESET_DE4X5 {\
1064    int i;\
1065    i=inl(DE4X5_BMR);\
1066    mdelay(1);\
1067    outl(i | BMR_SWR, DE4X5_BMR);\
1068    mdelay(1);\
1069    outl(i, DE4X5_BMR);\
1070    mdelay(1);\
1071    for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1072    mdelay(1);\
1073}
1074
1075#define PHY_HARD_RESET {\
1076    outl(GEP_HRST, DE4X5_GEP);           /* Hard RESET the PHY dev. */\
1077    mdelay(1);                           /* Assert for 1ms */\
1078    outl(0x00, DE4X5_GEP);\
1079    mdelay(2);                           /* Wait for 2ms */\
1080}
1081
1082static const struct net_device_ops de4x5_netdev_ops = {
1083    .ndo_open           = de4x5_open,
1084    .ndo_stop           = de4x5_close,
1085    .ndo_start_xmit     = de4x5_queue_pkt,
1086    .ndo_get_stats      = de4x5_get_stats,
1087    .ndo_set_multicast_list = set_multicast_list,
1088    .ndo_do_ioctl       = de4x5_ioctl,
1089    .ndo_change_mtu     = eth_change_mtu,
1090    .ndo_set_mac_address= eth_mac_addr,
1091    .ndo_validate_addr  = eth_validate_addr,
1092};
1093
1094
1095static int __devinit
1096de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1097{
1098    char name[DE4X5_NAME_LENGTH + 1];
1099    struct de4x5_private *lp = netdev_priv(dev);
1100    struct pci_dev *pdev = NULL;
1101    int i, status=0;
1102
1103    dev_set_drvdata(gendev, dev);
1104
1105    /* Ensure we're not sleeping */
1106    if (lp->bus == EISA) {
1107        outb(WAKEUP, PCI_CFPM);
1108    } else {
1109        pdev = to_pci_dev (gendev);
1110        pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1111    }
1112    mdelay(10);
1113
1114    RESET_DE4X5;
1115
1116    if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1117        return -ENXIO;                       /* Hardware could not reset */
1118    }
1119
1120    /*
1121    ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1122    */
1123    lp->useSROM = false;
1124    if (lp->bus == PCI) {
1125        PCI_signature(name, lp);
1126    } else {
1127        EISA_signature(name, gendev);
1128    }
1129
1130    if (*name == '\0') {                     /* Not found a board signature */
1131        return -ENXIO;
1132    }
1133
1134    dev->base_addr = iobase;
1135    printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1136
1137    status = get_hw_addr(dev);
1138    printk(", h/w address %pM\n", dev->dev_addr);
1139
1140    if (status != 0) {
1141        printk("      which has an Ethernet PROM CRC error.\n");
1142        return -ENXIO;
1143    } else {
1144        skb_queue_head_init(&lp->cache.queue);
1145        lp->cache.gepc = GEP_INIT;
1146        lp->asBit = GEP_SLNK;
1147        lp->asPolarity = GEP_SLNK;
1148        lp->asBitValid = ~0;
1149        lp->timeout = -1;
1150        lp->gendev = gendev;
1151        spin_lock_init(&lp->lock);
1152        init_timer(&lp->timer);
1153        lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1154        lp->timer.data = (unsigned long)dev;
1155        de4x5_parse_params(dev);
1156
1157        /*
1158        ** Choose correct autosensing in case someone messed up
1159        */
1160        lp->autosense = lp->params.autosense;
1161        if (lp->chipset != DC21140) {
1162            if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1163                lp->params.autosense = TP;
1164            }
1165            if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1166                lp->params.autosense = BNC;
1167            }
1168        }
1169        lp->fdx = lp->params.fdx;
1170        sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1171
1172        lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1173#if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1174        lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1175#endif
1176        lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1177                                         &lp->dma_rings, GFP_ATOMIC);
1178        if (lp->rx_ring == NULL) {
1179            return -ENOMEM;
1180        }
1181
1182        lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1183
1184        /*
1185        ** Set up the RX descriptor ring (Intels)
1186        ** Allocate contiguous receive buffers, long word aligned (Alphas)
1187        */
1188#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1189        for (i=0; i<NUM_RX_DESC; i++) {
1190            lp->rx_ring[i].status = 0;
1191            lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1192            lp->rx_ring[i].buf = 0;
1193            lp->rx_ring[i].next = 0;
1194            lp->rx_skb[i] = (struct sk_buff *) 1;     /* Dummy entry */
1195        }
1196
1197#else
1198        {
1199                dma_addr_t dma_rx_bufs;
1200
1201                dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1202                        * sizeof(struct de4x5_desc);
1203                dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1204                lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1205                        + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1206                for (i=0; i<NUM_RX_DESC; i++) {
1207                        lp->rx_ring[i].status = 0;
1208                        lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1209                        lp->rx_ring[i].buf =
1210                                cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1211                        lp->rx_ring[i].next = 0;
1212                        lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1213                }
1214
1215        }
1216#endif
1217
1218        barrier();
1219
1220        lp->rxRingSize = NUM_RX_DESC;
1221        lp->txRingSize = NUM_TX_DESC;
1222
1223        /* Write the end of list marker to the descriptor lists */
1224        lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1225        lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1226
1227        /* Tell the adapter where the TX/RX rings are located. */
1228        outl(lp->dma_rings, DE4X5_RRBA);
1229        outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1230             DE4X5_TRBA);
1231
1232        /* Initialise the IRQ mask and Enable/Disable */
1233        lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1234        lp->irq_en   = IMR_NIM | IMR_AIM;
1235
1236        /* Create a loopback packet frame for later media probing */
1237        create_packet(dev, lp->frame, sizeof(lp->frame));
1238
1239        /* Check if the RX overflow bug needs testing for */
1240        i = lp->cfrv & 0x000000fe;
1241        if ((lp->chipset == DC21140) && (i == 0x20)) {
1242            lp->rx_ovf = 1;
1243        }
1244
1245        /* Initialise the SROM pointers if possible */
1246        if (lp->useSROM) {
1247            lp->state = INITIALISED;
1248            if (srom_infoleaf_info(dev)) {
1249                dma_free_coherent (gendev, lp->dma_size,
1250                               lp->rx_ring, lp->dma_rings);
1251                return -ENXIO;
1252            }
1253            srom_init(dev);
1254        }
1255
1256        lp->state = CLOSED;
1257
1258        /*
1259        ** Check for an MII interface
1260        */
1261        if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1262            mii_get_phy(dev);
1263        }
1264
1265        printk("      and requires IRQ%d (provided by %s).\n", dev->irq,
1266               ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1267    }
1268
1269    if (de4x5_debug & DEBUG_VERSION) {
1270        printk(version);
1271    }
1272
1273    /* The DE4X5-specific entries in the device structure. */
1274    SET_NETDEV_DEV(dev, gendev);
1275    dev->netdev_ops = &de4x5_netdev_ops;
1276    dev->mem_start = 0;
1277
1278    /* Fill in the generic fields of the device structure. */
1279    if ((status = register_netdev (dev))) {
1280            dma_free_coherent (gendev, lp->dma_size,
1281                               lp->rx_ring, lp->dma_rings);
1282            return status;
1283    }
1284
1285    /* Let the adapter sleep to save power */
1286    yawn(dev, SLEEP);
1287
1288    return status;
1289}
1290
1291
1292static int
1293de4x5_open(struct net_device *dev)
1294{
1295    struct de4x5_private *lp = netdev_priv(dev);
1296    u_long iobase = dev->base_addr;
1297    int i, status = 0;
1298    s32 omr;
1299
1300    /* Allocate the RX buffers */
1301    for (i=0; i<lp->rxRingSize; i++) {
1302        if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1303            de4x5_free_rx_buffs(dev);
1304            return -EAGAIN;
1305        }
1306    }
1307
1308    /*
1309    ** Wake up the adapter
1310    */
1311    yawn(dev, WAKEUP);
1312
1313    /*
1314    ** Re-initialize the DE4X5...
1315    */
1316    status = de4x5_init(dev);
1317    spin_lock_init(&lp->lock);
1318    lp->state = OPEN;
1319    de4x5_dbg_open(dev);
1320
1321    if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1322                                                     lp->adapter_name, dev)) {
1323        printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1324        if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1325                                                     lp->adapter_name, dev)) {
1326            printk("\n              Cannot get IRQ- reconfigure your hardware.\n");
1327            disable_ast(dev);
1328            de4x5_free_rx_buffs(dev);
1329            de4x5_free_tx_buffs(dev);
1330            yawn(dev, SLEEP);
1331            lp->state = CLOSED;
1332            return -EAGAIN;
1333        } else {
1334            printk("\n              Succeeded, but you should reconfigure your hardware to avoid this.\n");
1335            printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1336        }
1337    }
1338
1339    lp->interrupt = UNMASK_INTERRUPTS;
1340    dev->trans_start = jiffies;
1341
1342    START_DE4X5;
1343
1344    de4x5_setup_intr(dev);
1345
1346    if (de4x5_debug & DEBUG_OPEN) {
1347        printk("\tsts:  0x%08x\n", inl(DE4X5_STS));
1348        printk("\tbmr:  0x%08x\n", inl(DE4X5_BMR));
1349        printk("\timr:  0x%08x\n", inl(DE4X5_IMR));
1350        printk("\tomr:  0x%08x\n", inl(DE4X5_OMR));
1351        printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1352        printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1353        printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1354        printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1355    }
1356
1357    return status;
1358}
1359
1360/*
1361** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1362** DC21140 requires using perfect filtering mode for that chip. Since I can't
1363** see why I'd want > 14 multicast addresses, I have changed all chips to use
1364** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1365** to be data corruption problems if it is larger (UDP errors seen from a
1366** ttcp source).
1367*/
1368static int
1369de4x5_init(struct net_device *dev)
1370{
1371    /* Lock out other processes whilst setting up the hardware */
1372    netif_stop_queue(dev);
1373
1374    de4x5_sw_reset(dev);
1375
1376    /* Autoconfigure the connected port */
1377    autoconf_media(dev);
1378
1379    return 0;
1380}
1381
1382static int
1383de4x5_sw_reset(struct net_device *dev)
1384{
1385    struct de4x5_private *lp = netdev_priv(dev);
1386    u_long iobase = dev->base_addr;
1387    int i, j, status = 0;
1388    s32 bmr, omr;
1389
1390    /* Select the MII or SRL port now and RESET the MAC */
1391    if (!lp->useSROM) {
1392        if (lp->phy[lp->active].id != 0) {
1393            lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1394        } else {
1395            lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1396        }
1397        de4x5_switch_mac_port(dev);
1398    }
1399
1400    /*
1401    ** Set the programmable burst length to 8 longwords for all the DC21140
1402    ** Fasternet chips and 4 longwords for all others: DMA errors result
1403    ** without these values. Cache align 16 long.
1404    */
1405    bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1406    bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1407    outl(bmr, DE4X5_BMR);
1408
1409    omr = inl(DE4X5_OMR) & ~OMR_PR;             /* Turn off promiscuous mode */
1410    if (lp->chipset == DC21140) {
1411        omr |= (OMR_SDP | OMR_SB);
1412    }
1413    lp->setup_f = PERFECT;
1414    outl(lp->dma_rings, DE4X5_RRBA);
1415    outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1416         DE4X5_TRBA);
1417
1418    lp->rx_new = lp->rx_old = 0;
1419    lp->tx_new = lp->tx_old = 0;
1420
1421    for (i = 0; i < lp->rxRingSize; i++) {
1422        lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1423    }
1424
1425    for (i = 0; i < lp->txRingSize; i++) {
1426        lp->tx_ring[i].status = cpu_to_le32(0);
1427    }
1428
1429    barrier();
1430
1431    /* Build the setup frame depending on filtering mode */
1432    SetMulticastFilter(dev);
1433
1434    load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1435    outl(omr|OMR_ST, DE4X5_OMR);
1436
1437    /* Poll for setup frame completion (adapter interrupts are disabled now) */
1438
1439    for (j=0, i=0;(i<500) && (j==0);i++) {       /* Upto 500ms delay */
1440        mdelay(1);
1441        if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1442    }
1443    outl(omr, DE4X5_OMR);                        /* Stop everything! */
1444
1445    if (j == 0) {
1446        printk("%s: Setup frame timed out, status %08x\n", dev->name,
1447               inl(DE4X5_STS));
1448        status = -EIO;
1449    }
1450
1451    lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1452    lp->tx_old = lp->tx_new;
1453
1454    return status;
1455}
1456
1457/*
1458** Writes a socket buffer address to the next available transmit descriptor.
1459*/
1460static netdev_tx_t
1461de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1462{
1463    struct de4x5_private *lp = netdev_priv(dev);
1464    u_long iobase = dev->base_addr;
1465    u_long flags = 0;
1466
1467    netif_stop_queue(dev);
1468    if (!lp->tx_enable)                   /* Cannot send for now */
1469        return NETDEV_TX_LOCKED;
1470
1471    /*
1472    ** Clean out the TX ring asynchronously to interrupts - sometimes the
1473    ** interrupts are lost by delayed descriptor status updates relative to
1474    ** the irq assertion, especially with a busy PCI bus.
1475    */
1476    spin_lock_irqsave(&lp->lock, flags);
1477    de4x5_tx(dev);
1478    spin_unlock_irqrestore(&lp->lock, flags);
1479
1480    /* Test if cache is already locked - requeue skb if so */
1481    if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1482        return NETDEV_TX_LOCKED;
1483
1484    /* Transmit descriptor ring full or stale skb */
1485    if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1486        if (lp->interrupt) {
1487            de4x5_putb_cache(dev, skb);          /* Requeue the buffer */
1488        } else {
1489            de4x5_put_cache(dev, skb);
1490        }
1491        if (de4x5_debug & DEBUG_TX) {
1492            printk("%s: transmit busy, lost media or stale skb found:\n  STS:%08x\n  tbusy:%d\n  IMR:%08x\n  OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1493        }
1494    } else if (skb->len > 0) {
1495        /* If we already have stuff queued locally, use that first */
1496        if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1497            de4x5_put_cache(dev, skb);
1498            skb = de4x5_get_cache(dev);
1499        }
1500
1501        while (skb && !netif_queue_stopped(dev) &&
1502               (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1503            spin_lock_irqsave(&lp->lock, flags);
1504            netif_stop_queue(dev);
1505            load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1506            lp->stats.tx_bytes += skb->len;
1507            outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1508
1509            lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1510            dev->trans_start = jiffies;
1511
1512            if (TX_BUFFS_AVAIL) {
1513                netif_start_queue(dev);         /* Another pkt may be queued */
1514            }
1515            skb = de4x5_get_cache(dev);
1516            spin_unlock_irqrestore(&lp->lock, flags);
1517        }
1518        if (skb) de4x5_putb_cache(dev, skb);
1519    }
1520
1521    lp->cache.lock = 0;
1522
1523    return NETDEV_TX_OK;
1524}
1525
1526/*
1527** The DE4X5 interrupt handler.
1528**
1529** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1530** so that the asserted interrupt always has some real data to work with -
1531** if these I/O accesses are ever changed to memory accesses, ensure the
1532** STS write is read immediately to complete the transaction if the adapter
1533** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1534** is high and descriptor status bits cannot be set before the associated
1535** interrupt is asserted and this routine entered.
1536*/
1537static irqreturn_t
1538de4x5_interrupt(int irq, void *dev_id)
1539{
1540    struct net_device *dev = dev_id;
1541    struct de4x5_private *lp;
1542    s32 imr, omr, sts, limit;
1543    u_long iobase;
1544    unsigned int handled = 0;
1545
1546    lp = netdev_priv(dev);
1547    spin_lock(&lp->lock);
1548    iobase = dev->base_addr;
1549
1550    DISABLE_IRQs;                        /* Ensure non re-entrancy */
1551
1552    if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1553        printk("%s: Re-entering the interrupt handler.\n", dev->name);
1554
1555    synchronize_irq(dev->irq);
1556
1557    for (limit=0; limit<8; limit++) {
1558        sts = inl(DE4X5_STS);            /* Read IRQ status */
1559        outl(sts, DE4X5_STS);            /* Reset the board interrupts */
1560
1561        if (!(sts & lp->irq_mask)) break;/* All done */
1562        handled = 1;
1563
1564        if (sts & (STS_RI | STS_RU))     /* Rx interrupt (packet[s] arrived) */
1565          de4x5_rx(dev);
1566
1567        if (sts & (STS_TI | STS_TU))     /* Tx interrupt (packet sent) */
1568          de4x5_tx(dev);
1569
1570        if (sts & STS_LNF) {             /* TP Link has failed */
1571            lp->irq_mask &= ~IMR_LFM;
1572        }
1573
1574        if (sts & STS_UNF) {             /* Transmit underrun */
1575            de4x5_txur(dev);
1576        }
1577
1578        if (sts & STS_SE) {              /* Bus Error */
1579            STOP_DE4X5;
1580            printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1581                   dev->name, sts);
1582            spin_unlock(&lp->lock);
1583            return IRQ_HANDLED;
1584        }
1585    }
1586
1587    /* Load the TX ring with any locally stored packets */
1588    if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1589        while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1590            de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1591        }
1592        lp->cache.lock = 0;
1593    }
1594
1595    lp->interrupt = UNMASK_INTERRUPTS;
1596    ENABLE_IRQs;
1597    spin_unlock(&lp->lock);
1598
1599    return IRQ_RETVAL(handled);
1600}
1601
1602static int
1603de4x5_rx(struct net_device *dev)
1604{
1605    struct de4x5_private *lp = netdev_priv(dev);
1606    u_long iobase = dev->base_addr;
1607    int entry;
1608    s32 status;
1609
1610    for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1611                                                            entry=lp->rx_new) {
1612        status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1613
1614        if (lp->rx_ovf) {
1615            if (inl(DE4X5_MFC) & MFC_FOCM) {
1616                de4x5_rx_ovfc(dev);
1617                break;
1618            }
1619        }
1620
1621        if (status & RD_FS) {                 /* Remember the start of frame */
1622            lp->rx_old = entry;
1623        }
1624
1625        if (status & RD_LS) {                 /* Valid frame status */
1626            if (lp->tx_enable) lp->linkOK++;
1627            if (status & RD_ES) {             /* There was an error. */
1628                lp->stats.rx_errors++;        /* Update the error stats. */
1629                if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1630                if (status & RD_CE)           lp->stats.rx_crc_errors++;
1631                if (status & RD_OF)           lp->stats.rx_fifo_errors++;
1632                if (status & RD_TL)           lp->stats.rx_length_errors++;
1633                if (status & RD_RF)           lp->pktStats.rx_runt_frames++;
1634                if (status & RD_CS)           lp->pktStats.rx_collision++;
1635                if (status & RD_DB)           lp->pktStats.rx_dribble++;
1636                if (status & RD_OF)           lp->pktStats.rx_overflow++;
1637            } else {                          /* A valid frame received */
1638                struct sk_buff *skb;
1639                short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1640                                                                    >> 16) - 4;
1641
1642                if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1643                    printk("%s: Insufficient memory; nuking packet.\n",
1644                                                                    dev->name);
1645                    lp->stats.rx_dropped++;
1646                } else {
1647                    de4x5_dbg_rx(skb, pkt_len);
1648
1649                    /* Push up the protocol stack */
1650                    skb->protocol=eth_type_trans(skb,dev);
1651                    de4x5_local_stats(dev, skb->data, pkt_len);
1652                    netif_rx(skb);
1653
1654                    /* Update stats */
1655                    lp->stats.rx_packets++;
1656                    lp->stats.rx_bytes += pkt_len;
1657                }
1658            }
1659
1660            /* Change buffer ownership for this frame, back to the adapter */
1661            for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1662                lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1663                barrier();
1664            }
1665            lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1666            barrier();
1667        }
1668
1669        /*
1670        ** Update entry information
1671        */
1672        lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1673    }
1674
1675    return 0;
1676}
1677
1678static inline void
1679de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1680{
1681    dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1682                     le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1683                     DMA_TO_DEVICE);
1684    if ((u_long) lp->tx_skb[entry] > 1)
1685        dev_kfree_skb_irq(lp->tx_skb[entry]);
1686    lp->tx_skb[entry] = NULL;
1687}
1688
1689/*
1690** Buffer sent - check for TX buffer errors.
1691*/
1692static int
1693de4x5_tx(struct net_device *dev)
1694{
1695    struct de4x5_private *lp = netdev_priv(dev);
1696    u_long iobase = dev->base_addr;
1697    int entry;
1698    s32 status;
1699
1700    for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1701        status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1702        if (status < 0) {                     /* Buffer not sent yet */
1703            break;
1704        } else if (status != 0x7fffffff) {    /* Not setup frame */
1705            if (status & TD_ES) {             /* An error happened */
1706                lp->stats.tx_errors++;
1707                if (status & TD_NC) lp->stats.tx_carrier_errors++;
1708                if (status & TD_LC) lp->stats.tx_window_errors++;
1709                if (status & TD_UF) lp->stats.tx_fifo_errors++;
1710                if (status & TD_EC) lp->pktStats.excessive_collisions++;
1711                if (status & TD_DE) lp->stats.tx_aborted_errors++;
1712
1713                if (TX_PKT_PENDING) {
1714                    outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1715                }
1716            } else {                      /* Packet sent */
1717                lp->stats.tx_packets++;
1718                if (lp->tx_enable) lp->linkOK++;
1719            }
1720            /* Update the collision counter */
1721            lp->stats.collisions += ((status & TD_EC) ? 16 :
1722                                                      ((status & TD_CC) >> 3));
1723
1724            /* Free the buffer. */
1725            if (lp->tx_skb[entry] != NULL)
1726                de4x5_free_tx_buff(lp, entry);
1727        }
1728
1729        /* Update all the pointers */
1730        lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1731    }
1732
1733    /* Any resources available? */
1734    if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1735        if (lp->interrupt)
1736            netif_wake_queue(dev);
1737        else
1738            netif_start_queue(dev);
1739    }
1740
1741    return 0;
1742}
1743
1744static void
1745de4x5_ast(struct net_device *dev)
1746{
1747        struct de4x5_private *lp = netdev_priv(dev);
1748        int next_tick = DE4X5_AUTOSENSE_MS;
1749        int dt;
1750
1751        if (lp->useSROM)
1752                next_tick = srom_autoconf(dev);
1753        else if (lp->chipset == DC21140)
1754                next_tick = dc21140m_autoconf(dev);
1755        else if (lp->chipset == DC21041)
1756                next_tick = dc21041_autoconf(dev);
1757        else if (lp->chipset == DC21040)
1758                next_tick = dc21040_autoconf(dev);
1759        lp->linkOK = 0;
1760
1761        dt = (next_tick * HZ) / 1000;
1762
1763        if (!dt)
1764                dt = 1;
1765
1766        mod_timer(&lp->timer, jiffies + dt);
1767}
1768
1769static int
1770de4x5_txur(struct net_device *dev)
1771{
1772    struct de4x5_private *lp = netdev_priv(dev);
1773    u_long iobase = dev->base_addr;
1774    int omr;
1775
1776    omr = inl(DE4X5_OMR);
1777    if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1778        omr &= ~(OMR_ST|OMR_SR);
1779        outl(omr, DE4X5_OMR);
1780        while (inl(DE4X5_STS) & STS_TS);
1781        if ((omr & OMR_TR) < OMR_TR) {
1782            omr += 0x4000;
1783        } else {
1784            omr |= OMR_SF;
1785        }
1786        outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1787    }
1788
1789    return 0;
1790}
1791
1792static int
1793de4x5_rx_ovfc(struct net_device *dev)
1794{
1795    struct de4x5_private *lp = netdev_priv(dev);
1796    u_long iobase = dev->base_addr;
1797    int omr;
1798
1799    omr = inl(DE4X5_OMR);
1800    outl(omr & ~OMR_SR, DE4X5_OMR);
1801    while (inl(DE4X5_STS) & STS_RS);
1802
1803    for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1804        lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1805        lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1806    }
1807
1808    outl(omr, DE4X5_OMR);
1809
1810    return 0;
1811}
1812
1813static int
1814de4x5_close(struct net_device *dev)
1815{
1816    struct de4x5_private *lp = netdev_priv(dev);
1817    u_long iobase = dev->base_addr;
1818    s32 imr, omr;
1819
1820    disable_ast(dev);
1821
1822    netif_stop_queue(dev);
1823
1824    if (de4x5_debug & DEBUG_CLOSE) {
1825        printk("%s: Shutting down ethercard, status was %8.8x.\n",
1826               dev->name, inl(DE4X5_STS));
1827    }
1828
1829    /*
1830    ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1831    */
1832    DISABLE_IRQs;
1833    STOP_DE4X5;
1834
1835    /* Free the associated irq */
1836    free_irq(dev->irq, dev);
1837    lp->state = CLOSED;
1838
1839    /* Free any socket buffers */
1840    de4x5_free_rx_buffs(dev);
1841    de4x5_free_tx_buffs(dev);
1842
1843    /* Put the adapter to sleep to save power */
1844    yawn(dev, SLEEP);
1845
1846    return 0;
1847}
1848
1849static struct net_device_stats *
1850de4x5_get_stats(struct net_device *dev)
1851{
1852    struct de4x5_private *lp = netdev_priv(dev);
1853    u_long iobase = dev->base_addr;
1854
1855    lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1856
1857    return &lp->stats;
1858}
1859
1860static void
1861de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1862{
1863    struct de4x5_private *lp = netdev_priv(dev);
1864    int i;
1865
1866    for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1867        if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1868            lp->pktStats.bins[i]++;
1869            i = DE4X5_PKT_STAT_SZ;
1870        }
1871    }
1872    if (buf[0] & 0x01) {          /* Multicast/Broadcast */
1873        if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1874            lp->pktStats.broadcast++;
1875        } else {
1876            lp->pktStats.multicast++;
1877        }
1878    } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1879               (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1880        lp->pktStats.unicast++;
1881    }
1882
1883    lp->pktStats.bins[0]++;       /* Duplicates stats.rx_packets */
1884    if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1885        memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1886    }
1887
1888    return;
1889}
1890
1891/*
1892** Removes the TD_IC flag from previous descriptor to improve TX performance.
1893** If the flag is changed on a descriptor that is being read by the hardware,
1894** I assume PCI transaction ordering will mean you are either successful or
1895** just miss asserting the change to the hardware. Anyway you're messing with
1896** a descriptor you don't own, but this shouldn't kill the chip provided
1897** the descriptor register is read only to the hardware.
1898*/
1899static void
1900load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1901{
1902    struct de4x5_private *lp = netdev_priv(dev);
1903    int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1904    dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1905
1906    lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1907    lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1908    lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1909    lp->tx_skb[lp->tx_new] = skb;
1910    lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1911    barrier();
1912
1913    lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1914    barrier();
1915}
1916
1917/*
1918** Set or clear the multicast filter for this adaptor.
1919*/
1920static void
1921set_multicast_list(struct net_device *dev)
1922{
1923    struct de4x5_private *lp = netdev_priv(dev);
1924    u_long iobase = dev->base_addr;
1925
1926    /* First, double check that the adapter is open */
1927    if (lp->state == OPEN) {
1928        if (dev->flags & IFF_PROMISC) {         /* set promiscuous mode */
1929            u32 omr;
1930            omr = inl(DE4X5_OMR);
1931            omr |= OMR_PR;
1932            outl(omr, DE4X5_OMR);
1933        } else {
1934            SetMulticastFilter(dev);
1935            load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1936                                                        SETUP_FRAME_LEN, (struct sk_buff *)1);
1937
1938            lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1939            outl(POLL_DEMAND, DE4X5_TPD);       /* Start the TX */
1940            dev->trans_start = jiffies;
1941        }
1942    }
1943}
1944
1945/*
1946** Calculate the hash code and update the logical address filter
1947** from a list of ethernet multicast addresses.
1948** Little endian crc one liner from Matt Thomas, DEC.
1949*/
1950static void
1951SetMulticastFilter(struct net_device *dev)
1952{
1953    struct de4x5_private *lp = netdev_priv(dev);
1954    struct dev_mc_list *dmi=dev->mc_list;
1955    u_long iobase = dev->base_addr;
1956    int i, j, bit, byte;
1957    u16 hashcode;
1958    u32 omr, crc;
1959    char *pa;
1960    unsigned char *addrs;
1961
1962    omr = inl(DE4X5_OMR);
1963    omr &= ~(OMR_PR | OMR_PM);
1964    pa = build_setup_frame(dev, ALL);        /* Build the basic frame */
1965
1966    if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1967        omr |= OMR_PM;                       /* Pass all multicasts */
1968    } else if (lp->setup_f == HASH_PERF) {   /* Hash Filtering */
1969        for (i=0;i<dev->mc_count;i++) {      /* for each address in the list */
1970            addrs=dmi->dmi_addr;
1971            dmi=dmi->next;
1972            if ((*addrs & 0x01) == 1) {      /* multicast address? */
1973                crc = ether_crc_le(ETH_ALEN, addrs);
1974                hashcode = crc & HASH_BITS;  /* hashcode is 9 LSb of CRC */
1975
1976                byte = hashcode >> 3;        /* bit[3-8] -> byte in filter */
1977                bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1978
1979                byte <<= 1;                  /* calc offset into setup frame */
1980                if (byte & 0x02) {
1981                    byte -= 1;
1982                }
1983                lp->setup_frame[byte] |= bit;
1984            }
1985        }
1986    } else {                                 /* Perfect filtering */
1987        for (j=0; j<dev->mc_count; j++) {
1988            addrs=dmi->dmi_addr;
1989            dmi=dmi->next;
1990            for (i=0; i<ETH_ALEN; i++) {
1991                *(pa + (i&1)) = *addrs++;
1992                if (i & 0x01) pa += 4;
1993            }
1994        }
1995    }
1996    outl(omr, DE4X5_OMR);
1997
1998    return;
1999}
2000
2001#ifdef CONFIG_EISA
2002
2003static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2004
2005static int __init de4x5_eisa_probe (struct device *gendev)
2006{
2007        struct eisa_device *edev;
2008        u_long iobase;
2009        u_char irq, regval;
2010        u_short vendor;
2011        u32 cfid;
2012        int status, device;
2013        struct net_device *dev;
2014        struct de4x5_private *lp;
2015
2016        edev = to_eisa_device (gendev);
2017        iobase = edev->base_addr;
2018
2019        if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2020                return -EBUSY;
2021
2022        if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2023                             DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2024                status = -EBUSY;
2025                goto release_reg_1;
2026        }
2027
2028        if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2029                status = -ENOMEM;
2030                goto release_reg_2;
2031        }
2032        lp = netdev_priv(dev);
2033
2034        cfid = (u32) inl(PCI_CFID);
2035        lp->cfrv = (u_short) inl(PCI_CFRV);
2036        device = (cfid >> 8) & 0x00ffff00;
2037        vendor = (u_short) cfid;
2038
2039        /* Read the EISA Configuration Registers */
2040        regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2041#ifdef CONFIG_ALPHA
2042        /* Looks like the Jensen firmware (rev 2.2) doesn't really
2043         * care about the EISA configuration, and thus doesn't
2044         * configure the PLX bridge properly. Oh well... Simply mimic
2045         * the EISA config file to sort it out. */
2046
2047        /* EISA REG1: Assert DecChip 21040 HW Reset */
2048        outb (ER1_IAM | 1, EISA_REG1);
2049        mdelay (1);
2050
2051        /* EISA REG1: Deassert DecChip 21040 HW Reset */
2052        outb (ER1_IAM, EISA_REG1);
2053        mdelay (1);
2054
2055        /* EISA REG3: R/W Burst Transfer Enable */
2056        outb (ER3_BWE | ER3_BRE, EISA_REG3);
2057
2058        /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2059        outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2060#endif
2061        irq = de4x5_irq[(regval >> 1) & 0x03];
2062
2063        if (is_DC2114x) {
2064            device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2065        }
2066        lp->chipset = device;
2067        lp->bus = EISA;
2068
2069        /* Write the PCI Configuration Registers */
2070        outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2071        outl(0x00006000, PCI_CFLT);
2072        outl(iobase, PCI_CBIO);
2073
2074        DevicePresent(dev, EISA_APROM);
2075
2076        dev->irq = irq;
2077
2078        if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2079                return 0;
2080        }
2081
2082        free_netdev (dev);
2083 release_reg_2:
2084        release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2085 release_reg_1:
2086        release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2087
2088        return status;
2089}
2090
2091static int __devexit de4x5_eisa_remove (struct device *device)
2092{
2093        struct net_device *dev;
2094        u_long iobase;
2095
2096        dev = dev_get_drvdata(device);
2097        iobase = dev->base_addr;
2098
2099        unregister_netdev (dev);
2100        free_netdev (dev);
2101        release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2102        release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2103
2104        return 0;
2105}
2106
2107static struct eisa_device_id de4x5_eisa_ids[] = {
2108        { "DEC4250", 0 },       /* 0 is the board name index... */
2109        { "" }
2110};
2111MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2112
2113static struct eisa_driver de4x5_eisa_driver = {
2114        .id_table = de4x5_eisa_ids,
2115        .driver   = {
2116                .name    = "de4x5",
2117                .probe   = de4x5_eisa_probe,
2118                .remove  = __devexit_p (de4x5_eisa_remove),
2119        }
2120};
2121MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2122#endif
2123
2124#ifdef CONFIG_PCI
2125
2126/*
2127** This function searches the current bus (which is >0) for a DECchip with an
2128** SROM, so that in multiport cards that have one SROM shared between multiple
2129** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2130** For single port cards this is a time waster...
2131*/
2132static void __devinit
2133srom_search(struct net_device *dev, struct pci_dev *pdev)
2134{
2135    u_char pb;
2136    u_short vendor, status;
2137    u_int irq = 0, device;
2138    u_long iobase = 0;                     /* Clear upper 32 bits in Alphas */
2139    int i, j;
2140    struct de4x5_private *lp = netdev_priv(dev);
2141    struct list_head *walk;
2142
2143    list_for_each(walk, &pdev->bus_list) {
2144        struct pci_dev *this_dev = pci_dev_b(walk);
2145
2146        /* Skip the pci_bus list entry */
2147        if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2148
2149        vendor = this_dev->vendor;
2150        device = this_dev->device << 8;
2151        if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2152
2153        /* Get the chip configuration revision register */
2154        pb = this_dev->bus->number;
2155
2156        /* Set the device number information */
2157        lp->device = PCI_SLOT(this_dev->devfn);
2158        lp->bus_num = pb;
2159
2160        /* Set the chipset information */
2161        if (is_DC2114x) {
2162            device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2163                      ? DC21142 : DC21143);
2164        }
2165        lp->chipset = device;
2166
2167        /* Get the board I/O address (64 bits on sparc64) */
2168        iobase = pci_resource_start(this_dev, 0);
2169
2170        /* Fetch the IRQ to be used */
2171        irq = this_dev->irq;
2172        if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2173
2174        /* Check if I/O accesses are enabled */
2175        pci_read_config_word(this_dev, PCI_COMMAND, &status);
2176        if (!(status & PCI_COMMAND_IO)) continue;
2177
2178        /* Search for a valid SROM attached to this DECchip */
2179        DevicePresent(dev, DE4X5_APROM);
2180        for (j=0, i=0; i<ETH_ALEN; i++) {
2181            j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2182        }
2183        if (j != 0 && j != 6 * 0xff) {
2184            last.chipset = device;
2185            last.bus = pb;
2186            last.irq = irq;
2187            for (i=0; i<ETH_ALEN; i++) {
2188                last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2189            }
2190            return;
2191        }
2192    }
2193
2194    return;
2195}
2196
2197/*
2198** PCI bus I/O device probe
2199** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2200** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2201** enabled by the user first in the set up utility. Hence we just check for
2202** enabled features and silently ignore the card if they're not.
2203**
2204** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2205** bit. Here, check for I/O accesses and then set BM. If you put the card in
2206** a non BM slot, you're on your own (and complain to the PC vendor that your
2207** PC doesn't conform to the PCI standard)!
2208**
2209** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2210** kernels use the V0.535[n] drivers.
2211*/
2212
2213static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2214                                   const struct pci_device_id *ent)
2215{
2216        u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2217        u_short vendor, status;
2218        u_int irq = 0, device;
2219        u_long iobase = 0;      /* Clear upper 32 bits in Alphas */
2220        int error;
2221        struct net_device *dev;
2222        struct de4x5_private *lp;
2223
2224        dev_num = PCI_SLOT(pdev->devfn);
2225        pb = pdev->bus->number;
2226
2227        if (io) { /* probe a single PCI device */
2228                pbus = (u_short)(io >> 8);
2229                dnum = (u_short)(io & 0xff);
2230                if ((pbus != pb) || (dnum != dev_num))
2231                        return -ENODEV;
2232        }
2233
2234        vendor = pdev->vendor;
2235        device = pdev->device << 8;
2236        if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2237                return -ENODEV;
2238
2239        /* Ok, the device seems to be for us. */
2240        if ((error = pci_enable_device (pdev)))
2241                return error;
2242
2243        if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2244                error = -ENOMEM;
2245                goto disable_dev;
2246        }
2247
2248        lp = netdev_priv(dev);
2249        lp->bus = PCI;
2250        lp->bus_num = 0;
2251
2252        /* Search for an SROM on this bus */
2253        if (lp->bus_num != pb) {
2254            lp->bus_num = pb;
2255            srom_search(dev, pdev);
2256        }
2257
2258        /* Get the chip configuration revision register */
2259        lp->cfrv = pdev->revision;
2260
2261        /* Set the device number information */
2262        lp->device = dev_num;
2263        lp->bus_num = pb;
2264
2265        /* Set the chipset information */
2266        if (is_DC2114x) {
2267            device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2268        }
2269        lp->chipset = device;
2270
2271        /* Get the board I/O address (64 bits on sparc64) */
2272        iobase = pci_resource_start(pdev, 0);
2273
2274        /* Fetch the IRQ to be used */
2275        irq = pdev->irq;
2276        if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2277                error = -ENODEV;
2278                goto free_dev;
2279        }
2280
2281        /* Check if I/O accesses and Bus Mastering are enabled */
2282        pci_read_config_word(pdev, PCI_COMMAND, &status);
2283#ifdef __powerpc__
2284        if (!(status & PCI_COMMAND_IO)) {
2285            status |= PCI_COMMAND_IO;
2286            pci_write_config_word(pdev, PCI_COMMAND, status);
2287            pci_read_config_word(pdev, PCI_COMMAND, &status);
2288        }
2289#endif /* __powerpc__ */
2290        if (!(status & PCI_COMMAND_IO)) {
2291                error = -ENODEV;
2292                goto free_dev;
2293        }
2294
2295        if (!(status & PCI_COMMAND_MASTER)) {
2296            status |= PCI_COMMAND_MASTER;
2297            pci_write_config_word(pdev, PCI_COMMAND, status);
2298            pci_read_config_word(pdev, PCI_COMMAND, &status);
2299        }
2300        if (!(status & PCI_COMMAND_MASTER)) {
2301                error = -ENODEV;
2302                goto free_dev;
2303        }
2304
2305        /* Check the latency timer for values >= 0x60 */
2306        pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2307        if (timer < 0x60) {
2308            pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2309        }
2310
2311        DevicePresent(dev, DE4X5_APROM);
2312
2313        if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2314                error = -EBUSY;
2315                goto free_dev;
2316        }
2317
2318        dev->irq = irq;
2319
2320        if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2321                goto release;
2322        }
2323
2324        return 0;
2325
2326 release:
2327        release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2328 free_dev:
2329        free_netdev (dev);
2330 disable_dev:
2331        pci_disable_device (pdev);
2332        return error;
2333}
2334
2335static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2336{
2337        struct net_device *dev;
2338        u_long iobase;
2339
2340        dev = dev_get_drvdata(&pdev->dev);
2341        iobase = dev->base_addr;
2342
2343        unregister_netdev (dev);
2344        free_netdev (dev);
2345        release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2346        pci_disable_device (pdev);
2347}
2348
2349static struct pci_device_id de4x5_pci_tbl[] = {
2350        { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2351          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2352        { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2353          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2354        { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2355          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2356        { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2357          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2358        { },
2359};
2360
2361static struct pci_driver de4x5_pci_driver = {
2362        .name           = "de4x5",
2363        .id_table       = de4x5_pci_tbl,
2364        .probe          = de4x5_pci_probe,
2365        .remove         = __devexit_p (de4x5_pci_remove),
2366};
2367
2368#endif
2369
2370/*
2371** Auto configure the media here rather than setting the port at compile
2372** time. This routine is called by de4x5_init() and when a loss of media is
2373** detected (excessive collisions, loss of carrier, no carrier or link fail
2374** [TP] or no recent receive activity) to check whether the user has been
2375** sneaky and changed the port on us.
2376*/
2377static int
2378autoconf_media(struct net_device *dev)
2379{
2380        struct de4x5_private *lp = netdev_priv(dev);
2381        u_long iobase = dev->base_addr;
2382
2383        disable_ast(dev);
2384
2385        lp->c_media = AUTO;                     /* Bogus last media */
2386        inl(DE4X5_MFC);                         /* Zero the lost frames counter */
2387        lp->media = INIT;
2388        lp->tcount = 0;
2389
2390        de4x5_ast(dev);
2391
2392        return lp->media;
2393}
2394
2395/*
2396** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2397** from BNC as the port has a jumper to set thick or thin wire. When set for
2398** BNC, the BNC port will indicate activity if it's not terminated correctly.
2399** The only way to test for that is to place a loopback packet onto the
2400** network and watch for errors. Since we're messing with the interrupt mask
2401** register, disable the board interrupts and do not allow any more packets to
2402** be queued to the hardware. Re-enable everything only when the media is
2403** found.
2404** I may have to "age out" locally queued packets so that the higher layer
2405** timeouts don't effectively duplicate packets on the network.
2406*/
2407static int
2408dc21040_autoconf(struct net_device *dev)
2409{
2410    struct de4x5_private *lp = netdev_priv(dev);
2411    u_long iobase = dev->base_addr;
2412    int next_tick = DE4X5_AUTOSENSE_MS;
2413    s32 imr;
2414
2415    switch (lp->media) {
2416    case INIT:
2417        DISABLE_IRQs;
2418        lp->tx_enable = false;
2419        lp->timeout = -1;
2420        de4x5_save_skbs(dev);
2421        if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2422            lp->media = TP;
2423        } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2424            lp->media = BNC_AUI;
2425        } else if (lp->autosense == EXT_SIA) {
2426            lp->media = EXT_SIA;
2427        } else {
2428            lp->media = NC;
2429        }
2430        lp->local_state = 0;
2431        next_tick = dc21040_autoconf(dev);
2432        break;
2433
2434    case TP:
2435        next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2436                                                         TP_SUSPECT, test_tp);
2437        break;
2438
2439    case TP_SUSPECT:
2440        next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2441        break;
2442
2443    case BNC:
2444    case AUI:
2445    case BNC_AUI:
2446        next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2447                                                  BNC_AUI_SUSPECT, ping_media);
2448        break;
2449
2450    case BNC_AUI_SUSPECT:
2451        next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2452        break;
2453
2454    case EXT_SIA:
2455        next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2456                                              NC, EXT_SIA_SUSPECT, ping_media);
2457        break;
2458
2459    case EXT_SIA_SUSPECT:
2460        next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2461        break;
2462
2463    case NC:
2464        /* default to TP for all */
2465        reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2466        if (lp->media != lp->c_media) {
2467            de4x5_dbg_media(dev);
2468            lp->c_media = lp->media;
2469        }
2470        lp->media = INIT;
2471        lp->tx_enable = false;
2472        break;
2473    }
2474
2475    return next_tick;
2476}
2477
2478static int
2479dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2480              int next_state, int suspect_state,
2481              int (*fn)(struct net_device *, int))
2482{
2483    struct de4x5_private *lp = netdev_priv(dev);
2484    int next_tick = DE4X5_AUTOSENSE_MS;
2485    int linkBad;
2486
2487    switch (lp->local_state) {
2488    case 0:
2489        reset_init_sia(dev, csr13, csr14, csr15);
2490        lp->local_state++;
2491        next_tick = 500;
2492        break;
2493
2494    case 1:
2495        if (!lp->tx_enable) {
2496            linkBad = fn(dev, timeout);
2497            if (linkBad < 0) {
2498                next_tick = linkBad & ~TIMER_CB;
2499            } else {
2500                if (linkBad && (lp->autosense == AUTO)) {
2501                    lp->local_state = 0;
2502                    lp->media = next_state;
2503                } else {
2504                    de4x5_init_connection(dev);
2505                }
2506            }
2507        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2508            lp->media = suspect_state;
2509            next_tick = 3000;
2510        }
2511        break;
2512    }
2513
2514    return next_tick;
2515}
2516
2517static int
2518de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2519                      int (*fn)(struct net_device *, int),
2520                      int (*asfn)(struct net_device *))
2521{
2522    struct de4x5_private *lp = netdev_priv(dev);
2523    int next_tick = DE4X5_AUTOSENSE_MS;
2524    int linkBad;
2525
2526    switch (lp->local_state) {
2527    case 1:
2528        if (lp->linkOK) {
2529            lp->media = prev_state;
2530        } else {
2531            lp->local_state++;
2532            next_tick = asfn(dev);
2533        }
2534        break;
2535
2536    case 2:
2537        linkBad = fn(dev, timeout);
2538        if (linkBad < 0) {
2539            next_tick = linkBad & ~TIMER_CB;
2540        } else if (!linkBad) {
2541            lp->local_state--;
2542            lp->media = prev_state;
2543        } else {
2544            lp->media = INIT;
2545            lp->tcount++;
2546        }
2547    }
2548
2549    return next_tick;
2550}
2551
2552/*
2553** Autoconfigure the media when using the DC21041. AUI needs to be tested
2554** before BNC, because the BNC port will indicate activity if it's not
2555** terminated correctly. The only way to test for that is to place a loopback
2556** packet onto the network and watch for errors. Since we're messing with
2557** the interrupt mask register, disable the board interrupts and do not allow
2558** any more packets to be queued to the hardware. Re-enable everything only
2559** when the media is found.
2560*/
2561static int
2562dc21041_autoconf(struct net_device *dev)
2563{
2564    struct de4x5_private *lp = netdev_priv(dev);
2565    u_long iobase = dev->base_addr;
2566    s32 sts, irqs, irq_mask, imr, omr;
2567    int next_tick = DE4X5_AUTOSENSE_MS;
2568
2569    switch (lp->media) {
2570    case INIT:
2571        DISABLE_IRQs;
2572        lp->tx_enable = false;
2573        lp->timeout = -1;
2574        de4x5_save_skbs(dev);          /* Save non transmitted skb's */
2575        if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2576            lp->media = TP;            /* On chip auto negotiation is broken */
2577        } else if (lp->autosense == TP) {
2578            lp->media = TP;
2579        } else if (lp->autosense == BNC) {
2580            lp->media = BNC;
2581        } else if (lp->autosense == AUI) {
2582            lp->media = AUI;
2583        } else {
2584            lp->media = NC;
2585        }
2586        lp->local_state = 0;
2587        next_tick = dc21041_autoconf(dev);
2588        break;
2589
2590    case TP_NW:
2591        if (lp->timeout < 0) {
2592            omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2593            outl(omr | OMR_FDX, DE4X5_OMR);
2594        }
2595        irqs = STS_LNF | STS_LNP;
2596        irq_mask = IMR_LFM | IMR_LPM;
2597        sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2598        if (sts < 0) {
2599            next_tick = sts & ~TIMER_CB;
2600        } else {
2601            if (sts & STS_LNP) {
2602                lp->media = ANS;
2603            } else {
2604                lp->media = AUI;
2605            }
2606            next_tick = dc21041_autoconf(dev);
2607        }
2608        break;
2609
2610    case ANS:
2611        if (!lp->tx_enable) {
2612            irqs = STS_LNP;
2613            irq_mask = IMR_LPM;
2614            sts = test_ans(dev, irqs, irq_mask, 3000);
2615            if (sts < 0) {
2616                next_tick = sts & ~TIMER_CB;
2617            } else {
2618                if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2619                    lp->media = TP;
2620                    next_tick = dc21041_autoconf(dev);
2621                } else {
2622                    lp->local_state = 1;
2623                    de4x5_init_connection(dev);
2624                }
2625            }
2626        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2627            lp->media = ANS_SUSPECT;
2628            next_tick = 3000;
2629        }
2630        break;
2631
2632    case ANS_SUSPECT:
2633        next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2634        break;
2635
2636    case TP:
2637        if (!lp->tx_enable) {
2638            if (lp->timeout < 0) {
2639                omr = inl(DE4X5_OMR);          /* Set up half duplex for TP */
2640                outl(omr & ~OMR_FDX, DE4X5_OMR);
2641            }
2642            irqs = STS_LNF | STS_LNP;
2643            irq_mask = IMR_LFM | IMR_LPM;
2644            sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2645            if (sts < 0) {
2646                next_tick = sts & ~TIMER_CB;
2647            } else {
2648                if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2649                    if (inl(DE4X5_SISR) & SISR_NRA) {
2650                        lp->media = AUI;       /* Non selected port activity */
2651                    } else {
2652                        lp->media = BNC;
2653                    }
2654                    next_tick = dc21041_autoconf(dev);
2655                } else {
2656                    lp->local_state = 1;
2657                    de4x5_init_connection(dev);
2658                }
2659            }
2660        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2661            lp->media = TP_SUSPECT;
2662            next_tick = 3000;
2663        }
2664        break;
2665
2666    case TP_SUSPECT:
2667        next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2668        break;
2669
2670    case AUI:
2671        if (!lp->tx_enable) {
2672            if (lp->timeout < 0) {
2673                omr = inl(DE4X5_OMR);          /* Set up half duplex for AUI */
2674                outl(omr & ~OMR_FDX, DE4X5_OMR);
2675            }
2676            irqs = 0;
2677            irq_mask = 0;
2678            sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2679            if (sts < 0) {
2680                next_tick = sts & ~TIMER_CB;
2681            } else {
2682                if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2683                    lp->media = BNC;
2684                    next_tick = dc21041_autoconf(dev);
2685                } else {
2686                    lp->local_state = 1;
2687                    de4x5_init_connection(dev);
2688                }
2689            }
2690        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2691            lp->media = AUI_SUSPECT;
2692            next_tick = 3000;
2693        }
2694        break;
2695
2696    case AUI_SUSPECT:
2697        next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2698        break;
2699
2700    case BNC:
2701        switch (lp->local_state) {
2702        case 0:
2703            if (lp->timeout < 0) {
2704                omr = inl(DE4X5_OMR);          /* Set up half duplex for BNC */
2705                outl(omr & ~OMR_FDX, DE4X5_OMR);
2706            }
2707            irqs = 0;
2708            irq_mask = 0;
2709            sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2710            if (sts < 0) {
2711                next_tick = sts & ~TIMER_CB;
2712            } else {
2713                lp->local_state++;             /* Ensure media connected */
2714                next_tick = dc21041_autoconf(dev);
2715            }
2716            break;
2717
2718        case 1:
2719            if (!lp->tx_enable) {
2720                if ((sts = ping_media(dev, 3000)) < 0) {
2721                    next_tick = sts & ~TIMER_CB;
2722                } else {
2723                    if (sts) {
2724                        lp->local_state = 0;
2725                        lp->media = NC;
2726                    } else {
2727                        de4x5_init_connection(dev);
2728                    }
2729                }
2730            } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2731                lp->media = BNC_SUSPECT;
2732                next_tick = 3000;
2733            }
2734            break;
2735        }
2736        break;
2737
2738    case BNC_SUSPECT:
2739        next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2740        break;
2741
2742    case NC:
2743        omr = inl(DE4X5_OMR);    /* Set up full duplex for the autonegotiate */
2744        outl(omr | OMR_FDX, DE4X5_OMR);
2745        reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2746        if (lp->media != lp->c_media) {
2747            de4x5_dbg_media(dev);
2748            lp->c_media = lp->media;
2749        }
2750        lp->media = INIT;
2751        lp->tx_enable = false;
2752        break;
2753    }
2754
2755    return next_tick;
2756}
2757
2758/*
2759** Some autonegotiation chips are broken in that they do not return the
2760** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2761** register, except at the first power up negotiation.
2762*/
2763static int
2764dc21140m_autoconf(struct net_device *dev)
2765{
2766    struct de4x5_private *lp = netdev_priv(dev);
2767    int ana, anlpa, cap, cr, slnk, sr;
2768    int next_tick = DE4X5_AUTOSENSE_MS;
2769    u_long imr, omr, iobase = dev->base_addr;
2770
2771    switch(lp->media) {
2772    case INIT:
2773        if (lp->timeout < 0) {
2774            DISABLE_IRQs;
2775            lp->tx_enable = false;
2776            lp->linkOK = 0;
2777            de4x5_save_skbs(dev);          /* Save non transmitted skb's */
2778        }
2779        if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2780            next_tick &= ~TIMER_CB;
2781        } else {
2782            if (lp->useSROM) {
2783                if (srom_map_media(dev) < 0) {
2784                    lp->tcount++;
2785                    return next_tick;
2786                }
2787                srom_exec(dev, lp->phy[lp->active].gep);
2788                if (lp->infoblock_media == ANS) {
2789                    ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2790                    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2791                }
2792            } else {
2793                lp->tmp = MII_SR_ASSC;     /* Fake out the MII speed set */
2794                SET_10Mb;
2795                if (lp->autosense == _100Mb) {
2796                    lp->media = _100Mb;
2797                } else if (lp->autosense == _10Mb) {
2798                    lp->media = _10Mb;
2799                } else if ((lp->autosense == AUTO) &&
2800                                    ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2801                    ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2802                    ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2803                    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2804                    lp->media = ANS;
2805                } else if (lp->autosense == AUTO) {
2806                    lp->media = SPD_DET;
2807                } else if (is_spd_100(dev) && is_100_up(dev)) {
2808                    lp->media = _100Mb;
2809                } else {
2810                    lp->media = NC;
2811                }
2812            }
2813            lp->local_state = 0;
2814            next_tick = dc21140m_autoconf(dev);
2815        }
2816        break;
2817
2818    case ANS:
2819        switch (lp->local_state) {
2820        case 0:
2821            if (lp->timeout < 0) {
2822                mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2823            }
2824            cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2825            if (cr < 0) {
2826                next_tick = cr & ~TIMER_CB;
2827            } else {
2828                if (cr) {
2829                    lp->local_state = 0;
2830                    lp->media = SPD_DET;
2831                } else {
2832                    lp->local_state++;
2833                }
2834                next_tick = dc21140m_autoconf(dev);
2835            }
2836            break;
2837
2838        case 1:
2839            if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2840                next_tick = sr & ~TIMER_CB;
2841            } else {
2842                lp->media = SPD_DET;
2843                lp->local_state = 0;
2844                if (sr) {                         /* Success! */
2845                    lp->tmp = MII_SR_ASSC;
2846                    anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2847                    ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2848                    if (!(anlpa & MII_ANLPA_RF) &&
2849                         (cap = anlpa & MII_ANLPA_TAF & ana)) {
2850                        if (cap & MII_ANA_100M) {
2851                            lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2852                            lp->media = _100Mb;
2853                        } else if (cap & MII_ANA_10M) {
2854                            lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2855
2856                            lp->media = _10Mb;
2857                        }
2858                    }
2859                }                       /* Auto Negotiation failed to finish */
2860                next_tick = dc21140m_autoconf(dev);
2861            }                           /* Auto Negotiation failed to start */
2862            break;
2863        }
2864        break;
2865
2866    case SPD_DET:                              /* Choose 10Mb/s or 100Mb/s */
2867        if (lp->timeout < 0) {
2868            lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2869                                                  (~gep_rd(dev) & GEP_LNP));
2870            SET_100Mb_PDET;
2871        }
2872        if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2873            next_tick = slnk & ~TIMER_CB;
2874        } else {
2875            if (is_spd_100(dev) && is_100_up(dev)) {
2876                lp->media = _100Mb;
2877            } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2878                lp->media = _10Mb;
2879            } else {
2880                lp->media = NC;
2881            }
2882            next_tick = dc21140m_autoconf(dev);
2883        }
2884        break;
2885
2886    case _100Mb:                               /* Set 100Mb/s */
2887        next_tick = 3000;
2888        if (!lp->tx_enable) {
2889            SET_100Mb;
2890            de4x5_init_connection(dev);
2891        } else {
2892            if (!lp->linkOK && (lp->autosense == AUTO)) {
2893                if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2894                    lp->media = INIT;
2895                    lp->tcount++;
2896                    next_tick = DE4X5_AUTOSENSE_MS;
2897                }
2898            }
2899        }
2900        break;
2901
2902    case BNC:
2903    case AUI:
2904    case _10Mb:                                /* Set 10Mb/s */
2905        next_tick = 3000;
2906        if (!lp->tx_enable) {
2907            SET_10Mb;
2908            de4x5_init_connection(dev);
2909        } else {
2910            if (!lp->linkOK && (lp->autosense == AUTO)) {
2911                if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2912                    lp->media = INIT;
2913                    lp->tcount++;
2914                    next_tick = DE4X5_AUTOSENSE_MS;
2915                }
2916            }
2917        }
2918        break;
2919
2920    case NC:
2921        if (lp->media != lp->c_media) {
2922            de4x5_dbg_media(dev);
2923            lp->c_media = lp->media;
2924        }
2925        lp->media = INIT;
2926        lp->tx_enable = false;
2927        break;
2928    }
2929
2930    return next_tick;
2931}
2932
2933/*
2934** This routine may be merged into dc21140m_autoconf() sometime as I'm
2935** changing how I figure out the media - but trying to keep it backwards
2936** compatible with the de500-xa and de500-aa.
2937** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2938** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2939** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2940** active.
2941** When autonegotiation is working, the ANS part searches the SROM for
2942** the highest common speed (TP) link that both can run and if that can
2943** be full duplex. That infoblock is executed and then the link speed set.
2944**
2945** Only _10Mb and _100Mb are tested here.
2946*/
2947static int
2948dc2114x_autoconf(struct net_device *dev)
2949{
2950    struct de4x5_private *lp = netdev_priv(dev);
2951    u_long iobase = dev->base_addr;
2952    s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2953    int next_tick = DE4X5_AUTOSENSE_MS;
2954
2955    switch (lp->media) {
2956    case INIT:
2957        if (lp->timeout < 0) {
2958            DISABLE_IRQs;
2959            lp->tx_enable = false;
2960            lp->linkOK = 0;
2961            lp->timeout = -1;
2962            de4x5_save_skbs(dev);            /* Save non transmitted skb's */
2963            if (lp->params.autosense & ~AUTO) {
2964                srom_map_media(dev);         /* Fixed media requested      */
2965                if (lp->media != lp->params.autosense) {
2966                    lp->tcount++;
2967                    lp->media = INIT;
2968                    return next_tick;
2969                }
2970                lp->media = INIT;
2971            }
2972        }
2973        if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2974            next_tick &= ~TIMER_CB;
2975        } else {
2976            if (lp->autosense == _100Mb) {
2977                lp->media = _100Mb;
2978            } else if (lp->autosense == _10Mb) {
2979                lp->media = _10Mb;
2980            } else if (lp->autosense == TP) {
2981                lp->media = TP;
2982            } else if (lp->autosense == BNC) {
2983                lp->media = BNC;
2984            } else if (lp->autosense == AUI) {
2985                lp->media = AUI;
2986            } else {
2987                lp->media = SPD_DET;
2988                if ((lp->infoblock_media == ANS) &&
2989                                    ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2990                    ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2991                    ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2992                    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2993                    lp->media = ANS;
2994                }
2995            }
2996            lp->local_state = 0;
2997            next_tick = dc2114x_autoconf(dev);
2998        }
2999        break;
3000
3001    case ANS:
3002        switch (lp->local_state) {
3003        case 0:
3004            if (lp->timeout < 0) {
3005                mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3006            }
3007            cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
3008            if (cr < 0) {
3009                next_tick = cr & ~TIMER_CB;
3010            } else {
3011                if (cr) {
3012                    lp->local_state = 0;
3013                    lp->media = SPD_DET;
3014                } else {
3015                    lp->local_state++;
3016                }
3017                next_tick = dc2114x_autoconf(dev);
3018            }
3019            break;
3020
3021        case 1:
3022            sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3023            if (sr < 0) {
3024                next_tick = sr & ~TIMER_CB;
3025            } else {
3026                lp->media = SPD_DET;
3027                lp->local_state = 0;
3028                if (sr) {                         /* Success! */
3029                    lp->tmp = MII_SR_ASSC;
3030                    anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3031                    ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3032                    if (!(anlpa & MII_ANLPA_RF) &&
3033                         (cap = anlpa & MII_ANLPA_TAF & ana)) {
3034                        if (cap & MII_ANA_100M) {
3035                            lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3036                            lp->media = _100Mb;
3037                        } else if (cap & MII_ANA_10M) {
3038                            lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3039                            lp->media = _10Mb;
3040                        }
3041                    }
3042                }                       /* Auto Negotiation failed to finish */
3043                next_tick = dc2114x_autoconf(dev);
3044            }                           /* Auto Negotiation failed to start  */
3045            break;
3046        }
3047        break;
3048
3049    case AUI:
3050        if (!lp->tx_enable) {
3051            if (lp->timeout < 0) {
3052                omr = inl(DE4X5_OMR);   /* Set up half duplex for AUI        */
3053                outl(omr & ~OMR_FDX, DE4X5_OMR);
3054            }
3055            irqs = 0;
3056            irq_mask = 0;
3057            sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3058            if (sts < 0) {
3059                next_tick = sts & ~TIMER_CB;
3060            } else {
3061                if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3062                    lp->media = BNC;
3063                    next_tick = dc2114x_autoconf(dev);
3064                } else {
3065                    lp->local_state = 1;
3066                    de4x5_init_connection(dev);
3067                }
3068            }
3069        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3070            lp->media = AUI_SUSPECT;
3071            next_tick = 3000;
3072        }
3073        break;
3074
3075    case AUI_SUSPECT:
3076        next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3077        break;
3078
3079    case BNC:
3080        switch (lp->local_state) {
3081        case 0:
3082            if (lp->timeout < 0) {
3083                omr = inl(DE4X5_OMR);          /* Set up half duplex for BNC */
3084                outl(omr & ~OMR_FDX, DE4X5_OMR);
3085            }
3086            irqs = 0;
3087            irq_mask = 0;
3088            sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3089            if (sts < 0) {
3090                next_tick = sts & ~TIMER_CB;
3091            } else {
3092                lp->local_state++;             /* Ensure media connected */
3093                next_tick = dc2114x_autoconf(dev);
3094            }
3095            break;
3096
3097        case 1:
3098            if (!lp->tx_enable) {
3099                if ((sts = ping_media(dev, 3000)) < 0) {
3100                    next_tick = sts & ~TIMER_CB;
3101                } else {
3102                    if (sts) {
3103                        lp->local_state = 0;
3104                        lp->tcount++;
3105                        lp->media = INIT;
3106                    } else {
3107                        de4x5_init_connection(dev);
3108                    }
3109                }
3110            } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3111                lp->media = BNC_SUSPECT;
3112                next_tick = 3000;
3113            }
3114            break;
3115        }
3116        break;
3117
3118    case BNC_SUSPECT:
3119        next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3120        break;
3121
3122    case SPD_DET:                              /* Choose 10Mb/s or 100Mb/s */
3123          if (srom_map_media(dev) < 0) {
3124              lp->tcount++;
3125              lp->media = INIT;
3126              return next_tick;
3127          }
3128          if (lp->media == _100Mb) {
3129              if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3130                  lp->media = SPD_DET;
3131                  return  (slnk & ~TIMER_CB);
3132              }
3133          } else {
3134              if (wait_for_link(dev) < 0) {
3135                  lp->media = SPD_DET;
3136                  return PDET_LINK_WAIT;
3137              }
3138          }
3139          if (lp->media == ANS) {           /* Do MII parallel detection */
3140              if (is_spd_100(dev)) {
3141                  lp->media = _100Mb;
3142              } else {
3143                  lp->media = _10Mb;
3144              }
3145              next_tick = dc2114x_autoconf(dev);
3146          } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3147                     (((lp->media == _10Mb) || (lp->media == TP) ||
3148                       (lp->media == BNC)   || (lp->media == AUI)) &&
3149                      is_10_up(dev))) {
3150              next_tick = dc2114x_autoconf(dev);
3151          } else {
3152              lp->tcount++;
3153              lp->media = INIT;
3154          }
3155          break;
3156
3157    case _10Mb:
3158        next_tick = 3000;
3159        if (!lp->tx_enable) {
3160            SET_10Mb;
3161            de4x5_init_connection(dev);
3162        } else {
3163            if (!lp->linkOK && (lp->autosense == AUTO)) {
3164                if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3165                    lp->media = INIT;
3166                    lp->tcount++;
3167                    next_tick = DE4X5_AUTOSENSE_MS;
3168                }
3169            }
3170        }
3171        break;
3172
3173    case _100Mb:
3174        next_tick = 3000;
3175        if (!lp->tx_enable) {
3176            SET_100Mb;
3177            de4x5_init_connection(dev);
3178        } else {
3179            if (!lp->linkOK && (lp->autosense == AUTO)) {
3180                if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3181                    lp->media = INIT;
3182                    lp->tcount++;
3183                    next_tick = DE4X5_AUTOSENSE_MS;
3184                }
3185            }
3186        }
3187        break;
3188
3189    default:
3190        lp->tcount++;
3191printk("Huh?: media:%02x\n", lp->media);
3192        lp->media = INIT;
3193        break;
3194    }
3195
3196    return next_tick;
3197}
3198
3199static int
3200srom_autoconf(struct net_device *dev)
3201{
3202    struct de4x5_private *lp = netdev_priv(dev);
3203
3204    return lp->infoleaf_fn(dev);
3205}
3206
3207/*
3208** This mapping keeps the original media codes and FDX flag unchanged.
3209** While it isn't strictly necessary, it helps me for the moment...
3210** The early return avoids a media state / SROM media space clash.
3211*/
3212static int
3213srom_map_media(struct net_device *dev)
3214{
3215    struct de4x5_private *lp = netdev_priv(dev);
3216
3217    lp->fdx = false;
3218    if (lp->infoblock_media == lp->media)
3219      return 0;
3220
3221    switch(lp->infoblock_media) {
3222      case SROM_10BASETF:
3223        if (!lp->params.fdx) return -1;
3224        lp->fdx = true;
3225      case SROM_10BASET:
3226        if (lp->params.fdx && !lp->fdx) return -1;
3227        if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3228            lp->media = _10Mb;
3229        } else {
3230            lp->media = TP;
3231        }
3232        break;
3233
3234      case SROM_10BASE2:
3235        lp->media = BNC;
3236        break;
3237
3238      case SROM_10BASE5:
3239        lp->media = AUI;
3240        break;
3241
3242      case SROM_100BASETF:
3243        if (!lp->params.fdx) return -1;
3244        lp->fdx = true;
3245      case SROM_100BASET:
3246        if (lp->params.fdx && !lp->fdx) return -1;
3247        lp->media = _100Mb;
3248        break;
3249
3250      case SROM_100BASET4:
3251        lp->media = _100Mb;
3252        break;
3253
3254      case SROM_100BASEFF:
3255        if (!lp->params.fdx) return -1;
3256        lp->fdx = true;
3257      case SROM_100BASEF:
3258        if (lp->params.fdx && !lp->fdx) return -1;
3259        lp->media = _100Mb;
3260        break;
3261
3262      case ANS:
3263        lp->media = ANS;
3264        lp->fdx = lp->params.fdx;
3265        break;
3266
3267      default:
3268        printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3269                                                          lp->infoblock_media);
3270        return -1;
3271        break;
3272    }
3273
3274    return 0;
3275}
3276
3277static void
3278de4x5_init_connection(struct net_device *dev)
3279{
3280    struct de4x5_private *lp = netdev_priv(dev);
3281    u_long iobase = dev->base_addr;
3282    u_long flags = 0;
3283
3284    if (lp->media != lp->c_media) {
3285        de4x5_dbg_media(dev);
3286        lp->c_media = lp->media;          /* Stop scrolling media messages */
3287    }
3288
3289    spin_lock_irqsave(&lp->lock, flags);
3290    de4x5_rst_desc_ring(dev);
3291    de4x5_setup_intr(dev);
3292    lp->tx_enable = true;
3293    spin_unlock_irqrestore(&lp->lock, flags);
3294    outl(POLL_DEMAND, DE4X5_TPD);
3295
3296    netif_wake_queue(dev);
3297
3298    return;
3299}
3300
3301/*
3302** General PHY reset function. Some MII devices don't reset correctly
3303** since their MII address pins can float at voltages that are dependent
3304** on the signal pin use. Do a double reset to ensure a reset.
3305*/
3306static int
3307de4x5_reset_phy(struct net_device *dev)
3308{
3309    struct de4x5_private *lp = netdev_priv(dev);
3310    u_long iobase = dev->base_addr;
3311    int next_tick = 0;
3312
3313    if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3314        if (lp->timeout < 0) {
3315            if (lp->useSROM) {
3316                if (lp->phy[lp->active].rst) {
3317                    srom_exec(dev, lp->phy[lp->active].rst);
3318                    srom_exec(dev, lp->phy[lp->active].rst);
3319                } else if (lp->rst) {          /* Type 5 infoblock reset */
3320                    srom_exec(dev, lp->rst);
3321                    srom_exec(dev, lp->rst);
3322                }
3323            } else {
3324                PHY_HARD_RESET;
3325            }
3326            if (lp->useMII) {
3327                mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3328            }
3329        }
3330        if (lp->useMII) {
3331            next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3332        }
3333    } else if (lp->chipset == DC21140) {
3334        PHY_HARD_RESET;
3335    }
3336
3337    return next_tick;
3338}
3339
3340static int
3341test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3342{
3343    struct de4x5_private *lp = netdev_priv(dev);
3344    u_long iobase = dev->base_addr;
3345    s32 sts, csr12;
3346
3347    if (lp->timeout < 0) {
3348        lp->timeout = msec/100;
3349        if (!lp->useSROM) {      /* Already done if by SROM, else dc2104[01] */
3350            reset_init_sia(dev, csr13, csr14, csr15);
3351        }
3352
3353        /* set up the interrupt mask */
3354        outl(irq_mask, DE4X5_IMR);
3355
3356        /* clear all pending interrupts */
3357        sts = inl(DE4X5_STS);
3358        outl(sts, DE4X5_STS);
3359
3360        /* clear csr12 NRA and SRA bits */
3361        if ((lp->chipset == DC21041) || lp->useSROM) {
3362            csr12 = inl(DE4X5_SISR);
3363            outl(csr12, DE4X5_SISR);
3364        }
3365    }
3366
3367    sts = inl(DE4X5_STS) & ~TIMER_CB;
3368
3369    if (!(sts & irqs) && --lp->timeout) {
3370        sts = 100 | TIMER_CB;
3371    } else {
3372        lp->timeout = -1;
3373    }
3374
3375    return sts;
3376}
3377
3378static int
3379test_tp(struct net_device *dev, s32 msec)
3380{
3381    struct de4x5_private *lp = netdev_priv(dev);
3382    u_long iobase = dev->base_addr;
3383    int sisr;
3384
3385    if (lp->timeout < 0) {
3386        lp->timeout = msec/100;
3387    }
3388
3389    sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3390
3391    if (sisr && --lp->timeout) {
3392        sisr = 100 | TIMER_CB;
3393    } else {
3394        lp->timeout = -1;
3395    }
3396
3397    return sisr;
3398}
3399
3400/*
3401** Samples the 100Mb Link State Signal. The sample interval is important
3402** because too fast a rate can give erroneous results and confuse the
3403** speed sense algorithm.
3404*/
3405#define SAMPLE_INTERVAL 500  /* ms */
3406#define SAMPLE_DELAY    2000 /* ms */
3407static int
3408test_for_100Mb(struct net_device *dev, int msec)
3409{
3410    struct de4x5_private *lp = netdev_priv(dev);
3411    int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3412
3413    if (lp->timeout < 0) {
3414        if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3415        if (msec > SAMPLE_DELAY) {
3416            lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3417            gep = SAMPLE_DELAY | TIMER_CB;
3418            return gep;
3419        } else {
3420            lp->timeout = msec/SAMPLE_INTERVAL;
3421        }
3422    }
3423
3424    if (lp->phy[lp->active].id || lp->useSROM) {
3425        gep = is_100_up(dev) | is_spd_100(dev);
3426    } else {
3427        gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3428    }
3429    if (!(gep & ret) && --lp->timeout) {
3430        gep = SAMPLE_INTERVAL | TIMER_CB;
3431    } else {
3432        lp->timeout = -1;
3433    }
3434
3435    return gep;
3436}
3437
3438static int
3439wait_for_link(struct net_device *dev)
3440{
3441    struct de4x5_private *lp = netdev_priv(dev);
3442
3443    if (lp->timeout < 0) {
3444        lp->timeout = 1;
3445    }
3446
3447    if (lp->timeout--) {
3448        return TIMER_CB;
3449    } else {
3450        lp->timeout = -1;
3451    }
3452
3453    return 0;
3454}
3455
3456/*
3457**
3458**
3459*/
3460static int
3461test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3462{
3463    struct de4x5_private *lp = netdev_priv(dev);
3464    int test;
3465    u_long iobase = dev->base_addr;
3466
3467    if (lp->timeout < 0) {
3468        lp->timeout = msec/100;
3469    }
3470
3471    reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3472    test = (reg ^ (pol ? ~0 : 0)) & mask;
3473
3474    if (test && --lp->timeout) {
3475        reg = 100 | TIMER_CB;
3476    } else {
3477        lp->timeout = -1;
3478    }
3479
3480    return reg;
3481}
3482
3483static int
3484is_spd_100(struct net_device *dev)
3485{
3486    struct de4x5_private *lp = netdev_priv(dev);
3487    u_long iobase = dev->base_addr;
3488    int spd;
3489
3490    if (lp->useMII) {
3491        spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3492        spd = ~(spd ^ lp->phy[lp->active].spd.value);
3493        spd &= lp->phy[lp->active].spd.mask;
3494    } else if (!lp->useSROM) {                      /* de500-xa */
3495        spd = ((~gep_rd(dev)) & GEP_SLNK);
3496    } else {
3497        if ((lp->ibn == 2) || !lp->asBitValid)
3498            return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3499
3500        spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3501                  (lp->linkOK & ~lp->asBitValid);
3502    }
3503
3504    return spd;
3505}
3506
3507static int
3508is_100_up(struct net_device *dev)
3509{
3510    struct de4x5_private *lp = netdev_priv(dev);
3511    u_long iobase = dev->base_addr;
3512
3513    if (lp->useMII) {
3514        /* Double read for sticky bits & temporary drops */
3515        mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3516        return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3517    } else if (!lp->useSROM) {                       /* de500-xa */
3518        return ((~gep_rd(dev)) & GEP_SLNK);
3519    } else {
3520        if ((lp->ibn == 2) || !lp->asBitValid)
3521            return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3522
3523        return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3524                (lp->linkOK & ~lp->asBitValid));
3525    }
3526}
3527
3528static int
3529is_10_up(struct net_device *dev)
3530{
3531    struct de4x5_private *lp = netdev_priv(dev);
3532    u_long iobase = dev->base_addr;
3533
3534    if (lp->useMII) {
3535        /* Double read for sticky bits & temporary drops */
3536        mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3537        return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3538    } else if (!lp->useSROM) {                       /* de500-xa */
3539        return ((~gep_rd(dev)) & GEP_LNP);
3540    } else {
3541        if ((lp->ibn == 2) || !lp->asBitValid)
3542            return (((lp->chipset & ~0x00ff) == DC2114x) ?
3543                    (~inl(DE4X5_SISR)&SISR_LS10):
3544                    0);
3545
3546        return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3547                (lp->linkOK & ~lp->asBitValid));
3548    }
3549}
3550
3551static int
3552is_anc_capable(struct net_device *dev)
3553{
3554    struct de4x5_private *lp = netdev_priv(dev);
3555    u_long iobase = dev->base_addr;
3556
3557    if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3558        return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3559    } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3560        return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3561    } else {
3562        return 0;
3563    }
3564}
3565
3566/*
3567** Send a packet onto the media and watch for send errors that indicate the
3568** media is bad or unconnected.
3569*/
3570static int
3571ping_media(struct net_device *dev, int msec)
3572{
3573    struct de4x5_private *lp = netdev_priv(dev);
3574    u_long iobase = dev->base_addr;
3575    int sisr;
3576
3577    if (lp->timeout < 0) {
3578        lp->timeout = msec/100;
3579
3580        lp->tmp = lp->tx_new;                /* Remember the ring position */
3581        load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3582        lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3583        outl(POLL_DEMAND, DE4X5_TPD);
3584    }
3585
3586    sisr = inl(DE4X5_SISR);
3587
3588    if ((!(sisr & SISR_NCR)) &&
3589        ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3590         (--lp->timeout)) {
3591        sisr = 100 | TIMER_CB;
3592    } else {
3593        if ((!(sisr & SISR_NCR)) &&
3594            !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3595            lp->timeout) {
3596            sisr = 0;
3597        } else {
3598            sisr = 1;
3599        }
3600        lp->timeout = -1;
3601    }
3602
3603    return sisr;
3604}
3605
3606/*
3607** This function does 2 things: on Intels it kmalloc's another buffer to
3608** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3609** into which the packet is copied.
3610*/
3611static struct sk_buff *
3612de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3613{
3614    struct de4x5_private *lp = netdev_priv(dev);
3615    struct sk_buff *p;
3616
3617#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3618    struct sk_buff *ret;
3619    u_long i=0, tmp;
3620
3621    p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3622    if (!p) return NULL;
3623
3624    tmp = virt_to_bus(p->data);
3625    i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3626    skb_reserve(p, i);
3627    lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3628
3629    ret = lp->rx_skb[index];
3630    lp->rx_skb[index] = p;
3631
3632    if ((u_long) ret > 1) {
3633        skb_put(ret, len);
3634    }
3635
3636    return ret;
3637
3638#else
3639    if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3640
3641    p = dev_alloc_skb(len + 2);
3642    if (!p) return NULL;
3643
3644    skb_reserve(p, 2);                                 /* Align */
3645    if (index < lp->rx_old) {                          /* Wrapped buffer */
3646        short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3647        memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3648        memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3649    } else {                                           /* Linear buffer */
3650        memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3651    }
3652
3653    return p;
3654#endif
3655}
3656
3657static void
3658de4x5_free_rx_buffs(struct net_device *dev)
3659{
3660    struct de4x5_private *lp = netdev_priv(dev);
3661    int i;
3662
3663    for (i=0; i<lp->rxRingSize; i++) {
3664        if ((u_long) lp->rx_skb[i] > 1) {
3665            dev_kfree_skb(lp->rx_skb[i]);
3666        }
3667        lp->rx_ring[i].status = 0;
3668        lp->rx_skb[i] = (struct sk_buff *)1;    /* Dummy entry */
3669    }
3670
3671    return;
3672}
3673
3674static void
3675de4x5_free_tx_buffs(struct net_device *dev)
3676{
3677    struct de4x5_private *lp = netdev_priv(dev);
3678    int i;
3679
3680    for (i=0; i<lp->txRingSize; i++) {
3681        if (lp->tx_skb[i])
3682            de4x5_free_tx_buff(lp, i);
3683        lp->tx_ring[i].status = 0;
3684    }
3685
3686    /* Unload the locally queued packets */
3687    __skb_queue_purge(&lp->cache.queue);
3688}
3689
3690/*
3691** When a user pulls a connection, the DECchip can end up in a
3692** 'running - waiting for end of transmission' state. This means that we
3693** have to perform a chip soft reset to ensure that we can synchronize
3694** the hardware and software and make any media probes using a loopback
3695** packet meaningful.
3696*/
3697static void
3698de4x5_save_skbs(struct net_device *dev)
3699{
3700    struct de4x5_private *lp = netdev_priv(dev);
3701    u_long iobase = dev->base_addr;
3702    s32 omr;
3703
3704    if (!lp->cache.save_cnt) {
3705        STOP_DE4X5;
3706        de4x5_tx(dev);                          /* Flush any sent skb's */
3707        de4x5_free_tx_buffs(dev);
3708        de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3709        de4x5_sw_reset(dev);
3710        de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3711        lp->cache.save_cnt++;
3712        START_DE4X5;
3713    }
3714
3715    return;
3716}
3717
3718static void
3719de4x5_rst_desc_ring(struct net_device *dev)
3720{
3721    struct de4x5_private *lp = netdev_priv(dev);
3722    u_long iobase = dev->base_addr;
3723    int i;
3724    s32 omr;
3725
3726    if (lp->cache.save_cnt) {
3727        STOP_DE4X5;
3728        outl(lp->dma_rings, DE4X5_RRBA);
3729        outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3730             DE4X5_TRBA);
3731
3732        lp->rx_new = lp->rx_old = 0;
3733        lp->tx_new = lp->tx_old = 0;
3734
3735        for (i = 0; i < lp->rxRingSize; i++) {
3736            lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3737        }
3738
3739        for (i = 0; i < lp->txRingSize; i++) {
3740            lp->tx_ring[i].status = cpu_to_le32(0);
3741        }
3742
3743        barrier();
3744        lp->cache.save_cnt--;
3745        START_DE4X5;
3746    }
3747
3748    return;
3749}
3750
3751static void
3752de4x5_cache_state(struct net_device *dev, int flag)
3753{
3754    struct de4x5_private *lp = netdev_priv(dev);
3755    u_long iobase = dev->base_addr;
3756
3757    switch(flag) {
3758      case DE4X5_SAVE_STATE:
3759        lp->cache.csr0 = inl(DE4X5_BMR);
3760        lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3761        lp->cache.csr7 = inl(DE4X5_IMR);
3762        break;
3763
3764      case DE4X5_RESTORE_STATE:
3765        outl(lp->cache.csr0, DE4X5_BMR);
3766        outl(lp->cache.csr6, DE4X5_OMR);
3767        outl(lp->cache.csr7, DE4X5_IMR);
3768        if (lp->chipset == DC21140) {
3769            gep_wr(lp->cache.gepc, dev);
3770            gep_wr(lp->cache.gep, dev);
3771        } else {
3772            reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3773                                                              lp->cache.csr15);
3774        }
3775        break;
3776    }
3777
3778    return;
3779}
3780
3781static void
3782de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3783{
3784    struct de4x5_private *lp = netdev_priv(dev);
3785
3786    __skb_queue_tail(&lp->cache.queue, skb);
3787}
3788
3789static void
3790de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3791{
3792    struct de4x5_private *lp = netdev_priv(dev);
3793
3794    __skb_queue_head(&lp->cache.queue, skb);
3795}
3796
3797static struct sk_buff *
3798de4x5_get_cache(struct net_device *dev)
3799{
3800    struct de4x5_private *lp = netdev_priv(dev);
3801
3802    return __skb_dequeue(&lp->cache.queue);
3803}
3804
3805/*
3806** Check the Auto Negotiation State. Return OK when a link pass interrupt
3807** is received and the auto-negotiation status is NWAY OK.
3808*/
3809static int
3810test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3811{
3812    struct de4x5_private *lp = netdev_priv(dev);
3813    u_long iobase = dev->base_addr;
3814    s32 sts, ans;
3815
3816    if (lp->timeout < 0) {
3817        lp->timeout = msec/100;
3818        outl(irq_mask, DE4X5_IMR);
3819
3820        /* clear all pending interrupts */
3821        sts = inl(DE4X5_STS);
3822        outl(sts, DE4X5_STS);
3823    }
3824
3825    ans = inl(DE4X5_SISR) & SISR_ANS;
3826    sts = inl(DE4X5_STS) & ~TIMER_CB;
3827
3828    if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3829        sts = 100 | TIMER_CB;
3830    } else {
3831        lp->timeout = -1;
3832    }
3833
3834    return sts;
3835}
3836
3837static void
3838de4x5_setup_intr(struct net_device *dev)
3839{
3840    struct de4x5_private *lp = netdev_priv(dev);
3841    u_long iobase = dev->base_addr;
3842    s32 imr, sts;
3843
3844    if (inl(DE4X5_OMR) & OMR_SR) {   /* Only unmask if TX/RX is enabled */
3845        imr = 0;
3846        UNMASK_IRQs;
3847        sts = inl(DE4X5_STS);        /* Reset any pending (stale) interrupts */
3848        outl(sts, DE4X5_STS);
3849        ENABLE_IRQs;
3850    }
3851
3852    return;
3853}
3854
3855/*
3856**
3857*/
3858static void
3859reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3860{
3861    struct de4x5_private *lp = netdev_priv(dev);
3862    u_long iobase = dev->base_addr;
3863
3864    RESET_SIA;
3865    if (lp->useSROM) {
3866        if (lp->ibn == 3) {
3867            srom_exec(dev, lp->phy[lp->active].rst);
3868            srom_exec(dev, lp->phy[lp->active].gep);
3869            outl(1, DE4X5_SICR);
3870            return;
3871        } else {
3872            csr15 = lp->cache.csr15;
3873            csr14 = lp->cache.csr14;
3874            csr13 = lp->cache.csr13;
3875            outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3876            outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3877        }
3878    } else {
3879        outl(csr15, DE4X5_SIGR);
3880    }
3881    outl(csr14, DE4X5_STRR);
3882    outl(csr13, DE4X5_SICR);
3883
3884    mdelay(10);
3885
3886    return;
3887}
3888
3889/*
3890** Create a loopback ethernet packet
3891*/
3892static void
3893create_packet(struct net_device *dev, char *frame, int len)
3894{
3895    int i;
3896    char *buf = frame;
3897
3898    for (i=0; i<ETH_ALEN; i++) {             /* Use this source address */
3899        *buf++ = dev->dev_addr[i];
3900    }
3901    for (i=0; i<ETH_ALEN; i++) {             /* Use this destination address */
3902        *buf++ = dev->dev_addr[i];
3903    }
3904
3905    *buf++ = 0;                              /* Packet length (2 bytes) */
3906    *buf++ = 1;
3907
3908    return;
3909}
3910
3911/*
3912** Look for a particular board name in the EISA configuration space
3913*/
3914static int
3915EISA_signature(char *name, struct device *device)
3916{
3917    int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3918    struct eisa_device *edev;
3919
3920    *name = '\0';
3921    edev = to_eisa_device (device);
3922    i = edev->id.driver_data;
3923
3924    if (i >= 0 && i < siglen) {
3925            strcpy (name, de4x5_signatures[i]);
3926            status = 1;
3927    }
3928
3929    return status;                         /* return the device name string */
3930}
3931
3932/*
3933** Look for a particular board name in the PCI configuration space
3934*/
3935static int
3936PCI_signature(char *name, struct de4x5_private *lp)
3937{
3938    int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3939
3940    if (lp->chipset == DC21040) {
3941        strcpy(name, "DE434/5");
3942        return status;
3943    } else {                           /* Search for a DEC name in the SROM */
3944        int tmp = *((char *)&lp->srom + 19) * 3;
3945        strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3946    }
3947    name[8] = '\0';
3948    for (i=0; i<siglen; i++) {
3949        if (strstr(name,de4x5_signatures[i])!=NULL) break;
3950    }
3951    if (i == siglen) {
3952        if (dec_only) {
3953            *name = '\0';
3954        } else {                        /* Use chip name to avoid confusion */
3955            strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3956                           ((lp->chipset == DC21041) ? "DC21041" :
3957                            ((lp->chipset == DC21140) ? "DC21140" :
3958                             ((lp->chipset == DC21142) ? "DC21142" :
3959                              ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3960                             )))))));
3961        }
3962        if (lp->chipset != DC21041) {
3963            lp->useSROM = true;             /* card is not recognisably DEC */
3964        }
3965    } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3966        lp->useSROM = true;
3967    }
3968
3969    return status;
3970}
3971
3972/*
3973** Set up the Ethernet PROM counter to the start of the Ethernet address on
3974** the DC21040, else  read the SROM for the other chips.
3975** The SROM may not be present in a multi-MAC card, so first read the
3976** MAC address and check for a bad address. If there is a bad one then exit
3977** immediately with the prior srom contents intact (the h/w address will
3978** be fixed up later).
3979*/
3980static void
3981DevicePresent(struct net_device *dev, u_long aprom_addr)
3982{
3983    int i, j=0;
3984    struct de4x5_private *lp = netdev_priv(dev);
3985
3986    if (lp->chipset == DC21040) {
3987        if (lp->bus == EISA) {
3988            enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3989        } else {
3990            outl(0, aprom_addr);       /* Reset Ethernet Address ROM Pointer */
3991        }
3992    } else {                           /* Read new srom */
3993        u_short tmp;
3994        __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3995        for (i=0; i<(ETH_ALEN>>1); i++) {
3996            tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3997            j += tmp;   /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3998            *p = cpu_to_le16(tmp);
3999        }
4000        if (j == 0 || j == 3 * 0xffff) {
4001                /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
4002                return;
4003        }
4004
4005        p = (__le16 *)&lp->srom;
4006        for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4007            tmp = srom_rd(aprom_addr, i);
4008            *p++ = cpu_to_le16(tmp);
4009        }
4010        de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4011    }
4012
4013    return;
4014}
4015
4016/*
4017** Since the write on the Enet PROM register doesn't seem to reset the PROM
4018** pointer correctly (at least on my DE425 EISA card), this routine should do
4019** it...from depca.c.
4020*/
4021static void
4022enet_addr_rst(u_long aprom_addr)
4023{
4024    union {
4025        struct {
4026            u32 a;
4027            u32 b;
4028        } llsig;
4029        char Sig[sizeof(u32) << 1];
4030    } dev;
4031    short sigLength=0;
4032    s8 data;
4033    int i, j;
4034
4035    dev.llsig.a = ETH_PROM_SIG;
4036    dev.llsig.b = ETH_PROM_SIG;
4037    sigLength = sizeof(u32) << 1;
4038
4039    for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4040        data = inb(aprom_addr);
4041        if (dev.Sig[j] == data) {    /* track signature */
4042            j++;
4043        } else {                     /* lost signature; begin search again */
4044            if (data == dev.Sig[0]) {  /* rare case.... */
4045                j=1;
4046            } else {
4047                j=0;
4048            }
4049        }
4050    }
4051
4052    return;
4053}
4054
4055/*
4056** For the bad status case and no SROM, then add one to the previous
4057** address. However, need to add one backwards in case we have 0xff
4058** as one or more of the bytes. Only the last 3 bytes should be checked
4059** as the first three are invariant - assigned to an organisation.
4060*/
4061static int
4062get_hw_addr(struct net_device *dev)
4063{
4064    u_long iobase = dev->base_addr;
4065    int broken, i, k, tmp, status = 0;
4066    u_short j,chksum;
4067    struct de4x5_private *lp = netdev_priv(dev);
4068
4069    broken = de4x5_bad_srom(lp);
4070
4071    for (i=0,k=0,j=0;j<3;j++) {
4072        k <<= 1;
4073        if (k > 0xffff) k-=0xffff;
4074
4075        if (lp->bus == PCI) {
4076            if (lp->chipset == DC21040) {
4077                while ((tmp = inl(DE4X5_APROM)) < 0);
4078                k += (u_char) tmp;
4079                dev->dev_addr[i++] = (u_char) tmp;
4080                while ((tmp = inl(DE4X5_APROM)) < 0);
4081                k += (u_short) (tmp << 8);
4082                dev->dev_addr[i++] = (u_char) tmp;
4083            } else if (!broken) {
4084                dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4085                dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4086            } else if ((broken == SMC) || (broken == ACCTON)) {
4087                dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4088                dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4089            }
4090        } else {
4091            k += (u_char) (tmp = inb(EISA_APROM));
4092            dev->dev_addr[i++] = (u_char) tmp;
4093            k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4094            dev->dev_addr[i++] = (u_char) tmp;
4095        }
4096
4097        if (k > 0xffff) k-=0xffff;
4098    }
4099    if (k == 0xffff) k=0;
4100
4101    if (lp->bus == PCI) {
4102        if (lp->chipset == DC21040) {
4103            while ((tmp = inl(DE4X5_APROM)) < 0);
4104            chksum = (u_char) tmp;
4105            while ((tmp = inl(DE4X5_APROM)) < 0);
4106            chksum |= (u_short) (tmp << 8);
4107            if ((k != chksum) && (dec_only)) status = -1;
4108        }
4109    } else {
4110        chksum = (u_char) inb(EISA_APROM);
4111        chksum |= (u_short) (inb(EISA_APROM) << 8);
4112        if ((k != chksum) && (dec_only)) status = -1;
4113    }
4114
4115    /* If possible, try to fix a broken card - SMC only so far */
4116    srom_repair(dev, broken);
4117
4118#ifdef CONFIG_PPC_PMAC
4119    /*
4120    ** If the address starts with 00 a0, we have to bit-reverse
4121    ** each byte of the address.
4122    */
4123    if ( machine_is(powermac) &&
4124         (dev->dev_addr[0] == 0) &&
4125         (dev->dev_addr[1] == 0xa0) )
4126    {
4127            for (i = 0; i < ETH_ALEN; ++i)
4128            {
4129                    int x = dev->dev_addr[i];
4130                    x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4131                    x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4132                    dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4133            }
4134    }
4135#endif /* CONFIG_PPC_PMAC */
4136
4137    /* Test for a bad enet address */
4138    status = test_bad_enet(dev, status);
4139
4140    return status;
4141}
4142
4143/*
4144** Test for enet addresses in the first 32 bytes. The built-in strncmp
4145** didn't seem to work here...?
4146*/
4147static int
4148de4x5_bad_srom(struct de4x5_private *lp)
4149{
4150    int i, status = 0;
4151
4152    for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4153        if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4154            !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4155            if (i == 0) {
4156                status = SMC;
4157            } else if (i == 1) {
4158                status = ACCTON;
4159            }
4160            break;
4161        }
4162    }
4163
4164    return status;
4165}
4166
4167static int
4168de4x5_strncmp(char *a, char *b, int n)
4169{
4170    int ret=0;
4171
4172    for (;n && !ret; n--) {
4173        ret = *a++ - *b++;
4174    }
4175
4176    return ret;
4177}
4178
4179static void
4180srom_repair(struct net_device *dev, int card)
4181{
4182    struct de4x5_private *lp = netdev_priv(dev);
4183
4184    switch(card) {
4185      case SMC:
4186        memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4187        memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4188        memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4189        lp->useSROM = true;
4190        break;
4191    }
4192
4193    return;
4194}
4195
4196/*
4197** Assume that the irq's do not follow the PCI spec - this is seems
4198** to be true so far (2 for 2).
4199*/
4200static int
4201test_bad_enet(struct net_device *dev, int status)
4202{
4203    struct de4x5_private *lp = netdev_priv(dev);
4204    int i, tmp;
4205
4206    for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4207    if ((tmp == 0) || (tmp == 0x5fa)) {
4208        if ((lp->chipset == last.chipset) &&
4209            (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4210            for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4211            for (i=ETH_ALEN-1; i>2; --i) {
4212                dev->dev_addr[i] += 1;
4213                if (dev->dev_addr[i] != 0) break;
4214            }
4215            for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4216            if (!an_exception(lp)) {
4217                dev->irq = last.irq;
4218            }
4219
4220            status = 0;
4221        }
4222    } else if (!status) {
4223        last.chipset = lp->chipset;
4224        last.bus = lp->bus_num;
4225        last.irq = dev->irq;
4226        for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4227    }
4228
4229    return status;
4230}
4231
4232/*
4233** List of board exceptions with correctly wired IRQs
4234*/
4235static int
4236an_exception(struct de4x5_private *lp)
4237{
4238    if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4239        (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4240        return -1;
4241    }
4242
4243    return 0;
4244}
4245
4246/*
4247** SROM Read
4248*/
4249static short
4250srom_rd(u_long addr, u_char offset)
4251{
4252    sendto_srom(SROM_RD | SROM_SR, addr);
4253
4254    srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4255    srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4256    srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4257
4258    return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4259}
4260
4261static void
4262srom_latch(u_int command, u_long addr)
4263{
4264    sendto_srom(command, addr);
4265    sendto_srom(command | DT_CLK, addr);
4266    sendto_srom(command, addr);
4267
4268    return;
4269}
4270
4271static void
4272srom_command(u_int command, u_long addr)
4273{
4274    srom_latch(command, addr);
4275    srom_latch(command, addr);
4276    srom_latch((command & 0x0000ff00) | DT_CS, addr);
4277
4278    return;
4279}
4280
4281static void
4282srom_address(u_int command, u_long addr, u_char offset)
4283{
4284    int i, a;
4285
4286    a = offset << 2;
4287    for (i=0; i<6; i++, a <<= 1) {
4288        srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4289    }
4290    udelay(1);
4291
4292    i = (getfrom_srom(addr) >> 3) & 0x01;
4293
4294    return;
4295}
4296
4297static short
4298srom_data(u_int command, u_long addr)
4299{
4300    int i;
4301    short word = 0;
4302    s32 tmp;
4303
4304    for (i=0; i<16; i++) {
4305        sendto_srom(command  | DT_CLK, addr);
4306        tmp = getfrom_srom(addr);
4307        sendto_srom(command, addr);
4308
4309        word = (word << 1) | ((tmp >> 3) & 0x01);
4310    }
4311
4312    sendto_srom(command & 0x0000ff00, addr);
4313
4314    return word;
4315}
4316
4317/*
4318static void
4319srom_busy(u_int command, u_long addr)
4320{
4321   sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4322
4323   while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4324       mdelay(1);
4325   }
4326
4327   sendto_srom(command & 0x0000ff00, addr);
4328
4329   return;
4330}
4331*/
4332
4333static void
4334sendto_srom(u_int command, u_long addr)
4335{
4336    outl(command, addr);
4337    udelay(1);
4338
4339    return;
4340}
4341
4342static int
4343getfrom_srom(u_long addr)
4344{
4345    s32 tmp;
4346
4347    tmp = inl(addr);
4348    udelay(1);
4349
4350    return tmp;
4351}
4352
4353static int
4354srom_infoleaf_info(struct net_device *dev)
4355{
4356    struct de4x5_private *lp = netdev_priv(dev);
4357    int i, count;
4358    u_char *p;
4359
4360    /* Find the infoleaf decoder function that matches this chipset */
4361    for (i=0; i<INFOLEAF_SIZE; i++) {
4362        if (lp->chipset == infoleaf_array[i].chipset) break;
4363    }
4364    if (i == INFOLEAF_SIZE) {
4365        lp->useSROM = false;
4366        printk("%s: Cannot find correct chipset for SROM decoding!\n",
4367                                                                  dev->name);
4368        return -ENXIO;
4369    }
4370
4371    lp->infoleaf_fn = infoleaf_array[i].fn;
4372
4373    /* Find the information offset that this function should use */
4374    count = *((u_char *)&lp->srom + 19);
4375    p  = (u_char *)&lp->srom + 26;
4376
4377    if (count > 1) {
4378        for (i=count; i; --i, p+=3) {
4379            if (lp->device == *p) break;
4380        }
4381        if (i == 0) {
4382            lp->useSROM = false;
4383            printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4384                                                       dev->name, lp->device);
4385            return -ENXIO;
4386        }
4387    }
4388
4389        lp->infoleaf_offset = get_unaligned_le16(p + 1);
4390
4391    return 0;
4392}
4393
4394/*
4395** This routine loads any type 1 or 3 MII info into the mii device
4396** struct and executes any type 5 code to reset PHY devices for this
4397** controller.
4398** The info for the MII devices will be valid since the index used
4399** will follow the discovery process from MII address 1-31 then 0.
4400*/
4401static void
4402srom_init(struct net_device *dev)
4403{
4404    struct de4x5_private *lp = netdev_priv(dev);
4405    u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4406    u_char count;
4407
4408    p+=2;
4409    if (lp->chipset == DC21140) {
4410        lp->cache.gepc = (*p++ | GEP_CTRL);
4411        gep_wr(lp->cache.gepc, dev);
4412    }
4413
4414    /* Block count */
4415    count = *p++;
4416
4417    /* Jump the infoblocks to find types */
4418    for (;count; --count) {
4419        if (*p < 128) {
4420            p += COMPACT_LEN;
4421        } else if (*(p+1) == 5) {
4422            type5_infoblock(dev, 1, p);
4423            p += ((*p & BLOCK_LEN) + 1);
4424        } else if (*(p+1) == 4) {
4425            p += ((*p & BLOCK_LEN) + 1);
4426        } else if (*(p+1) == 3) {
4427            type3_infoblock(dev, 1, p);
4428            p += ((*p & BLOCK_LEN) + 1);
4429        } else if (*(p+1) == 2) {
4430            p += ((*p & BLOCK_LEN) + 1);
4431        } else if (*(p+1) == 1) {
4432            type1_infoblock(dev, 1, p);
4433            p += ((*p & BLOCK_LEN) + 1);
4434        } else {
4435            p += ((*p & BLOCK_LEN) + 1);
4436        }
4437    }
4438
4439    return;
4440}
4441
4442/*
4443** A generic routine that writes GEP control, data and reset information
4444** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4445*/
4446static void
4447srom_exec(struct net_device *dev, u_char *p)
4448{
4449    struct de4x5_private *lp = netdev_priv(dev);
4450    u_long iobase = dev->base_addr;
4451    u_char count = (p ? *p++ : 0);
4452    u_short *w = (u_short *)p;
4453
4454    if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4455
4456    if (lp->chipset != DC21140) RESET_SIA;
4457
4458    while (count--) {
4459        gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4460                                                   *p++ : get_unaligned_le16(w++)), dev);
4461        mdelay(2);                          /* 2ms per action */
4462    }
4463
4464    if (lp->chipset != DC21140) {
4465        outl(lp->cache.csr14, DE4X5_STRR);
4466        outl(lp->cache.csr13, DE4X5_SICR);
4467    }
4468
4469    return;
4470}
4471
4472/*
4473** Basically this function is a NOP since it will never be called,
4474** unless I implement the DC21041 SROM functions. There's no need
4475** since the existing code will be satisfactory for all boards.
4476*/
4477static int
4478dc21041_infoleaf(struct net_device *dev)
4479{
4480    return DE4X5_AUTOSENSE_MS;
4481}
4482
4483static int
4484dc21140_infoleaf(struct net_device *dev)
4485{
4486    struct de4x5_private *lp = netdev_priv(dev);
4487    u_char count = 0;
4488    u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4489    int next_tick = DE4X5_AUTOSENSE_MS;
4490
4491    /* Read the connection type */
4492    p+=2;
4493
4494    /* GEP control */
4495    lp->cache.gepc = (*p++ | GEP_CTRL);
4496
4497    /* Block count */
4498    count = *p++;
4499
4500    /* Recursively figure out the info blocks */
4501    if (*p < 128) {
4502        next_tick = dc_infoblock[COMPACT](dev, count, p);
4503    } else {
4504        next_tick = dc_infoblock[*(p+1)](dev, count, p);
4505    }
4506
4507    if (lp->tcount == count) {
4508        lp->media = NC;
4509        if (lp->media != lp->c_media) {
4510            de4x5_dbg_media(dev);
4511            lp->c_media = lp->media;
4512        }
4513        lp->media = INIT;
4514        lp->tcount = 0;
4515        lp->tx_enable = false;
4516    }
4517
4518    return next_tick & ~TIMER_CB;
4519}
4520
4521static int
4522dc21142_infoleaf(struct net_device *dev)
4523{
4524    struct de4x5_private *lp = netdev_priv(dev);
4525    u_char count = 0;
4526    u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4527    int next_tick = DE4X5_AUTOSENSE_MS;
4528
4529    /* Read the connection type */
4530    p+=2;
4531
4532    /* Block count */
4533    count = *p++;
4534
4535    /* Recursively figure out the info blocks */
4536    if (*p < 128) {
4537        next_tick = dc_infoblock[COMPACT](dev, count, p);
4538    } else {
4539        next_tick = dc_infoblock[*(p+1)](dev, count, p);
4540    }
4541
4542    if (lp->tcount == count) {
4543        lp->media = NC;
4544        if (lp->media != lp->c_media) {
4545            de4x5_dbg_media(dev);
4546            lp->c_media = lp->media;
4547        }
4548        lp->media = INIT;
4549        lp->tcount = 0;
4550        lp->tx_enable = false;
4551    }
4552
4553    return next_tick & ~TIMER_CB;
4554}
4555
4556static int
4557dc21143_infoleaf(struct net_device *dev)
4558{
4559    struct de4x5_private *lp = netdev_priv(dev);
4560    u_char count = 0;
4561    u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4562    int next_tick = DE4X5_AUTOSENSE_MS;
4563
4564    /* Read the connection type */
4565    p+=2;
4566
4567    /* Block count */
4568    count = *p++;
4569
4570    /* Recursively figure out the info blocks */
4571    if (*p < 128) {
4572        next_tick = dc_infoblock[COMPACT](dev, count, p);
4573    } else {
4574        next_tick = dc_infoblock[*(p+1)](dev, count, p);
4575    }
4576    if (lp->tcount == count) {
4577        lp->media = NC;
4578        if (lp->media != lp->c_media) {
4579            de4x5_dbg_media(dev);
4580            lp->c_media = lp->media;
4581        }
4582        lp->media = INIT;
4583        lp->tcount = 0;
4584        lp->tx_enable = false;
4585    }
4586
4587    return next_tick & ~TIMER_CB;
4588}
4589
4590/*
4591** The compact infoblock is only designed for DC21140[A] chips, so
4592** we'll reuse the dc21140m_autoconf function. Non MII media only.
4593*/
4594static int
4595compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4596{
4597    struct de4x5_private *lp = netdev_priv(dev);
4598    u_char flags, csr6;
4599
4600    /* Recursively figure out the info blocks */
4601    if (--count > lp->tcount) {
4602        if (*(p+COMPACT_LEN) < 128) {
4603            return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4604        } else {
4605            return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4606        }
4607    }
4608
4609    if ((lp->media == INIT) && (lp->timeout < 0)) {
4610        lp->ibn = COMPACT;
4611        lp->active = 0;
4612        gep_wr(lp->cache.gepc, dev);
4613        lp->infoblock_media = (*p++) & COMPACT_MC;
4614        lp->cache.gep = *p++;
4615        csr6 = *p++;
4616        flags = *p++;
4617
4618        lp->asBitValid = (flags & 0x80) ? 0 : -1;
4619        lp->defMedium = (flags & 0x40) ? -1 : 0;
4620        lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4621        lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4622        lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4623        lp->useMII = false;
4624
4625        de4x5_switch_mac_port(dev);
4626    }
4627
4628    return dc21140m_autoconf(dev);
4629}
4630
4631/*
4632** This block describes non MII media for the DC21140[A] only.
4633*/
4634static int
4635type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4636{
4637    struct de4x5_private *lp = netdev_priv(dev);
4638    u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4639
4640    /* Recursively figure out the info blocks */
4641    if (--count > lp->tcount) {
4642        if (*(p+len) < 128) {
4643            return dc_infoblock[COMPACT](dev, count, p+len);
4644        } else {
4645            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4646        }
4647    }
4648
4649    if ((lp->media == INIT) && (lp->timeout < 0)) {
4650        lp->ibn = 0;
4651        lp->active = 0;
4652        gep_wr(lp->cache.gepc, dev);
4653        p+=2;
4654        lp->infoblock_media = (*p++) & BLOCK0_MC;
4655        lp->cache.gep = *p++;
4656        csr6 = *p++;
4657        flags = *p++;
4658
4659        lp->asBitValid = (flags & 0x80) ? 0 : -1;
4660        lp->defMedium = (flags & 0x40) ? -1 : 0;
4661        lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4662        lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4663        lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4664        lp->useMII = false;
4665
4666        de4x5_switch_mac_port(dev);
4667    }
4668
4669    return dc21140m_autoconf(dev);
4670}
4671
4672/* These functions are under construction! */
4673
4674static int
4675type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4676{
4677    struct de4x5_private *lp = netdev_priv(dev);
4678    u_char len = (*p & BLOCK_LEN)+1;
4679
4680    /* Recursively figure out the info blocks */
4681    if (--count > lp->tcount) {
4682        if (*(p+len) < 128) {
4683            return dc_infoblock[COMPACT](dev, count, p+len);
4684        } else {
4685            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4686        }
4687    }
4688
4689    p += 2;
4690    if (lp->state == INITIALISED) {
4691        lp->ibn = 1;
4692        lp->active = *p++;
4693        lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4694        lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4695        lp->phy[lp->active].mc  = get_unaligned_le16(p); p += 2;
4696        lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4697        lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4698        lp->phy[lp->active].ttm = get_unaligned_le16(p);
4699        return 0;
4700    } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4701        lp->ibn = 1;
4702        lp->active = *p;
4703        lp->infoblock_csr6 = OMR_MII_100;
4704        lp->useMII = true;
4705        lp->infoblock_media = ANS;
4706
4707        de4x5_switch_mac_port(dev);
4708    }
4709
4710    return dc21140m_autoconf(dev);
4711}
4712
4713static int
4714type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4715{
4716    struct de4x5_private *lp = netdev_priv(dev);
4717    u_char len = (*p & BLOCK_LEN)+1;
4718
4719    /* Recursively figure out the info blocks */
4720    if (--count > lp->tcount) {
4721        if (*(p+len) < 128) {
4722            return dc_infoblock[COMPACT](dev, count, p+len);
4723        } else {
4724            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4725        }
4726    }
4727
4728    if ((lp->media == INIT) && (lp->timeout < 0)) {
4729        lp->ibn = 2;
4730        lp->active = 0;
4731        p += 2;
4732        lp->infoblock_media = (*p) & MEDIA_CODE;
4733
4734        if ((*p++) & EXT_FIELD) {
4735            lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4736            lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4737            lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4738        } else {
4739            lp->cache.csr13 = CSR13;
4740            lp->cache.csr14 = CSR14;
4741            lp->cache.csr15 = CSR15;
4742        }
4743        lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4744        lp->cache.gep  = ((s32)(get_unaligned_le16(p)) << 16);
4745        lp->infoblock_csr6 = OMR_SIA;
4746        lp->useMII = false;
4747
4748        de4x5_switch_mac_port(dev);
4749    }
4750
4751    return dc2114x_autoconf(dev);
4752}
4753
4754static int
4755type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4756{
4757    struct de4x5_private *lp = netdev_priv(dev);
4758    u_char len = (*p & BLOCK_LEN)+1;
4759
4760    /* Recursively figure out the info blocks */
4761    if (--count > lp->tcount) {
4762        if (*(p+len) < 128) {
4763            return dc_infoblock[COMPACT](dev, count, p+len);
4764        } else {
4765            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4766        }
4767    }
4768
4769    p += 2;
4770    if (lp->state == INITIALISED) {
4771        lp->ibn = 3;
4772        lp->active = *p++;
4773        if (MOTO_SROM_BUG) lp->active = 0;
4774        lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4775        lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4776        lp->phy[lp->active].mc  = get_unaligned_le16(p); p += 2;
4777        lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4778        lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4779        lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4780        lp->phy[lp->active].mci = *p;
4781        return 0;
4782    } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4783        lp->ibn = 3;
4784        lp->active = *p;
4785        if (MOTO_SROM_BUG) lp->active = 0;
4786        lp->infoblock_csr6 = OMR_MII_100;
4787        lp->useMII = true;
4788        lp->infoblock_media = ANS;
4789
4790        de4x5_switch_mac_port(dev);
4791    }
4792
4793    return dc2114x_autoconf(dev);
4794}
4795
4796static int
4797type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4798{
4799    struct de4x5_private *lp = netdev_priv(dev);
4800    u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4801
4802    /* Recursively figure out the info blocks */
4803    if (--count > lp->tcount) {
4804        if (*(p+len) < 128) {
4805            return dc_infoblock[COMPACT](dev, count, p+len);
4806        } else {
4807            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4808        }
4809    }
4810
4811    if ((lp->media == INIT) && (lp->timeout < 0)) {
4812        lp->ibn = 4;
4813        lp->active = 0;
4814        p+=2;
4815        lp->infoblock_media = (*p++) & MEDIA_CODE;
4816        lp->cache.csr13 = CSR13;              /* Hard coded defaults */
4817        lp->cache.csr14 = CSR14;
4818        lp->cache.csr15 = CSR15;
4819        lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4820        lp->cache.gep  = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4821        csr6 = *p++;
4822        flags = *p++;
4823
4824        lp->asBitValid = (flags & 0x80) ? 0 : -1;
4825        lp->defMedium = (flags & 0x40) ? -1 : 0;
4826        lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4827        lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4828        lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4829        lp->useMII = false;
4830
4831        de4x5_switch_mac_port(dev);
4832    }
4833
4834    return dc2114x_autoconf(dev);
4835}
4836
4837/*
4838** This block type provides information for resetting external devices
4839** (chips) through the General Purpose Register.
4840*/
4841static int
4842type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4843{
4844    struct de4x5_private *lp = netdev_priv(dev);
4845    u_char len = (*p & BLOCK_LEN)+1;
4846
4847    /* Recursively figure out the info blocks */
4848    if (--count > lp->tcount) {
4849        if (*(p+len) < 128) {
4850            return dc_infoblock[COMPACT](dev, count, p+len);
4851        } else {
4852            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4853        }
4854    }
4855
4856    /* Must be initializing to run this code */
4857    if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4858        p+=2;
4859        lp->rst = p;
4860        srom_exec(dev, lp->rst);
4861    }
4862
4863    return DE4X5_AUTOSENSE_MS;
4864}
4865
4866/*
4867** MII Read/Write
4868*/
4869
4870static int
4871mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4872{
4873    mii_wdata(MII_PREAMBLE,  2, ioaddr);   /* Start of 34 bit preamble...    */
4874    mii_wdata(MII_PREAMBLE, 32, ioaddr);   /* ...continued                   */
4875    mii_wdata(MII_STRD, 4, ioaddr);        /* SFD and Read operation         */
4876    mii_address(phyaddr, ioaddr);          /* PHY address to be accessed     */
4877    mii_address(phyreg, ioaddr);           /* PHY Register to read           */
4878    mii_ta(MII_STRD, ioaddr);              /* Turn around time - 2 MDC       */
4879
4880    return mii_rdata(ioaddr);              /* Read data                      */
4881}
4882
4883static void
4884mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4885{
4886    mii_wdata(MII_PREAMBLE,  2, ioaddr);   /* Start of 34 bit preamble...    */
4887    mii_wdata(MII_PREAMBLE, 32, ioaddr);   /* ...continued                   */
4888    mii_wdata(MII_STWR, 4, ioaddr);        /* SFD and Write operation        */
4889    mii_address(phyaddr, ioaddr);          /* PHY address to be accessed     */
4890    mii_address(phyreg, ioaddr);           /* PHY Register to write          */
4891    mii_ta(MII_STWR, ioaddr);              /* Turn around time - 2 MDC       */
4892    data = mii_swap(data, 16);             /* Swap data bit ordering         */
4893    mii_wdata(data, 16, ioaddr);           /* Write data                     */
4894
4895    return;
4896}
4897
4898static int
4899mii_rdata(u_long ioaddr)
4900{
4901    int i;
4902    s32 tmp = 0;
4903
4904    for (i=0; i<16; i++) {
4905        tmp <<= 1;
4906        tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4907    }
4908
4909    return tmp;
4910}
4911
4912static void
4913mii_wdata(int data, int len, u_long ioaddr)
4914{
4915    int i;
4916
4917    for (i=0; i<len; i++) {
4918        sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4919        data >>= 1;
4920    }
4921
4922    return;
4923}
4924
4925static void
4926mii_address(u_char addr, u_long ioaddr)
4927{
4928    int i;
4929
4930    addr = mii_swap(addr, 5);
4931    for (i=0; i<5; i++) {
4932        sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4933        addr >>= 1;
4934    }
4935
4936    return;
4937}
4938
4939static void
4940mii_ta(u_long rw, u_long ioaddr)
4941{
4942    if (rw == MII_STWR) {
4943        sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4944        sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4945    } else {
4946        getfrom_mii(MII_MRD | MII_RD, ioaddr);        /* Tri-state MDIO */
4947    }
4948
4949    return;
4950}
4951
4952static int
4953mii_swap(int data, int len)
4954{
4955    int i, tmp = 0;
4956
4957    for (i=0; i<len; i++) {
4958        tmp <<= 1;
4959        tmp |= (data & 1);
4960        data >>= 1;
4961    }
4962
4963    return tmp;
4964}
4965
4966static void
4967sendto_mii(u32 command, int data, u_long ioaddr)
4968{
4969    u32 j;
4970
4971    j = (data & 1) << 17;
4972    outl(command | j, ioaddr);
4973    udelay(1);
4974    outl(command | MII_MDC | j, ioaddr);
4975    udelay(1);
4976
4977    return;
4978}
4979
4980static int
4981getfrom_mii(u32 command, u_long ioaddr)
4982{
4983    outl(command, ioaddr);
4984    udelay(1);
4985    outl(command | MII_MDC, ioaddr);
4986    udelay(1);
4987
4988    return ((inl(ioaddr) >> 19) & 1);
4989}
4990
4991/*
4992** Here's 3 ways to calculate the OUI from the ID registers.
4993*/
4994static int
4995mii_get_oui(u_char phyaddr, u_long ioaddr)
4996{
4997/*
4998    union {
4999        u_short reg;
5000        u_char breg[2];
5001    } a;
5002    int i, r2, r3, ret=0;*/
5003    int r2, r3;
5004
5005    /* Read r2 and r3 */
5006    r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5007    r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5008                                                /* SEEQ and Cypress way * /
5009    / * Shuffle r2 and r3 * /
5010    a.reg=0;
5011    r3 = ((r3>>10)|(r2<<6))&0x0ff;
5012    r2 = ((r2>>2)&0x3fff);
5013
5014    / * Bit reverse r3 * /
5015    for (i=0;i<8;i++) {
5016        ret<<=1;
5017        ret |= (r3&1);
5018        r3>>=1;
5019    }
5020
5021    / * Bit reverse r2 * /
5022    for (i=0;i<16;i++) {
5023        a.reg<<=1;
5024        a.reg |= (r2&1);
5025        r2>>=1;
5026    }
5027
5028    / * Swap r2 bytes * /
5029    i=a.breg[0];
5030    a.breg[0]=a.breg[1];
5031    a.breg[1]=i;
5032
5033    return ((a.reg<<8)|ret); */                 /* SEEQ and Cypress way */
5034/*    return ((r2<<6)|(u_int)(r3>>10)); */      /* NATIONAL and BROADCOM way */
5035    return r2;                                  /* (I did it) My way */
5036}
5037
5038/*
5039** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5040*/
5041static int
5042mii_get_phy(struct net_device *dev)
5043{
5044    struct de4x5_private *lp = netdev_priv(dev);
5045    u_long iobase = dev->base_addr;
5046    int i, j, k, n, limit=ARRAY_SIZE(phy_info);
5047    int id;
5048
5049    lp->active = 0;
5050    lp->useMII = true;
5051
5052    /* Search the MII address space for possible PHY devices */
5053    for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5054        lp->phy[lp->active].addr = i;
5055        if (i==0) n++;                             /* Count cycles */
5056        while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5057        id = mii_get_oui(i, DE4X5_MII);
5058        if ((id == 0) || (id == 65535)) continue;  /* Valid ID? */
5059        for (j=0; j<limit; j++) {                  /* Search PHY table */
5060            if (id != phy_info[j].id) continue;    /* ID match? */
5061            for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5062            if (k < DE4X5_MAX_PHY) {
5063                memcpy((char *)&lp->phy[k],
5064                       (char *)&phy_info[j], sizeof(struct phy_table));
5065                lp->phy[k].addr = i;
5066                lp->mii_cnt++;
5067                lp->active++;
5068            } else {
5069                goto purgatory;                    /* Stop the search */
5070            }
5071            break;
5072        }
5073        if ((j == limit) && (i < DE4X5_MAX_MII)) {
5074            for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5075            lp->phy[k].addr = i;
5076            lp->phy[k].id = id;
5077            lp->phy[k].spd.reg = GENERIC_REG;      /* ANLPA register         */
5078            lp->phy[k].spd.mask = GENERIC_MASK;    /* 100Mb/s technologies   */
5079            lp->phy[k].spd.value = GENERIC_VALUE;  /* TX & T4, H/F Duplex    */
5080            lp->mii_cnt++;
5081            lp->active++;
5082            printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5083            j = de4x5_debug;
5084            de4x5_debug |= DEBUG_MII;
5085            de4x5_dbg_mii(dev, k);
5086            de4x5_debug = j;
5087            printk("\n");
5088        }
5089    }
5090  purgatory:
5091    lp->active = 0;
5092    if (lp->phy[0].id) {                           /* Reset the PHY devices */
5093        for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5094            mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5095            while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5096
5097            de4x5_dbg_mii(dev, k);
5098        }
5099    }
5100    if (!lp->mii_cnt) lp->useMII = false;
5101
5102    return lp->mii_cnt;
5103}
5104
5105static char *
5106build_setup_frame(struct net_device *dev, int mode)
5107{
5108    struct de4x5_private *lp = netdev_priv(dev);
5109    int i;
5110    char *pa = lp->setup_frame;
5111
5112    /* Initialise the setup frame */
5113    if (mode == ALL) {
5114        memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5115    }
5116
5117    if (lp->setup_f == HASH_PERF) {
5118        for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5119            *(pa + i) = dev->dev_addr[i];                 /* Host address */
5120            if (i & 0x01) pa += 2;
5121        }
5122        *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5123    } else {
5124        for (i=0; i<ETH_ALEN; i++) { /* Host address */
5125            *(pa + (i&1)) = dev->dev_addr[i];
5126            if (i & 0x01) pa += 4;
5127        }
5128        for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5129            *(pa + (i&1)) = (char) 0xff;
5130            if (i & 0x01) pa += 4;
5131        }
5132    }
5133
5134    return pa;                     /* Points to the next entry */
5135}
5136
5137static void
5138disable_ast(struct net_device *dev)
5139{
5140        struct de4x5_private *lp = netdev_priv(dev);
5141        del_timer_sync(&lp->timer);
5142}
5143
5144static long
5145de4x5_switch_mac_port(struct net_device *dev)
5146{
5147    struct de4x5_private *lp = netdev_priv(dev);
5148    u_long iobase = dev->base_addr;
5149    s32 omr;
5150
5151    STOP_DE4X5;
5152
5153    /* Assert the OMR_PS bit in CSR6 */
5154    omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5155                                                                     OMR_FDX));
5156    omr |= lp->infoblock_csr6;
5157    if (omr & OMR_PS) omr |= OMR_HBD;
5158    outl(omr, DE4X5_OMR);
5159
5160    /* Soft Reset */
5161    RESET_DE4X5;
5162
5163    /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5164    if (lp->chipset == DC21140) {
5165        gep_wr(lp->cache.gepc, dev);
5166        gep_wr(lp->cache.gep, dev);
5167    } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5168        reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5169    }
5170
5171    /* Restore CSR6 */
5172    outl(omr, DE4X5_OMR);
5173
5174    /* Reset CSR8 */
5175    inl(DE4X5_MFC);
5176
5177    return omr;
5178}
5179
5180static void
5181gep_wr(s32 data, struct net_device *dev)
5182{
5183    struct de4x5_private *lp = netdev_priv(dev);
5184    u_long iobase = dev->base_addr;
5185
5186    if (lp->chipset == DC21140) {
5187        outl(data, DE4X5_GEP);
5188    } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5189        outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5190    }
5191
5192    return;
5193}
5194
5195static int
5196gep_rd(struct net_device *dev)
5197{
5198    struct de4x5_private *lp = netdev_priv(dev);
5199    u_long iobase = dev->base_addr;
5200
5201    if (lp->chipset == DC21140) {
5202        return inl(DE4X5_GEP);
5203    } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5204        return (inl(DE4X5_SIGR) & 0x000fffff);
5205    }
5206
5207    return 0;
5208}
5209
5210static void
5211yawn(struct net_device *dev, int state)
5212{
5213    struct de4x5_private *lp = netdev_priv(dev);
5214    u_long iobase = dev->base_addr;
5215
5216    if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5217
5218    if(lp->bus == EISA) {
5219        switch(state) {
5220          case WAKEUP:
5221            outb(WAKEUP, PCI_CFPM);
5222            mdelay(10);
5223            break;
5224
5225          case SNOOZE:
5226            outb(SNOOZE, PCI_CFPM);
5227            break;
5228
5229          case SLEEP:
5230            outl(0, DE4X5_SICR);
5231            outb(SLEEP, PCI_CFPM);
5232            break;
5233        }
5234    } else {
5235        struct pci_dev *pdev = to_pci_dev (lp->gendev);
5236        switch(state) {
5237          case WAKEUP:
5238            pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5239            mdelay(10);
5240            break;
5241
5242          case SNOOZE:
5243            pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5244            break;
5245
5246          case SLEEP:
5247            outl(0, DE4X5_SICR);
5248            pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5249            break;
5250        }
5251    }
5252
5253    return;
5254}
5255
5256static void
5257de4x5_parse_params(struct net_device *dev)
5258{
5259    struct de4x5_private *lp = netdev_priv(dev);
5260    char *p, *q, t;
5261
5262    lp->params.fdx = 0;
5263    lp->params.autosense = AUTO;
5264
5265    if (args == NULL) return;
5266
5267    if ((p = strstr(args, dev->name))) {
5268        if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5269        t = *q;
5270        *q = '\0';
5271
5272        if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5273
5274        if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5275            if (strstr(p, "TP")) {
5276                lp->params.autosense = TP;
5277            } else if (strstr(p, "TP_NW")) {
5278                lp->params.autosense = TP_NW;
5279            } else if (strstr(p, "BNC")) {
5280                lp->params.autosense = BNC;
5281            } else if (strstr(p, "AUI")) {
5282                lp->params.autosense = AUI;
5283            } else if (strstr(p, "BNC_AUI")) {
5284                lp->params.autosense = BNC;
5285            } else if (strstr(p, "10Mb")) {
5286                lp->params.autosense = _10Mb;
5287            } else if (strstr(p, "100Mb")) {
5288                lp->params.autosense = _100Mb;
5289            } else if (strstr(p, "AUTO")) {
5290                lp->params.autosense = AUTO;
5291            }
5292        }
5293        *q = t;
5294    }
5295
5296    return;
5297}
5298
5299static void
5300de4x5_dbg_open(struct net_device *dev)
5301{
5302    struct de4x5_private *lp = netdev_priv(dev);
5303    int i;
5304
5305    if (de4x5_debug & DEBUG_OPEN) {
5306        printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5307        printk("\tphysical address: ");
5308        for (i=0;i<6;i++) {
5309            printk("%2.2x:",(short)dev->dev_addr[i]);
5310        }
5311        printk("\n");
5312        printk("Descriptor head addresses:\n");
5313        printk("\t0x%8.8lx  0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5314        printk("Descriptor addresses:\nRX: ");
5315        for (i=0;i<lp->rxRingSize-1;i++){
5316            if (i < 3) {
5317                printk("0x%8.8lx  ",(u_long)&lp->rx_ring[i].status);
5318            }
5319        }
5320        printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5321        printk("TX: ");
5322        for (i=0;i<lp->txRingSize-1;i++){
5323            if (i < 3) {
5324                printk("0x%8.8lx  ", (u_long)&lp->tx_ring[i].status);
5325            }
5326        }
5327        printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5328        printk("Descriptor buffers:\nRX: ");
5329        for (i=0;i<lp->rxRingSize-1;i++){
5330            if (i < 3) {
5331                printk("0x%8.8x  ",le32_to_cpu(lp->rx_ring[i].buf));
5332            }
5333        }
5334        printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5335        printk("TX: ");
5336        for (i=0;i<lp->txRingSize-1;i++){
5337            if (i < 3) {
5338                printk("0x%8.8x  ", le32_to_cpu(lp->tx_ring[i].buf));
5339            }
5340        }
5341        printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5342        printk("Ring size: \nRX: %d\nTX: %d\n",
5343               (short)lp->rxRingSize,
5344               (short)lp->txRingSize);
5345    }
5346
5347    return;
5348}
5349
5350static void
5351de4x5_dbg_mii(struct net_device *dev, int k)
5352{
5353    struct de4x5_private *lp = netdev_priv(dev);
5354    u_long iobase = dev->base_addr;
5355
5356    if (de4x5_debug & DEBUG_MII) {
5357        printk("\nMII device address: %d\n", lp->phy[k].addr);
5358        printk("MII CR:  %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5359        printk("MII SR:  %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5360        printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5361        printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5362        if (lp->phy[k].id != BROADCOM_T4) {
5363            printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5364            printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5365        }
5366        printk("MII 16:  %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5367        if (lp->phy[k].id != BROADCOM_T4) {
5368            printk("MII 17:  %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5369            printk("MII 18:  %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5370        } else {
5371            printk("MII 20:  %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5372        }
5373    }
5374
5375    return;
5376}
5377
5378static void
5379de4x5_dbg_media(struct net_device *dev)
5380{
5381    struct de4x5_private *lp = netdev_priv(dev);
5382
5383    if (lp->media != lp->c_media) {
5384        if (de4x5_debug & DEBUG_MEDIA) {
5385            printk("%s: media is %s%s\n", dev->name,
5386                   (lp->media == NC  ? "unconnected, link down or incompatible connection" :
5387                    (lp->media == TP  ? "TP" :
5388                     (lp->media == ANS ? "TP/Nway" :
5389                      (lp->media == BNC ? "BNC" :
5390                       (lp->media == AUI ? "AUI" :
5391                        (lp->media == BNC_AUI ? "BNC/AUI" :
5392                         (lp->media == EXT_SIA ? "EXT SIA" :
5393                          (lp->media == _100Mb  ? "100Mb/s" :
5394                           (lp->media == _10Mb   ? "10Mb/s" :
5395                            "???"
5396                            ))))))))), (lp->fdx?" full duplex.":"."));
5397        }
5398        lp->c_media = lp->media;
5399    }
5400
5401    return;
5402}
5403
5404static void
5405de4x5_dbg_srom(struct de4x5_srom *p)
5406{
5407    int i;
5408
5409    if (de4x5_debug & DEBUG_SROM) {
5410        printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5411        printk("Sub-system ID:        %04x\n", *((u_short *)p->sub_system_id));
5412        printk("ID Block CRC:         %02x\n", (u_char)(p->id_block_crc));
5413        printk("SROM version:         %02x\n", (u_char)(p->version));
5414        printk("# controllers:        %02x\n", (u_char)(p->num_controllers));
5415
5416        printk("Hardware Address:     %pM\n", p->ieee_addr);
5417        printk("CRC checksum:         %04x\n", (u_short)(p->chksum));
5418        for (i=0; i<64; i++) {
5419            printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5420        }
5421    }
5422
5423    return;
5424}
5425
5426static void
5427de4x5_dbg_rx(struct sk_buff *skb, int len)
5428{
5429    int i, j;
5430
5431    if (de4x5_debug & DEBUG_RX) {
5432        printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5433               skb->data, &skb->data[6],
5434               (u_char)skb->data[12],
5435               (u_char)skb->data[13],
5436               len);
5437        for (j=0; len>0;j+=16, len-=16) {
5438          printk("    %03x: ",j);
5439          for (i=0; i<16 && i<len; i++) {
5440            printk("%02x ",(u_char)skb->data[i+j]);
5441          }
5442          printk("\n");
5443        }
5444    }
5445
5446    return;
5447}
5448
5449/*
5450** Perform IOCTL call functions here. Some are privileged operations and the
5451** effective uid is checked in those cases. In the normal course of events
5452** this function is only used for my testing.
5453*/
5454static int
5455de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5456{
5457    struct de4x5_private *lp = netdev_priv(dev);
5458    struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5459    u_long iobase = dev->base_addr;
5460    int i, j, status = 0;
5461    s32 omr;
5462    union {
5463        u8  addr[144];
5464        u16 sval[72];
5465        u32 lval[36];
5466    } tmp;
5467    u_long flags = 0;
5468
5469    switch(ioc->cmd) {
5470    case DE4X5_GET_HWADDR:           /* Get the hardware address */
5471        ioc->len = ETH_ALEN;
5472        for (i=0; i<ETH_ALEN; i++) {
5473            tmp.addr[i] = dev->dev_addr[i];
5474        }
5475        if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5476        break;
5477
5478    case DE4X5_SET_HWADDR:           /* Set the hardware address */
5479        if (!capable(CAP_NET_ADMIN)) return -EPERM;
5480        if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5481        if (netif_queue_stopped(dev))
5482                return -EBUSY;
5483        netif_stop_queue(dev);
5484        for (i=0; i<ETH_ALEN; i++) {
5485            dev->dev_addr[i] = tmp.addr[i];
5486        }
5487        build_setup_frame(dev, PHYS_ADDR_ONLY);
5488        /* Set up the descriptor and give ownership to the card */
5489        load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5490                                                       SETUP_FRAME_LEN, (struct sk_buff *)1);
5491        lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5492        outl(POLL_DEMAND, DE4X5_TPD);                /* Start the TX */
5493        netif_wake_queue(dev);                      /* Unlock the TX ring */
5494        break;
5495
5496    case DE4X5_SAY_BOO:              /* Say "Boo!" to the kernel log file */
5497        if (!capable(CAP_NET_ADMIN)) return -EPERM;
5498        printk("%s: Boo!\n", dev->name);
5499        break;
5500
5501    case DE4X5_MCA_EN:               /* Enable pass all multicast addressing */
5502        if (!capable(CAP_NET_ADMIN)) return -EPERM;
5503        omr = inl(DE4X5_OMR);
5504        omr |= OMR_PM;
5505        outl(omr, DE4X5_OMR);
5506        break;
5507
5508    case DE4X5_GET_STATS:            /* Get the driver statistics */
5509    {
5510        struct pkt_stats statbuf;
5511        ioc->len = sizeof(statbuf);
5512        spin_lock_irqsave(&lp->lock, flags);
5513        memcpy(&statbuf, &lp->pktStats, ioc->len);
5514        spin_unlock_irqrestore(&lp->lock, flags);
5515        if (copy_to_user(ioc->data, &statbuf, ioc->len))
5516                return -EFAULT;
5517        break;
5518    }
5519    case DE4X5_CLR_STATS:            /* Zero out the driver statistics */
5520        if (!capable(CAP_NET_ADMIN)) return -EPERM;
5521        spin_lock_irqsave(&lp->lock, flags);
5522        memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5523        spin_unlock_irqrestore(&lp->lock, flags);
5524        break;
5525
5526    case DE4X5_GET_OMR:              /* Get the OMR Register contents */
5527        tmp.addr[0] = inl(DE4X5_OMR);
5528        if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5529        break;
5530
5531    case DE4X5_SET_OMR:              /* Set the OMR Register contents */
5532        if (!capable(CAP_NET_ADMIN)) return -EPERM;
5533        if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5534        outl(tmp.addr[0], DE4X5_OMR);
5535        break;
5536
5537    case DE4X5_GET_REG:              /* Get the DE4X5 Registers */
5538        j = 0;
5539        tmp.lval[0] = inl(DE4X5_STS); j+=4;
5540        tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5541        tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5542        tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5543        tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5544        tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5545        tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5546        tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5547        ioc->len = j;
5548        if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5549        break;
5550
5551#define DE4X5_DUMP              0x0f /* Dump the DE4X5 Status */
5552/*
5553      case DE4X5_DUMP:
5554        j = 0;
5555        tmp.addr[j++] = dev->irq;
5556        for (i=0; i<ETH_ALEN; i++) {
5557            tmp.addr[j++] = dev->dev_addr[i];
5558        }
5559        tmp.addr[j++] = lp->rxRingSize;
5560        tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5561        tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5562
5563        for (i=0;i<lp->rxRingSize-1;i++){
5564            if (i < 3) {
5565                tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5566            }
5567        }
5568        tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5569        for (i=0;i<lp->txRingSize-1;i++){
5570            if (i < 3) {
5571                tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5572            }
5573        }
5574        tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5575
5576        for (i=0;i<lp->rxRingSize-1;i++){
5577            if (i < 3) {
5578                tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5579            }
5580        }
5581        tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5582        for (i=0;i<lp->txRingSize-1;i++){
5583            if (i < 3) {
5584                tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5585            }
5586        }
5587        tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5588
5589        for (i=0;i<lp->rxRingSize;i++){
5590            tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5591        }
5592        for (i=0;i<lp->txRingSize;i++){
5593            tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5594        }
5595
5596        tmp.lval[j>>2] = inl(DE4X5_BMR);  j+=4;
5597        tmp.lval[j>>2] = inl(DE4X5_TPD);  j+=4;
5598        tmp.lval[j>>2] = inl(DE4X5_RPD);  j+=4;
5599        tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5600        tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5601        tmp.lval[j>>2] = inl(DE4X5_STS);  j+=4;
5602        tmp.lval[j>>2] = inl(DE4X5_OMR);  j+=4;
5603        tmp.lval[j>>2] = inl(DE4X5_IMR);  j+=4;
5604        tmp.lval[j>>2] = lp->chipset; j+=4;
5605        if (lp->chipset == DC21140) {
5606            tmp.lval[j>>2] = gep_rd(dev);  j+=4;
5607        } else {
5608            tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5609            tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5610            tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5611            tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5612        }
5613        tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5614        if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5615            tmp.lval[j>>2] = lp->active; j+=4;
5616            tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5617            tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5618            tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5619            tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5620            if (lp->phy[lp->active].id != BROADCOM_T4) {
5621                tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5622                tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5623            }
5624            tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5625            if (lp->phy[lp->active].id != BROADCOM_T4) {
5626                tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5627                tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5628            } else {
5629                tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5630            }
5631        }
5632
5633        tmp.addr[j++] = lp->txRingSize;
5634        tmp.addr[j++] = netif_queue_stopped(dev);
5635
5636        ioc->len = j;
5637        if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5638        break;
5639
5640*/
5641    default:
5642        return -EOPNOTSUPP;
5643    }
5644
5645    return status;
5646}
5647
5648static int __init de4x5_module_init (void)
5649{
5650        int err = 0;
5651
5652#ifdef CONFIG_PCI
5653        err = pci_register_driver(&de4x5_pci_driver);
5654#endif
5655#ifdef CONFIG_EISA
5656        err |= eisa_driver_register (&de4x5_eisa_driver);
5657#endif
5658
5659        return err;
5660}
5661
5662static void __exit de4x5_module_exit (void)
5663{
5664#ifdef CONFIG_PCI
5665        pci_unregister_driver (&de4x5_pci_driver);
5666#endif
5667#ifdef CONFIG_EISA
5668        eisa_driver_unregister (&de4x5_eisa_driver);
5669#endif
5670}
5671
5672module_init (de4x5_module_init);
5673module_exit (de4x5_module_exit);
5674