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15#define DRV_NAME "uli526x"
16#define DRV_VERSION "0.9.3"
17#define DRV_RELDATE "2005-7-29"
18
19#include <linux/module.h>
20
21#include <linux/kernel.h>
22#include <linux/string.h>
23#include <linux/timer.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/slab.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/skbuff.h>
34#include <linux/delay.h>
35#include <linux/spinlock.h>
36#include <linux/dma-mapping.h>
37#include <linux/bitops.h>
38
39#include <asm/processor.h>
40#include <asm/io.h>
41#include <asm/dma.h>
42#include <asm/uaccess.h>
43
44
45
46#define PCI_ULI5261_ID 0x526110B9
47#define PCI_ULI5263_ID 0x526310B9
48
49#define ULI526X_IO_SIZE 0x100
50#define TX_DESC_CNT 0x20
51#define RX_DESC_CNT 0x30
52#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2)
53#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3)
54#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55#define TX_BUF_ALLOC 0x600
56#define RX_ALLOC_SIZE 0x620
57#define ULI526X_RESET 1
58#define CR0_DEFAULT 0
59#define CR6_DEFAULT 0x22200000
60#define CR7_DEFAULT 0x180c1
61#define CR15_DEFAULT 0x06
62#define TDES0_ERR_MASK 0x4302
63#define MAX_PACKET_SIZE 1514
64#define ULI5261_MAX_MULTICAST 14
65#define RX_COPY_SIZE 100
66#define MAX_CHECK_PACKET 0x8000
67
68#define ULI526X_10MHF 0
69#define ULI526X_100MHF 1
70#define ULI526X_10MFD 4
71#define ULI526X_100MFD 5
72#define ULI526X_AUTO 8
73
74#define ULI526X_TXTH_72 0x400000
75#define ULI526X_TXTH_96 0x404000
76#define ULI526X_TXTH_128 0x0000
77#define ULI526X_TXTH_256 0x4000
78#define ULI526X_TXTH_512 0x8000
79#define ULI526X_TXTH_1K 0xC000
80
81#define ULI526X_TIMER_WUT (jiffies + HZ * 1)
82#define ULI526X_TX_TIMEOUT ((16*HZ)/2)
83#define ULI526X_TX_KICK (4*HZ/2)
84
85#define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90
91#define CR9_SROM_READ 0x4800
92#define CR9_SRCS 0x1
93#define CR9_SRCLK 0x2
94#define CR9_CRDOUT 0x8
95#define SROM_DATA_0 0x0
96#define SROM_DATA_1 0x4
97#define PHY_DATA_1 0x20000
98#define PHY_DATA_0 0x00000
99#define MDCLKH 0x10000
100
101#define PHY_POWER_DOWN 0x800
102
103#define SROM_V41_CODE 0x14
104
105#define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
112
113
114struct tx_desc {
115 __le32 tdes0, tdes1, tdes2, tdes3;
116 char *tx_buf_ptr;
117 struct tx_desc *next_tx_desc;
118} __attribute__(( aligned(32) ));
119
120struct rx_desc {
121 __le32 rdes0, rdes1, rdes2, rdes3;
122 struct sk_buff *rx_skb_ptr;
123 struct rx_desc *next_rx_desc;
124} __attribute__(( aligned(32) ));
125
126struct uli526x_board_info {
127 u32 chip_id;
128 struct net_device *next_dev;
129 struct pci_dev *pdev;
130 spinlock_t lock;
131
132 long ioaddr;
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139
140 dma_addr_t buf_pool_dma_ptr;
141 dma_addr_t buf_pool_dma_start;
142 dma_addr_t desc_pool_dma_ptr;
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146
147 unsigned char *buf_pool_ptr;
148 unsigned char *buf_pool_start;
149 unsigned char *desc_pool_ptr;
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr;
156 unsigned long tx_packet_cnt;
157 unsigned long rx_avail_cnt;
158 unsigned long interval_rx_cnt;
159
160 u16 dbug_cnt;
161 u16 NIC_capability;
162 u16 PHY_reg4;
163
164 u8 media_mode;
165 u8 op_mode;
166 u8 phy_addr;
167 u8 link_failed;
168 u8 wait_reset;
169 struct timer_list timer;
170
171
172 unsigned long tx_fifo_underrun;
173 unsigned long tx_loss_carrier;
174 unsigned long tx_no_carrier;
175 unsigned long tx_late_collision;
176 unsigned long tx_excessive_collision;
177 unsigned long tx_jabber_timeout;
178 unsigned long reset_count;
179 unsigned long reset_cr8;
180 unsigned long reset_fatal;
181 unsigned long reset_TXtimeout;
182
183
184 unsigned char srom[128];
185 u8 init;
186};
187
188enum uli526x_offsets {
189 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
190 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
191 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
192 DCR15 = 0x78
193};
194
195enum uli526x_CR6_bits {
196 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
197 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
198 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
199};
200
201
202static int __devinitdata printed_version;
203static const char version[] __devinitconst =
204 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
205 DRV_VERSION " (" DRV_RELDATE ")\n";
206
207static int uli526x_debug;
208static unsigned char uli526x_media_mode = ULI526X_AUTO;
209static u32 uli526x_cr6_user_set;
210
211
212static int debug;
213static u32 cr6set;
214static int mode = 8;
215
216
217static int uli526x_open(struct net_device *);
218static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
219 struct net_device *);
220static int uli526x_stop(struct net_device *);
221static void uli526x_set_filter_mode(struct net_device *);
222static const struct ethtool_ops netdev_ethtool_ops;
223static u16 read_srom_word(long, int);
224static irqreturn_t uli526x_interrupt(int, void *);
225#ifdef CONFIG_NET_POLL_CONTROLLER
226static void uli526x_poll(struct net_device *dev);
227#endif
228static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
229static void allocate_rx_buffer(struct uli526x_board_info *);
230static void update_cr6(u32, unsigned long);
231static void send_filter_frame(struct net_device *, int);
232static u16 phy_read(unsigned long, u8, u8, u32);
233static u16 phy_readby_cr10(unsigned long, u8, u8);
234static void phy_write(unsigned long, u8, u8, u16, u32);
235static void phy_writeby_cr10(unsigned long, u8, u8, u16);
236static void phy_write_1bit(unsigned long, u32, u32);
237static u16 phy_read_1bit(unsigned long, u32);
238static u8 uli526x_sense_speed(struct uli526x_board_info *);
239static void uli526x_process_mode(struct uli526x_board_info *);
240static void uli526x_timer(unsigned long);
241static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
242static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
243static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
244static void uli526x_dynamic_reset(struct net_device *);
245static void uli526x_free_rxbuffer(struct uli526x_board_info *);
246static void uli526x_init(struct net_device *);
247static void uli526x_set_phyxcer(struct uli526x_board_info *);
248
249
250
251static const struct net_device_ops netdev_ops = {
252 .ndo_open = uli526x_open,
253 .ndo_stop = uli526x_stop,
254 .ndo_start_xmit = uli526x_start_xmit,
255 .ndo_set_multicast_list = uli526x_set_filter_mode,
256 .ndo_change_mtu = eth_change_mtu,
257 .ndo_set_mac_address = eth_mac_addr,
258 .ndo_validate_addr = eth_validate_addr,
259#ifdef CONFIG_NET_POLL_CONTROLLER
260 .ndo_poll_controller = uli526x_poll,
261#endif
262};
263
264
265
266
267
268static int __devinit uli526x_init_one (struct pci_dev *pdev,
269 const struct pci_device_id *ent)
270{
271 struct uli526x_board_info *db;
272 struct net_device *dev;
273 int i, err;
274
275 ULI526X_DBUG(0, "uli526x_init_one()", 0);
276
277 if (!printed_version++)
278 printk(version);
279
280
281 dev = alloc_etherdev(sizeof(*db));
282 if (dev == NULL)
283 return -ENOMEM;
284 SET_NETDEV_DEV(dev, &pdev->dev);
285
286 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
287 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
288 err = -ENODEV;
289 goto err_out_free;
290 }
291
292
293 err = pci_enable_device(pdev);
294 if (err)
295 goto err_out_free;
296
297 if (!pci_resource_start(pdev, 0)) {
298 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
299 err = -ENODEV;
300 goto err_out_disable;
301 }
302
303 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
304 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
305 err = -ENODEV;
306 goto err_out_disable;
307 }
308
309 if (pci_request_regions(pdev, DRV_NAME)) {
310 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
311 err = -ENODEV;
312 goto err_out_disable;
313 }
314
315
316 db = netdev_priv(dev);
317
318
319 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
320 if(db->desc_pool_ptr == NULL)
321 {
322 err = -ENOMEM;
323 goto err_out_nomem;
324 }
325 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
326 if(db->buf_pool_ptr == NULL)
327 {
328 err = -ENOMEM;
329 goto err_out_nomem;
330 }
331
332 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
333 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
334 db->buf_pool_start = db->buf_pool_ptr;
335 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
336
337 db->chip_id = ent->driver_data;
338 db->ioaddr = pci_resource_start(pdev, 0);
339
340 db->pdev = pdev;
341 db->init = 1;
342
343 dev->base_addr = db->ioaddr;
344 dev->irq = pdev->irq;
345 pci_set_drvdata(pdev, dev);
346
347
348 dev->netdev_ops = &netdev_ops;
349 dev->ethtool_ops = &netdev_ethtool_ops;
350
351 spin_lock_init(&db->lock);
352
353
354
355 for (i = 0; i < 64; i++)
356 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
357
358
359 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)
360 {
361 outl(0x10000, db->ioaddr + DCR0);
362 outl(0x1c0, db->ioaddr + DCR13);
363 outl(0, db->ioaddr + DCR14);
364 outl(0x10, db->ioaddr + DCR14);
365 outl(0, db->ioaddr + DCR14);
366 outl(0, db->ioaddr + DCR13);
367 outl(0x1b0, db->ioaddr + DCR13);
368
369 for (i = 0; i < 6; i++)
370 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
371
372 outl(0, db->ioaddr + DCR13);
373 outl(0, db->ioaddr + DCR0);
374 udelay(10);
375 }
376 else
377 {
378 for (i = 0; i < 6; i++)
379 dev->dev_addr[i] = db->srom[20 + i];
380 }
381 err = register_netdev (dev);
382 if (err)
383 goto err_out_res;
384
385 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %pM, irq %d.\n",
386 dev->name,ent->driver_data >> 16,pci_name(pdev),
387 dev->dev_addr, dev->irq);
388
389 pci_set_master(pdev);
390
391 return 0;
392
393err_out_res:
394 pci_release_regions(pdev);
395err_out_nomem:
396 if(db->desc_pool_ptr)
397 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
398 db->desc_pool_ptr, db->desc_pool_dma_ptr);
399
400 if(db->buf_pool_ptr != NULL)
401 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
402 db->buf_pool_ptr, db->buf_pool_dma_ptr);
403err_out_disable:
404 pci_disable_device(pdev);
405err_out_free:
406 pci_set_drvdata(pdev, NULL);
407 free_netdev(dev);
408
409 return err;
410}
411
412
413static void __devexit uli526x_remove_one (struct pci_dev *pdev)
414{
415 struct net_device *dev = pci_get_drvdata(pdev);
416 struct uli526x_board_info *db = netdev_priv(dev);
417
418 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
419
420 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
421 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
422 db->desc_pool_dma_ptr);
423 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
424 db->buf_pool_ptr, db->buf_pool_dma_ptr);
425 unregister_netdev(dev);
426 pci_release_regions(pdev);
427 free_netdev(dev);
428 pci_set_drvdata(pdev, NULL);
429 pci_disable_device(pdev);
430 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
431}
432
433
434
435
436
437
438
439static int uli526x_open(struct net_device *dev)
440{
441 int ret;
442 struct uli526x_board_info *db = netdev_priv(dev);
443
444 ULI526X_DBUG(0, "uli526x_open", 0);
445
446
447 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
448 db->tx_packet_cnt = 0;
449 db->rx_avail_cnt = 0;
450 db->link_failed = 1;
451 netif_carrier_off(dev);
452 db->wait_reset = 0;
453
454 db->NIC_capability = 0xf;
455 db->PHY_reg4 = 0x1e0;
456
457
458 db->cr6_data |= ULI526X_TXTH_256;
459 db->cr0_data = CR0_DEFAULT;
460
461
462 uli526x_init(dev);
463
464 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
465 if (ret)
466 return ret;
467
468
469 netif_wake_queue(dev);
470
471
472 init_timer(&db->timer);
473 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
474 db->timer.data = (unsigned long)dev;
475 db->timer.function = &uli526x_timer;
476 add_timer(&db->timer);
477
478 return 0;
479}
480
481
482
483
484
485
486
487
488
489static void uli526x_init(struct net_device *dev)
490{
491 struct uli526x_board_info *db = netdev_priv(dev);
492 unsigned long ioaddr = db->ioaddr;
493 u8 phy_tmp;
494 u8 timeout;
495 u16 phy_value;
496 u16 phy_reg_reset;
497
498
499 ULI526X_DBUG(0, "uli526x_init()", 0);
500
501
502 outl(ULI526X_RESET, ioaddr + DCR0);
503 udelay(100);
504 outl(db->cr0_data, ioaddr + DCR0);
505 udelay(5);
506
507
508 db->phy_addr = 1;
509 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
510 {
511 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);
512 if(phy_value != 0xffff&&phy_value!=0)
513 {
514 db->phy_addr = phy_tmp;
515 break;
516 }
517 }
518 if(phy_tmp == 32)
519 printk(KERN_WARNING "Can not find the phy address!!!");
520
521 db->media_mode = uli526x_media_mode;
522
523
524 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
525 phy_reg_reset = (phy_reg_reset | 0x8000);
526 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
527
528
529
530
531 udelay(500);
532 timeout = 10;
533 while (timeout-- &&
534 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
535 udelay(100);
536
537
538 uli526x_set_phyxcer(db);
539
540
541 if ( !(db->media_mode & ULI526X_AUTO) )
542 db->op_mode = db->media_mode;
543
544
545 uli526x_descriptor_init(db, ioaddr);
546
547
548 update_cr6(db->cr6_data, ioaddr);
549
550
551 send_filter_frame(dev, dev->mc_count);
552
553
554 db->cr7_data = CR7_DEFAULT;
555 outl(db->cr7_data, ioaddr + DCR7);
556
557
558 outl(db->cr15_data, ioaddr + DCR15);
559
560
561 db->cr6_data |= CR6_RXSC | CR6_TXSC;
562 update_cr6(db->cr6_data, ioaddr);
563}
564
565
566
567
568
569
570
571static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
572 struct net_device *dev)
573{
574 struct uli526x_board_info *db = netdev_priv(dev);
575 struct tx_desc *txptr;
576 unsigned long flags;
577
578 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
579
580
581 netif_stop_queue(dev);
582
583
584 if (skb->len > MAX_PACKET_SIZE) {
585 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
586 dev_kfree_skb(skb);
587 return NETDEV_TX_OK;
588 }
589
590 spin_lock_irqsave(&db->lock, flags);
591
592
593 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
594 spin_unlock_irqrestore(&db->lock, flags);
595 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
596 return NETDEV_TX_BUSY;
597 }
598
599
600 outl(0, dev->base_addr + DCR7);
601
602
603 txptr = db->tx_insert_ptr;
604 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
605 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
606
607
608 db->tx_insert_ptr = txptr->next_tx_desc;
609
610
611 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
612 txptr->tdes0 = cpu_to_le32(0x80000000);
613 db->tx_packet_cnt++;
614 outl(0x1, dev->base_addr + DCR1);
615 dev->trans_start = jiffies;
616 }
617
618
619 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
620 netif_wake_queue(dev);
621
622
623 spin_unlock_irqrestore(&db->lock, flags);
624 outl(db->cr7_data, dev->base_addr + DCR7);
625
626
627 dev_kfree_skb(skb);
628
629 return NETDEV_TX_OK;
630}
631
632
633
634
635
636
637
638static int uli526x_stop(struct net_device *dev)
639{
640 struct uli526x_board_info *db = netdev_priv(dev);
641 unsigned long ioaddr = dev->base_addr;
642
643 ULI526X_DBUG(0, "uli526x_stop", 0);
644
645
646 netif_stop_queue(dev);
647
648
649 del_timer_sync(&db->timer);
650
651
652 outl(ULI526X_RESET, ioaddr + DCR0);
653 udelay(5);
654 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
655
656
657 free_irq(dev->irq, dev);
658
659
660 uli526x_free_rxbuffer(db);
661
662#if 0
663
664 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
665 db->tx_fifo_underrun, db->tx_excessive_collision,
666 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
667 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
668 db->reset_fatal, db->reset_TXtimeout);
669#endif
670
671 return 0;
672}
673
674
675
676
677
678
679
680static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
681{
682 struct net_device *dev = dev_id;
683 struct uli526x_board_info *db = netdev_priv(dev);
684 unsigned long ioaddr = dev->base_addr;
685 unsigned long flags;
686
687 spin_lock_irqsave(&db->lock, flags);
688 outl(0, ioaddr + DCR7);
689
690
691 db->cr5_data = inl(ioaddr + DCR5);
692 outl(db->cr5_data, ioaddr + DCR5);
693 if ( !(db->cr5_data & 0x180c1) ) {
694
695 outl(db->cr7_data, ioaddr + DCR7);
696 spin_unlock_irqrestore(&db->lock, flags);
697 return IRQ_HANDLED;
698 }
699
700
701 if (db->cr5_data & 0x2000) {
702
703 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
704 db->reset_fatal++;
705 db->wait_reset = 1;
706 spin_unlock_irqrestore(&db->lock, flags);
707 return IRQ_HANDLED;
708 }
709
710
711 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
712 uli526x_rx_packet(dev, db);
713
714
715 if (db->rx_avail_cnt<RX_DESC_CNT)
716 allocate_rx_buffer(db);
717
718
719 if ( db->cr5_data & 0x01)
720 uli526x_free_tx_pkt(dev, db);
721
722
723 outl(db->cr7_data, ioaddr + DCR7);
724
725 spin_unlock_irqrestore(&db->lock, flags);
726 return IRQ_HANDLED;
727}
728
729#ifdef CONFIG_NET_POLL_CONTROLLER
730static void uli526x_poll(struct net_device *dev)
731{
732
733 uli526x_interrupt(dev->irq, dev);
734}
735#endif
736
737
738
739
740
741static void uli526x_free_tx_pkt(struct net_device *dev,
742 struct uli526x_board_info * db)
743{
744 struct tx_desc *txptr;
745 u32 tdes0;
746
747 txptr = db->tx_remove_ptr;
748 while(db->tx_packet_cnt) {
749 tdes0 = le32_to_cpu(txptr->tdes0);
750
751 if (tdes0 & 0x80000000)
752 break;
753
754
755 db->tx_packet_cnt--;
756 dev->stats.tx_packets++;
757
758
759 if ( tdes0 != 0x7fffffff ) {
760
761 dev->stats.collisions += (tdes0 >> 3) & 0xf;
762 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
763 if (tdes0 & TDES0_ERR_MASK) {
764 dev->stats.tx_errors++;
765 if (tdes0 & 0x0002) {
766 db->tx_fifo_underrun++;
767 if ( !(db->cr6_data & CR6_SFT) ) {
768 db->cr6_data = db->cr6_data | CR6_SFT;
769 update_cr6(db->cr6_data, db->ioaddr);
770 }
771 }
772 if (tdes0 & 0x0100)
773 db->tx_excessive_collision++;
774 if (tdes0 & 0x0200)
775 db->tx_late_collision++;
776 if (tdes0 & 0x0400)
777 db->tx_no_carrier++;
778 if (tdes0 & 0x0800)
779 db->tx_loss_carrier++;
780 if (tdes0 & 0x4000)
781 db->tx_jabber_timeout++;
782 }
783 }
784
785 txptr = txptr->next_tx_desc;
786 }
787
788
789 db->tx_remove_ptr = txptr;
790
791
792 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
793 netif_wake_queue(dev);
794}
795
796
797
798
799
800
801static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
802{
803 struct rx_desc *rxptr;
804 struct sk_buff *skb;
805 int rxlen;
806 u32 rdes0;
807
808 rxptr = db->rx_ready_ptr;
809
810 while(db->rx_avail_cnt) {
811 rdes0 = le32_to_cpu(rxptr->rdes0);
812 if (rdes0 & 0x80000000)
813 {
814 break;
815 }
816
817 db->rx_avail_cnt--;
818 db->interval_rx_cnt++;
819
820 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
821 if ( (rdes0 & 0x300) != 0x300) {
822
823
824 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
825 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
826 } else {
827
828 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
829
830
831 if (rdes0 & 0x8000) {
832
833
834 dev->stats.rx_errors++;
835 if (rdes0 & 1)
836 dev->stats.rx_fifo_errors++;
837 if (rdes0 & 2)
838 dev->stats.rx_crc_errors++;
839 if (rdes0 & 0x80)
840 dev->stats.rx_length_errors++;
841 }
842
843 if ( !(rdes0 & 0x8000) ||
844 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
845 skb = rxptr->rx_skb_ptr;
846
847
848
849 if ( (rxlen < RX_COPY_SIZE) &&
850 ( (skb = dev_alloc_skb(rxlen + 2) )
851 != NULL) ) {
852
853 skb_reserve(skb, 2);
854 memcpy(skb_put(skb, rxlen),
855 skb_tail_pointer(rxptr->rx_skb_ptr),
856 rxlen);
857 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
858 } else
859 skb_put(skb, rxlen);
860
861 skb->protocol = eth_type_trans(skb, dev);
862 netif_rx(skb);
863 dev->stats.rx_packets++;
864 dev->stats.rx_bytes += rxlen;
865
866 } else {
867
868 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
869 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
870 }
871 }
872
873 rxptr = rxptr->next_rx_desc;
874 }
875
876 db->rx_ready_ptr = rxptr;
877}
878
879
880
881
882
883
884static void uli526x_set_filter_mode(struct net_device * dev)
885{
886 struct uli526x_board_info *db = netdev_priv(dev);
887 unsigned long flags;
888
889 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
890 spin_lock_irqsave(&db->lock, flags);
891
892 if (dev->flags & IFF_PROMISC) {
893 ULI526X_DBUG(0, "Enable PROM Mode", 0);
894 db->cr6_data |= CR6_PM | CR6_PBF;
895 update_cr6(db->cr6_data, db->ioaddr);
896 spin_unlock_irqrestore(&db->lock, flags);
897 return;
898 }
899
900 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
901 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
902 db->cr6_data &= ~(CR6_PM | CR6_PBF);
903 db->cr6_data |= CR6_PAM;
904 spin_unlock_irqrestore(&db->lock, flags);
905 return;
906 }
907
908 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
909 send_filter_frame(dev, dev->mc_count);
910 spin_unlock_irqrestore(&db->lock, flags);
911}
912
913static void
914ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
915{
916 ecmd->supported = (SUPPORTED_10baseT_Half |
917 SUPPORTED_10baseT_Full |
918 SUPPORTED_100baseT_Half |
919 SUPPORTED_100baseT_Full |
920 SUPPORTED_Autoneg |
921 SUPPORTED_MII);
922
923 ecmd->advertising = (ADVERTISED_10baseT_Half |
924 ADVERTISED_10baseT_Full |
925 ADVERTISED_100baseT_Half |
926 ADVERTISED_100baseT_Full |
927 ADVERTISED_Autoneg |
928 ADVERTISED_MII);
929
930
931 ecmd->port = PORT_MII;
932 ecmd->phy_address = db->phy_addr;
933
934 ecmd->transceiver = XCVR_EXTERNAL;
935
936 ecmd->speed = 10;
937 ecmd->duplex = DUPLEX_HALF;
938
939 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
940 {
941 ecmd->speed = 100;
942 }
943 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
944 {
945 ecmd->duplex = DUPLEX_FULL;
946 }
947 if(db->link_failed)
948 {
949 ecmd->speed = -1;
950 ecmd->duplex = -1;
951 }
952
953 if (db->media_mode & ULI526X_AUTO)
954 {
955 ecmd->autoneg = AUTONEG_ENABLE;
956 }
957}
958
959static void netdev_get_drvinfo(struct net_device *dev,
960 struct ethtool_drvinfo *info)
961{
962 struct uli526x_board_info *np = netdev_priv(dev);
963
964 strcpy(info->driver, DRV_NAME);
965 strcpy(info->version, DRV_VERSION);
966 if (np->pdev)
967 strcpy(info->bus_info, pci_name(np->pdev));
968 else
969 sprintf(info->bus_info, "EISA 0x%lx %d",
970 dev->base_addr, dev->irq);
971}
972
973static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
974 struct uli526x_board_info *np = netdev_priv(dev);
975
976 ULi_ethtool_gset(np, cmd);
977
978 return 0;
979}
980
981static u32 netdev_get_link(struct net_device *dev) {
982 struct uli526x_board_info *np = netdev_priv(dev);
983
984 if(np->link_failed)
985 return 0;
986 else
987 return 1;
988}
989
990static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
991{
992 wol->supported = WAKE_PHY | WAKE_MAGIC;
993 wol->wolopts = 0;
994}
995
996static const struct ethtool_ops netdev_ethtool_ops = {
997 .get_drvinfo = netdev_get_drvinfo,
998 .get_settings = netdev_get_settings,
999 .get_link = netdev_get_link,
1000 .get_wol = uli526x_get_wol,
1001};
1002
1003
1004
1005
1006
1007
1008static void uli526x_timer(unsigned long data)
1009{
1010 u32 tmp_cr8;
1011 unsigned char tmp_cr12=0;
1012 struct net_device *dev = (struct net_device *) data;
1013 struct uli526x_board_info *db = netdev_priv(dev);
1014 unsigned long flags;
1015 u8 TmpSpeed=10;
1016
1017
1018 spin_lock_irqsave(&db->lock, flags);
1019
1020
1021
1022 tmp_cr8 = inl(db->ioaddr + DCR8);
1023 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1024 db->reset_cr8++;
1025 db->wait_reset = 1;
1026 }
1027 db->interval_rx_cnt = 0;
1028
1029
1030 if ( db->tx_packet_cnt &&
1031 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
1032 outl(0x1, dev->base_addr + DCR1);
1033
1034
1035 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1036 db->reset_TXtimeout++;
1037 db->wait_reset = 1;
1038 printk( "%s: Tx timeout - resetting\n",
1039 dev->name);
1040 }
1041 }
1042
1043 if (db->wait_reset) {
1044 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1045 db->reset_count++;
1046 uli526x_dynamic_reset(dev);
1047 db->timer.expires = ULI526X_TIMER_WUT;
1048 add_timer(&db->timer);
1049 spin_unlock_irqrestore(&db->lock, flags);
1050 return;
1051 }
1052
1053
1054 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1055 tmp_cr12 = 3;
1056
1057 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1058
1059 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1060 netif_carrier_off(dev);
1061 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1062 db->link_failed = 1;
1063
1064
1065
1066 if ( !(db->media_mode & 0x8) )
1067 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1068
1069
1070 if (db->media_mode & ULI526X_AUTO) {
1071 db->cr6_data&=~0x00000200;
1072 update_cr6(db->cr6_data, db->ioaddr);
1073 }
1074 } else
1075 if ((tmp_cr12 & 0x3) && db->link_failed) {
1076 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1077 db->link_failed = 0;
1078
1079
1080 if ( (db->media_mode & ULI526X_AUTO) &&
1081 uli526x_sense_speed(db) )
1082 db->link_failed = 1;
1083 uli526x_process_mode(db);
1084
1085 if(db->link_failed==0)
1086 {
1087 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1088 {
1089 TmpSpeed = 100;
1090 }
1091 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1092 {
1093 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1094 }
1095 else
1096 {
1097 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1098 }
1099 netif_carrier_on(dev);
1100 }
1101
1102 }
1103 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1104 {
1105 if(db->init==1)
1106 {
1107 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1108 netif_carrier_off(dev);
1109 }
1110 }
1111 db->init=0;
1112
1113
1114 db->timer.expires = ULI526X_TIMER_WUT;
1115 add_timer(&db->timer);
1116 spin_unlock_irqrestore(&db->lock, flags);
1117}
1118
1119
1120
1121
1122
1123
1124
1125
1126static void uli526x_reset_prepare(struct net_device *dev)
1127{
1128 struct uli526x_board_info *db = netdev_priv(dev);
1129
1130
1131 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
1132 update_cr6(db->cr6_data, dev->base_addr);
1133 outl(0, dev->base_addr + DCR7);
1134 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1135
1136
1137 netif_stop_queue(dev);
1138
1139
1140 uli526x_free_rxbuffer(db);
1141
1142
1143 db->tx_packet_cnt = 0;
1144 db->rx_avail_cnt = 0;
1145 db->link_failed = 1;
1146 db->init=1;
1147 db->wait_reset = 0;
1148}
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159static void uli526x_dynamic_reset(struct net_device *dev)
1160{
1161 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1162
1163 uli526x_reset_prepare(dev);
1164
1165
1166 uli526x_init(dev);
1167
1168
1169 netif_wake_queue(dev);
1170}
1171
1172
1173#ifdef CONFIG_PM
1174
1175
1176
1177
1178
1179static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1180{
1181 struct net_device *dev = pci_get_drvdata(pdev);
1182 pci_power_t power_state;
1183 int err;
1184
1185 ULI526X_DBUG(0, "uli526x_suspend", 0);
1186
1187 if (!netdev_priv(dev))
1188 return 0;
1189
1190 pci_save_state(pdev);
1191
1192 if (!netif_running(dev))
1193 return 0;
1194
1195 netif_device_detach(dev);
1196 uli526x_reset_prepare(dev);
1197
1198 power_state = pci_choose_state(pdev, state);
1199 pci_enable_wake(pdev, power_state, 0);
1200 err = pci_set_power_state(pdev, power_state);
1201 if (err) {
1202 netif_device_attach(dev);
1203
1204 uli526x_init(dev);
1205
1206 netif_wake_queue(dev);
1207 }
1208
1209 return err;
1210}
1211
1212
1213
1214
1215
1216static int uli526x_resume(struct pci_dev *pdev)
1217{
1218 struct net_device *dev = pci_get_drvdata(pdev);
1219 int err;
1220
1221 ULI526X_DBUG(0, "uli526x_resume", 0);
1222
1223 if (!netdev_priv(dev))
1224 return 0;
1225
1226 pci_restore_state(pdev);
1227
1228 if (!netif_running(dev))
1229 return 0;
1230
1231 err = pci_set_power_state(pdev, PCI_D0);
1232 if (err) {
1233 printk(KERN_WARNING "%s: Could not put device into D0\n",
1234 dev->name);
1235 return err;
1236 }
1237
1238 netif_device_attach(dev);
1239
1240 uli526x_init(dev);
1241
1242 netif_wake_queue(dev);
1243
1244 return 0;
1245}
1246
1247#else
1248
1249#define uli526x_suspend NULL
1250#define uli526x_resume NULL
1251
1252#endif
1253
1254
1255
1256
1257
1258
1259static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1260{
1261 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1262
1263
1264 while (db->rx_avail_cnt) {
1265 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1266 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1267 db->rx_avail_cnt--;
1268 }
1269}
1270
1271
1272
1273
1274
1275
1276static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1277{
1278 struct rx_desc *rxptr = db->rx_insert_ptr;
1279
1280 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1281 rxptr->rx_skb_ptr = skb;
1282 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1283 skb_tail_pointer(skb),
1284 RX_ALLOC_SIZE,
1285 PCI_DMA_FROMDEVICE));
1286 wmb();
1287 rxptr->rdes0 = cpu_to_le32(0x80000000);
1288 db->rx_avail_cnt++;
1289 db->rx_insert_ptr = rxptr->next_rx_desc;
1290 } else
1291 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1292}
1293
1294
1295
1296
1297
1298
1299
1300static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1301{
1302 struct tx_desc *tmp_tx;
1303 struct rx_desc *tmp_rx;
1304 unsigned char *tmp_buf;
1305 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1306 dma_addr_t tmp_buf_dma;
1307 int i;
1308
1309 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1310
1311
1312 db->tx_insert_ptr = db->first_tx_desc;
1313 db->tx_remove_ptr = db->first_tx_desc;
1314 outl(db->first_tx_desc_dma, ioaddr + DCR4);
1315
1316
1317 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1318 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1319 db->rx_insert_ptr = db->first_rx_desc;
1320 db->rx_ready_ptr = db->first_rx_desc;
1321 outl(db->first_rx_desc_dma, ioaddr + DCR3);
1322
1323
1324 tmp_buf = db->buf_pool_start;
1325 tmp_buf_dma = db->buf_pool_dma_start;
1326 tmp_tx_dma = db->first_tx_desc_dma;
1327 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1328 tmp_tx->tx_buf_ptr = tmp_buf;
1329 tmp_tx->tdes0 = cpu_to_le32(0);
1330 tmp_tx->tdes1 = cpu_to_le32(0x81000000);
1331 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1332 tmp_tx_dma += sizeof(struct tx_desc);
1333 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1334 tmp_tx->next_tx_desc = tmp_tx + 1;
1335 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1336 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1337 }
1338 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1339 tmp_tx->next_tx_desc = db->first_tx_desc;
1340
1341
1342 tmp_rx_dma=db->first_rx_desc_dma;
1343 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1344 tmp_rx->rdes0 = cpu_to_le32(0);
1345 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1346 tmp_rx_dma += sizeof(struct rx_desc);
1347 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1348 tmp_rx->next_rx_desc = tmp_rx + 1;
1349 }
1350 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1351 tmp_rx->next_rx_desc = db->first_rx_desc;
1352
1353
1354 allocate_rx_buffer(db);
1355}
1356
1357
1358
1359
1360
1361
1362
1363static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1364{
1365
1366 outl(cr6_data, ioaddr + DCR6);
1367 udelay(5);
1368}
1369
1370
1371
1372
1373
1374
1375
1376#ifdef __BIG_ENDIAN
1377#define FLT_SHIFT 16
1378#else
1379#define FLT_SHIFT 0
1380#endif
1381
1382static void send_filter_frame(struct net_device *dev, int mc_cnt)
1383{
1384 struct uli526x_board_info *db = netdev_priv(dev);
1385 struct dev_mc_list *mcptr;
1386 struct tx_desc *txptr;
1387 u16 * addrptr;
1388 u32 * suptr;
1389 int i;
1390
1391 ULI526X_DBUG(0, "send_filter_frame()", 0);
1392
1393 txptr = db->tx_insert_ptr;
1394 suptr = (u32 *) txptr->tx_buf_ptr;
1395
1396
1397 addrptr = (u16 *) dev->dev_addr;
1398 *suptr++ = addrptr[0] << FLT_SHIFT;
1399 *suptr++ = addrptr[1] << FLT_SHIFT;
1400 *suptr++ = addrptr[2] << FLT_SHIFT;
1401
1402
1403 *suptr++ = 0xffff << FLT_SHIFT;
1404 *suptr++ = 0xffff << FLT_SHIFT;
1405 *suptr++ = 0xffff << FLT_SHIFT;
1406
1407
1408 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1409 addrptr = (u16 *) mcptr->dmi_addr;
1410 *suptr++ = addrptr[0] << FLT_SHIFT;
1411 *suptr++ = addrptr[1] << FLT_SHIFT;
1412 *suptr++ = addrptr[2] << FLT_SHIFT;
1413 }
1414
1415 for (; i<14; i++) {
1416 *suptr++ = 0xffff << FLT_SHIFT;
1417 *suptr++ = 0xffff << FLT_SHIFT;
1418 *suptr++ = 0xffff << FLT_SHIFT;
1419 }
1420
1421
1422 db->tx_insert_ptr = txptr->next_tx_desc;
1423 txptr->tdes1 = cpu_to_le32(0x890000c0);
1424
1425
1426 if (db->tx_packet_cnt < TX_DESC_CNT) {
1427
1428 db->tx_packet_cnt++;
1429 txptr->tdes0 = cpu_to_le32(0x80000000);
1430 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1431 outl(0x1, dev->base_addr + DCR1);
1432 update_cr6(db->cr6_data, dev->base_addr);
1433 dev->trans_start = jiffies;
1434 } else
1435 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1436}
1437
1438
1439
1440
1441
1442
1443
1444static void allocate_rx_buffer(struct uli526x_board_info *db)
1445{
1446 struct rx_desc *rxptr;
1447 struct sk_buff *skb;
1448
1449 rxptr = db->rx_insert_ptr;
1450
1451 while(db->rx_avail_cnt < RX_DESC_CNT) {
1452 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1453 break;
1454 rxptr->rx_skb_ptr = skb;
1455 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1456 skb_tail_pointer(skb),
1457 RX_ALLOC_SIZE,
1458 PCI_DMA_FROMDEVICE));
1459 wmb();
1460 rxptr->rdes0 = cpu_to_le32(0x80000000);
1461 rxptr = rxptr->next_rx_desc;
1462 db->rx_avail_cnt++;
1463 }
1464
1465 db->rx_insert_ptr = rxptr;
1466}
1467
1468
1469
1470
1471
1472
1473static u16 read_srom_word(long ioaddr, int offset)
1474{
1475 int i;
1476 u16 srom_data = 0;
1477 long cr9_ioaddr = ioaddr + DCR9;
1478
1479 outl(CR9_SROM_READ, cr9_ioaddr);
1480 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1481
1482
1483 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1484 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1485 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1486
1487
1488 for (i = 5; i >= 0; i--) {
1489 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1490 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1491 }
1492
1493 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1494
1495 for (i = 16; i > 0; i--) {
1496 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1497 udelay(5);
1498 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1499 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1500 udelay(5);
1501 }
1502
1503 outl(CR9_SROM_READ, cr9_ioaddr);
1504 return srom_data;
1505}
1506
1507
1508
1509
1510
1511
1512static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1513{
1514 u8 ErrFlag = 0;
1515 u16 phy_mode;
1516
1517 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1518 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1519
1520 if ( (phy_mode & 0x24) == 0x24 ) {
1521
1522 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1523 if(phy_mode&0x8000)
1524 phy_mode = 0x8000;
1525 else if(phy_mode&0x4000)
1526 phy_mode = 0x4000;
1527 else if(phy_mode&0x2000)
1528 phy_mode = 0x2000;
1529 else
1530 phy_mode = 0x1000;
1531
1532
1533 switch (phy_mode) {
1534 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1535 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1536 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1537 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1538 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1539 }
1540 } else {
1541 db->op_mode = ULI526X_10MHF;
1542 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1543 ErrFlag = 1;
1544 }
1545
1546 return ErrFlag;
1547}
1548
1549
1550
1551
1552
1553
1554
1555
1556static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1557{
1558 u16 phy_reg;
1559
1560
1561 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1562
1563 if (db->media_mode & ULI526X_AUTO) {
1564
1565 phy_reg |= db->PHY_reg4;
1566 } else {
1567
1568 switch(db->media_mode) {
1569 case ULI526X_10MHF: phy_reg |= 0x20; break;
1570 case ULI526X_10MFD: phy_reg |= 0x40; break;
1571 case ULI526X_100MHF: phy_reg |= 0x80; break;
1572 case ULI526X_100MFD: phy_reg |= 0x100; break;
1573 }
1574
1575 }
1576
1577
1578 if ( !(phy_reg & 0x01e0)) {
1579 phy_reg|=db->PHY_reg4;
1580 db->media_mode|=ULI526X_AUTO;
1581 }
1582 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1583
1584
1585 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1586 udelay(50);
1587}
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597static void uli526x_process_mode(struct uli526x_board_info *db)
1598{
1599 u16 phy_reg;
1600
1601
1602 if (db->op_mode & 0x4)
1603 db->cr6_data |= CR6_FDM;
1604 else
1605 db->cr6_data &= ~CR6_FDM;
1606
1607 update_cr6(db->cr6_data, db->ioaddr);
1608
1609
1610 if ( !(db->media_mode & 0x8)) {
1611
1612 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1613 if ( !(phy_reg & 0x1) ) {
1614
1615 phy_reg = 0x0;
1616 switch(db->op_mode) {
1617 case ULI526X_10MHF: phy_reg = 0x0; break;
1618 case ULI526X_10MFD: phy_reg = 0x100; break;
1619 case ULI526X_100MHF: phy_reg = 0x2000; break;
1620 case ULI526X_100MFD: phy_reg = 0x2100; break;
1621 }
1622 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1623 }
1624 }
1625}
1626
1627
1628
1629
1630
1631
1632static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1633{
1634 u16 i;
1635 unsigned long ioaddr;
1636
1637 if(chip_id == PCI_ULI5263_ID)
1638 {
1639 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1640 return;
1641 }
1642
1643 ioaddr = iobase + DCR9;
1644
1645
1646 for (i = 0; i < 35; i++)
1647 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1648
1649
1650 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1651 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1652
1653
1654 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1655 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1656
1657
1658 for (i = 0x10; i > 0; i = i >> 1)
1659 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1660
1661
1662 for (i = 0x10; i > 0; i = i >> 1)
1663 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1664
1665
1666 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1667 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1668
1669
1670 for ( i = 0x8000; i > 0; i >>= 1)
1671 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1672
1673}
1674
1675
1676
1677
1678
1679
1680static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1681{
1682 int i;
1683 u16 phy_data;
1684 unsigned long ioaddr;
1685
1686 if(chip_id == PCI_ULI5263_ID)
1687 return phy_readby_cr10(iobase, phy_addr, offset);
1688
1689 ioaddr = iobase + DCR9;
1690
1691
1692 for (i = 0; i < 35; i++)
1693 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1694
1695
1696 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1697 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1698
1699
1700 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1701 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1702
1703
1704 for (i = 0x10; i > 0; i = i >> 1)
1705 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1706
1707
1708 for (i = 0x10; i > 0; i = i >> 1)
1709 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1710
1711
1712 phy_read_1bit(ioaddr, chip_id);
1713
1714
1715 for (phy_data = 0, i = 0; i < 16; i++) {
1716 phy_data <<= 1;
1717 phy_data |= phy_read_1bit(ioaddr, chip_id);
1718 }
1719
1720 return phy_data;
1721}
1722
1723static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1724{
1725 unsigned long ioaddr,cr10_value;
1726
1727 ioaddr = iobase + DCR10;
1728 cr10_value = phy_addr;
1729 cr10_value = (cr10_value<<5) + offset;
1730 cr10_value = (cr10_value<<16) + 0x08000000;
1731 outl(cr10_value,ioaddr);
1732 udelay(1);
1733 while(1)
1734 {
1735 cr10_value = inl(ioaddr);
1736 if(cr10_value&0x10000000)
1737 break;
1738 }
1739 return (cr10_value&0x0ffff);
1740}
1741
1742static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1743{
1744 unsigned long ioaddr,cr10_value;
1745
1746 ioaddr = iobase + DCR10;
1747 cr10_value = phy_addr;
1748 cr10_value = (cr10_value<<5) + offset;
1749 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1750 outl(cr10_value,ioaddr);
1751 udelay(1);
1752}
1753
1754
1755
1756
1757static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1758{
1759 outl(phy_data , ioaddr);
1760 udelay(1);
1761 outl(phy_data | MDCLKH, ioaddr);
1762 udelay(1);
1763 outl(phy_data , ioaddr);
1764 udelay(1);
1765}
1766
1767
1768
1769
1770
1771
1772static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1773{
1774 u16 phy_data;
1775
1776 outl(0x50000 , ioaddr);
1777 udelay(1);
1778 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1779 outl(0x40000 , ioaddr);
1780 udelay(1);
1781
1782 return phy_data;
1783}
1784
1785
1786static struct pci_device_id uli526x_pci_tbl[] = {
1787 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1788 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1789 { 0, }
1790};
1791MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1792
1793
1794static struct pci_driver uli526x_driver = {
1795 .name = "uli526x",
1796 .id_table = uli526x_pci_tbl,
1797 .probe = uli526x_init_one,
1798 .remove = __devexit_p(uli526x_remove_one),
1799 .suspend = uli526x_suspend,
1800 .resume = uli526x_resume,
1801};
1802
1803MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1804MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1805MODULE_LICENSE("GPL");
1806
1807module_param(debug, int, 0644);
1808module_param(mode, int, 0);
1809module_param(cr6set, int, 0);
1810MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1811MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1812
1813
1814
1815
1816
1817
1818static int __init uli526x_init_module(void)
1819{
1820
1821 printk(version);
1822 printed_version = 1;
1823
1824 ULI526X_DBUG(0, "init_module() ", debug);
1825
1826 if (debug)
1827 uli526x_debug = debug;
1828 if (cr6set)
1829 uli526x_cr6_user_set = cr6set;
1830
1831 switch (mode) {
1832 case ULI526X_10MHF:
1833 case ULI526X_100MHF:
1834 case ULI526X_10MFD:
1835 case ULI526X_100MFD:
1836 uli526x_media_mode = mode;
1837 break;
1838 default:
1839 uli526x_media_mode = ULI526X_AUTO;
1840 break;
1841 }
1842
1843 return pci_register_driver(&uli526x_driver);
1844}
1845
1846
1847
1848
1849
1850
1851
1852
1853static void __exit uli526x_cleanup_module(void)
1854{
1855 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1856 pci_unregister_driver(&uli526x_driver);
1857}
1858
1859module_init(uli526x_init_module);
1860module_exit(uli526x_cleanup_module);
1861