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50
51static int rx_copybreak = 200;
52
53
54
55
56
57
58static unsigned int use_mmio = 2;
59
60
61
62
63
64static const int multicast_filter_limit = 32;
65
66
67
68
69
70
71
72
73
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75
76
77
78
79#define TXHI_ENTRIES 2
80#define TXLO_ENTRIES 128
81#define RX_ENTRIES 32
82#define COMMAND_ENTRIES 16
83#define RESPONSE_ENTRIES 32
84
85#define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
86#define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
87
88
89
90
91
92#define RXFREE_ENTRIES 128
93#define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
94
95
96
97
98#define TX_TIMEOUT (2*HZ)
99
100#define PKT_BUF_SZ 1536
101
102#define DRV_MODULE_NAME "typhoon"
103#define DRV_MODULE_VERSION "1.5.9"
104#define DRV_MODULE_RELDATE "Mar 2, 2009"
105#define PFX DRV_MODULE_NAME ": "
106#define ERR_PFX KERN_ERR PFX
107#define FIRMWARE_NAME "3com/typhoon.bin"
108
109#include <linux/module.h>
110#include <linux/kernel.h>
111#include <linux/sched.h>
112#include <linux/string.h>
113#include <linux/timer.h>
114#include <linux/errno.h>
115#include <linux/ioport.h>
116#include <linux/slab.h>
117#include <linux/interrupt.h>
118#include <linux/pci.h>
119#include <linux/netdevice.h>
120#include <linux/etherdevice.h>
121#include <linux/skbuff.h>
122#include <linux/mm.h>
123#include <linux/init.h>
124#include <linux/delay.h>
125#include <linux/ethtool.h>
126#include <linux/if_vlan.h>
127#include <linux/crc32.h>
128#include <linux/bitops.h>
129#include <asm/processor.h>
130#include <asm/io.h>
131#include <asm/uaccess.h>
132#include <linux/in6.h>
133#include <linux/dma-mapping.h>
134#include <linux/firmware.h>
135
136#include "typhoon.h"
137
138static char version[] __devinitdata =
139 "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
140
141MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
142MODULE_VERSION(DRV_MODULE_VERSION);
143MODULE_LICENSE("GPL");
144MODULE_FIRMWARE(FIRMWARE_NAME);
145MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
146MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
147 "the buffer given back to the NIC. Default "
148 "is 200.");
149MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
150 "Default is to try MMIO and fallback to PIO.");
151module_param(rx_copybreak, int, 0);
152module_param(use_mmio, int, 0);
153
154#if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
155#warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
156#undef NETIF_F_TSO
157#endif
158
159#if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
160#error TX ring too small!
161#endif
162
163struct typhoon_card_info {
164 char *name;
165 int capabilities;
166};
167
168#define TYPHOON_CRYPTO_NONE 0x00
169#define TYPHOON_CRYPTO_DES 0x01
170#define TYPHOON_CRYPTO_3DES 0x02
171#define TYPHOON_CRYPTO_VARIABLE 0x04
172#define TYPHOON_FIBER 0x08
173#define TYPHOON_WAKEUP_NEEDS_RESET 0x10
174
175enum typhoon_cards {
176 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
177 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
178 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
179 TYPHOON_FXM,
180};
181
182
183static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
184 { "3Com Typhoon (3C990-TX)",
185 TYPHOON_CRYPTO_NONE},
186 { "3Com Typhoon (3CR990-TX-95)",
187 TYPHOON_CRYPTO_DES},
188 { "3Com Typhoon (3CR990-TX-97)",
189 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
190 { "3Com Typhoon (3C990SVR)",
191 TYPHOON_CRYPTO_NONE},
192 { "3Com Typhoon (3CR990SVR95)",
193 TYPHOON_CRYPTO_DES},
194 { "3Com Typhoon (3CR990SVR97)",
195 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
196 { "3Com Typhoon2 (3C990B-TX-M)",
197 TYPHOON_CRYPTO_VARIABLE},
198 { "3Com Typhoon2 (3C990BSVR)",
199 TYPHOON_CRYPTO_VARIABLE},
200 { "3Com Typhoon (3CR990-FX-95)",
201 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
202 { "3Com Typhoon (3CR990-FX-97)",
203 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
204 { "3Com Typhoon (3CR990-FX-95 Server)",
205 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
206 { "3Com Typhoon (3CR990-FX-97 Server)",
207 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
208 { "3Com Typhoon2 (3C990B-FX-97)",
209 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
210};
211
212
213
214
215
216
217
218static struct pci_device_id typhoon_pci_tbl[] = {
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
226 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
227 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
228 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
229 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
230 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
231 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
232 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
233 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
234 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
235 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
236 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
237 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
238 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
239 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
241 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
243 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
245 { 0, }
246};
247MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
248
249
250
251
252
253#define __3xp_aligned ____cacheline_aligned
254struct typhoon_shared {
255 struct typhoon_interface iface;
256 struct typhoon_indexes indexes __3xp_aligned;
257 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
258 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
259 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
260 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
261 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
262 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
263 u32 zeroWord;
264 struct tx_desc txHi[TXHI_ENTRIES];
265} __attribute__ ((packed));
266
267struct rxbuff_ent {
268 struct sk_buff *skb;
269 dma_addr_t dma_addr;
270};
271
272struct typhoon {
273
274 struct transmit_ring txLoRing ____cacheline_aligned;
275 struct pci_dev * tx_pdev;
276 void __iomem *tx_ioaddr;
277 u32 txlo_dma_addr;
278
279
280 void __iomem *ioaddr ____cacheline_aligned;
281 struct typhoon_indexes *indexes;
282 u8 awaiting_resp;
283 u8 duplex;
284 u8 speed;
285 u8 card_state;
286 struct basic_ring rxLoRing;
287 struct pci_dev * pdev;
288 struct net_device * dev;
289 struct napi_struct napi;
290 spinlock_t state_lock;
291 struct vlan_group * vlgrp;
292 struct basic_ring rxHiRing;
293 struct basic_ring rxBuffRing;
294 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
295
296
297 spinlock_t command_lock ____cacheline_aligned;
298 struct basic_ring cmdRing;
299 struct basic_ring respRing;
300 struct net_device_stats stats;
301 struct net_device_stats stats_saved;
302 const char * name;
303 struct typhoon_shared * shared;
304 dma_addr_t shared_dma;
305 __le16 xcvr_select;
306 __le16 wol_events;
307 __le32 offload;
308
309
310 int capabilities;
311 struct transmit_ring txHiRing;
312};
313
314enum completion_wait_values {
315 NoWait = 0, WaitNoSleep, WaitSleep,
316};
317
318
319
320
321
322enum state_values {
323 Sleeping = 0, Running,
324};
325
326
327
328
329#define typhoon_post_pci_writes(x) \
330 do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
331
332
333
334#define TYPHOON_UDELAY 50
335#define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
336#define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
337#define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
338
339#if defined(NETIF_F_TSO)
340#define skb_tso_size(x) (skb_shinfo(x)->gso_size)
341#define TSO_NUM_DESCRIPTORS 2
342#define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
343#else
344#define NETIF_F_TSO 0
345#define skb_tso_size(x) 0
346#define TSO_NUM_DESCRIPTORS 0
347#define TSO_OFFLOAD_ON 0
348#endif
349
350static inline void
351typhoon_inc_index(u32 *index, const int count, const int num_entries)
352{
353
354
355
356
357 *index += count * sizeof(struct cmd_desc);
358 *index %= num_entries * sizeof(struct cmd_desc);
359}
360
361static inline void
362typhoon_inc_cmd_index(u32 *index, const int count)
363{
364 typhoon_inc_index(index, count, COMMAND_ENTRIES);
365}
366
367static inline void
368typhoon_inc_resp_index(u32 *index, const int count)
369{
370 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
371}
372
373static inline void
374typhoon_inc_rxfree_index(u32 *index, const int count)
375{
376 typhoon_inc_index(index, count, RXFREE_ENTRIES);
377}
378
379static inline void
380typhoon_inc_tx_index(u32 *index, const int count)
381{
382
383 typhoon_inc_index(index, count, TXLO_ENTRIES);
384}
385
386static inline void
387typhoon_inc_rx_index(u32 *index, const int count)
388{
389
390 *index += count * sizeof(struct rx_desc);
391 *index %= RX_ENTRIES * sizeof(struct rx_desc);
392}
393
394static int
395typhoon_reset(void __iomem *ioaddr, int wait_type)
396{
397 int i, err = 0;
398 int timeout;
399
400 if(wait_type == WaitNoSleep)
401 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
402 else
403 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
404
405 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
406 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
407
408 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
409 typhoon_post_pci_writes(ioaddr);
410 udelay(1);
411 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
412
413 if(wait_type != NoWait) {
414 for(i = 0; i < timeout; i++) {
415 if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
416 TYPHOON_STATUS_WAITING_FOR_HOST)
417 goto out;
418
419 if(wait_type == WaitSleep)
420 schedule_timeout_uninterruptible(1);
421 else
422 udelay(TYPHOON_UDELAY);
423 }
424
425 err = -ETIMEDOUT;
426 }
427
428out:
429 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
430 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
431
432
433
434
435
436
437
438
439
440
441
442 if(wait_type == WaitSleep)
443 msleep(5);
444 else
445 udelay(500);
446 return err;
447}
448
449static int
450typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
451{
452 int i, err = 0;
453
454 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
455 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
456 goto out;
457 udelay(TYPHOON_UDELAY);
458 }
459
460 err = -ETIMEDOUT;
461
462out:
463 return err;
464}
465
466static inline void
467typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
468{
469 if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
470 netif_carrier_off(dev);
471 else
472 netif_carrier_on(dev);
473}
474
475static inline void
476typhoon_hello(struct typhoon *tp)
477{
478 struct basic_ring *ring = &tp->cmdRing;
479 struct cmd_desc *cmd;
480
481
482
483
484
485 if(spin_trylock(&tp->command_lock)) {
486 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
487 typhoon_inc_cmd_index(&ring->lastWrite, 1);
488
489 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
490 smp_wmb();
491 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
492 spin_unlock(&tp->command_lock);
493 }
494}
495
496static int
497typhoon_process_response(struct typhoon *tp, int resp_size,
498 struct resp_desc *resp_save)
499{
500 struct typhoon_indexes *indexes = tp->indexes;
501 struct resp_desc *resp;
502 u8 *base = tp->respRing.ringBase;
503 int count, len, wrap_len;
504 u32 cleared;
505 u32 ready;
506
507 cleared = le32_to_cpu(indexes->respCleared);
508 ready = le32_to_cpu(indexes->respReady);
509 while(cleared != ready) {
510 resp = (struct resp_desc *)(base + cleared);
511 count = resp->numDesc + 1;
512 if(resp_save && resp->seqNo) {
513 if(count > resp_size) {
514 resp_save->flags = TYPHOON_RESP_ERROR;
515 goto cleanup;
516 }
517
518 wrap_len = 0;
519 len = count * sizeof(*resp);
520 if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
521 wrap_len = cleared + len - RESPONSE_RING_SIZE;
522 len = RESPONSE_RING_SIZE - cleared;
523 }
524
525 memcpy(resp_save, resp, len);
526 if(unlikely(wrap_len)) {
527 resp_save += len / sizeof(*resp);
528 memcpy(resp_save, base, wrap_len);
529 }
530
531 resp_save = NULL;
532 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
533 typhoon_media_status(tp->dev, resp);
534 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
535 typhoon_hello(tp);
536 } else {
537 printk(KERN_ERR "%s: dumping unexpected response "
538 "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
539 tp->name, le16_to_cpu(resp->cmd),
540 resp->numDesc, resp->flags,
541 le16_to_cpu(resp->parm1),
542 le32_to_cpu(resp->parm2),
543 le32_to_cpu(resp->parm3));
544 }
545
546cleanup:
547 typhoon_inc_resp_index(&cleared, count);
548 }
549
550 indexes->respCleared = cpu_to_le32(cleared);
551 wmb();
552 return (resp_save == NULL);
553}
554
555static inline int
556typhoon_num_free(int lastWrite, int lastRead, int ringSize)
557{
558
559
560
561 lastWrite /= sizeof(struct cmd_desc);
562 lastRead /= sizeof(struct cmd_desc);
563 return (ringSize + lastRead - lastWrite - 1) % ringSize;
564}
565
566static inline int
567typhoon_num_free_cmd(struct typhoon *tp)
568{
569 int lastWrite = tp->cmdRing.lastWrite;
570 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
571
572 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
573}
574
575static inline int
576typhoon_num_free_resp(struct typhoon *tp)
577{
578 int respReady = le32_to_cpu(tp->indexes->respReady);
579 int respCleared = le32_to_cpu(tp->indexes->respCleared);
580
581 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
582}
583
584static inline int
585typhoon_num_free_tx(struct transmit_ring *ring)
586{
587
588 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
589}
590
591static int
592typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
593 int num_resp, struct resp_desc *resp)
594{
595 struct typhoon_indexes *indexes = tp->indexes;
596 struct basic_ring *ring = &tp->cmdRing;
597 struct resp_desc local_resp;
598 int i, err = 0;
599 int got_resp;
600 int freeCmd, freeResp;
601 int len, wrap_len;
602
603 spin_lock(&tp->command_lock);
604
605 freeCmd = typhoon_num_free_cmd(tp);
606 freeResp = typhoon_num_free_resp(tp);
607
608 if(freeCmd < num_cmd || freeResp < num_resp) {
609 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
610 "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
611 freeResp, num_resp);
612 err = -ENOMEM;
613 goto out;
614 }
615
616 if(cmd->flags & TYPHOON_CMD_RESPOND) {
617
618
619
620 tp->awaiting_resp = 1;
621 if(resp == NULL) {
622 resp = &local_resp;
623 num_resp = 1;
624 }
625 }
626
627 wrap_len = 0;
628 len = num_cmd * sizeof(*cmd);
629 if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
630 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
631 len = COMMAND_RING_SIZE - ring->lastWrite;
632 }
633
634 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
635 if(unlikely(wrap_len)) {
636 struct cmd_desc *wrap_ptr = cmd;
637 wrap_ptr += len / sizeof(*cmd);
638 memcpy(ring->ringBase, wrap_ptr, wrap_len);
639 }
640
641 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
642
643
644
645 wmb();
646 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
647 typhoon_post_pci_writes(tp->ioaddr);
648
649 if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
650 goto out;
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668 got_resp = 0;
669 for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
670 if(indexes->respCleared != indexes->respReady)
671 got_resp = typhoon_process_response(tp, num_resp,
672 resp);
673 udelay(TYPHOON_UDELAY);
674 }
675
676 if(!got_resp) {
677 err = -ETIMEDOUT;
678 goto out;
679 }
680
681
682
683
684 if(resp->flags & TYPHOON_RESP_ERROR)
685 err = -EIO;
686
687out:
688 if(tp->awaiting_resp) {
689 tp->awaiting_resp = 0;
690 smp_wmb();
691
692
693
694
695
696
697
698
699 if(indexes->respCleared != indexes->respReady)
700 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
701 }
702
703 spin_unlock(&tp->command_lock);
704 return err;
705}
706
707static void
708typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
709{
710 struct typhoon *tp = netdev_priv(dev);
711 struct cmd_desc xp_cmd;
712 int err;
713
714 spin_lock_bh(&tp->state_lock);
715 if(!tp->vlgrp != !grp) {
716
717
718
719 if(grp)
720 tp->offload |= TYPHOON_OFFLOAD_VLAN;
721 else
722 tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
723
724
725
726
727
728
729 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
730 TYPHOON_CMD_SET_OFFLOAD_TASKS);
731 xp_cmd.parm2 = tp->offload;
732 xp_cmd.parm3 = tp->offload;
733 spin_unlock_bh(&tp->state_lock);
734 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
735 if(err < 0)
736 printk("%s: vlan offload error %d\n", tp->name, -err);
737 spin_lock_bh(&tp->state_lock);
738 }
739
740
741 tp->vlgrp = grp;
742 spin_unlock_bh(&tp->state_lock);
743}
744
745static inline void
746typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
747 u32 ring_dma)
748{
749 struct tcpopt_desc *tcpd;
750 u32 tcpd_offset = ring_dma;
751
752 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
753 tcpd_offset += txRing->lastWrite;
754 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
755 typhoon_inc_tx_index(&txRing->lastWrite, 1);
756
757 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
758 tcpd->numDesc = 1;
759 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
760 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
761 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
762 tcpd->bytesTx = cpu_to_le32(skb->len);
763 tcpd->status = 0;
764}
765
766static netdev_tx_t
767typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
768{
769 struct typhoon *tp = netdev_priv(dev);
770 struct transmit_ring *txRing;
771 struct tx_desc *txd, *first_txd;
772 dma_addr_t skb_dma;
773 int numDesc;
774
775
776
777
778
779
780
781 txRing = &tp->txLoRing;
782
783
784
785
786
787
788
789
790
791
792
793
794 numDesc = skb_shinfo(skb)->nr_frags + 1;
795 if (skb_is_gso(skb))
796 numDesc++;
797
798
799
800
801
802
803
804
805
806
807 while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
808 smp_rmb();
809
810 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
811 typhoon_inc_tx_index(&txRing->lastWrite, 1);
812
813 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
814 first_txd->numDesc = 0;
815 first_txd->len = 0;
816 first_txd->tx_addr = (u64)((unsigned long) skb);
817 first_txd->processFlags = 0;
818
819 if(skb->ip_summed == CHECKSUM_PARTIAL) {
820
821 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
822 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
823 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
824 }
825
826 if(vlan_tx_tag_present(skb)) {
827 first_txd->processFlags |=
828 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
829 first_txd->processFlags |=
830 cpu_to_le32(ntohs(vlan_tx_tag_get(skb)) <<
831 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
832 }
833
834 if (skb_is_gso(skb)) {
835 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
836 first_txd->numDesc++;
837
838 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
839 }
840
841 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
842 typhoon_inc_tx_index(&txRing->lastWrite, 1);
843
844
845
846
847 if(skb_shinfo(skb)->nr_frags == 0) {
848 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
849 PCI_DMA_TODEVICE);
850 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
851 txd->len = cpu_to_le16(skb->len);
852 txd->frag.addr = cpu_to_le32(skb_dma);
853 txd->frag.addrHi = 0;
854 first_txd->numDesc++;
855 } else {
856 int i, len;
857
858 len = skb_headlen(skb);
859 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
860 PCI_DMA_TODEVICE);
861 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
862 txd->len = cpu_to_le16(len);
863 txd->frag.addr = cpu_to_le32(skb_dma);
864 txd->frag.addrHi = 0;
865 first_txd->numDesc++;
866
867 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
868 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
869 void *frag_addr;
870
871 txd = (struct tx_desc *) (txRing->ringBase +
872 txRing->lastWrite);
873 typhoon_inc_tx_index(&txRing->lastWrite, 1);
874
875 len = frag->size;
876 frag_addr = (void *) page_address(frag->page) +
877 frag->page_offset;
878 skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
879 PCI_DMA_TODEVICE);
880 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
881 txd->len = cpu_to_le16(len);
882 txd->frag.addr = cpu_to_le32(skb_dma);
883 txd->frag.addrHi = 0;
884 first_txd->numDesc++;
885 }
886 }
887
888
889
890 wmb();
891 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
892
893 dev->trans_start = jiffies;
894
895
896
897
898
899
900 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
901
902 if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
903 netif_stop_queue(dev);
904
905
906
907
908
909 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
910 netif_wake_queue(dev);
911 }
912
913 return NETDEV_TX_OK;
914}
915
916static void
917typhoon_set_rx_mode(struct net_device *dev)
918{
919 struct typhoon *tp = netdev_priv(dev);
920 struct cmd_desc xp_cmd;
921 u32 mc_filter[2];
922 __le16 filter;
923
924 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
925 if(dev->flags & IFF_PROMISC) {
926 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
927 } else if((dev->mc_count > multicast_filter_limit) ||
928 (dev->flags & IFF_ALLMULTI)) {
929
930 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
931 } else if(dev->mc_count) {
932 struct dev_mc_list *mclist;
933 int i;
934
935 memset(mc_filter, 0, sizeof(mc_filter));
936 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
937 i++, mclist = mclist->next) {
938 int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
939 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
940 }
941
942 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
943 TYPHOON_CMD_SET_MULTICAST_HASH);
944 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
945 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
946 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
947 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
948
949 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
950 }
951
952 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
953 xp_cmd.parm1 = filter;
954 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
955}
956
957static int
958typhoon_do_get_stats(struct typhoon *tp)
959{
960 struct net_device_stats *stats = &tp->stats;
961 struct net_device_stats *saved = &tp->stats_saved;
962 struct cmd_desc xp_cmd;
963 struct resp_desc xp_resp[7];
964 struct stats_resp *s = (struct stats_resp *) xp_resp;
965 int err;
966
967 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
968 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
969 if(err < 0)
970 return err;
971
972
973
974
975
976
977
978 stats->tx_packets = le32_to_cpu(s->txPackets);
979 stats->tx_bytes = le64_to_cpu(s->txBytes);
980 stats->tx_errors = le32_to_cpu(s->txCarrierLost);
981 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
982 stats->collisions = le32_to_cpu(s->txMultipleCollisions);
983 stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
984 stats->rx_bytes = le64_to_cpu(s->rxBytesGood);
985 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
986 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
987 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
988 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
989 stats->rx_length_errors = le32_to_cpu(s->rxOversized);
990 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
991 SPEED_100 : SPEED_10;
992 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
993 DUPLEX_FULL : DUPLEX_HALF;
994
995
996
997 stats->tx_packets += saved->tx_packets;
998 stats->tx_bytes += saved->tx_bytes;
999 stats->tx_errors += saved->tx_errors;
1000 stats->collisions += saved->collisions;
1001 stats->rx_packets += saved->rx_packets;
1002 stats->rx_bytes += saved->rx_bytes;
1003 stats->rx_fifo_errors += saved->rx_fifo_errors;
1004 stats->rx_errors += saved->rx_errors;
1005 stats->rx_crc_errors += saved->rx_crc_errors;
1006 stats->rx_length_errors += saved->rx_length_errors;
1007
1008 return 0;
1009}
1010
1011static struct net_device_stats *
1012typhoon_get_stats(struct net_device *dev)
1013{
1014 struct typhoon *tp = netdev_priv(dev);
1015 struct net_device_stats *stats = &tp->stats;
1016 struct net_device_stats *saved = &tp->stats_saved;
1017
1018 smp_rmb();
1019 if(tp->card_state == Sleeping)
1020 return saved;
1021
1022 if(typhoon_do_get_stats(tp) < 0) {
1023 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1024 return saved;
1025 }
1026
1027 return stats;
1028}
1029
1030static int
1031typhoon_set_mac_address(struct net_device *dev, void *addr)
1032{
1033 struct sockaddr *saddr = (struct sockaddr *) addr;
1034
1035 if(netif_running(dev))
1036 return -EBUSY;
1037
1038 memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1039 return 0;
1040}
1041
1042static void
1043typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1044{
1045 struct typhoon *tp = netdev_priv(dev);
1046 struct pci_dev *pci_dev = tp->pdev;
1047 struct cmd_desc xp_cmd;
1048 struct resp_desc xp_resp[3];
1049
1050 smp_rmb();
1051 if(tp->card_state == Sleeping) {
1052 strcpy(info->fw_version, "Sleep image");
1053 } else {
1054 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1055 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1056 strcpy(info->fw_version, "Unknown runtime");
1057 } else {
1058 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
1059 snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1060 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1061 sleep_ver & 0xfff);
1062 }
1063 }
1064
1065 strcpy(info->driver, DRV_MODULE_NAME);
1066 strcpy(info->version, DRV_MODULE_VERSION);
1067 strcpy(info->bus_info, pci_name(pci_dev));
1068}
1069
1070static int
1071typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1072{
1073 struct typhoon *tp = netdev_priv(dev);
1074
1075 cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1076 SUPPORTED_Autoneg;
1077
1078 switch (tp->xcvr_select) {
1079 case TYPHOON_XCVR_10HALF:
1080 cmd->advertising = ADVERTISED_10baseT_Half;
1081 break;
1082 case TYPHOON_XCVR_10FULL:
1083 cmd->advertising = ADVERTISED_10baseT_Full;
1084 break;
1085 case TYPHOON_XCVR_100HALF:
1086 cmd->advertising = ADVERTISED_100baseT_Half;
1087 break;
1088 case TYPHOON_XCVR_100FULL:
1089 cmd->advertising = ADVERTISED_100baseT_Full;
1090 break;
1091 case TYPHOON_XCVR_AUTONEG:
1092 cmd->advertising = ADVERTISED_10baseT_Half |
1093 ADVERTISED_10baseT_Full |
1094 ADVERTISED_100baseT_Half |
1095 ADVERTISED_100baseT_Full |
1096 ADVERTISED_Autoneg;
1097 break;
1098 }
1099
1100 if(tp->capabilities & TYPHOON_FIBER) {
1101 cmd->supported |= SUPPORTED_FIBRE;
1102 cmd->advertising |= ADVERTISED_FIBRE;
1103 cmd->port = PORT_FIBRE;
1104 } else {
1105 cmd->supported |= SUPPORTED_10baseT_Half |
1106 SUPPORTED_10baseT_Full |
1107 SUPPORTED_TP;
1108 cmd->advertising |= ADVERTISED_TP;
1109 cmd->port = PORT_TP;
1110 }
1111
1112
1113 typhoon_do_get_stats(tp);
1114 cmd->speed = tp->speed;
1115 cmd->duplex = tp->duplex;
1116 cmd->phy_address = 0;
1117 cmd->transceiver = XCVR_INTERNAL;
1118 if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1119 cmd->autoneg = AUTONEG_ENABLE;
1120 else
1121 cmd->autoneg = AUTONEG_DISABLE;
1122 cmd->maxtxpkt = 1;
1123 cmd->maxrxpkt = 1;
1124
1125 return 0;
1126}
1127
1128static int
1129typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1130{
1131 struct typhoon *tp = netdev_priv(dev);
1132 struct cmd_desc xp_cmd;
1133 __le16 xcvr;
1134 int err;
1135
1136 err = -EINVAL;
1137 if(cmd->autoneg == AUTONEG_ENABLE) {
1138 xcvr = TYPHOON_XCVR_AUTONEG;
1139 } else {
1140 if(cmd->duplex == DUPLEX_HALF) {
1141 if(cmd->speed == SPEED_10)
1142 xcvr = TYPHOON_XCVR_10HALF;
1143 else if(cmd->speed == SPEED_100)
1144 xcvr = TYPHOON_XCVR_100HALF;
1145 else
1146 goto out;
1147 } else if(cmd->duplex == DUPLEX_FULL) {
1148 if(cmd->speed == SPEED_10)
1149 xcvr = TYPHOON_XCVR_10FULL;
1150 else if(cmd->speed == SPEED_100)
1151 xcvr = TYPHOON_XCVR_100FULL;
1152 else
1153 goto out;
1154 } else
1155 goto out;
1156 }
1157
1158 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1159 xp_cmd.parm1 = xcvr;
1160 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1161 if(err < 0)
1162 goto out;
1163
1164 tp->xcvr_select = xcvr;
1165 if(cmd->autoneg == AUTONEG_ENABLE) {
1166 tp->speed = 0xff;
1167 tp->duplex = 0xff;
1168 } else {
1169 tp->speed = cmd->speed;
1170 tp->duplex = cmd->duplex;
1171 }
1172
1173out:
1174 return err;
1175}
1176
1177static void
1178typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1179{
1180 struct typhoon *tp = netdev_priv(dev);
1181
1182 wol->supported = WAKE_PHY | WAKE_MAGIC;
1183 wol->wolopts = 0;
1184 if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1185 wol->wolopts |= WAKE_PHY;
1186 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1187 wol->wolopts |= WAKE_MAGIC;
1188 memset(&wol->sopass, 0, sizeof(wol->sopass));
1189}
1190
1191static int
1192typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1193{
1194 struct typhoon *tp = netdev_priv(dev);
1195
1196 if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1197 return -EINVAL;
1198
1199 tp->wol_events = 0;
1200 if(wol->wolopts & WAKE_PHY)
1201 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1202 if(wol->wolopts & WAKE_MAGIC)
1203 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1204
1205 return 0;
1206}
1207
1208static u32
1209typhoon_get_rx_csum(struct net_device *dev)
1210{
1211
1212
1213 return 1;
1214}
1215
1216static void
1217typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1218{
1219 ering->rx_max_pending = RXENT_ENTRIES;
1220 ering->rx_mini_max_pending = 0;
1221 ering->rx_jumbo_max_pending = 0;
1222 ering->tx_max_pending = TXLO_ENTRIES - 1;
1223
1224 ering->rx_pending = RXENT_ENTRIES;
1225 ering->rx_mini_pending = 0;
1226 ering->rx_jumbo_pending = 0;
1227 ering->tx_pending = TXLO_ENTRIES - 1;
1228}
1229
1230static const struct ethtool_ops typhoon_ethtool_ops = {
1231 .get_settings = typhoon_get_settings,
1232 .set_settings = typhoon_set_settings,
1233 .get_drvinfo = typhoon_get_drvinfo,
1234 .get_wol = typhoon_get_wol,
1235 .set_wol = typhoon_set_wol,
1236 .get_link = ethtool_op_get_link,
1237 .get_rx_csum = typhoon_get_rx_csum,
1238 .set_tx_csum = ethtool_op_set_tx_csum,
1239 .set_sg = ethtool_op_set_sg,
1240 .set_tso = ethtool_op_set_tso,
1241 .get_ringparam = typhoon_get_ringparam,
1242};
1243
1244static int
1245typhoon_wait_interrupt(void __iomem *ioaddr)
1246{
1247 int i, err = 0;
1248
1249 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1250 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1251 TYPHOON_INTR_BOOTCMD)
1252 goto out;
1253 udelay(TYPHOON_UDELAY);
1254 }
1255
1256 err = -ETIMEDOUT;
1257
1258out:
1259 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1260 return err;
1261}
1262
1263#define shared_offset(x) offsetof(struct typhoon_shared, x)
1264
1265static void
1266typhoon_init_interface(struct typhoon *tp)
1267{
1268 struct typhoon_interface *iface = &tp->shared->iface;
1269 dma_addr_t shared_dma;
1270
1271 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1272
1273
1274
1275 shared_dma = tp->shared_dma + shared_offset(indexes);
1276 iface->ringIndex = cpu_to_le32(shared_dma);
1277
1278 shared_dma = tp->shared_dma + shared_offset(txLo);
1279 iface->txLoAddr = cpu_to_le32(shared_dma);
1280 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1281
1282 shared_dma = tp->shared_dma + shared_offset(txHi);
1283 iface->txHiAddr = cpu_to_le32(shared_dma);
1284 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1285
1286 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1287 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1288 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1289 sizeof(struct rx_free));
1290
1291 shared_dma = tp->shared_dma + shared_offset(rxLo);
1292 iface->rxLoAddr = cpu_to_le32(shared_dma);
1293 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1294
1295 shared_dma = tp->shared_dma + shared_offset(rxHi);
1296 iface->rxHiAddr = cpu_to_le32(shared_dma);
1297 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1298
1299 shared_dma = tp->shared_dma + shared_offset(cmd);
1300 iface->cmdAddr = cpu_to_le32(shared_dma);
1301 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1302
1303 shared_dma = tp->shared_dma + shared_offset(resp);
1304 iface->respAddr = cpu_to_le32(shared_dma);
1305 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1306
1307 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1308 iface->zeroAddr = cpu_to_le32(shared_dma);
1309
1310 tp->indexes = &tp->shared->indexes;
1311 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1312 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1313 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1314 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1315 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1316 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1317 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1318
1319 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1320 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1321
1322 tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1323 tp->card_state = Sleeping;
1324 smp_wmb();
1325
1326 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1327 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1328
1329 spin_lock_init(&tp->command_lock);
1330 spin_lock_init(&tp->state_lock);
1331}
1332
1333static void
1334typhoon_init_rings(struct typhoon *tp)
1335{
1336 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1337
1338 tp->txLoRing.lastWrite = 0;
1339 tp->txHiRing.lastWrite = 0;
1340 tp->rxLoRing.lastWrite = 0;
1341 tp->rxHiRing.lastWrite = 0;
1342 tp->rxBuffRing.lastWrite = 0;
1343 tp->cmdRing.lastWrite = 0;
1344 tp->cmdRing.lastWrite = 0;
1345
1346 tp->txLoRing.lastRead = 0;
1347 tp->txHiRing.lastRead = 0;
1348}
1349
1350static const struct firmware *typhoon_fw;
1351
1352static int
1353typhoon_request_firmware(struct typhoon *tp)
1354{
1355 const struct typhoon_file_header *fHdr;
1356 const struct typhoon_section_header *sHdr;
1357 const u8 *image_data;
1358 u32 numSections;
1359 u32 section_len;
1360 u32 remaining;
1361 int err;
1362
1363 if (typhoon_fw)
1364 return 0;
1365
1366 err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1367 if (err) {
1368 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
1369 tp->name, FIRMWARE_NAME);
1370 return err;
1371 }
1372
1373 image_data = (u8 *) typhoon_fw->data;
1374 remaining = typhoon_fw->size;
1375 if (remaining < sizeof(struct typhoon_file_header))
1376 goto invalid_fw;
1377
1378 fHdr = (struct typhoon_file_header *) image_data;
1379 if (memcmp(fHdr->tag, "TYPHOON", 8))
1380 goto invalid_fw;
1381
1382 numSections = le32_to_cpu(fHdr->numSections);
1383 image_data += sizeof(struct typhoon_file_header);
1384 remaining -= sizeof(struct typhoon_file_header);
1385
1386 while (numSections--) {
1387 if (remaining < sizeof(struct typhoon_section_header))
1388 goto invalid_fw;
1389
1390 sHdr = (struct typhoon_section_header *) image_data;
1391 image_data += sizeof(struct typhoon_section_header);
1392 section_len = le32_to_cpu(sHdr->len);
1393
1394 if (remaining < section_len)
1395 goto invalid_fw;
1396
1397 image_data += section_len;
1398 remaining -= section_len;
1399 }
1400
1401 return 0;
1402
1403invalid_fw:
1404 printk(KERN_ERR "%s: Invalid firmware image\n", tp->name);
1405 release_firmware(typhoon_fw);
1406 typhoon_fw = NULL;
1407 return -EINVAL;
1408}
1409
1410static int
1411typhoon_download_firmware(struct typhoon *tp)
1412{
1413 void __iomem *ioaddr = tp->ioaddr;
1414 struct pci_dev *pdev = tp->pdev;
1415 const struct typhoon_file_header *fHdr;
1416 const struct typhoon_section_header *sHdr;
1417 const u8 *image_data;
1418 void *dpage;
1419 dma_addr_t dpage_dma;
1420 __sum16 csum;
1421 u32 irqEnabled;
1422 u32 irqMasked;
1423 u32 numSections;
1424 u32 section_len;
1425 u32 len;
1426 u32 load_addr;
1427 u32 hmac;
1428 int i;
1429 int err;
1430
1431 image_data = (u8 *) typhoon_fw->data;
1432 fHdr = (struct typhoon_file_header *) image_data;
1433
1434
1435
1436
1437
1438 err = -ENOMEM;
1439 dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1440 if(!dpage) {
1441 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1442 goto err_out;
1443 }
1444
1445 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1446 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1447 ioaddr + TYPHOON_REG_INTR_ENABLE);
1448 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1449 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1450 ioaddr + TYPHOON_REG_INTR_MASK);
1451
1452 err = -ETIMEDOUT;
1453 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1454 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1455 goto err_out_irq;
1456 }
1457
1458 numSections = le32_to_cpu(fHdr->numSections);
1459 load_addr = le32_to_cpu(fHdr->startAddr);
1460
1461 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1462 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1463 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1464 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1465 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1466 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1467 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1468 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1469 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1470 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1471 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1472 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1473 typhoon_post_pci_writes(ioaddr);
1474 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1475
1476 image_data += sizeof(struct typhoon_file_header);
1477
1478
1479
1480
1481
1482 for(i = 0; i < numSections; i++) {
1483 sHdr = (struct typhoon_section_header *) image_data;
1484 image_data += sizeof(struct typhoon_section_header);
1485 load_addr = le32_to_cpu(sHdr->startAddr);
1486 section_len = le32_to_cpu(sHdr->len);
1487
1488 while(section_len) {
1489 len = min_t(u32, section_len, PAGE_SIZE);
1490
1491 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1492 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1493 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1494 printk(KERN_ERR "%s: segment ready timeout\n",
1495 tp->name);
1496 goto err_out_irq;
1497 }
1498
1499
1500
1501
1502
1503
1504 csum = csum_fold(csum_partial_copy_nocheck(image_data,
1505 dpage, len,
1506 0));
1507
1508 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1509 iowrite32(le16_to_cpu((__force __le16)csum),
1510 ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1511 iowrite32(load_addr,
1512 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1513 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1514 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1515 typhoon_post_pci_writes(ioaddr);
1516 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1517 ioaddr + TYPHOON_REG_COMMAND);
1518
1519 image_data += len;
1520 load_addr += len;
1521 section_len -= len;
1522 }
1523 }
1524
1525 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1526 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1527 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1528 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1529 goto err_out_irq;
1530 }
1531
1532 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1533
1534 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1535 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1536 tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1537 goto err_out_irq;
1538 }
1539
1540 err = 0;
1541
1542err_out_irq:
1543 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1544 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1545
1546 pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1547
1548err_out:
1549 return err;
1550}
1551
1552static int
1553typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1554{
1555 void __iomem *ioaddr = tp->ioaddr;
1556
1557 if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1558 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1559 goto out_timeout;
1560 }
1561
1562 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1563 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1564 typhoon_post_pci_writes(ioaddr);
1565 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1566 ioaddr + TYPHOON_REG_COMMAND);
1567
1568 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1569 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1570 tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1571 goto out_timeout;
1572 }
1573
1574
1575
1576 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1577 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1578 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1579 typhoon_post_pci_writes(ioaddr);
1580 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1581
1582 return 0;
1583
1584out_timeout:
1585 return -ETIMEDOUT;
1586}
1587
1588static u32
1589typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1590 volatile __le32 * index)
1591{
1592 u32 lastRead = txRing->lastRead;
1593 struct tx_desc *tx;
1594 dma_addr_t skb_dma;
1595 int dma_len;
1596 int type;
1597
1598 while(lastRead != le32_to_cpu(*index)) {
1599 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1600 type = tx->flags & TYPHOON_TYPE_MASK;
1601
1602 if(type == TYPHOON_TX_DESC) {
1603
1604
1605 unsigned long ptr = tx->tx_addr;
1606 struct sk_buff *skb = (struct sk_buff *) ptr;
1607 dev_kfree_skb_irq(skb);
1608 } else if(type == TYPHOON_FRAG_DESC) {
1609
1610
1611 skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1612 dma_len = le16_to_cpu(tx->len);
1613 pci_unmap_single(tp->pdev, skb_dma, dma_len,
1614 PCI_DMA_TODEVICE);
1615 }
1616
1617 tx->flags = 0;
1618 typhoon_inc_tx_index(&lastRead, 1);
1619 }
1620
1621 return lastRead;
1622}
1623
1624static void
1625typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1626 volatile __le32 * index)
1627{
1628 u32 lastRead;
1629 int numDesc = MAX_SKB_FRAGS + 1;
1630
1631
1632 lastRead = typhoon_clean_tx(tp, txRing, index);
1633 if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1634 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1635 netif_wake_queue(tp->dev);
1636
1637 txRing->lastRead = lastRead;
1638 smp_wmb();
1639}
1640
1641static void
1642typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1643{
1644 struct typhoon_indexes *indexes = tp->indexes;
1645 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1646 struct basic_ring *ring = &tp->rxBuffRing;
1647 struct rx_free *r;
1648
1649 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1650 le32_to_cpu(indexes->rxBuffCleared)) {
1651
1652
1653 dev_kfree_skb_any(rxb->skb);
1654 rxb->skb = NULL;
1655 return;
1656 }
1657
1658 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1659 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1660 r->virtAddr = idx;
1661 r->physAddr = cpu_to_le32(rxb->dma_addr);
1662
1663
1664 wmb();
1665 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1666}
1667
1668static int
1669typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1670{
1671 struct typhoon_indexes *indexes = tp->indexes;
1672 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1673 struct basic_ring *ring = &tp->rxBuffRing;
1674 struct rx_free *r;
1675 struct sk_buff *skb;
1676 dma_addr_t dma_addr;
1677
1678 rxb->skb = NULL;
1679
1680 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1681 le32_to_cpu(indexes->rxBuffCleared))
1682 return -ENOMEM;
1683
1684 skb = dev_alloc_skb(PKT_BUF_SZ);
1685 if(!skb)
1686 return -ENOMEM;
1687
1688#if 0
1689
1690
1691
1692 skb_reserve(skb, 2);
1693#endif
1694
1695 skb->dev = tp->dev;
1696 dma_addr = pci_map_single(tp->pdev, skb->data,
1697 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1698
1699
1700
1701
1702 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1703 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1704 r->virtAddr = idx;
1705 r->physAddr = cpu_to_le32(dma_addr);
1706 rxb->skb = skb;
1707 rxb->dma_addr = dma_addr;
1708
1709
1710 wmb();
1711 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1712 return 0;
1713}
1714
1715static int
1716typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1717 volatile __le32 * cleared, int budget)
1718{
1719 struct rx_desc *rx;
1720 struct sk_buff *skb, *new_skb;
1721 struct rxbuff_ent *rxb;
1722 dma_addr_t dma_addr;
1723 u32 local_ready;
1724 u32 rxaddr;
1725 int pkt_len;
1726 u32 idx;
1727 __le32 csum_bits;
1728 int received;
1729
1730 received = 0;
1731 local_ready = le32_to_cpu(*ready);
1732 rxaddr = le32_to_cpu(*cleared);
1733 while(rxaddr != local_ready && budget > 0) {
1734 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1735 idx = rx->addr;
1736 rxb = &tp->rxbuffers[idx];
1737 skb = rxb->skb;
1738 dma_addr = rxb->dma_addr;
1739
1740 typhoon_inc_rx_index(&rxaddr, 1);
1741
1742 if(rx->flags & TYPHOON_RX_ERROR) {
1743 typhoon_recycle_rx_skb(tp, idx);
1744 continue;
1745 }
1746
1747 pkt_len = le16_to_cpu(rx->frameLen);
1748
1749 if(pkt_len < rx_copybreak &&
1750 (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1751 skb_reserve(new_skb, 2);
1752 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1753 PKT_BUF_SZ,
1754 PCI_DMA_FROMDEVICE);
1755 skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1756 pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1757 PKT_BUF_SZ,
1758 PCI_DMA_FROMDEVICE);
1759 skb_put(new_skb, pkt_len);
1760 typhoon_recycle_rx_skb(tp, idx);
1761 } else {
1762 new_skb = skb;
1763 skb_put(new_skb, pkt_len);
1764 pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1765 PCI_DMA_FROMDEVICE);
1766 typhoon_alloc_rx_skb(tp, idx);
1767 }
1768 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1769 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1770 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1771 if(csum_bits ==
1772 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1773 || csum_bits ==
1774 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1775 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1776 } else
1777 new_skb->ip_summed = CHECKSUM_NONE;
1778
1779 spin_lock(&tp->state_lock);
1780 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1781 vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1782 ntohl(rx->vlanTag) & 0xffff);
1783 else
1784 netif_receive_skb(new_skb);
1785 spin_unlock(&tp->state_lock);
1786
1787 received++;
1788 budget--;
1789 }
1790 *cleared = cpu_to_le32(rxaddr);
1791
1792 return received;
1793}
1794
1795static void
1796typhoon_fill_free_ring(struct typhoon *tp)
1797{
1798 u32 i;
1799
1800 for(i = 0; i < RXENT_ENTRIES; i++) {
1801 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1802 if(rxb->skb)
1803 continue;
1804 if(typhoon_alloc_rx_skb(tp, i) < 0)
1805 break;
1806 }
1807}
1808
1809static int
1810typhoon_poll(struct napi_struct *napi, int budget)
1811{
1812 struct typhoon *tp = container_of(napi, struct typhoon, napi);
1813 struct typhoon_indexes *indexes = tp->indexes;
1814 int work_done;
1815
1816 rmb();
1817 if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1818 typhoon_process_response(tp, 0, NULL);
1819
1820 if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1821 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1822
1823 work_done = 0;
1824
1825 if(indexes->rxHiCleared != indexes->rxHiReady) {
1826 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1827 &indexes->rxHiCleared, budget);
1828 }
1829
1830 if(indexes->rxLoCleared != indexes->rxLoReady) {
1831 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1832 &indexes->rxLoCleared, budget - work_done);
1833 }
1834
1835 if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1836
1837 typhoon_fill_free_ring(tp);
1838 }
1839
1840 if (work_done < budget) {
1841 napi_complete(napi);
1842 iowrite32(TYPHOON_INTR_NONE,
1843 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1844 typhoon_post_pci_writes(tp->ioaddr);
1845 }
1846
1847 return work_done;
1848}
1849
1850static irqreturn_t
1851typhoon_interrupt(int irq, void *dev_instance)
1852{
1853 struct net_device *dev = dev_instance;
1854 struct typhoon *tp = netdev_priv(dev);
1855 void __iomem *ioaddr = tp->ioaddr;
1856 u32 intr_status;
1857
1858 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1859 if(!(intr_status & TYPHOON_INTR_HOST_INT))
1860 return IRQ_NONE;
1861
1862 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1863
1864 if (napi_schedule_prep(&tp->napi)) {
1865 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1866 typhoon_post_pci_writes(ioaddr);
1867 __napi_schedule(&tp->napi);
1868 } else {
1869 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1870 dev->name);
1871 }
1872 return IRQ_HANDLED;
1873}
1874
1875static void
1876typhoon_free_rx_rings(struct typhoon *tp)
1877{
1878 u32 i;
1879
1880 for(i = 0; i < RXENT_ENTRIES; i++) {
1881 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1882 if(rxb->skb) {
1883 pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1884 PCI_DMA_FROMDEVICE);
1885 dev_kfree_skb(rxb->skb);
1886 rxb->skb = NULL;
1887 }
1888 }
1889}
1890
1891static int
1892typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1893{
1894 struct pci_dev *pdev = tp->pdev;
1895 void __iomem *ioaddr = tp->ioaddr;
1896 struct cmd_desc xp_cmd;
1897 int err;
1898
1899 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1900 xp_cmd.parm1 = events;
1901 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1902 if(err < 0) {
1903 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1904 tp->name, err);
1905 return err;
1906 }
1907
1908 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1909 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1910 if(err < 0) {
1911 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1912 tp->name, err);
1913 return err;
1914 }
1915
1916 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1917 return -ETIMEDOUT;
1918
1919
1920
1921
1922 netif_carrier_off(tp->dev);
1923
1924 pci_enable_wake(tp->pdev, state, 1);
1925 pci_disable_device(pdev);
1926 return pci_set_power_state(pdev, state);
1927}
1928
1929static int
1930typhoon_wakeup(struct typhoon *tp, int wait_type)
1931{
1932 struct pci_dev *pdev = tp->pdev;
1933 void __iomem *ioaddr = tp->ioaddr;
1934
1935 pci_set_power_state(pdev, PCI_D0);
1936 pci_restore_state(pdev);
1937
1938
1939
1940
1941
1942 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1943 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1944 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1945 return typhoon_reset(ioaddr, wait_type);
1946
1947 return 0;
1948}
1949
1950static int
1951typhoon_start_runtime(struct typhoon *tp)
1952{
1953 struct net_device *dev = tp->dev;
1954 void __iomem *ioaddr = tp->ioaddr;
1955 struct cmd_desc xp_cmd;
1956 int err;
1957
1958 typhoon_init_rings(tp);
1959 typhoon_fill_free_ring(tp);
1960
1961 err = typhoon_download_firmware(tp);
1962 if(err < 0) {
1963 printk("%s: cannot load runtime on 3XP\n", tp->name);
1964 goto error_out;
1965 }
1966
1967 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1968 printk("%s: cannot boot 3XP\n", tp->name);
1969 err = -EIO;
1970 goto error_out;
1971 }
1972
1973 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1974 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1975 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1976 if(err < 0)
1977 goto error_out;
1978
1979 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1980 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1981 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1982 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1983 if(err < 0)
1984 goto error_out;
1985
1986
1987
1988
1989 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1990 xp_cmd.parm1 = 0;
1991 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1992 if(err < 0)
1993 goto error_out;
1994
1995 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1996 xp_cmd.parm1 = tp->xcvr_select;
1997 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1998 if(err < 0)
1999 goto error_out;
2000
2001 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
2002 xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
2003 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2004 if(err < 0)
2005 goto error_out;
2006
2007 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
2008 spin_lock_bh(&tp->state_lock);
2009 xp_cmd.parm2 = tp->offload;
2010 xp_cmd.parm3 = tp->offload;
2011 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2012 spin_unlock_bh(&tp->state_lock);
2013 if(err < 0)
2014 goto error_out;
2015
2016 typhoon_set_rx_mode(dev);
2017
2018 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
2019 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2020 if(err < 0)
2021 goto error_out;
2022
2023 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
2024 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2025 if(err < 0)
2026 goto error_out;
2027
2028 tp->card_state = Running;
2029 smp_wmb();
2030
2031 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2032 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
2033 typhoon_post_pci_writes(ioaddr);
2034
2035 return 0;
2036
2037error_out:
2038 typhoon_reset(ioaddr, WaitNoSleep);
2039 typhoon_free_rx_rings(tp);
2040 typhoon_init_rings(tp);
2041 return err;
2042}
2043
2044static int
2045typhoon_stop_runtime(struct typhoon *tp, int wait_type)
2046{
2047 struct typhoon_indexes *indexes = tp->indexes;
2048 struct transmit_ring *txLo = &tp->txLoRing;
2049 void __iomem *ioaddr = tp->ioaddr;
2050 struct cmd_desc xp_cmd;
2051 int i;
2052
2053
2054
2055
2056
2057 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2058
2059 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2060 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2061
2062
2063
2064
2065 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2066 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2067 break;
2068 udelay(TYPHOON_UDELAY);
2069 }
2070
2071 if(i == TYPHOON_WAIT_TIMEOUT)
2072 printk(KERN_ERR
2073 "%s: halt timed out waiting for Tx to complete\n",
2074 tp->name);
2075
2076 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2077 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2078
2079
2080
2081
2082 tp->card_state = Sleeping;
2083 smp_wmb();
2084 typhoon_do_get_stats(tp);
2085 memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2086
2087 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2088 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2089
2090 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2091 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2092 tp->name);
2093
2094 if(typhoon_reset(ioaddr, wait_type) < 0) {
2095 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2096 return -ETIMEDOUT;
2097 }
2098
2099
2100 if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2101 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2102 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2103 }
2104
2105 return 0;
2106}
2107
2108static void
2109typhoon_tx_timeout(struct net_device *dev)
2110{
2111 struct typhoon *tp = netdev_priv(dev);
2112
2113 if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2114 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2115 dev->name);
2116 goto truely_dead;
2117 }
2118
2119
2120 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2121 typhoon_free_rx_rings(tp);
2122
2123 if(typhoon_start_runtime(tp) < 0) {
2124 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2125 dev->name);
2126 goto truely_dead;
2127 }
2128
2129 netif_wake_queue(dev);
2130 return;
2131
2132truely_dead:
2133
2134 typhoon_reset(tp->ioaddr, NoWait);
2135 netif_carrier_off(dev);
2136}
2137
2138static int
2139typhoon_open(struct net_device *dev)
2140{
2141 struct typhoon *tp = netdev_priv(dev);
2142 int err;
2143
2144 err = typhoon_request_firmware(tp);
2145 if (err)
2146 goto out;
2147
2148 err = typhoon_wakeup(tp, WaitSleep);
2149 if(err < 0) {
2150 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2151 goto out_sleep;
2152 }
2153
2154 err = request_irq(dev->irq, &typhoon_interrupt, IRQF_SHARED,
2155 dev->name, dev);
2156 if(err < 0)
2157 goto out_sleep;
2158
2159 napi_enable(&tp->napi);
2160
2161 err = typhoon_start_runtime(tp);
2162 if(err < 0) {
2163 napi_disable(&tp->napi);
2164 goto out_irq;
2165 }
2166
2167 netif_start_queue(dev);
2168 return 0;
2169
2170out_irq:
2171 free_irq(dev->irq, dev);
2172
2173out_sleep:
2174 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2175 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2176 dev->name);
2177 typhoon_reset(tp->ioaddr, NoWait);
2178 goto out;
2179 }
2180
2181 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2182 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2183
2184out:
2185 return err;
2186}
2187
2188static int
2189typhoon_close(struct net_device *dev)
2190{
2191 struct typhoon *tp = netdev_priv(dev);
2192
2193 netif_stop_queue(dev);
2194 napi_disable(&tp->napi);
2195
2196 if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2197 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2198
2199
2200 free_irq(dev->irq, dev);
2201
2202 typhoon_free_rx_rings(tp);
2203 typhoon_init_rings(tp);
2204
2205 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2206 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2207
2208 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2209 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2210
2211 return 0;
2212}
2213
2214#ifdef CONFIG_PM
2215static int
2216typhoon_resume(struct pci_dev *pdev)
2217{
2218 struct net_device *dev = pci_get_drvdata(pdev);
2219 struct typhoon *tp = netdev_priv(dev);
2220
2221
2222
2223 if(!netif_running(dev))
2224 return 0;
2225
2226 if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2227 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2228 dev->name);
2229 goto reset;
2230 }
2231
2232 if(typhoon_start_runtime(tp) < 0) {
2233 printk(KERN_ERR "%s: critical: could not start runtime in "
2234 "resume\n", dev->name);
2235 goto reset;
2236 }
2237
2238 netif_device_attach(dev);
2239 return 0;
2240
2241reset:
2242 typhoon_reset(tp->ioaddr, NoWait);
2243 return -EBUSY;
2244}
2245
2246static int
2247typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2248{
2249 struct net_device *dev = pci_get_drvdata(pdev);
2250 struct typhoon *tp = netdev_priv(dev);
2251 struct cmd_desc xp_cmd;
2252
2253
2254
2255 if(!netif_running(dev))
2256 return 0;
2257
2258 spin_lock_bh(&tp->state_lock);
2259 if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2260 spin_unlock_bh(&tp->state_lock);
2261 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2262 dev->name);
2263 return -EBUSY;
2264 }
2265 spin_unlock_bh(&tp->state_lock);
2266
2267 netif_device_detach(dev);
2268
2269 if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2270 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2271 goto need_resume;
2272 }
2273
2274 typhoon_free_rx_rings(tp);
2275 typhoon_init_rings(tp);
2276
2277 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2278 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2279 goto need_resume;
2280 }
2281
2282 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2283 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2284 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2285 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2286 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2287 dev->name);
2288 goto need_resume;
2289 }
2290
2291 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2292 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2293 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2294 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2295 dev->name);
2296 goto need_resume;
2297 }
2298
2299 if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2300 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2301 goto need_resume;
2302 }
2303
2304 return 0;
2305
2306need_resume:
2307 typhoon_resume(pdev);
2308 return -EBUSY;
2309}
2310#endif
2311
2312static int __devinit
2313typhoon_test_mmio(struct pci_dev *pdev)
2314{
2315 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2316 int mode = 0;
2317 u32 val;
2318
2319 if(!ioaddr)
2320 goto out;
2321
2322 if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2323 TYPHOON_STATUS_WAITING_FOR_HOST)
2324 goto out_unmap;
2325
2326 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2327 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2328 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2329
2330
2331
2332
2333
2334 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2335 if((val & TYPHOON_INTR_SELF) == 0) {
2336 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2337 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2338 udelay(50);
2339 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2340 if(val & TYPHOON_INTR_SELF)
2341 mode = 1;
2342 }
2343
2344 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2345 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2346 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2347 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2348
2349out_unmap:
2350 pci_iounmap(pdev, ioaddr);
2351
2352out:
2353 if(!mode)
2354 printk(KERN_INFO PFX "falling back to port IO\n");
2355 return mode;
2356}
2357
2358static const struct net_device_ops typhoon_netdev_ops = {
2359 .ndo_open = typhoon_open,
2360 .ndo_stop = typhoon_close,
2361 .ndo_start_xmit = typhoon_start_tx,
2362 .ndo_set_multicast_list = typhoon_set_rx_mode,
2363 .ndo_tx_timeout = typhoon_tx_timeout,
2364 .ndo_get_stats = typhoon_get_stats,
2365 .ndo_validate_addr = eth_validate_addr,
2366 .ndo_set_mac_address = typhoon_set_mac_address,
2367 .ndo_change_mtu = eth_change_mtu,
2368 .ndo_vlan_rx_register = typhoon_vlan_rx_register,
2369};
2370
2371static int __devinit
2372typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2373{
2374 static int did_version = 0;
2375 struct net_device *dev;
2376 struct typhoon *tp;
2377 int card_id = (int) ent->driver_data;
2378 void __iomem *ioaddr;
2379 void *shared;
2380 dma_addr_t shared_dma;
2381 struct cmd_desc xp_cmd;
2382 struct resp_desc xp_resp[3];
2383 int err = 0;
2384
2385 if(!did_version++)
2386 printk(KERN_INFO "%s", version);
2387
2388 dev = alloc_etherdev(sizeof(*tp));
2389 if(dev == NULL) {
2390 printk(ERR_PFX "%s: unable to alloc new net device\n",
2391 pci_name(pdev));
2392 err = -ENOMEM;
2393 goto error_out;
2394 }
2395 SET_NETDEV_DEV(dev, &pdev->dev);
2396
2397 err = pci_enable_device(pdev);
2398 if(err < 0) {
2399 printk(ERR_PFX "%s: unable to enable device\n",
2400 pci_name(pdev));
2401 goto error_out_dev;
2402 }
2403
2404 err = pci_set_mwi(pdev);
2405 if(err < 0) {
2406 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2407 goto error_out_disable;
2408 }
2409
2410 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2411 if(err < 0) {
2412 printk(ERR_PFX "%s: No usable DMA configuration\n",
2413 pci_name(pdev));
2414 goto error_out_mwi;
2415 }
2416
2417
2418
2419 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2420 printk(ERR_PFX
2421 "%s: region #1 not a PCI IO resource, aborting\n",
2422 pci_name(pdev));
2423 err = -ENODEV;
2424 goto error_out_mwi;
2425 }
2426 if(pci_resource_len(pdev, 0) < 128) {
2427 printk(ERR_PFX "%s: Invalid PCI IO region size, aborting\n",
2428 pci_name(pdev));
2429 err = -ENODEV;
2430 goto error_out_mwi;
2431 }
2432 if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2433 printk(ERR_PFX
2434 "%s: region #1 not a PCI MMIO resource, aborting\n",
2435 pci_name(pdev));
2436 err = -ENODEV;
2437 goto error_out_mwi;
2438 }
2439 if(pci_resource_len(pdev, 1) < 128) {
2440 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2441 pci_name(pdev));
2442 err = -ENODEV;
2443 goto error_out_mwi;
2444 }
2445
2446 err = pci_request_regions(pdev, "typhoon");
2447 if(err < 0) {
2448 printk(ERR_PFX "%s: could not request regions\n",
2449 pci_name(pdev));
2450 goto error_out_mwi;
2451 }
2452
2453
2454
2455 if(use_mmio != 0 && use_mmio != 1)
2456 use_mmio = typhoon_test_mmio(pdev);
2457
2458 ioaddr = pci_iomap(pdev, use_mmio, 128);
2459 if (!ioaddr) {
2460 printk(ERR_PFX "%s: cannot remap registers, aborting\n",
2461 pci_name(pdev));
2462 err = -EIO;
2463 goto error_out_regions;
2464 }
2465
2466
2467
2468 shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2469 &shared_dma);
2470 if(!shared) {
2471 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2472 pci_name(pdev));
2473 err = -ENOMEM;
2474 goto error_out_remap;
2475 }
2476
2477 dev->irq = pdev->irq;
2478 tp = netdev_priv(dev);
2479 tp->shared = (struct typhoon_shared *) shared;
2480 tp->shared_dma = shared_dma;
2481 tp->pdev = pdev;
2482 tp->tx_pdev = pdev;
2483 tp->ioaddr = ioaddr;
2484 tp->tx_ioaddr = ioaddr;
2485 tp->dev = dev;
2486
2487
2488
2489
2490
2491
2492
2493
2494 if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2495 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2496 err = -EIO;
2497 goto error_out_dma;
2498 }
2499
2500
2501
2502
2503
2504 pci_set_master(pdev);
2505 pci_save_state(pdev);
2506
2507
2508
2509
2510
2511 tp->name = pci_name(pdev);
2512
2513 typhoon_init_interface(tp);
2514 typhoon_init_rings(tp);
2515
2516 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2517 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2518 pci_name(pdev));
2519 err = -EIO;
2520 goto error_out_reset;
2521 }
2522
2523 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2524 if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2525 printk(ERR_PFX "%s: cannot read MAC address\n",
2526 pci_name(pdev));
2527 err = -EIO;
2528 goto error_out_reset;
2529 }
2530
2531 *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2532 *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2533
2534 if(!is_valid_ether_addr(dev->dev_addr)) {
2535 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2536 "aborting\n", pci_name(pdev));
2537 goto error_out_reset;
2538 }
2539
2540
2541
2542
2543 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2544 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2545 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2546 pci_name(pdev));
2547 goto error_out_reset;
2548 }
2549
2550 tp->capabilities = typhoon_card_info[card_id].capabilities;
2551 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2552
2553
2554
2555
2556
2557
2558
2559 if(xp_resp[0].numDesc != 0)
2560 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2561
2562 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2563 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2564 pci_name(pdev));
2565 err = -EIO;
2566 goto error_out_reset;
2567 }
2568
2569
2570 dev->netdev_ops = &typhoon_netdev_ops;
2571 netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2572 dev->watchdog_timeo = TX_TIMEOUT;
2573
2574 SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2575
2576
2577
2578
2579 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2580 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2581 dev->features |= NETIF_F_TSO;
2582
2583 if(register_netdev(dev) < 0)
2584 goto error_out_reset;
2585
2586
2587 tp->name = dev->name;
2588
2589 pci_set_drvdata(pdev, dev);
2590
2591 printk(KERN_INFO "%s: %s at %s 0x%llx, %pM\n",
2592 dev->name, typhoon_card_info[card_id].name,
2593 use_mmio ? "MMIO" : "IO",
2594 (unsigned long long)pci_resource_start(pdev, use_mmio),
2595 dev->dev_addr);
2596
2597
2598
2599
2600 if(xp_resp[0].numDesc == 0) {
2601
2602
2603
2604 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2605 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2606 "%02u/%02u/2000\n", dev->name, monthday >> 8,
2607 monthday & 0xff);
2608 } else if(xp_resp[0].numDesc == 2) {
2609
2610
2611 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2612 u8 *ver_string = (u8 *) &xp_resp[1];
2613 ver_string[25] = 0;
2614 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2615 "%02x.%03x.%03x %s\n", dev->name, sleep_ver >> 24,
2616 (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff,
2617 ver_string);
2618 } else {
2619 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2620 "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2621 le32_to_cpu(xp_resp[0].parm2));
2622 }
2623
2624 return 0;
2625
2626error_out_reset:
2627 typhoon_reset(ioaddr, NoWait);
2628
2629error_out_dma:
2630 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2631 shared, shared_dma);
2632error_out_remap:
2633 pci_iounmap(pdev, ioaddr);
2634error_out_regions:
2635 pci_release_regions(pdev);
2636error_out_mwi:
2637 pci_clear_mwi(pdev);
2638error_out_disable:
2639 pci_disable_device(pdev);
2640error_out_dev:
2641 free_netdev(dev);
2642error_out:
2643 return err;
2644}
2645
2646static void __devexit
2647typhoon_remove_one(struct pci_dev *pdev)
2648{
2649 struct net_device *dev = pci_get_drvdata(pdev);
2650 struct typhoon *tp = netdev_priv(dev);
2651
2652 unregister_netdev(dev);
2653 pci_set_power_state(pdev, PCI_D0);
2654 pci_restore_state(pdev);
2655 typhoon_reset(tp->ioaddr, NoWait);
2656 pci_iounmap(pdev, tp->ioaddr);
2657 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2658 tp->shared, tp->shared_dma);
2659 pci_release_regions(pdev);
2660 pci_clear_mwi(pdev);
2661 pci_disable_device(pdev);
2662 pci_set_drvdata(pdev, NULL);
2663 free_netdev(dev);
2664}
2665
2666static struct pci_driver typhoon_driver = {
2667 .name = DRV_MODULE_NAME,
2668 .id_table = typhoon_pci_tbl,
2669 .probe = typhoon_init_one,
2670 .remove = __devexit_p(typhoon_remove_one),
2671#ifdef CONFIG_PM
2672 .suspend = typhoon_suspend,
2673 .resume = typhoon_resume,
2674#endif
2675};
2676
2677static int __init
2678typhoon_init(void)
2679{
2680 return pci_register_driver(&typhoon_driver);
2681}
2682
2683static void __exit
2684typhoon_cleanup(void)
2685{
2686 if (typhoon_fw)
2687 release_firmware(typhoon_fw);
2688 pci_unregister_driver(&typhoon_driver);
2689}
2690
2691module_init(typhoon_init);
2692module_exit(typhoon_cleanup);
2693