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46
47#include <linux/module.h>
48#include <linux/types.h>
49#include <linux/init.h>
50#include <linux/mm.h>
51#include <linux/errno.h>
52#include <linux/ioport.h>
53#include <linux/pci.h>
54#include <linux/kernel.h>
55#include <linux/netdevice.h>
56#include <linux/etherdevice.h>
57#include <linux/skbuff.h>
58#include <linux/delay.h>
59#include <linux/timer.h>
60#include <linux/slab.h>
61#include <linux/interrupt.h>
62#include <linux/string.h>
63#include <linux/wait.h>
64#include <linux/io.h>
65#include <linux/if.h>
66#include <linux/uaccess.h>
67#include <linux/proc_fs.h>
68#include <linux/inetdevice.h>
69#include <linux/reboot.h>
70#include <linux/ethtool.h>
71#include <linux/mii.h>
72#include <linux/in.h>
73#include <linux/if_arp.h>
74#include <linux/if_vlan.h>
75#include <linux/ip.h>
76#include <linux/tcp.h>
77#include <linux/udp.h>
78#include <linux/crc-ccitt.h>
79#include <linux/crc32.h>
80
81#include "via-velocity.h"
82
83
84static int velocity_nics;
85static int msglevel = MSG_LEVEL_INFO;
86
87
88
89
90
91
92
93
94
95static void mac_get_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
96{
97 int i;
98
99
100 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
101
102 writeb(0, ®s->CAMADDR);
103
104
105 for (i = 0; i < 8; i++)
106 *mask++ = readb(&(regs->MARCAM[i]));
107
108
109 writeb(0, ®s->CAMADDR);
110
111
112 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
113}
114
115
116
117
118
119
120
121
122
123static void mac_set_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
124{
125 int i;
126
127 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
128
129 writeb(CAMADDR_CAMEN, ®s->CAMADDR);
130
131 for (i = 0; i < 8; i++)
132 writeb(*mask++, &(regs->MARCAM[i]));
133
134
135 writeb(0, ®s->CAMADDR);
136
137
138 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
139}
140
141static void mac_set_vlan_cam_mask(struct mac_regs __iomem *regs, u8 *mask)
142{
143 int i;
144
145 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
146
147 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, ®s->CAMADDR);
148
149 for (i = 0; i < 8; i++)
150 writeb(*mask++, &(regs->MARCAM[i]));
151
152
153 writeb(0, ®s->CAMADDR);
154
155
156 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
157}
158
159
160
161
162
163
164
165
166
167static void mac_set_cam(struct mac_regs __iomem *regs, int idx, const u8 *addr)
168{
169 int i;
170
171
172 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
173
174 idx &= (64 - 1);
175
176 writeb(CAMADDR_CAMEN | idx, ®s->CAMADDR);
177
178 for (i = 0; i < 6; i++)
179 writeb(*addr++, &(regs->MARCAM[i]));
180
181 BYTE_REG_BITS_ON(CAMCR_CAMWR, ®s->CAMCR);
182
183 udelay(10);
184
185 writeb(0, ®s->CAMADDR);
186
187
188 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
189}
190
191static void mac_set_vlan_cam(struct mac_regs __iomem *regs, int idx,
192 const u8 *addr)
193{
194
195
196 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
197
198 idx &= (64 - 1);
199
200 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx, ®s->CAMADDR);
201 writew(*((u16 *) addr), ®s->MARCAM[0]);
202
203 BYTE_REG_BITS_ON(CAMCR_CAMWR, ®s->CAMCR);
204
205 udelay(10);
206
207 writeb(0, ®s->CAMADDR);
208
209
210 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0, ®s->CAMCR);
211}
212
213
214
215
216
217
218
219
220
221
222static void mac_wol_reset(struct mac_regs __iomem *regs)
223{
224
225
226 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, ®s->STICKHW);
227
228 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), ®s->STICKHW);
229
230 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, ®s->CHIPGCR);
231 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
232
233 writeb(WOLCFG_PMEOVR, ®s->WOLCFGClr);
234
235 writew(0xFFFF, ®s->WOLCRClr);
236
237 writew(0xFFFF, ®s->WOLSRClr);
238}
239
240static const struct ethtool_ops velocity_ethtool_ops;
241
242
243
244
245
246MODULE_AUTHOR("VIA Networking Technologies, Inc.");
247MODULE_LICENSE("GPL");
248MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
249
250#define VELOCITY_PARAM(N, D) \
251 static int N[MAX_UNITS] = OPTION_DEFAULT;\
252 module_param_array(N, int, NULL, 0); \
253 MODULE_PARM_DESC(N, D);
254
255#define RX_DESC_MIN 64
256#define RX_DESC_MAX 255
257#define RX_DESC_DEF 64
258VELOCITY_PARAM(RxDescriptors, "Number of receive descriptors");
259
260#define TX_DESC_MIN 16
261#define TX_DESC_MAX 256
262#define TX_DESC_DEF 64
263VELOCITY_PARAM(TxDescriptors, "Number of transmit descriptors");
264
265#define RX_THRESH_MIN 0
266#define RX_THRESH_MAX 3
267#define RX_THRESH_DEF 0
268
269
270
271
272
273
274VELOCITY_PARAM(rx_thresh, "Receive fifo threshold");
275
276#define DMA_LENGTH_MIN 0
277#define DMA_LENGTH_MAX 7
278#define DMA_LENGTH_DEF 0
279
280
281
282
283
284
285
286
287
288
289
290VELOCITY_PARAM(DMA_length, "DMA length");
291
292#define IP_ALIG_DEF 0
293
294
295
296
297
298
299VELOCITY_PARAM(IP_byte_align, "Enable IP header dword aligned");
300
301#define TX_CSUM_DEF 1
302
303
304
305
306
307VELOCITY_PARAM(txcsum_offload, "Enable transmit packet checksum offload");
308
309#define FLOW_CNTL_DEF 1
310#define FLOW_CNTL_MIN 1
311#define FLOW_CNTL_MAX 5
312
313
314
315
316
317
318
319
320VELOCITY_PARAM(flow_control, "Enable flow control ability");
321
322#define MED_LNK_DEF 0
323#define MED_LNK_MIN 0
324#define MED_LNK_MAX 4
325
326
327
328
329
330
331
332
333
334
335
336VELOCITY_PARAM(speed_duplex, "Setting the speed and duplex mode");
337
338#define VAL_PKT_LEN_DEF 0
339
340
341
342
343VELOCITY_PARAM(ValPktLen, "Receiving or Drop invalid 802.3 frame");
344
345#define WOL_OPT_DEF 0
346#define WOL_OPT_MIN 0
347#define WOL_OPT_MAX 7
348
349
350
351
352
353
354
355VELOCITY_PARAM(wol_opts, "Wake On Lan options");
356
357#define INT_WORKS_DEF 20
358#define INT_WORKS_MIN 10
359#define INT_WORKS_MAX 64
360
361VELOCITY_PARAM(int_works, "Number of packets per interrupt services");
362
363static int rx_copybreak = 200;
364module_param(rx_copybreak, int, 0644);
365MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
366
367#ifdef CONFIG_PM
368static DEFINE_SPINLOCK(velocity_dev_list_lock);
369static LIST_HEAD(velocity_dev_list);
370#endif
371
372
373
374
375static struct velocity_info_tbl chip_info_table[] = {
376 {CHIP_TYPE_VT6110, "VIA Networking Velocity Family Gigabit Ethernet Adapter", 1, 0x00FFFFFFUL},
377 { }
378};
379
380
381
382
383
384static const struct pci_device_id velocity_id_table[] __devinitdata = {
385 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_612X) },
386 { }
387};
388
389MODULE_DEVICE_TABLE(pci, velocity_id_table);
390
391
392
393
394
395
396
397
398static const char __devinit *get_chip_name(enum chip_type chip_id)
399{
400 int i;
401 for (i = 0; chip_info_table[i].name != NULL; i++)
402 if (chip_info_table[i].chip_id == chip_id)
403 break;
404 return chip_info_table[i].name;
405}
406
407
408
409
410
411
412
413
414
415static void __devexit velocity_remove1(struct pci_dev *pdev)
416{
417 struct net_device *dev = pci_get_drvdata(pdev);
418 struct velocity_info *vptr = netdev_priv(dev);
419
420#ifdef CONFIG_PM
421 unsigned long flags;
422
423 spin_lock_irqsave(&velocity_dev_list_lock, flags);
424 if (!list_empty(&velocity_dev_list))
425 list_del(&vptr->list);
426 spin_unlock_irqrestore(&velocity_dev_list_lock, flags);
427#endif
428 unregister_netdev(dev);
429 iounmap(vptr->mac_regs);
430 pci_release_regions(pdev);
431 pci_disable_device(pdev);
432 pci_set_drvdata(pdev, NULL);
433 free_netdev(dev);
434
435 velocity_nics--;
436}
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452static void __devinit velocity_set_int_opt(int *opt, int val, int min, int max, int def, char *name, const char *devname)
453{
454 if (val == -1)
455 *opt = def;
456 else if (val < min || val > max) {
457 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
458 devname, name, min, max);
459 *opt = def;
460 } else {
461 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
462 devname, name, val);
463 *opt = val;
464 }
465}
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480static void __devinit velocity_set_bool_opt(u32 *opt, int val, int def, u32 flag, char *name, const char *devname)
481{
482 (*opt) &= (~flag);
483 if (val == -1)
484 *opt |= (def ? flag : 0);
485 else if (val < 0 || val > 1) {
486 printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
487 devname, name);
488 *opt |= (def ? flag : 0);
489 } else {
490 printk(KERN_INFO "%s: set parameter %s to %s\n",
491 devname, name, val ? "TRUE" : "FALSE");
492 *opt |= (val ? flag : 0);
493 }
494}
495
496
497
498
499
500
501
502
503
504
505static void __devinit velocity_get_options(struct velocity_opt *opts, int index, const char *devname)
506{
507
508 velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
509 velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
510 velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
511 velocity_set_int_opt(&opts->numtx, TxDescriptors[index], TX_DESC_MIN, TX_DESC_MAX, TX_DESC_DEF, "TxDescriptors", devname);
512
513 velocity_set_bool_opt(&opts->flags, txcsum_offload[index], TX_CSUM_DEF, VELOCITY_FLAGS_TX_CSUM, "txcsum_offload", devname);
514 velocity_set_int_opt(&opts->flow_cntl, flow_control[index], FLOW_CNTL_MIN, FLOW_CNTL_MAX, FLOW_CNTL_DEF, "flow_control", devname);
515 velocity_set_bool_opt(&opts->flags, IP_byte_align[index], IP_ALIG_DEF, VELOCITY_FLAGS_IP_ALIGN, "IP_byte_align", devname);
516 velocity_set_bool_opt(&opts->flags, ValPktLen[index], VAL_PKT_LEN_DEF, VELOCITY_FLAGS_VAL_PKT_LEN, "ValPktLen", devname);
517 velocity_set_int_opt((int *) &opts->spd_dpx, speed_duplex[index], MED_LNK_MIN, MED_LNK_MAX, MED_LNK_DEF, "Media link mode", devname);
518 velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
519 velocity_set_int_opt((int *) &opts->int_works, int_works[index], INT_WORKS_MIN, INT_WORKS_MAX, INT_WORKS_DEF, "Interrupt service works", devname);
520 opts->numrx = (opts->numrx & ~3);
521}
522
523
524
525
526
527
528
529
530static void velocity_init_cam_filter(struct velocity_info *vptr)
531{
532 struct mac_regs __iomem *regs = vptr->mac_regs;
533
534
535 WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, ®s->MCFG);
536 WORD_REG_BITS_ON(MCFG_VIDFR, ®s->MCFG);
537
538
539 memset(vptr->vCAMmask, 0, sizeof(u8) * 8);
540 memset(vptr->mCAMmask, 0, sizeof(u8) * 8);
541 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
542 mac_set_cam_mask(regs, vptr->mCAMmask);
543
544
545 if (vptr->vlgrp) {
546 unsigned int vid, i = 0;
547
548 if (!vlan_group_get_device(vptr->vlgrp, 0))
549 WORD_REG_BITS_ON(MCFG_RTGOPT, ®s->MCFG);
550
551 for (vid = 1; (vid < VLAN_VID_MASK); vid++) {
552 if (vlan_group_get_device(vptr->vlgrp, vid)) {
553 mac_set_vlan_cam(regs, i, (u8 *) &vid);
554 vptr->vCAMmask[i / 8] |= 0x1 << (i % 8);
555 if (++i >= VCAM_SIZE)
556 break;
557 }
558 }
559 mac_set_vlan_cam_mask(regs, vptr->vCAMmask);
560 }
561}
562
563static void velocity_vlan_rx_register(struct net_device *dev,
564 struct vlan_group *grp)
565{
566 struct velocity_info *vptr = netdev_priv(dev);
567
568 vptr->vlgrp = grp;
569}
570
571static void velocity_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
572{
573 struct velocity_info *vptr = netdev_priv(dev);
574
575 spin_lock_irq(&vptr->lock);
576 velocity_init_cam_filter(vptr);
577 spin_unlock_irq(&vptr->lock);
578}
579
580static void velocity_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
581{
582 struct velocity_info *vptr = netdev_priv(dev);
583
584 spin_lock_irq(&vptr->lock);
585 vlan_group_set_device(vptr->vlgrp, vid, NULL);
586 velocity_init_cam_filter(vptr);
587 spin_unlock_irq(&vptr->lock);
588}
589
590static void velocity_init_rx_ring_indexes(struct velocity_info *vptr)
591{
592 vptr->rx.dirty = vptr->rx.filled = vptr->rx.curr = 0;
593}
594
595
596
597
598
599
600
601
602static void velocity_rx_reset(struct velocity_info *vptr)
603{
604
605 struct mac_regs __iomem *regs = vptr->mac_regs;
606 int i;
607
608 velocity_init_rx_ring_indexes(vptr);
609
610
611
612
613 for (i = 0; i < vptr->options.numrx; ++i)
614 vptr->rx.ring[i].rdesc0.len |= OWNED_BY_NIC;
615
616 writew(vptr->options.numrx, ®s->RBRDU);
617 writel(vptr->rx.pool_dma, ®s->RDBaseLo);
618 writew(0, ®s->RDIdx);
619 writew(vptr->options.numrx - 1, ®s->RDCSize);
620}
621
622
623
624
625
626
627
628
629
630static u32 velocity_get_opt_media_mode(struct velocity_info *vptr)
631{
632 u32 status = 0;
633
634 switch (vptr->options.spd_dpx) {
635 case SPD_DPX_AUTO:
636 status = VELOCITY_AUTONEG_ENABLE;
637 break;
638 case SPD_DPX_100_FULL:
639 status = VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL;
640 break;
641 case SPD_DPX_10_FULL:
642 status = VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL;
643 break;
644 case SPD_DPX_100_HALF:
645 status = VELOCITY_SPEED_100;
646 break;
647 case SPD_DPX_10_HALF:
648 status = VELOCITY_SPEED_10;
649 break;
650 }
651 vptr->mii_status = status;
652 return status;
653}
654
655
656
657
658
659
660
661static void safe_disable_mii_autopoll(struct mac_regs __iomem *regs)
662{
663 u16 ww;
664
665
666 writeb(0, ®s->MIICR);
667 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
668 udelay(1);
669 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
670 break;
671 }
672}
673
674
675
676
677
678
679
680
681static void enable_mii_autopoll(struct mac_regs __iomem *regs)
682{
683 int ii;
684
685 writeb(0, &(regs->MIICR));
686 writeb(MIIADR_SWMPL, ®s->MIIADR);
687
688 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
689 udelay(1);
690 if (BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
691 break;
692 }
693
694 writeb(MIICR_MAUTO, ®s->MIICR);
695
696 for (ii = 0; ii < W_MAX_TIMEOUT; ii++) {
697 udelay(1);
698 if (!BYTE_REG_BITS_IS_ON(MIISR_MIDLE, ®s->MIISR))
699 break;
700 }
701
702}
703
704
705
706
707
708
709
710
711
712
713static int velocity_mii_read(struct mac_regs __iomem *regs, u8 index, u16 *data)
714{
715 u16 ww;
716
717
718
719
720 safe_disable_mii_autopoll(regs);
721
722 writeb(index, ®s->MIIADR);
723
724 BYTE_REG_BITS_ON(MIICR_RCMD, ®s->MIICR);
725
726 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
727 if (!(readb(®s->MIICR) & MIICR_RCMD))
728 break;
729 }
730
731 *data = readw(®s->MIIDATA);
732
733 enable_mii_autopoll(regs);
734 if (ww == W_MAX_TIMEOUT)
735 return -ETIMEDOUT;
736 return 0;
737}
738
739
740
741
742
743
744
745
746
747static u32 mii_check_media_mode(struct mac_regs __iomem *regs)
748{
749 u32 status = 0;
750 u16 ANAR;
751
752 if (!MII_REG_BITS_IS_ON(BMSR_LNK, MII_REG_BMSR, regs))
753 status |= VELOCITY_LINK_FAIL;
754
755 if (MII_REG_BITS_IS_ON(G1000CR_1000FD, MII_REG_G1000CR, regs))
756 status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
757 else if (MII_REG_BITS_IS_ON(G1000CR_1000, MII_REG_G1000CR, regs))
758 status |= (VELOCITY_SPEED_1000);
759 else {
760 velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
761 if (ANAR & ANAR_TXFD)
762 status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
763 else if (ANAR & ANAR_TX)
764 status |= VELOCITY_SPEED_100;
765 else if (ANAR & ANAR_10FD)
766 status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
767 else
768 status |= (VELOCITY_SPEED_10);
769 }
770
771 if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, regs)) {
772 velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
773 if ((ANAR & (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10))
774 == (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) {
775 if (MII_REG_BITS_IS_ON(G1000CR_1000 | G1000CR_1000FD, MII_REG_G1000CR, regs))
776 status |= VELOCITY_AUTONEG_ENABLE;
777 }
778 }
779
780 return status;
781}
782
783
784
785
786
787
788
789
790
791
792static int velocity_mii_write(struct mac_regs __iomem *regs, u8 mii_addr, u16 data)
793{
794 u16 ww;
795
796
797
798
799 safe_disable_mii_autopoll(regs);
800
801
802 writeb(mii_addr, ®s->MIIADR);
803
804 writew(data, ®s->MIIDATA);
805
806
807 BYTE_REG_BITS_ON(MIICR_WCMD, ®s->MIICR);
808
809
810 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
811 udelay(5);
812 if (!(readb(®s->MIICR) & MIICR_WCMD))
813 break;
814 }
815 enable_mii_autopoll(regs);
816
817 if (ww == W_MAX_TIMEOUT)
818 return -ETIMEDOUT;
819 return 0;
820}
821
822
823
824
825
826
827
828
829static void set_mii_flow_control(struct velocity_info *vptr)
830{
831
832 switch (vptr->options.flow_cntl) {
833 case FLOW_CNTL_TX:
834 MII_REG_BITS_OFF(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
835 MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
836 break;
837
838 case FLOW_CNTL_RX:
839 MII_REG_BITS_ON(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
840 MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
841 break;
842
843 case FLOW_CNTL_TX_RX:
844 MII_REG_BITS_ON(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
845 MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
846 break;
847
848 case FLOW_CNTL_DISABLE:
849 MII_REG_BITS_OFF(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
850 MII_REG_BITS_OFF(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
851 break;
852 default:
853 break;
854 }
855}
856
857
858
859
860
861
862
863static void mii_set_auto_on(struct velocity_info *vptr)
864{
865 if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs))
866 MII_REG_BITS_ON(BMCR_REAUTO, MII_REG_BMCR, vptr->mac_regs);
867 else
868 MII_REG_BITS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs);
869}
870
871static u32 check_connection_type(struct mac_regs __iomem *regs)
872{
873 u32 status = 0;
874 u8 PHYSR0;
875 u16 ANAR;
876 PHYSR0 = readb(®s->PHYSR0);
877
878
879
880
881
882
883 if (PHYSR0 & PHYSR0_FDPX)
884 status |= VELOCITY_DUPLEX_FULL;
885
886 if (PHYSR0 & PHYSR0_SPDG)
887 status |= VELOCITY_SPEED_1000;
888 else if (PHYSR0 & PHYSR0_SPD10)
889 status |= VELOCITY_SPEED_10;
890 else
891 status |= VELOCITY_SPEED_100;
892
893 if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, regs)) {
894 velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
895 if ((ANAR & (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10))
896 == (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) {
897 if (MII_REG_BITS_IS_ON(G1000CR_1000 | G1000CR_1000FD, MII_REG_G1000CR, regs))
898 status |= VELOCITY_AUTONEG_ENABLE;
899 }
900 }
901
902 return status;
903}
904
905
906
907
908
909
910
911
912
913
914
915static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
916{
917 u32 curr_status;
918 struct mac_regs __iomem *regs = vptr->mac_regs;
919
920 vptr->mii_status = mii_check_media_mode(vptr->mac_regs);
921 curr_status = vptr->mii_status & (~VELOCITY_LINK_FAIL);
922
923
924 set_mii_flow_control(vptr);
925
926
927
928
929
930
931
932
933
934
935
936
937 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
938 MII_REG_BITS_ON(AUXCR_MDPPS, MII_REG_AUXCR, vptr->mac_regs);
939
940
941
942
943 if (mii_status & VELOCITY_AUTONEG_ENABLE) {
944 VELOCITY_PRT(MSG_LEVEL_INFO, "Velocity is AUTO mode\n");
945
946 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
947
948 MII_REG_BITS_ON(ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10, MII_REG_ANAR, vptr->mac_regs);
949 MII_REG_BITS_ON(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
950 MII_REG_BITS_ON(BMCR_SPEED1G, MII_REG_BMCR, vptr->mac_regs);
951
952
953 mii_set_auto_on(vptr);
954 } else {
955 u16 ANAR;
956 u8 CHIPGCR;
957
958
959
960
961
962
963
964
965
966 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
967
968 CHIPGCR = readb(®s->CHIPGCR);
969 CHIPGCR &= ~CHIPGCR_FCGMII;
970
971 if (mii_status & VELOCITY_DUPLEX_FULL) {
972 CHIPGCR |= CHIPGCR_FCFDX;
973 writeb(CHIPGCR, ®s->CHIPGCR);
974 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced full mode\n");
975 if (vptr->rev_id < REV_ID_VT3216_A0)
976 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
977 } else {
978 CHIPGCR &= ~CHIPGCR_FCFDX;
979 VELOCITY_PRT(MSG_LEVEL_INFO, "set Velocity to forced half mode\n");
980 writeb(CHIPGCR, ®s->CHIPGCR);
981 if (vptr->rev_id < REV_ID_VT3216_A0)
982 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
983 }
984
985 MII_REG_BITS_OFF(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
986
987 if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10))
988 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
989 else
990 BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
991
992
993 velocity_mii_read(vptr->mac_regs, MII_REG_ANAR, &ANAR);
994 ANAR &= (~(ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10));
995 if (mii_status & VELOCITY_SPEED_100) {
996 if (mii_status & VELOCITY_DUPLEX_FULL)
997 ANAR |= ANAR_TXFD;
998 else
999 ANAR |= ANAR_TX;
1000 } else {
1001 if (mii_status & VELOCITY_DUPLEX_FULL)
1002 ANAR |= ANAR_10FD;
1003 else
1004 ANAR |= ANAR_10;
1005 }
1006 velocity_mii_write(vptr->mac_regs, MII_REG_ANAR, ANAR);
1007
1008 mii_set_auto_on(vptr);
1009
1010 }
1011
1012
1013 return VELOCITY_LINK_CHANGE;
1014}
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024static void velocity_print_link_status(struct velocity_info *vptr)
1025{
1026
1027 if (vptr->mii_status & VELOCITY_LINK_FAIL) {
1028 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: failed to detect cable link\n", vptr->dev->name);
1029 } else if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1030 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link auto-negotiation", vptr->dev->name);
1031
1032 if (vptr->mii_status & VELOCITY_SPEED_1000)
1033 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 1000M bps");
1034 else if (vptr->mii_status & VELOCITY_SPEED_100)
1035 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps");
1036 else
1037 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps");
1038
1039 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1040 VELOCITY_PRT(MSG_LEVEL_INFO, " full duplex\n");
1041 else
1042 VELOCITY_PRT(MSG_LEVEL_INFO, " half duplex\n");
1043 } else {
1044 VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: Link forced", vptr->dev->name);
1045 switch (vptr->options.spd_dpx) {
1046 case SPD_DPX_100_HALF:
1047 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps half duplex\n");
1048 break;
1049 case SPD_DPX_100_FULL:
1050 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 100M bps full duplex\n");
1051 break;
1052 case SPD_DPX_10_HALF:
1053 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps half duplex\n");
1054 break;
1055 case SPD_DPX_10_FULL:
1056 VELOCITY_PRT(MSG_LEVEL_INFO, " speed 10M bps full duplex\n");
1057 break;
1058 default:
1059 break;
1060 }
1061 }
1062}
1063
1064
1065
1066
1067
1068
1069
1070
1071static void enable_flow_control_ability(struct velocity_info *vptr)
1072{
1073
1074 struct mac_regs __iomem *regs = vptr->mac_regs;
1075
1076 switch (vptr->options.flow_cntl) {
1077
1078 case FLOW_CNTL_DEFAULT:
1079 if (BYTE_REG_BITS_IS_ON(PHYSR0_RXFLC, ®s->PHYSR0))
1080 writel(CR0_FDXRFCEN, ®s->CR0Set);
1081 else
1082 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1083
1084 if (BYTE_REG_BITS_IS_ON(PHYSR0_TXFLC, ®s->PHYSR0))
1085 writel(CR0_FDXTFCEN, ®s->CR0Set);
1086 else
1087 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1088 break;
1089
1090 case FLOW_CNTL_TX:
1091 writel(CR0_FDXTFCEN, ®s->CR0Set);
1092 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1093 break;
1094
1095 case FLOW_CNTL_RX:
1096 writel(CR0_FDXRFCEN, ®s->CR0Set);
1097 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1098 break;
1099
1100 case FLOW_CNTL_TX_RX:
1101 writel(CR0_FDXTFCEN, ®s->CR0Set);
1102 writel(CR0_FDXRFCEN, ®s->CR0Set);
1103 break;
1104
1105 case FLOW_CNTL_DISABLE:
1106 writel(CR0_FDXRFCEN, ®s->CR0Clr);
1107 writel(CR0_FDXTFCEN, ®s->CR0Clr);
1108 break;
1109
1110 default:
1111 break;
1112 }
1113
1114}
1115
1116
1117
1118
1119
1120
1121
1122
1123static int velocity_soft_reset(struct velocity_info *vptr)
1124{
1125 struct mac_regs __iomem *regs = vptr->mac_regs;
1126 int i = 0;
1127
1128 writel(CR0_SFRST, ®s->CR0Set);
1129
1130 for (i = 0; i < W_MAX_TIMEOUT; i++) {
1131 udelay(5);
1132 if (!DWORD_REG_BITS_IS_ON(CR0_SFRST, ®s->CR0Set))
1133 break;
1134 }
1135
1136 if (i == W_MAX_TIMEOUT) {
1137 writel(CR0_FORSRST, ®s->CR0Set);
1138
1139
1140 mdelay(2);
1141 }
1142 return 0;
1143}
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153static void velocity_set_multi(struct net_device *dev)
1154{
1155 struct velocity_info *vptr = netdev_priv(dev);
1156 struct mac_regs __iomem *regs = vptr->mac_regs;
1157 u8 rx_mode;
1158 int i;
1159 struct dev_mc_list *mclist;
1160
1161 if (dev->flags & IFF_PROMISC) {
1162 writel(0xffffffff, ®s->MARCAM[0]);
1163 writel(0xffffffff, ®s->MARCAM[4]);
1164 rx_mode = (RCR_AM | RCR_AB | RCR_PROM);
1165 } else if ((dev->mc_count > vptr->multicast_limit)
1166 || (dev->flags & IFF_ALLMULTI)) {
1167 writel(0xffffffff, ®s->MARCAM[0]);
1168 writel(0xffffffff, ®s->MARCAM[4]);
1169 rx_mode = (RCR_AM | RCR_AB);
1170 } else {
1171 int offset = MCAM_SIZE - vptr->multicast_limit;
1172 mac_get_cam_mask(regs, vptr->mCAMmask);
1173
1174 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; i++, mclist = mclist->next) {
1175 mac_set_cam(regs, i + offset, mclist->dmi_addr);
1176 vptr->mCAMmask[(offset + i) / 8] |= 1 << ((offset + i) & 7);
1177 }
1178
1179 mac_set_cam_mask(regs, vptr->mCAMmask);
1180 rx_mode = RCR_AM | RCR_AB | RCR_AP;
1181 }
1182 if (dev->mtu > 1500)
1183 rx_mode |= RCR_AL;
1184
1185 BYTE_REG_BITS_ON(rx_mode, ®s->RCR);
1186
1187}
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200static void mii_init(struct velocity_info *vptr, u32 mii_status)
1201{
1202 u16 BMCR;
1203
1204 switch (PHYID_GET_PHY_ID(vptr->phy_id)) {
1205 case PHYID_CICADA_CS8201:
1206
1207
1208
1209 MII_REG_BITS_OFF((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
1210
1211
1212
1213
1214
1215 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1216 MII_REG_BITS_ON(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
1217 else
1218 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
1219
1220
1221
1222 MII_REG_BITS_ON(PLED_LALBE, MII_REG_PLED, vptr->mac_regs);
1223 break;
1224 case PHYID_VT3216_32BIT:
1225 case PHYID_VT3216_64BIT:
1226
1227
1228
1229 MII_REG_BITS_ON((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
1230
1231
1232
1233
1234
1235 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1236 MII_REG_BITS_ON(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
1237 else
1238 MII_REG_BITS_OFF(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
1239 break;
1240
1241 case PHYID_MARVELL_1000:
1242 case PHYID_MARVELL_1000S:
1243
1244
1245
1246 MII_REG_BITS_ON(PSCR_ACRSTX, MII_REG_PSCR, vptr->mac_regs);
1247
1248
1249
1250 MII_REG_BITS_ON((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
1251 break;
1252 default:
1253 ;
1254 }
1255 velocity_mii_read(vptr->mac_regs, MII_REG_BMCR, &BMCR);
1256 if (BMCR & BMCR_ISO) {
1257 BMCR &= ~BMCR_ISO;
1258 velocity_mii_write(vptr->mac_regs, MII_REG_BMCR, BMCR);
1259 }
1260}
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271static void velocity_init_registers(struct velocity_info *vptr,
1272 enum velocity_init_type type)
1273{
1274 struct mac_regs __iomem *regs = vptr->mac_regs;
1275 int i, mii_status;
1276
1277 mac_wol_reset(regs);
1278
1279 switch (type) {
1280 case VELOCITY_INIT_RESET:
1281 case VELOCITY_INIT_WOL:
1282
1283 netif_stop_queue(vptr->dev);
1284
1285
1286
1287
1288 velocity_rx_reset(vptr);
1289 mac_rx_queue_run(regs);
1290 mac_rx_queue_wake(regs);
1291
1292 mii_status = velocity_get_opt_media_mode(vptr);
1293 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1294 velocity_print_link_status(vptr);
1295 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1296 netif_wake_queue(vptr->dev);
1297 }
1298
1299 enable_flow_control_ability(vptr);
1300
1301 mac_clear_isr(regs);
1302 writel(CR0_STOP, ®s->CR0Clr);
1303 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
1304 ®s->CR0Set);
1305
1306 break;
1307
1308 case VELOCITY_INIT_COLD:
1309 default:
1310
1311
1312
1313 velocity_soft_reset(vptr);
1314 mdelay(5);
1315
1316 mac_eeprom_reload(regs);
1317 for (i = 0; i < 6; i++)
1318 writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
1319
1320
1321
1322
1323 BYTE_REG_BITS_OFF(CFGA_PACPI, &(regs->CFGA));
1324 mac_set_rx_thresh(regs, vptr->options.rx_thresh);
1325 mac_set_dma_length(regs, vptr->options.DMA_length);
1326
1327 writeb(WOLCFG_SAM | WOLCFG_SAB, ®s->WOLCFGSet);
1328
1329
1330
1331 BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), ®s->CFGB);
1332
1333
1334
1335
1336 velocity_init_cam_filter(vptr);
1337
1338
1339
1340
1341 velocity_set_multi(vptr->dev);
1342
1343
1344
1345
1346 enable_mii_autopoll(regs);
1347
1348 vptr->int_mask = INT_MASK_DEF;
1349
1350 writel(vptr->rx.pool_dma, ®s->RDBaseLo);
1351 writew(vptr->options.numrx - 1, ®s->RDCSize);
1352 mac_rx_queue_run(regs);
1353 mac_rx_queue_wake(regs);
1354
1355 writew(vptr->options.numtx - 1, ®s->TDCSize);
1356
1357 for (i = 0; i < vptr->tx.numq; i++) {
1358 writel(vptr->tx.pool_dma[i], ®s->TDBaseLo[i]);
1359 mac_tx_queue_run(regs, i);
1360 }
1361
1362 init_flow_control_register(vptr);
1363
1364 writel(CR0_STOP, ®s->CR0Clr);
1365 writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), ®s->CR0Set);
1366
1367 mii_status = velocity_get_opt_media_mode(vptr);
1368 netif_stop_queue(vptr->dev);
1369
1370 mii_init(vptr, mii_status);
1371
1372 if (velocity_set_media_mode(vptr, mii_status) != VELOCITY_LINK_CHANGE) {
1373 velocity_print_link_status(vptr);
1374 if (!(vptr->mii_status & VELOCITY_LINK_FAIL))
1375 netif_wake_queue(vptr->dev);
1376 }
1377
1378 enable_flow_control_ability(vptr);
1379 mac_hw_mibs_init(regs);
1380 mac_write_int_mask(vptr->int_mask, regs);
1381 mac_clear_isr(regs);
1382
1383 }
1384}
1385
1386static void velocity_give_many_rx_descs(struct velocity_info *vptr)
1387{
1388 struct mac_regs __iomem *regs = vptr->mac_regs;
1389 int avail, dirty, unusable;
1390
1391
1392
1393
1394
1395 if (vptr->rx.filled < 4)
1396 return;
1397
1398 wmb();
1399
1400 unusable = vptr->rx.filled & 0x0003;
1401 dirty = vptr->rx.dirty - unusable;
1402 for (avail = vptr->rx.filled & 0xfffc; avail; avail--) {
1403 dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
1404 vptr->rx.ring[dirty].rdesc0.len |= OWNED_BY_NIC;
1405 }
1406
1407 writew(vptr->rx.filled & 0xfffc, ®s->RBRDU);
1408 vptr->rx.filled = unusable;
1409}
1410
1411
1412
1413
1414
1415
1416
1417
1418static int velocity_init_dma_rings(struct velocity_info *vptr)
1419{
1420 struct velocity_opt *opt = &vptr->options;
1421 const unsigned int rx_ring_size = opt->numrx * sizeof(struct rx_desc);
1422 const unsigned int tx_ring_size = opt->numtx * sizeof(struct tx_desc);
1423 struct pci_dev *pdev = vptr->pdev;
1424 dma_addr_t pool_dma;
1425 void *pool;
1426 unsigned int i;
1427
1428
1429
1430
1431
1432
1433
1434 pool = pci_alloc_consistent(pdev, tx_ring_size * vptr->tx.numq +
1435 rx_ring_size, &pool_dma);
1436 if (!pool) {
1437 dev_err(&pdev->dev, "%s : DMA memory allocation failed.\n",
1438 vptr->dev->name);
1439 return -ENOMEM;
1440 }
1441
1442 vptr->rx.ring = pool;
1443 vptr->rx.pool_dma = pool_dma;
1444
1445 pool += rx_ring_size;
1446 pool_dma += rx_ring_size;
1447
1448 for (i = 0; i < vptr->tx.numq; i++) {
1449 vptr->tx.rings[i] = pool;
1450 vptr->tx.pool_dma[i] = pool_dma;
1451 pool += tx_ring_size;
1452 pool_dma += tx_ring_size;
1453 }
1454
1455 return 0;
1456}
1457
1458static void velocity_set_rxbufsize(struct velocity_info *vptr, int mtu)
1459{
1460 vptr->rx.buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1461}
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473static int velocity_alloc_rx_buf(struct velocity_info *vptr, int idx)
1474{
1475 struct rx_desc *rd = &(vptr->rx.ring[idx]);
1476 struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
1477
1478 rd_info->skb = dev_alloc_skb(vptr->rx.buf_sz + 64);
1479 if (rd_info->skb == NULL)
1480 return -ENOMEM;
1481
1482
1483
1484
1485
1486 skb_reserve(rd_info->skb, (unsigned long) rd_info->skb->data & 63);
1487 rd_info->skb_dma = pci_map_single(vptr->pdev, rd_info->skb->data,
1488 vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
1489
1490
1491
1492
1493
1494 *((u32 *) & (rd->rdesc0)) = 0;
1495 rd->size = cpu_to_le16(vptr->rx.buf_sz) | RX_INTEN;
1496 rd->pa_low = cpu_to_le32(rd_info->skb_dma);
1497 rd->pa_high = 0;
1498 return 0;
1499}
1500
1501
1502static int velocity_rx_refill(struct velocity_info *vptr)
1503{
1504 int dirty = vptr->rx.dirty, done = 0;
1505
1506 do {
1507 struct rx_desc *rd = vptr->rx.ring + dirty;
1508
1509
1510 if (rd->rdesc0.len & OWNED_BY_NIC)
1511 break;
1512
1513 if (!vptr->rx.info[dirty].skb) {
1514 if (velocity_alloc_rx_buf(vptr, dirty) < 0)
1515 break;
1516 }
1517 done++;
1518 dirty = (dirty < vptr->options.numrx - 1) ? dirty + 1 : 0;
1519 } while (dirty != vptr->rx.curr);
1520
1521 if (done) {
1522 vptr->rx.dirty = dirty;
1523 vptr->rx.filled += done;
1524 }
1525
1526 return done;
1527}
1528
1529
1530
1531
1532
1533
1534
1535
1536static void velocity_free_rd_ring(struct velocity_info *vptr)
1537{
1538 int i;
1539
1540 if (vptr->rx.info == NULL)
1541 return;
1542
1543 for (i = 0; i < vptr->options.numrx; i++) {
1544 struct velocity_rd_info *rd_info = &(vptr->rx.info[i]);
1545 struct rx_desc *rd = vptr->rx.ring + i;
1546
1547 memset(rd, 0, sizeof(*rd));
1548
1549 if (!rd_info->skb)
1550 continue;
1551 pci_unmap_single(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
1552 PCI_DMA_FROMDEVICE);
1553 rd_info->skb_dma = 0;
1554
1555 dev_kfree_skb(rd_info->skb);
1556 rd_info->skb = NULL;
1557 }
1558
1559 kfree(vptr->rx.info);
1560 vptr->rx.info = NULL;
1561}
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572static int velocity_init_rd_ring(struct velocity_info *vptr)
1573{
1574 int ret = -ENOMEM;
1575
1576 vptr->rx.info = kcalloc(vptr->options.numrx,
1577 sizeof(struct velocity_rd_info), GFP_KERNEL);
1578 if (!vptr->rx.info)
1579 goto out;
1580
1581 velocity_init_rx_ring_indexes(vptr);
1582
1583 if (velocity_rx_refill(vptr) != vptr->options.numrx) {
1584 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_ERR
1585 "%s: failed to allocate RX buffer.\n", vptr->dev->name);
1586 velocity_free_rd_ring(vptr);
1587 goto out;
1588 }
1589
1590 ret = 0;
1591out:
1592 return ret;
1593}
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603static int velocity_init_td_ring(struct velocity_info *vptr)
1604{
1605 dma_addr_t curr;
1606 int j;
1607
1608
1609 for (j = 0; j < vptr->tx.numq; j++) {
1610 curr = vptr->tx.pool_dma[j];
1611
1612 vptr->tx.infos[j] = kcalloc(vptr->options.numtx,
1613 sizeof(struct velocity_td_info),
1614 GFP_KERNEL);
1615 if (!vptr->tx.infos[j]) {
1616 while (--j >= 0)
1617 kfree(vptr->tx.infos[j]);
1618 return -ENOMEM;
1619 }
1620
1621 vptr->tx.tail[j] = vptr->tx.curr[j] = vptr->tx.used[j] = 0;
1622 }
1623 return 0;
1624}
1625
1626
1627
1628
1629
1630
1631
1632static void velocity_free_dma_rings(struct velocity_info *vptr)
1633{
1634 const int size = vptr->options.numrx * sizeof(struct rx_desc) +
1635 vptr->options.numtx * sizeof(struct tx_desc) * vptr->tx.numq;
1636
1637 pci_free_consistent(vptr->pdev, size, vptr->rx.ring, vptr->rx.pool_dma);
1638}
1639
1640
1641static int velocity_init_rings(struct velocity_info *vptr, int mtu)
1642{
1643 int ret;
1644
1645 velocity_set_rxbufsize(vptr, mtu);
1646
1647 ret = velocity_init_dma_rings(vptr);
1648 if (ret < 0)
1649 goto out;
1650
1651 ret = velocity_init_rd_ring(vptr);
1652 if (ret < 0)
1653 goto err_free_dma_rings_0;
1654
1655 ret = velocity_init_td_ring(vptr);
1656 if (ret < 0)
1657 goto err_free_rd_ring_1;
1658out:
1659 return ret;
1660
1661err_free_rd_ring_1:
1662 velocity_free_rd_ring(vptr);
1663err_free_dma_rings_0:
1664 velocity_free_dma_rings(vptr);
1665 goto out;
1666}
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_info *tdinfo)
1677{
1678 struct sk_buff *skb = tdinfo->skb;
1679 int i;
1680 int pktlen;
1681
1682
1683
1684
1685 if (tdinfo->skb_dma) {
1686
1687 pktlen = max_t(unsigned int, skb->len, ETH_ZLEN);
1688 for (i = 0; i < tdinfo->nskb_dma; i++) {
1689 pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], pktlen, PCI_DMA_TODEVICE);
1690 tdinfo->skb_dma[i] = 0;
1691 }
1692 }
1693 dev_kfree_skb_irq(skb);
1694 tdinfo->skb = NULL;
1695}
1696
1697
1698
1699
1700
1701static void velocity_free_td_ring_entry(struct velocity_info *vptr,
1702 int q, int n)
1703{
1704 struct velocity_td_info *td_info = &(vptr->tx.infos[q][n]);
1705 int i;
1706
1707 if (td_info == NULL)
1708 return;
1709
1710 if (td_info->skb) {
1711 for (i = 0; i < td_info->nskb_dma; i++) {
1712 if (td_info->skb_dma[i]) {
1713 pci_unmap_single(vptr->pdev, td_info->skb_dma[i],
1714 td_info->skb->len, PCI_DMA_TODEVICE);
1715 td_info->skb_dma[i] = 0;
1716 }
1717 }
1718 dev_kfree_skb(td_info->skb);
1719 td_info->skb = NULL;
1720 }
1721}
1722
1723
1724
1725
1726
1727
1728
1729
1730static void velocity_free_td_ring(struct velocity_info *vptr)
1731{
1732 int i, j;
1733
1734 for (j = 0; j < vptr->tx.numq; j++) {
1735 if (vptr->tx.infos[j] == NULL)
1736 continue;
1737 for (i = 0; i < vptr->options.numtx; i++)
1738 velocity_free_td_ring_entry(vptr, j, i);
1739
1740 kfree(vptr->tx.infos[j]);
1741 vptr->tx.infos[j] = NULL;
1742 }
1743}
1744
1745
1746static void velocity_free_rings(struct velocity_info *vptr)
1747{
1748 velocity_free_td_ring(vptr);
1749 velocity_free_rd_ring(vptr);
1750 velocity_free_dma_rings(vptr);
1751}
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764static void velocity_error(struct velocity_info *vptr, int status)
1765{
1766
1767 if (status & ISR_TXSTLI) {
1768 struct mac_regs __iomem *regs = vptr->mac_regs;
1769
1770 printk(KERN_ERR "TD structure error TDindex=%hx\n", readw(®s->TDIdx[0]));
1771 BYTE_REG_BITS_ON(TXESR_TDSTR, ®s->TXESR);
1772 writew(TRDCSR_RUN, ®s->TDCSRClr);
1773 netif_stop_queue(vptr->dev);
1774
1775
1776
1777 }
1778
1779 if (status & ISR_SRCI) {
1780 struct mac_regs __iomem *regs = vptr->mac_regs;
1781 int linked;
1782
1783 if (vptr->options.spd_dpx == SPD_DPX_AUTO) {
1784 vptr->mii_status = check_connection_type(regs);
1785
1786
1787
1788
1789
1790
1791 if (vptr->rev_id < REV_ID_VT3216_A0) {
1792 if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
1793 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
1794 else
1795 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR);
1796 }
1797
1798
1799
1800 if (!(vptr->mii_status & VELOCITY_DUPLEX_FULL) && (vptr->mii_status & VELOCITY_SPEED_10))
1801 BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
1802 else
1803 BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
1804 }
1805
1806
1807
1808 linked = readb(®s->PHYSR0) & PHYSR0_LINKGD;
1809
1810 if (linked) {
1811 vptr->mii_status &= ~VELOCITY_LINK_FAIL;
1812 netif_carrier_on(vptr->dev);
1813 } else {
1814 vptr->mii_status |= VELOCITY_LINK_FAIL;
1815 netif_carrier_off(vptr->dev);
1816 }
1817
1818 velocity_print_link_status(vptr);
1819 enable_flow_control_ability(vptr);
1820
1821
1822
1823
1824
1825
1826 enable_mii_autopoll(regs);
1827
1828 if (vptr->mii_status & VELOCITY_LINK_FAIL)
1829 netif_stop_queue(vptr->dev);
1830 else
1831 netif_wake_queue(vptr->dev);
1832
1833 };
1834 if (status & ISR_MIBFI)
1835 velocity_update_hw_mibs(vptr);
1836 if (status & ISR_LSTEI)
1837 mac_rx_queue_wake(vptr->mac_regs);
1838}
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849static int velocity_tx_srv(struct velocity_info *vptr, u32 status)
1850{
1851 struct tx_desc *td;
1852 int qnum;
1853 int full = 0;
1854 int idx;
1855 int works = 0;
1856 struct velocity_td_info *tdinfo;
1857 struct net_device_stats *stats = &vptr->dev->stats;
1858
1859 for (qnum = 0; qnum < vptr->tx.numq; qnum++) {
1860 for (idx = vptr->tx.tail[qnum]; vptr->tx.used[qnum] > 0;
1861 idx = (idx + 1) % vptr->options.numtx) {
1862
1863
1864
1865
1866 td = &(vptr->tx.rings[qnum][idx]);
1867 tdinfo = &(vptr->tx.infos[qnum][idx]);
1868
1869 if (td->tdesc0.len & OWNED_BY_NIC)
1870 break;
1871
1872 if ((works++ > 15))
1873 break;
1874
1875 if (td->tdesc0.TSR & TSR0_TERR) {
1876 stats->tx_errors++;
1877 stats->tx_dropped++;
1878 if (td->tdesc0.TSR & TSR0_CDH)
1879 stats->tx_heartbeat_errors++;
1880 if (td->tdesc0.TSR & TSR0_CRS)
1881 stats->tx_carrier_errors++;
1882 if (td->tdesc0.TSR & TSR0_ABT)
1883 stats->tx_aborted_errors++;
1884 if (td->tdesc0.TSR & TSR0_OWC)
1885 stats->tx_window_errors++;
1886 } else {
1887 stats->tx_packets++;
1888 stats->tx_bytes += tdinfo->skb->len;
1889 }
1890 velocity_free_tx_buf(vptr, tdinfo);
1891 vptr->tx.used[qnum]--;
1892 }
1893 vptr->tx.tail[qnum] = idx;
1894
1895 if (AVAIL_TD(vptr, qnum) < 1)
1896 full = 1;
1897 }
1898
1899
1900
1901
1902 if (netif_queue_stopped(vptr->dev) && (full == 0)
1903 && (!(vptr->mii_status & VELOCITY_LINK_FAIL))) {
1904 netif_wake_queue(vptr->dev);
1905 }
1906 return works;
1907}
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
1918{
1919 skb->ip_summed = CHECKSUM_NONE;
1920
1921 if (rd->rdesc1.CSM & CSM_IPKT) {
1922 if (rd->rdesc1.CSM & CSM_IPOK) {
1923 if ((rd->rdesc1.CSM & CSM_TCPKT) ||
1924 (rd->rdesc1.CSM & CSM_UDPKT)) {
1925 if (!(rd->rdesc1.CSM & CSM_TUPOK))
1926 return;
1927 }
1928 skb->ip_summed = CHECKSUM_UNNECESSARY;
1929 }
1930 }
1931}
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945static int velocity_rx_copy(struct sk_buff **rx_skb, int pkt_size,
1946 struct velocity_info *vptr)
1947{
1948 int ret = -1;
1949 if (pkt_size < rx_copybreak) {
1950 struct sk_buff *new_skb;
1951
1952 new_skb = netdev_alloc_skb(vptr->dev, pkt_size + 2);
1953 if (new_skb) {
1954 new_skb->ip_summed = rx_skb[0]->ip_summed;
1955 skb_reserve(new_skb, 2);
1956 skb_copy_from_linear_data(*rx_skb, new_skb->data, pkt_size);
1957 *rx_skb = new_skb;
1958 ret = 0;
1959 }
1960
1961 }
1962 return ret;
1963}
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974static inline void velocity_iph_realign(struct velocity_info *vptr,
1975 struct sk_buff *skb, int pkt_size)
1976{
1977 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
1978 memmove(skb->data + 2, skb->data, pkt_size);
1979 skb_reserve(skb, 2);
1980 }
1981}
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992static int velocity_receive_frame(struct velocity_info *vptr, int idx)
1993{
1994 void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
1995 struct net_device_stats *stats = &vptr->dev->stats;
1996 struct velocity_rd_info *rd_info = &(vptr->rx.info[idx]);
1997 struct rx_desc *rd = &(vptr->rx.ring[idx]);
1998 int pkt_len = le16_to_cpu(rd->rdesc0.len) & 0x3fff;
1999 struct sk_buff *skb;
2000
2001 if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
2002 VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
2003 stats->rx_length_errors++;
2004 return -EINVAL;
2005 }
2006
2007 if (rd->rdesc0.RSR & RSR_MAR)
2008 stats->multicast++;
2009
2010 skb = rd_info->skb;
2011
2012 pci_dma_sync_single_for_cpu(vptr->pdev, rd_info->skb_dma,
2013 vptr->rx.buf_sz, PCI_DMA_FROMDEVICE);
2014
2015
2016
2017
2018
2019 if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
2020 if (rd->rdesc0.RSR & RSR_RL) {
2021 stats->rx_length_errors++;
2022 return -EINVAL;
2023 }
2024 }
2025
2026 pci_action = pci_dma_sync_single_for_device;
2027
2028 velocity_rx_csum(rd, skb);
2029
2030 if (velocity_rx_copy(&skb, pkt_len, vptr) < 0) {
2031 velocity_iph_realign(vptr, skb, pkt_len);
2032 pci_action = pci_unmap_single;
2033 rd_info->skb = NULL;
2034 }
2035
2036 pci_action(vptr->pdev, rd_info->skb_dma, vptr->rx.buf_sz,
2037 PCI_DMA_FROMDEVICE);
2038
2039 skb_put(skb, pkt_len - 4);
2040 skb->protocol = eth_type_trans(skb, vptr->dev);
2041
2042 if (vptr->vlgrp && (rd->rdesc0.RSR & RSR_DETAG)) {
2043 vlan_hwaccel_rx(skb, vptr->vlgrp,
2044 swab16(le16_to_cpu(rd->rdesc1.PQTAG)));
2045 } else
2046 netif_rx(skb);
2047
2048 stats->rx_bytes += pkt_len;
2049
2050 return 0;
2051}
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063static int velocity_rx_srv(struct velocity_info *vptr, int status)
2064{
2065 struct net_device_stats *stats = &vptr->dev->stats;
2066 int rd_curr = vptr->rx.curr;
2067 int works = 0;
2068
2069 do {
2070 struct rx_desc *rd = vptr->rx.ring + rd_curr;
2071
2072 if (!vptr->rx.info[rd_curr].skb)
2073 break;
2074
2075 if (rd->rdesc0.len & OWNED_BY_NIC)
2076 break;
2077
2078 rmb();
2079
2080
2081
2082
2083 if (rd->rdesc0.RSR & (RSR_RXOK | RSR_CE | RSR_RL)) {
2084 if (velocity_receive_frame(vptr, rd_curr) < 0)
2085 stats->rx_dropped++;
2086 } else {
2087 if (rd->rdesc0.RSR & RSR_CRC)
2088 stats->rx_crc_errors++;
2089 if (rd->rdesc0.RSR & RSR_FAE)
2090 stats->rx_frame_errors++;
2091
2092 stats->rx_dropped++;
2093 }
2094
2095 rd->size |= RX_INTEN;
2096
2097 rd_curr++;
2098 if (rd_curr >= vptr->options.numrx)
2099 rd_curr = 0;
2100 } while (++works <= 15);
2101
2102 vptr->rx.curr = rd_curr;
2103
2104 if ((works > 0) && (velocity_rx_refill(vptr) > 0))
2105 velocity_give_many_rx_descs(vptr);
2106
2107 VAR_USED(stats);
2108 return works;
2109}
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122static irqreturn_t velocity_intr(int irq, void *dev_instance)
2123{
2124 struct net_device *dev = dev_instance;
2125 struct velocity_info *vptr = netdev_priv(dev);
2126 u32 isr_status;
2127 int max_count = 0;
2128
2129
2130 spin_lock(&vptr->lock);
2131 isr_status = mac_read_isr(vptr->mac_regs);
2132
2133
2134 if (isr_status == 0) {
2135 spin_unlock(&vptr->lock);
2136 return IRQ_NONE;
2137 }
2138
2139 mac_disable_int(vptr->mac_regs);
2140
2141
2142
2143
2144
2145
2146 while (isr_status != 0) {
2147 mac_write_isr(vptr->mac_regs, isr_status);
2148 if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
2149 velocity_error(vptr, isr_status);
2150 if (isr_status & (ISR_PRXI | ISR_PPRXI))
2151 max_count += velocity_rx_srv(vptr, isr_status);
2152 if (isr_status & (ISR_PTXI | ISR_PPTXI))
2153 max_count += velocity_tx_srv(vptr, isr_status);
2154 isr_status = mac_read_isr(vptr->mac_regs);
2155 if (max_count > vptr->options.int_works) {
2156 printk(KERN_WARNING "%s: excessive work at interrupt.\n",
2157 dev->name);
2158 max_count = 0;
2159 }
2160 }
2161 spin_unlock(&vptr->lock);
2162 mac_enable_int(vptr->mac_regs);
2163 return IRQ_HANDLED;
2164
2165}
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177static int velocity_open(struct net_device *dev)
2178{
2179 struct velocity_info *vptr = netdev_priv(dev);
2180 int ret;
2181
2182 ret = velocity_init_rings(vptr, dev->mtu);
2183 if (ret < 0)
2184 goto out;
2185
2186
2187 pci_set_power_state(vptr->pdev, PCI_D0);
2188
2189 velocity_give_many_rx_descs(vptr);
2190
2191 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2192
2193 ret = request_irq(vptr->pdev->irq, &velocity_intr, IRQF_SHARED,
2194 dev->name, dev);
2195 if (ret < 0) {
2196
2197 pci_set_power_state(vptr->pdev, PCI_D3hot);
2198 velocity_free_rings(vptr);
2199 goto out;
2200 }
2201
2202 mac_enable_int(vptr->mac_regs);
2203 netif_start_queue(dev);
2204 vptr->flags |= VELOCITY_FLAGS_OPENED;
2205out:
2206 return ret;
2207}
2208
2209
2210
2211
2212
2213
2214
2215
2216static void velocity_shutdown(struct velocity_info *vptr)
2217{
2218 struct mac_regs __iomem *regs = vptr->mac_regs;
2219 mac_disable_int(regs);
2220 writel(CR0_STOP, ®s->CR0Set);
2221 writew(0xFFFF, ®s->TDCSRClr);
2222 writeb(0xFF, ®s->RDCSRClr);
2223 safe_disable_mii_autopoll(regs);
2224 mac_clear_isr(regs);
2225}
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236static int velocity_change_mtu(struct net_device *dev, int new_mtu)
2237{
2238 struct velocity_info *vptr = netdev_priv(dev);
2239 int ret = 0;
2240
2241 if ((new_mtu < VELOCITY_MIN_MTU) || new_mtu > (VELOCITY_MAX_MTU)) {
2242 VELOCITY_PRT(MSG_LEVEL_ERR, KERN_NOTICE "%s: Invalid MTU.\n",
2243 vptr->dev->name);
2244 ret = -EINVAL;
2245 goto out_0;
2246 }
2247
2248 if (!netif_running(dev)) {
2249 dev->mtu = new_mtu;
2250 goto out_0;
2251 }
2252
2253 if (dev->mtu != new_mtu) {
2254 struct velocity_info *tmp_vptr;
2255 unsigned long flags;
2256 struct rx_info rx;
2257 struct tx_info tx;
2258
2259 tmp_vptr = kzalloc(sizeof(*tmp_vptr), GFP_KERNEL);
2260 if (!tmp_vptr) {
2261 ret = -ENOMEM;
2262 goto out_0;
2263 }
2264
2265 tmp_vptr->dev = dev;
2266 tmp_vptr->pdev = vptr->pdev;
2267 tmp_vptr->options = vptr->options;
2268 tmp_vptr->tx.numq = vptr->tx.numq;
2269
2270 ret = velocity_init_rings(tmp_vptr, new_mtu);
2271 if (ret < 0)
2272 goto out_free_tmp_vptr_1;
2273
2274 spin_lock_irqsave(&vptr->lock, flags);
2275
2276 netif_stop_queue(dev);
2277 velocity_shutdown(vptr);
2278
2279 rx = vptr->rx;
2280 tx = vptr->tx;
2281
2282 vptr->rx = tmp_vptr->rx;
2283 vptr->tx = tmp_vptr->tx;
2284
2285 tmp_vptr->rx = rx;
2286 tmp_vptr->tx = tx;
2287
2288 dev->mtu = new_mtu;
2289
2290 velocity_give_many_rx_descs(vptr);
2291
2292 velocity_init_registers(vptr, VELOCITY_INIT_COLD);
2293
2294 mac_enable_int(vptr->mac_regs);
2295 netif_start_queue(dev);
2296
2297 spin_unlock_irqrestore(&vptr->lock, flags);
2298
2299 velocity_free_rings(tmp_vptr);
2300
2301out_free_tmp_vptr_1:
2302 kfree(tmp_vptr);
2303 }
2304out_0:
2305 return ret;
2306}
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318static int velocity_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2319{
2320 struct velocity_info *vptr = netdev_priv(dev);
2321 struct mac_regs __iomem *regs = vptr->mac_regs;
2322 unsigned long flags;
2323 struct mii_ioctl_data *miidata = if_mii(ifr);
2324 int err;
2325
2326 switch (cmd) {
2327 case SIOCGMIIPHY:
2328 miidata->phy_id = readb(®s->MIIADR) & 0x1f;
2329 break;
2330 case SIOCGMIIREG:
2331 if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)
2332 return -ETIMEDOUT;
2333 break;
2334 case SIOCSMIIREG:
2335 spin_lock_irqsave(&vptr->lock, flags);
2336 err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);
2337 spin_unlock_irqrestore(&vptr->lock, flags);
2338 check_connection_type(vptr->mac_regs);
2339 if (err)
2340 return err;
2341 break;
2342 default:
2343 return -EOPNOTSUPP;
2344 }
2345 return 0;
2346}
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358static int velocity_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2359{
2360 struct velocity_info *vptr = netdev_priv(dev);
2361 int ret;
2362
2363
2364
2365
2366 if (!netif_running(dev))
2367 pci_set_power_state(vptr->pdev, PCI_D0);
2368
2369 switch (cmd) {
2370 case SIOCGMIIPHY:
2371 case SIOCGMIIREG:
2372 case SIOCSMIIREG:
2373 ret = velocity_mii_ioctl(dev, rq, cmd);
2374 break;
2375
2376 default:
2377 ret = -EOPNOTSUPP;
2378 }
2379 if (!netif_running(dev))
2380 pci_set_power_state(vptr->pdev, PCI_D3hot);
2381
2382
2383 return ret;
2384}
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396static struct net_device_stats *velocity_get_stats(struct net_device *dev)
2397{
2398 struct velocity_info *vptr = netdev_priv(dev);
2399
2400
2401 if (!netif_running(dev))
2402 return &dev->stats;
2403
2404 spin_lock_irq(&vptr->lock);
2405 velocity_update_hw_mibs(vptr);
2406 spin_unlock_irq(&vptr->lock);
2407
2408 dev->stats.rx_packets = vptr->mib_counter[HW_MIB_ifRxAllPkts];
2409 dev->stats.rx_errors = vptr->mib_counter[HW_MIB_ifRxErrorPkts];
2410 dev->stats.rx_length_errors = vptr->mib_counter[HW_MIB_ifInRangeLengthErrors];
2411
2412
2413 dev->stats.collisions = vptr->mib_counter[HW_MIB_ifTxEtherCollisions];
2414
2415
2416
2417 dev->stats.rx_crc_errors = vptr->mib_counter[HW_MIB_ifRxPktCRCE];
2418
2419
2420
2421
2422
2423
2424
2425 return &dev->stats;
2426}
2427
2428
2429
2430
2431
2432
2433
2434
2435static int velocity_close(struct net_device *dev)
2436{
2437 struct velocity_info *vptr = netdev_priv(dev);
2438
2439 netif_stop_queue(dev);
2440 velocity_shutdown(vptr);
2441
2442 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED)
2443 velocity_get_ip(vptr);
2444 if (dev->irq != 0)
2445 free_irq(dev->irq, dev);
2446
2447
2448 pci_set_power_state(vptr->pdev, PCI_D3hot);
2449
2450 velocity_free_rings(vptr);
2451
2452 vptr->flags &= (~VELOCITY_FLAGS_OPENED);
2453 return 0;
2454}
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464static netdev_tx_t velocity_xmit(struct sk_buff *skb,
2465 struct net_device *dev)
2466{
2467 struct velocity_info *vptr = netdev_priv(dev);
2468 int qnum = 0;
2469 struct tx_desc *td_ptr;
2470 struct velocity_td_info *tdinfo;
2471 unsigned long flags;
2472 int pktlen;
2473 __le16 len;
2474 int index;
2475
2476 if (skb_padto(skb, ETH_ZLEN))
2477 goto out;
2478 pktlen = max_t(unsigned int, skb->len, ETH_ZLEN);
2479
2480 len = cpu_to_le16(pktlen);
2481
2482 spin_lock_irqsave(&vptr->lock, flags);
2483
2484 index = vptr->tx.curr[qnum];
2485 td_ptr = &(vptr->tx.rings[qnum][index]);
2486 tdinfo = &(vptr->tx.infos[qnum][index]);
2487
2488 td_ptr->tdesc1.TCR = TCR0_TIC;
2489 td_ptr->td_buf[0].size &= ~TD_QUEUE;
2490
2491
2492
2493
2494
2495 tdinfo->skb = skb;
2496 tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
2497 td_ptr->tdesc0.len = len;
2498 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
2499 td_ptr->td_buf[0].pa_high = 0;
2500 td_ptr->td_buf[0].size = len;
2501 tdinfo->nskb_dma = 1;
2502
2503 td_ptr->tdesc1.cmd = TCPLS_NORMAL + (tdinfo->nskb_dma + 1) * 16;
2504
2505 if (vptr->vlgrp && vlan_tx_tag_present(skb)) {
2506 td_ptr->tdesc1.vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2507 td_ptr->tdesc1.TCR |= TCR0_VETAG;
2508 }
2509
2510
2511
2512
2513 if ((vptr->flags & VELOCITY_FLAGS_TX_CSUM)
2514 && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2515 const struct iphdr *ip = ip_hdr(skb);
2516 if (ip->protocol == IPPROTO_TCP)
2517 td_ptr->tdesc1.TCR |= TCR0_TCPCK;
2518 else if (ip->protocol == IPPROTO_UDP)
2519 td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
2520 td_ptr->tdesc1.TCR |= TCR0_IPCK;
2521 }
2522 {
2523
2524 int prev = index - 1;
2525
2526 if (prev < 0)
2527 prev = vptr->options.numtx - 1;
2528 td_ptr->tdesc0.len |= OWNED_BY_NIC;
2529 vptr->tx.used[qnum]++;
2530 vptr->tx.curr[qnum] = (index + 1) % vptr->options.numtx;
2531
2532 if (AVAIL_TD(vptr, qnum) < 1)
2533 netif_stop_queue(dev);
2534
2535 td_ptr = &(vptr->tx.rings[qnum][prev]);
2536 td_ptr->td_buf[0].size |= TD_QUEUE;
2537 mac_tx_queue_wake(vptr->mac_regs, qnum);
2538 }
2539 dev->trans_start = jiffies;
2540 spin_unlock_irqrestore(&vptr->lock, flags);
2541out:
2542 return NETDEV_TX_OK;
2543}
2544
2545
2546static const struct net_device_ops velocity_netdev_ops = {
2547 .ndo_open = velocity_open,
2548 .ndo_stop = velocity_close,
2549 .ndo_start_xmit = velocity_xmit,
2550 .ndo_get_stats = velocity_get_stats,
2551 .ndo_validate_addr = eth_validate_addr,
2552 .ndo_set_mac_address = eth_mac_addr,
2553 .ndo_set_multicast_list = velocity_set_multi,
2554 .ndo_change_mtu = velocity_change_mtu,
2555 .ndo_do_ioctl = velocity_ioctl,
2556 .ndo_vlan_rx_add_vid = velocity_vlan_rx_add_vid,
2557 .ndo_vlan_rx_kill_vid = velocity_vlan_rx_kill_vid,
2558 .ndo_vlan_rx_register = velocity_vlan_rx_register,
2559};
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570static void __devinit velocity_init_info(struct pci_dev *pdev,
2571 struct velocity_info *vptr,
2572 const struct velocity_info_tbl *info)
2573{
2574 memset(vptr, 0, sizeof(struct velocity_info));
2575
2576 vptr->pdev = pdev;
2577 vptr->chip_id = info->chip_id;
2578 vptr->tx.numq = info->txqueue;
2579 vptr->multicast_limit = MCAM_SIZE;
2580 spin_lock_init(&vptr->lock);
2581 INIT_LIST_HEAD(&vptr->list);
2582}
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592static int __devinit velocity_get_pci_info(struct velocity_info *vptr, struct pci_dev *pdev)
2593{
2594 vptr->rev_id = pdev->revision;
2595
2596 pci_set_master(pdev);
2597
2598 vptr->ioaddr = pci_resource_start(pdev, 0);
2599 vptr->memaddr = pci_resource_start(pdev, 1);
2600
2601 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2602 dev_err(&pdev->dev,
2603 "region #0 is not an I/O resource, aborting.\n");
2604 return -EINVAL;
2605 }
2606
2607 if ((pci_resource_flags(pdev, 1) & IORESOURCE_IO)) {
2608 dev_err(&pdev->dev,
2609 "region #1 is an I/O resource, aborting.\n");
2610 return -EINVAL;
2611 }
2612
2613 if (pci_resource_len(pdev, 1) < VELOCITY_IO_SIZE) {
2614 dev_err(&pdev->dev, "region #1 is too small.\n");
2615 return -EINVAL;
2616 }
2617 vptr->pdev = pdev;
2618
2619 return 0;
2620}
2621
2622
2623
2624
2625
2626
2627
2628
2629static void __devinit velocity_print_info(struct velocity_info *vptr)
2630{
2631 struct net_device *dev = vptr->dev;
2632
2633 printk(KERN_INFO "%s: %s\n", dev->name, get_chip_name(vptr->chip_id));
2634 printk(KERN_INFO "%s: Ethernet Address: %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
2635 dev->name,
2636 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2637 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2638}
2639
2640static u32 velocity_get_link(struct net_device *dev)
2641{
2642 struct velocity_info *vptr = netdev_priv(dev);
2643 struct mac_regs __iomem *regs = vptr->mac_regs;
2644 return BYTE_REG_BITS_IS_ON(PHYSR0_LINKGD, ®s->PHYSR0) ? 1 : 0;
2645}
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656static int __devinit velocity_found1(struct pci_dev *pdev, const struct pci_device_id *ent)
2657{
2658 static int first = 1;
2659 struct net_device *dev;
2660 int i;
2661 const char *drv_string;
2662 const struct velocity_info_tbl *info = &chip_info_table[ent->driver_data];
2663 struct velocity_info *vptr;
2664 struct mac_regs __iomem *regs;
2665 int ret = -ENOMEM;
2666
2667
2668
2669
2670 if (velocity_nics >= MAX_UNITS) {
2671 dev_notice(&pdev->dev, "already found %d NICs.\n",
2672 velocity_nics);
2673 return -ENODEV;
2674 }
2675
2676 dev = alloc_etherdev(sizeof(struct velocity_info));
2677 if (!dev) {
2678 dev_err(&pdev->dev, "allocate net device failed.\n");
2679 goto out;
2680 }
2681
2682
2683
2684 SET_NETDEV_DEV(dev, &pdev->dev);
2685 vptr = netdev_priv(dev);
2686
2687
2688 if (first) {
2689 printk(KERN_INFO "%s Ver. %s\n",
2690 VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
2691 printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
2692 printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
2693 first = 0;
2694 }
2695
2696 velocity_init_info(pdev, vptr, info);
2697
2698 vptr->dev = dev;
2699
2700 dev->irq = pdev->irq;
2701
2702 ret = pci_enable_device(pdev);
2703 if (ret < 0)
2704 goto err_free_dev;
2705
2706 ret = velocity_get_pci_info(vptr, pdev);
2707 if (ret < 0) {
2708
2709 goto err_disable;
2710 }
2711
2712 ret = pci_request_regions(pdev, VELOCITY_NAME);
2713 if (ret < 0) {
2714 dev_err(&pdev->dev, "No PCI resources.\n");
2715 goto err_disable;
2716 }
2717
2718 regs = ioremap(vptr->memaddr, VELOCITY_IO_SIZE);
2719 if (regs == NULL) {
2720 ret = -EIO;
2721 goto err_release_res;
2722 }
2723
2724 vptr->mac_regs = regs;
2725
2726 mac_wol_reset(regs);
2727
2728 dev->base_addr = vptr->ioaddr;
2729
2730 for (i = 0; i < 6; i++)
2731 dev->dev_addr[i] = readb(®s->PAR[i]);
2732
2733
2734 drv_string = dev_driver_string(&pdev->dev);
2735
2736 velocity_get_options(&vptr->options, velocity_nics, drv_string);
2737
2738
2739
2740
2741
2742 vptr->options.flags &= info->flags;
2743
2744
2745
2746
2747
2748 vptr->flags = vptr->options.flags | (info->flags & 0xFF000000UL);
2749
2750 vptr->wol_opts = vptr->options.wol_opts;
2751 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
2752
2753 vptr->phy_id = MII_GET_PHY_ID(vptr->mac_regs);
2754
2755 dev->irq = pdev->irq;
2756 dev->netdev_ops = &velocity_netdev_ops;
2757 dev->ethtool_ops = &velocity_ethtool_ops;
2758
2759 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
2760 NETIF_F_HW_VLAN_RX;
2761
2762 if (vptr->flags & VELOCITY_FLAGS_TX_CSUM)
2763 dev->features |= NETIF_F_IP_CSUM;
2764
2765 ret = register_netdev(dev);
2766 if (ret < 0)
2767 goto err_iounmap;
2768
2769 if (!velocity_get_link(dev)) {
2770 netif_carrier_off(dev);
2771 vptr->mii_status |= VELOCITY_LINK_FAIL;
2772 }
2773
2774 velocity_print_info(vptr);
2775 pci_set_drvdata(pdev, dev);
2776
2777
2778
2779 pci_set_power_state(pdev, PCI_D3hot);
2780#ifdef CONFIG_PM
2781 {
2782 unsigned long flags;
2783
2784 spin_lock_irqsave(&velocity_dev_list_lock, flags);
2785 list_add(&vptr->list, &velocity_dev_list);
2786 spin_unlock_irqrestore(&velocity_dev_list_lock, flags);
2787 }
2788#endif
2789 velocity_nics++;
2790out:
2791 return ret;
2792
2793err_iounmap:
2794 iounmap(regs);
2795err_release_res:
2796 pci_release_regions(pdev);
2797err_disable:
2798 pci_disable_device(pdev);
2799err_free_dev:
2800 free_netdev(dev);
2801 goto out;
2802}
2803
2804
2805#ifdef CONFIG_PM
2806
2807
2808
2809
2810
2811
2812
2813
2814static u16 wol_calc_crc(int size, u8 *pattern, u8 *mask_pattern)
2815{
2816 u16 crc = 0xFFFF;
2817 u8 mask;
2818 int i, j;
2819
2820 for (i = 0; i < size; i++) {
2821 mask = mask_pattern[i];
2822
2823
2824 if (mask == 0x00)
2825 continue;
2826
2827 for (j = 0; j < 8; j++) {
2828 if ((mask & 0x01) == 0) {
2829 mask >>= 1;
2830 continue;
2831 }
2832 mask >>= 1;
2833 crc = crc_ccitt(crc, &(pattern[i * 8 + j]), 1);
2834 }
2835 }
2836
2837 crc = ~crc;
2838 return bitrev32(crc) >> 16;
2839}
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850static int velocity_set_wol(struct velocity_info *vptr)
2851{
2852 struct mac_regs __iomem *regs = vptr->mac_regs;
2853 static u8 buf[256];
2854 int i;
2855
2856 static u32 mask_pattern[2][4] = {
2857 {0x00203000, 0x000003C0, 0x00000000, 0x0000000},
2858 {0xfffff000, 0xffffffff, 0xffffffff, 0x000ffff}
2859 };
2860
2861 writew(0xFFFF, ®s->WOLCRClr);
2862 writeb(WOLCFG_SAB | WOLCFG_SAM, ®s->WOLCFGSet);
2863 writew(WOLCR_MAGIC_EN, ®s->WOLCRSet);
2864
2865
2866
2867
2868
2869
2870 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
2871 writew(WOLCR_UNICAST_EN, ®s->WOLCRSet);
2872
2873 if (vptr->wol_opts & VELOCITY_WOL_ARP) {
2874 struct arp_packet *arp = (struct arp_packet *) buf;
2875 u16 crc;
2876 memset(buf, 0, sizeof(struct arp_packet) + 7);
2877
2878 for (i = 0; i < 4; i++)
2879 writel(mask_pattern[0][i], ®s->ByteMask[0][i]);
2880
2881 arp->type = htons(ETH_P_ARP);
2882 arp->ar_op = htons(1);
2883
2884 memcpy(arp->ar_tip, vptr->ip_addr, 4);
2885
2886 crc = wol_calc_crc((sizeof(struct arp_packet) + 7) / 8, buf,
2887 (u8 *) & mask_pattern[0][0]);
2888
2889 writew(crc, ®s->PatternCRC[0]);
2890 writew(WOLCR_ARP_EN, ®s->WOLCRSet);
2891 }
2892
2893 BYTE_REG_BITS_ON(PWCFG_WOLTYPE, ®s->PWCFGSet);
2894 BYTE_REG_BITS_ON(PWCFG_LEGACY_WOLEN, ®s->PWCFGSet);
2895
2896 writew(0x0FFF, ®s->WOLSRClr);
2897
2898 if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
2899 if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
2900 MII_REG_BITS_ON(AUXCR_MDPPS, MII_REG_AUXCR, vptr->mac_regs);
2901
2902 MII_REG_BITS_OFF(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
2903 }
2904
2905 if (vptr->mii_status & VELOCITY_SPEED_1000)
2906 MII_REG_BITS_ON(BMCR_REAUTO, MII_REG_BMCR, vptr->mac_regs);
2907
2908 BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
2909
2910 {
2911 u8 GCR;
2912 GCR = readb(®s->CHIPGCR);
2913 GCR = (GCR & ~CHIPGCR_FCGMII) | CHIPGCR_FCFDX;
2914 writeb(GCR, ®s->CHIPGCR);
2915 }
2916
2917 BYTE_REG_BITS_OFF(ISR_PWEI, ®s->ISR);
2918
2919 BYTE_REG_BITS_ON(STICKHW_SWPTAG, ®s->STICKHW);
2920
2921 BYTE_REG_BITS_ON((STICKHW_DS1 | STICKHW_DS0), ®s->STICKHW);
2922
2923 return 0;
2924}
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936static void velocity_save_context(struct velocity_info *vptr, struct velocity_context *context)
2937{
2938 struct mac_regs __iomem *regs = vptr->mac_regs;
2939 u16 i;
2940 u8 __iomem *ptr = (u8 __iomem *)regs;
2941
2942 for (i = MAC_REG_PAR; i < MAC_REG_CR0_CLR; i += 4)
2943 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
2944
2945 for (i = MAC_REG_MAR; i < MAC_REG_TDCSR_CLR; i += 4)
2946 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
2947
2948 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
2949 *((u32 *) (context->mac_reg + i)) = readl(ptr + i);
2950
2951}
2952
2953static int velocity_suspend(struct pci_dev *pdev, pm_message_t state)
2954{
2955 struct net_device *dev = pci_get_drvdata(pdev);
2956 struct velocity_info *vptr = netdev_priv(dev);
2957 unsigned long flags;
2958
2959 if (!netif_running(vptr->dev))
2960 return 0;
2961
2962 netif_device_detach(vptr->dev);
2963
2964 spin_lock_irqsave(&vptr->lock, flags);
2965 pci_save_state(pdev);
2966#ifdef ETHTOOL_GWOL
2967 if (vptr->flags & VELOCITY_FLAGS_WOL_ENABLED) {
2968 velocity_get_ip(vptr);
2969 velocity_save_context(vptr, &vptr->context);
2970 velocity_shutdown(vptr);
2971 velocity_set_wol(vptr);
2972 pci_enable_wake(pdev, PCI_D3hot, 1);
2973 pci_set_power_state(pdev, PCI_D3hot);
2974 } else {
2975 velocity_save_context(vptr, &vptr->context);
2976 velocity_shutdown(vptr);
2977 pci_disable_device(pdev);
2978 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2979 }
2980#else
2981 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2982#endif
2983 spin_unlock_irqrestore(&vptr->lock, flags);
2984 return 0;
2985}
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995static void velocity_restore_context(struct velocity_info *vptr, struct velocity_context *context)
2996{
2997 struct mac_regs __iomem *regs = vptr->mac_regs;
2998 int i;
2999 u8 __iomem *ptr = (u8 __iomem *)regs;
3000
3001 for (i = MAC_REG_PAR; i < MAC_REG_CR0_SET; i += 4)
3002 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3003
3004
3005 for (i = MAC_REG_CR1_SET; i < MAC_REG_CR0_CLR; i++) {
3006
3007 writeb(~(*((u8 *) (context->mac_reg + i))), ptr + i + 4);
3008
3009 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3010 }
3011
3012 for (i = MAC_REG_MAR; i < MAC_REG_IMR; i += 4)
3013 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3014
3015 for (i = MAC_REG_RDBASE_LO; i < MAC_REG_FIFO_TEST0; i += 4)
3016 writel(*((u32 *) (context->mac_reg + i)), ptr + i);
3017
3018 for (i = MAC_REG_TDCSR_SET; i <= MAC_REG_RDCSR_SET; i++)
3019 writeb(*((u8 *) (context->mac_reg + i)), ptr + i);
3020}
3021
3022static int velocity_resume(struct pci_dev *pdev)
3023{
3024 struct net_device *dev = pci_get_drvdata(pdev);
3025 struct velocity_info *vptr = netdev_priv(dev);
3026 unsigned long flags;
3027 int i;
3028
3029 if (!netif_running(vptr->dev))
3030 return 0;
3031
3032 pci_set_power_state(pdev, PCI_D0);
3033 pci_enable_wake(pdev, 0, 0);
3034 pci_restore_state(pdev);
3035
3036 mac_wol_reset(vptr->mac_regs);
3037
3038 spin_lock_irqsave(&vptr->lock, flags);
3039 velocity_restore_context(vptr, &vptr->context);
3040 velocity_init_registers(vptr, VELOCITY_INIT_WOL);
3041 mac_disable_int(vptr->mac_regs);
3042
3043 velocity_tx_srv(vptr, 0);
3044
3045 for (i = 0; i < vptr->tx.numq; i++) {
3046 if (vptr->tx.used[i])
3047 mac_tx_queue_wake(vptr->mac_regs, i);
3048 }
3049
3050 mac_enable_int(vptr->mac_regs);
3051 spin_unlock_irqrestore(&vptr->lock, flags);
3052 netif_device_attach(vptr->dev);
3053
3054 return 0;
3055}
3056#endif
3057
3058
3059
3060
3061
3062static struct pci_driver velocity_driver = {
3063 .name = VELOCITY_NAME,
3064 .id_table = velocity_id_table,
3065 .probe = velocity_found1,
3066 .remove = __devexit_p(velocity_remove1),
3067#ifdef CONFIG_PM
3068 .suspend = velocity_suspend,
3069 .resume = velocity_resume,
3070#endif
3071};
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081static int velocity_ethtool_up(struct net_device *dev)
3082{
3083 struct velocity_info *vptr = netdev_priv(dev);
3084 if (!netif_running(dev))
3085 pci_set_power_state(vptr->pdev, PCI_D0);
3086 return 0;
3087}
3088
3089
3090
3091
3092
3093
3094
3095
3096static void velocity_ethtool_down(struct net_device *dev)
3097{
3098 struct velocity_info *vptr = netdev_priv(dev);
3099 if (!netif_running(dev))
3100 pci_set_power_state(vptr->pdev, PCI_D3hot);
3101}
3102
3103static int velocity_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3104{
3105 struct velocity_info *vptr = netdev_priv(dev);
3106 struct mac_regs __iomem *regs = vptr->mac_regs;
3107 u32 status;
3108 status = check_connection_type(vptr->mac_regs);
3109
3110 cmd->supported = SUPPORTED_TP |
3111 SUPPORTED_Autoneg |
3112 SUPPORTED_10baseT_Half |
3113 SUPPORTED_10baseT_Full |
3114 SUPPORTED_100baseT_Half |
3115 SUPPORTED_100baseT_Full |
3116 SUPPORTED_1000baseT_Half |
3117 SUPPORTED_1000baseT_Full;
3118 if (status & VELOCITY_SPEED_1000)
3119 cmd->speed = SPEED_1000;
3120 else if (status & VELOCITY_SPEED_100)
3121 cmd->speed = SPEED_100;
3122 else
3123 cmd->speed = SPEED_10;
3124 cmd->autoneg = (status & VELOCITY_AUTONEG_ENABLE) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3125 cmd->port = PORT_TP;
3126 cmd->transceiver = XCVR_INTERNAL;
3127 cmd->phy_address = readb(®s->MIIADR) & 0x1F;
3128
3129 if (status & VELOCITY_DUPLEX_FULL)
3130 cmd->duplex = DUPLEX_FULL;
3131 else
3132 cmd->duplex = DUPLEX_HALF;
3133
3134 return 0;
3135}
3136
3137static int velocity_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3138{
3139 struct velocity_info *vptr = netdev_priv(dev);
3140 u32 curr_status;
3141 u32 new_status = 0;
3142 int ret = 0;
3143
3144 curr_status = check_connection_type(vptr->mac_regs);
3145 curr_status &= (~VELOCITY_LINK_FAIL);
3146
3147 new_status |= ((cmd->autoneg) ? VELOCITY_AUTONEG_ENABLE : 0);
3148 new_status |= ((cmd->speed == SPEED_100) ? VELOCITY_SPEED_100 : 0);
3149 new_status |= ((cmd->speed == SPEED_10) ? VELOCITY_SPEED_10 : 0);
3150 new_status |= ((cmd->duplex == DUPLEX_FULL) ? VELOCITY_DUPLEX_FULL : 0);
3151
3152 if ((new_status & VELOCITY_AUTONEG_ENABLE) && (new_status != (curr_status | VELOCITY_AUTONEG_ENABLE)))
3153 ret = -EINVAL;
3154 else
3155 velocity_set_media_mode(vptr, new_status);
3156
3157 return ret;
3158}
3159
3160static void velocity_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3161{
3162 struct velocity_info *vptr = netdev_priv(dev);
3163 strcpy(info->driver, VELOCITY_NAME);
3164 strcpy(info->version, VELOCITY_VERSION);
3165 strcpy(info->bus_info, pci_name(vptr->pdev));
3166}
3167
3168static void velocity_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3169{
3170 struct velocity_info *vptr = netdev_priv(dev);
3171 wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP;
3172 wol->wolopts |= WAKE_MAGIC;
3173
3174
3175
3176
3177 if (vptr->wol_opts & VELOCITY_WOL_UCAST)
3178 wol->wolopts |= WAKE_UCAST;
3179 if (vptr->wol_opts & VELOCITY_WOL_ARP)
3180 wol->wolopts |= WAKE_ARP;
3181 memcpy(&wol->sopass, vptr->wol_passwd, 6);
3182}
3183
3184static int velocity_ethtool_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3185{
3186 struct velocity_info *vptr = netdev_priv(dev);
3187
3188 if (!(wol->wolopts & (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_ARP)))
3189 return -EFAULT;
3190 vptr->wol_opts = VELOCITY_WOL_MAGIC;
3191
3192
3193
3194
3195
3196
3197
3198
3199 if (wol->wolopts & WAKE_MAGIC) {
3200 vptr->wol_opts |= VELOCITY_WOL_MAGIC;
3201 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3202 }
3203 if (wol->wolopts & WAKE_UCAST) {
3204 vptr->wol_opts |= VELOCITY_WOL_UCAST;
3205 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3206 }
3207 if (wol->wolopts & WAKE_ARP) {
3208 vptr->wol_opts |= VELOCITY_WOL_ARP;
3209 vptr->flags |= VELOCITY_FLAGS_WOL_ENABLED;
3210 }
3211 memcpy(vptr->wol_passwd, wol->sopass, 6);
3212 return 0;
3213}
3214
3215static u32 velocity_get_msglevel(struct net_device *dev)
3216{
3217 return msglevel;
3218}
3219
3220static void velocity_set_msglevel(struct net_device *dev, u32 value)
3221{
3222 msglevel = value;
3223}
3224
3225static const struct ethtool_ops velocity_ethtool_ops = {
3226 .get_settings = velocity_get_settings,
3227 .set_settings = velocity_set_settings,
3228 .get_drvinfo = velocity_get_drvinfo,
3229 .get_wol = velocity_ethtool_get_wol,
3230 .set_wol = velocity_ethtool_set_wol,
3231 .get_msglevel = velocity_get_msglevel,
3232 .set_msglevel = velocity_set_msglevel,
3233 .get_link = velocity_get_link,
3234 .begin = velocity_ethtool_up,
3235 .complete = velocity_ethtool_down
3236};
3237
3238#ifdef CONFIG_PM
3239#ifdef CONFIG_INET
3240static int velocity_netdev_event(struct notifier_block *nb, unsigned long notification, void *ptr)
3241{
3242 struct in_ifaddr *ifa = (struct in_ifaddr *) ptr;
3243 struct net_device *dev = ifa->ifa_dev->dev;
3244 struct velocity_info *vptr;
3245 unsigned long flags;
3246
3247 if (dev_net(dev) != &init_net)
3248 return NOTIFY_DONE;
3249
3250 spin_lock_irqsave(&velocity_dev_list_lock, flags);
3251 list_for_each_entry(vptr, &velocity_dev_list, list) {
3252 if (vptr->dev == dev) {
3253 velocity_get_ip(vptr);
3254 break;
3255 }
3256 }
3257 spin_unlock_irqrestore(&velocity_dev_list_lock, flags);
3258
3259 return NOTIFY_DONE;
3260}
3261#endif
3262#endif
3263
3264#if defined(CONFIG_PM) && defined(CONFIG_INET)
3265static struct notifier_block velocity_inetaddr_notifier = {
3266 .notifier_call = velocity_netdev_event,
3267};
3268
3269static void velocity_register_notifier(void)
3270{
3271 register_inetaddr_notifier(&velocity_inetaddr_notifier);
3272}
3273
3274static void velocity_unregister_notifier(void)
3275{
3276 unregister_inetaddr_notifier(&velocity_inetaddr_notifier);
3277}
3278
3279#else
3280
3281#define velocity_register_notifier() do {} while (0)
3282#define velocity_unregister_notifier() do {} while (0)
3283
3284#endif
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294static int __init velocity_init_module(void)
3295{
3296 int ret;
3297
3298 velocity_register_notifier();
3299 ret = pci_register_driver(&velocity_driver);
3300 if (ret < 0)
3301 velocity_unregister_notifier();
3302 return ret;
3303}
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313static void __exit velocity_cleanup_module(void)
3314{
3315 velocity_unregister_notifier();
3316 pci_unregister_driver(&velocity_driver);
3317}
3318
3319module_init(velocity_init_module);
3320module_exit(velocity_cleanup_module);
3321