linux/drivers/net/vxge/vxge-config.h
<<
>>
Prefs
   1/******************************************************************************
   2 * This software may be used and distributed according to the terms of
   3 * the GNU General Public License (GPL), incorporated herein by reference.
   4 * Drivers based on or derived from this code fall under the GPL and must
   5 * retain the authorship, copyright and license notice.  This file is not
   6 * a complete program and may only be used when the entire operating
   7 * system is licensed under the GPL.
   8 * See the file COPYING in this distribution for more information.
   9 *
  10 * vxge-config.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O
  11 *                Virtualized Server Adapter.
  12 * Copyright(c) 2002-2009 Neterion Inc.
  13 ******************************************************************************/
  14#ifndef VXGE_CONFIG_H
  15#define VXGE_CONFIG_H
  16#include <linux/list.h>
  17
  18#ifndef VXGE_CACHE_LINE_SIZE
  19#define VXGE_CACHE_LINE_SIZE 128
  20#endif
  21
  22#define vxge_os_vaprintf(level, mask, fmt, ...) { \
  23        char buff[255]; \
  24                snprintf(buff, 255, fmt, __VA_ARGS__); \
  25                printk(buff); \
  26                printk("\n"); \
  27}
  28
  29#ifndef VXGE_ALIGN
  30#define VXGE_ALIGN(adrs, size) \
  31        (((size) - (((u64)adrs) & ((size)-1))) & ((size)-1))
  32#endif
  33
  34#define VXGE_HW_MIN_MTU                         68
  35#define VXGE_HW_MAX_MTU                         9600
  36#define VXGE_HW_DEFAULT_MTU                     1500
  37
  38#ifdef VXGE_DEBUG_ASSERT
  39
  40/**
  41 * vxge_assert
  42 * @test: C-condition to check
  43 * @fmt: printf like format string
  44 *
  45 * This function implements traditional assert. By default assertions
  46 * are enabled. It can be disabled by undefining VXGE_DEBUG_ASSERT macro in
  47 * compilation
  48 * time.
  49 */
  50#define vxge_assert(test) { \
  51        if (!(test)) \
  52                vxge_os_bug("bad cond: "#test" at %s:%d\n", \
  53                                __FILE__, __LINE__); }
  54#else
  55#define vxge_assert(test)
  56#endif /* end of VXGE_DEBUG_ASSERT */
  57
  58/**
  59 * enum enum vxge_debug_level
  60 * @VXGE_NONE: debug disabled
  61 * @VXGE_ERR: all errors going to be logged out
  62 * @VXGE_TRACE: all errors plus all kind of verbose tracing print outs
  63 *                 going to be logged out. Very noisy.
  64 *
  65 * This enumeration going to be used to switch between different
  66 * debug levels during runtime if DEBUG macro defined during
  67 * compilation. If DEBUG macro not defined than code will be
  68 * compiled out.
  69 */
  70enum vxge_debug_level {
  71        VXGE_NONE   = 0,
  72        VXGE_TRACE  = 1,
  73        VXGE_ERR    = 2
  74};
  75
  76#define NULL_VPID                                       0xFFFFFFFF
  77#ifdef CONFIG_VXGE_DEBUG_TRACE_ALL
  78#define VXGE_DEBUG_MODULE_MASK  0xffffffff
  79#define VXGE_DEBUG_TRACE_MASK   0xffffffff
  80#define VXGE_DEBUG_ERR_MASK     0xffffffff
  81#define VXGE_DEBUG_MASK         0x000001ff
  82#else
  83#define VXGE_DEBUG_MODULE_MASK  0x20000000
  84#define VXGE_DEBUG_TRACE_MASK   0x20000000
  85#define VXGE_DEBUG_ERR_MASK     0x20000000
  86#define VXGE_DEBUG_MASK         0x00000001
  87#endif
  88
  89/*
  90 * @VXGE_COMPONENT_LL: do debug for vxge link layer module
  91 * @VXGE_COMPONENT_ALL: activate debug for all modules with no exceptions
  92 *
  93 * This enumeration going to be used to distinguish modules
  94 * or libraries during compilation and runtime.  Makefile must declare
  95 * VXGE_DEBUG_MODULE_MASK macro and set it to proper value.
  96 */
  97#define VXGE_COMPONENT_LL                               0x20000000
  98#define VXGE_COMPONENT_ALL                              0xffffffff
  99
 100#define VXGE_HW_BASE_INF        100
 101#define VXGE_HW_BASE_ERR        200
 102#define VXGE_HW_BASE_BADCFG     300
 103
 104enum vxge_hw_status {
 105        VXGE_HW_OK                                = 0,
 106        VXGE_HW_FAIL                              = 1,
 107        VXGE_HW_PENDING                           = 2,
 108        VXGE_HW_COMPLETIONS_REMAIN                = 3,
 109
 110        VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS = VXGE_HW_BASE_INF + 1,
 111        VXGE_HW_INF_OUT_OF_DESCRIPTORS            = VXGE_HW_BASE_INF + 2,
 112
 113        VXGE_HW_ERR_INVALID_HANDLE                = VXGE_HW_BASE_ERR + 1,
 114        VXGE_HW_ERR_OUT_OF_MEMORY                 = VXGE_HW_BASE_ERR + 2,
 115        VXGE_HW_ERR_VPATH_NOT_AVAILABLE           = VXGE_HW_BASE_ERR + 3,
 116        VXGE_HW_ERR_VPATH_NOT_OPEN                = VXGE_HW_BASE_ERR + 4,
 117        VXGE_HW_ERR_WRONG_IRQ                     = VXGE_HW_BASE_ERR + 5,
 118        VXGE_HW_ERR_SWAPPER_CTRL                  = VXGE_HW_BASE_ERR + 6,
 119        VXGE_HW_ERR_INVALID_MTU_SIZE              = VXGE_HW_BASE_ERR + 7,
 120        VXGE_HW_ERR_INVALID_INDEX                 = VXGE_HW_BASE_ERR + 8,
 121        VXGE_HW_ERR_INVALID_TYPE                  = VXGE_HW_BASE_ERR + 9,
 122        VXGE_HW_ERR_INVALID_OFFSET                = VXGE_HW_BASE_ERR + 10,
 123        VXGE_HW_ERR_INVALID_DEVICE                = VXGE_HW_BASE_ERR + 11,
 124        VXGE_HW_ERR_VERSION_CONFLICT              = VXGE_HW_BASE_ERR + 12,
 125        VXGE_HW_ERR_INVALID_PCI_INFO              = VXGE_HW_BASE_ERR + 13,
 126        VXGE_HW_ERR_INVALID_TCODE                 = VXGE_HW_BASE_ERR + 14,
 127        VXGE_HW_ERR_INVALID_BLOCK_SIZE            = VXGE_HW_BASE_ERR + 15,
 128        VXGE_HW_ERR_INVALID_STATE                 = VXGE_HW_BASE_ERR + 16,
 129        VXGE_HW_ERR_PRIVILAGED_OPEARATION         = VXGE_HW_BASE_ERR + 17,
 130        VXGE_HW_ERR_INVALID_PORT                  = VXGE_HW_BASE_ERR + 18,
 131        VXGE_HW_ERR_FIFO                          = VXGE_HW_BASE_ERR + 19,
 132        VXGE_HW_ERR_VPATH                         = VXGE_HW_BASE_ERR + 20,
 133        VXGE_HW_ERR_CRITICAL                      = VXGE_HW_BASE_ERR + 21,
 134        VXGE_HW_ERR_SLOT_FREEZE                   = VXGE_HW_BASE_ERR + 22,
 135
 136        VXGE_HW_BADCFG_RING_INDICATE_MAX_PKTS     = VXGE_HW_BASE_BADCFG + 1,
 137        VXGE_HW_BADCFG_FIFO_BLOCKS                = VXGE_HW_BASE_BADCFG + 2,
 138        VXGE_HW_BADCFG_VPATH_MTU                  = VXGE_HW_BASE_BADCFG + 3,
 139        VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG   = VXGE_HW_BASE_BADCFG + 4,
 140        VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH        = VXGE_HW_BASE_BADCFG + 5,
 141        VXGE_HW_BADCFG_INTR_MODE                  = VXGE_HW_BASE_BADCFG + 6,
 142        VXGE_HW_BADCFG_RTS_MAC_EN                 = VXGE_HW_BASE_BADCFG + 7,
 143
 144        VXGE_HW_EOF_TRACE_BUF                     = -1
 145};
 146
 147/**
 148 * enum enum vxge_hw_device_link_state - Link state enumeration.
 149 * @VXGE_HW_LINK_NONE: Invalid link state.
 150 * @VXGE_HW_LINK_DOWN: Link is down.
 151 * @VXGE_HW_LINK_UP: Link is up.
 152 *
 153 */
 154enum vxge_hw_device_link_state {
 155        VXGE_HW_LINK_NONE,
 156        VXGE_HW_LINK_DOWN,
 157        VXGE_HW_LINK_UP
 158};
 159
 160/**
 161 * struct vxge_hw_device_date - Date Format
 162 * @day: Day
 163 * @month: Month
 164 * @year: Year
 165 * @date: Date in string format
 166 *
 167 * Structure for returning date
 168 */
 169
 170#define VXGE_HW_FW_STRLEN       32
 171struct vxge_hw_device_date {
 172        u32     day;
 173        u32     month;
 174        u32     year;
 175        char    date[VXGE_HW_FW_STRLEN];
 176};
 177
 178struct vxge_hw_device_version {
 179        u32     major;
 180        u32     minor;
 181        u32     build;
 182        char    version[VXGE_HW_FW_STRLEN];
 183};
 184
 185u64
 186__vxge_hw_vpath_pci_func_mode_get(
 187        u32 vp_id,
 188        struct vxge_hw_vpath_reg __iomem *vpath_reg);
 189
 190/**
 191 * struct vxge_hw_fifo_config - Configuration of fifo.
 192 * @enable: Is this fifo to be commissioned
 193 * @fifo_blocks: Numbers of TxDL (that is, lists of Tx descriptors)
 194 *              blocks per queue.
 195 * @max_frags: Max number of Tx buffers per TxDL (that is, per single
 196 *             transmit operation).
 197 *             No more than 256 transmit buffers can be specified.
 198 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
 199 *             bytes. Setting @memblock_size to page size ensures
 200 *             by-page allocation of descriptors. 128K bytes is the
 201 *             maximum supported block size.
 202 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data
 203 *             (e.g., to align on a cache line).
 204 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL.
 205 *             Use 0 otherwise.
 206 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
 207 *             which generally improves latency of the host bridge operation
 208 *             (see PCI specification). For valid values please refer
 209 *             to struct vxge_hw_fifo_config{} in the driver sources.
 210 * Configuration of all Titan fifos.
 211 * Note: Valid (min, max) range for each attribute is specified in the body of
 212 * the struct vxge_hw_fifo_config{} structure.
 213 */
 214struct vxge_hw_fifo_config {
 215        u32                             enable;
 216#define VXGE_HW_FIFO_ENABLE                             1
 217#define VXGE_HW_FIFO_DISABLE                            0
 218
 219        u32                             fifo_blocks;
 220#define VXGE_HW_MIN_FIFO_BLOCKS                         2
 221#define VXGE_HW_MAX_FIFO_BLOCKS                         128
 222
 223        u32                             max_frags;
 224#define VXGE_HW_MIN_FIFO_FRAGS                          1
 225#define VXGE_HW_MAX_FIFO_FRAGS                          256
 226
 227        u32                             memblock_size;
 228#define VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE                  VXGE_HW_BLOCK_SIZE
 229#define VXGE_HW_MAX_FIFO_MEMBLOCK_SIZE                  131072
 230#define VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE                  8096
 231
 232        u32                             alignment_size;
 233#define VXGE_HW_MIN_FIFO_ALIGNMENT_SIZE         0
 234#define VXGE_HW_MAX_FIFO_ALIGNMENT_SIZE         65536
 235#define VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE         VXGE_CACHE_LINE_SIZE
 236
 237        u32                             intr;
 238#define VXGE_HW_FIFO_QUEUE_INTR_ENABLE                  1
 239#define VXGE_HW_FIFO_QUEUE_INTR_DISABLE                 0
 240#define VXGE_HW_FIFO_QUEUE_INTR_DEFAULT                 0
 241
 242        u32                             no_snoop_bits;
 243#define VXGE_HW_FIFO_NO_SNOOP_DISABLED                  0
 244#define VXGE_HW_FIFO_NO_SNOOP_TXD                       1
 245#define VXGE_HW_FIFO_NO_SNOOP_FRM                       2
 246#define VXGE_HW_FIFO_NO_SNOOP_ALL                       3
 247#define VXGE_HW_FIFO_NO_SNOOP_DEFAULT                   0
 248
 249};
 250/**
 251 * struct vxge_hw_ring_config - Ring configurations.
 252 * @enable: Is this ring to be commissioned
 253 * @ring_blocks: Numbers of RxD blocks in the ring
 254 * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer
 255 *             to Titan User Guide.
 256 * @scatter_mode: Titan supports two receive scatter modes: A and B.
 257 *             For details please refer to Titan User Guide.
 258 * @rx_timer_val: The number of 32ns periods that would be counted between two
 259 *             timer interrupts.
 260 * @greedy_return: If Set it forces the device to return absolutely all RxD
 261 *             that are consumed and still on board when a timer interrupt
 262 *             triggers. If Clear, then if the device has already returned
 263 *             RxD before current timer interrupt trigerred and after the
 264 *             previous timer interrupt triggered, then the device is not
 265 *             forced to returned the rest of the consumed RxD that it has
 266 *             on board which account for a byte count less than the one
 267 *             programmed into PRC_CFG6.RXD_CRXDT field
 268 * @rx_timer_ci: TBD
 269 * @backoff_interval_us: Time (in microseconds), after which Titan
 270 *             tries to download RxDs posted by the host.
 271 *             Note that the "backoff" does not happen if host posts receive
 272 *             descriptors in the timely fashion.
 273 * Ring configuration.
 274 */
 275struct vxge_hw_ring_config {
 276        u32                             enable;
 277#define VXGE_HW_RING_ENABLE                                     1
 278#define VXGE_HW_RING_DISABLE                                    0
 279#define VXGE_HW_RING_DEFAULT                                    1
 280
 281        u32                             ring_blocks;
 282#define VXGE_HW_MIN_RING_BLOCKS                         1
 283#define VXGE_HW_MAX_RING_BLOCKS                         128
 284#define VXGE_HW_DEF_RING_BLOCKS                         2
 285
 286        u32                             buffer_mode;
 287#define VXGE_HW_RING_RXD_BUFFER_MODE_1                          1
 288#define VXGE_HW_RING_RXD_BUFFER_MODE_3                          3
 289#define VXGE_HW_RING_RXD_BUFFER_MODE_5                          5
 290#define VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT                    1
 291
 292        u32                             scatter_mode;
 293#define VXGE_HW_RING_SCATTER_MODE_A                             0
 294#define VXGE_HW_RING_SCATTER_MODE_B                             1
 295#define VXGE_HW_RING_SCATTER_MODE_C                             2
 296#define VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT             0xffffffff
 297
 298        u64                             rxds_limit;
 299#define VXGE_HW_DEF_RING_RXDS_LIMIT                             44
 300};
 301
 302/**
 303 * struct vxge_hw_vp_config - Configuration of virtual path
 304 * @vp_id: Virtual Path Id
 305 * @min_bandwidth: Minimum Guaranteed bandwidth
 306 * @ring: See struct vxge_hw_ring_config{}.
 307 * @fifo: See struct vxge_hw_fifo_config{}.
 308 * @tti: Configuration of interrupt associated with Transmit.
 309 *             see struct vxge_hw_tim_intr_config();
 310 * @rti: Configuration of interrupt associated with Receive.
 311 *              see struct vxge_hw_tim_intr_config();
 312 * @mtu: mtu size used on this port.
 313 * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to
 314 *             remove the VLAN tag from all received tagged frames that are not
 315 *             replicated at the internal L2 switch.
 316 *             0 - Do not strip the VLAN tag.
 317 *             1 - Strip the VLAN tag. Regardless of this setting, VLAN tags are
 318 *                 always placed into the RxDMA descriptor.
 319 *
 320 * This structure is used by the driver to pass the configuration parameters to
 321 * configure Virtual Path.
 322 */
 323struct vxge_hw_vp_config {
 324        u32                             vp_id;
 325
 326#define VXGE_HW_VPATH_PRIORITY_MIN                      0
 327#define VXGE_HW_VPATH_PRIORITY_MAX                      16
 328#define VXGE_HW_VPATH_PRIORITY_DEFAULT                  0
 329
 330        u32                             min_bandwidth;
 331#define VXGE_HW_VPATH_BANDWIDTH_MIN                     0
 332#define VXGE_HW_VPATH_BANDWIDTH_MAX                     100
 333#define VXGE_HW_VPATH_BANDWIDTH_DEFAULT                 0
 334
 335        struct vxge_hw_ring_config              ring;
 336        struct vxge_hw_fifo_config              fifo;
 337        struct vxge_hw_tim_intr_config  tti;
 338        struct vxge_hw_tim_intr_config  rti;
 339
 340        u32                             mtu;
 341#define VXGE_HW_VPATH_MIN_INITIAL_MTU                   VXGE_HW_MIN_MTU
 342#define VXGE_HW_VPATH_MAX_INITIAL_MTU                   VXGE_HW_MAX_MTU
 343#define VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU     0xffffffff
 344
 345        u32                             rpa_strip_vlan_tag;
 346#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE                 1
 347#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE                0
 348#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT      0xffffffff
 349
 350};
 351/**
 352 * struct vxge_hw_device_config - Device configuration.
 353 * @dma_blockpool_initial: Initial size of DMA Pool
 354 * @dma_blockpool_max: Maximum blocks in DMA pool
 355 * @intr_mode: Line, or MSI-X interrupt.
 356 *
 357 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table).
 358 * @rth_it_type: RTH IT table programming type
 359 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address
 360 * @vp_config: Configuration for virtual paths
 361 * @device_poll_millis: Specify the interval (in mulliseconds)
 362 *                      to wait for register reads
 363 *
 364 * Titan configuration.
 365 * Contains per-device configuration parameters, including:
 366 * - stats sampling interval, etc.
 367 *
 368 * In addition, struct vxge_hw_device_config{} includes "subordinate"
 369 * configurations, including:
 370 * - fifos and rings;
 371 * - MAC (done at firmware level).
 372 *
 373 * See Titan User Guide for more details.
 374 * Note: Valid (min, max) range for each attribute is specified in the body of
 375 * the struct vxge_hw_device_config{} structure. Please refer to the
 376 * corresponding include file.
 377 * See also: struct vxge_hw_tim_intr_config{}.
 378 */
 379struct vxge_hw_device_config {
 380        u32                             dma_blockpool_initial;
 381        u32                             dma_blockpool_max;
 382#define VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE                 0
 383#define VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE             0
 384#define VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE                4
 385#define VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE                 4096
 386
 387#define        VXGE_HW_MAX_PAYLOAD_SIZE_512             2
 388
 389        u32                             intr_mode;
 390#define VXGE_HW_INTR_MODE_IRQLINE                       0
 391#define VXGE_HW_INTR_MODE_MSIX                          1
 392#define VXGE_HW_INTR_MODE_MSIX_ONE_SHOT                 2
 393
 394#define VXGE_HW_INTR_MODE_DEF                           0
 395
 396        u32                             rth_en;
 397#define VXGE_HW_RTH_DISABLE                             0
 398#define VXGE_HW_RTH_ENABLE                              1
 399#define VXGE_HW_RTH_DEFAULT                             0
 400
 401        u32                             rth_it_type;
 402#define VXGE_HW_RTH_IT_TYPE_SOLO_IT                     0
 403#define VXGE_HW_RTH_IT_TYPE_MULTI_IT                    1
 404#define VXGE_HW_RTH_IT_TYPE_DEFAULT                     0
 405
 406        u32                             rts_mac_en;
 407#define VXGE_HW_RTS_MAC_DISABLE                 0
 408#define VXGE_HW_RTS_MAC_ENABLE                  1
 409#define VXGE_HW_RTS_MAC_DEFAULT                 0
 410
 411        struct vxge_hw_vp_config        vp_config[VXGE_HW_MAX_VIRTUAL_PATHS];
 412
 413        u32                             device_poll_millis;
 414#define VXGE_HW_MIN_DEVICE_POLL_MILLIS                  1
 415#define VXGE_HW_MAX_DEVICE_POLL_MILLIS                  100000
 416#define VXGE_HW_DEF_DEVICE_POLL_MILLIS                  1000
 417
 418};
 419
 420/**
 421 * function vxge_uld_link_up_f - Link-Up callback provided by driver.
 422 * @devh: HW device handle.
 423 * Link-up notification callback provided by the driver.
 424 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
 425 *
 426 * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_down_f{},
 427 * vxge_hw_driver_initialize().
 428 */
 429
 430/**
 431 * function vxge_uld_link_down_f - Link-Down callback provided by
 432 * driver.
 433 * @devh: HW device handle.
 434 *
 435 * Link-Down notification callback provided by the driver.
 436 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
 437 *
 438 * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{},
 439 * vxge_hw_driver_initialize().
 440 */
 441
 442/**
 443 * function vxge_uld_crit_err_f - Critical Error notification callback.
 444 * @devh: HW device handle.
 445 * (typically - at HW device iinitialization time).
 446 * @type: Enumerated hw error, e.g.: double ECC.
 447 * @serr_data: Titan status.
 448 * @ext_data: Extended data. The contents depends on the @type.
 449 *
 450 * Link-Down notification callback provided by the driver.
 451 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
 452 *
 453 * See also: struct vxge_hw_uld_cbs{}, enum vxge_hw_event{},
 454 * vxge_hw_driver_initialize().
 455 */
 456
 457/**
 458 * struct vxge_hw_uld_cbs - driver "slow-path" callbacks.
 459 * @link_up: See vxge_uld_link_up_f{}.
 460 * @link_down: See vxge_uld_link_down_f{}.
 461 * @crit_err: See vxge_uld_crit_err_f{}.
 462 *
 463 * Driver slow-path (per-driver) callbacks.
 464 * Implemented by driver and provided to HW via
 465 * vxge_hw_driver_initialize().
 466 * Note that these callbacks are not mandatory: HW will not invoke
 467 * a callback if NULL is specified.
 468 *
 469 * See also: vxge_hw_driver_initialize().
 470 */
 471struct vxge_hw_uld_cbs {
 472
 473        void (*link_up)(struct __vxge_hw_device *devh);
 474        void (*link_down)(struct __vxge_hw_device *devh);
 475        void (*crit_err)(struct __vxge_hw_device *devh,
 476                        enum vxge_hw_event type, u64 ext_data);
 477};
 478
 479/*
 480 * struct __vxge_hw_blockpool_entry - Block private data structure
 481 * @item: List header used to link.
 482 * @length: Length of the block
 483 * @memblock: Virtual address block
 484 * @dma_addr: DMA Address of the block.
 485 * @dma_handle: DMA handle of the block.
 486 * @acc_handle: DMA acc handle
 487 *
 488 * Block is allocated with a header to put the blocks into list.
 489 *
 490 */
 491struct __vxge_hw_blockpool_entry {
 492        struct list_head        item;
 493        u32                     length;
 494        void                    *memblock;
 495        dma_addr_t              dma_addr;
 496        struct pci_dev          *dma_handle;
 497        struct pci_dev          *acc_handle;
 498};
 499
 500/*
 501 * struct __vxge_hw_blockpool - Block Pool
 502 * @hldev: HW device
 503 * @block_size: size of each block.
 504 * @Pool_size: Number of blocks in the pool
 505 * @pool_max: Maximum number of blocks above which to free additional blocks
 506 * @req_out: Number of block requests with OS out standing
 507 * @free_block_list: List of free blocks
 508 *
 509 * Block pool contains the DMA blocks preallocated.
 510 *
 511 */
 512struct __vxge_hw_blockpool {
 513        struct __vxge_hw_device *hldev;
 514        u32                             block_size;
 515        u32                             pool_size;
 516        u32                             pool_max;
 517        u32                             req_out;
 518        struct list_head                free_block_list;
 519        struct list_head                free_entry_list;
 520};
 521
 522/*
 523 * enum enum __vxge_hw_channel_type - Enumerated channel types.
 524 * @VXGE_HW_CHANNEL_TYPE_UNKNOWN: Unknown channel.
 525 * @VXGE_HW_CHANNEL_TYPE_FIFO: fifo.
 526 * @VXGE_HW_CHANNEL_TYPE_RING: ring.
 527 * @VXGE_HW_CHANNEL_TYPE_MAX: Maximum number of HW-supported
 528 * (and recognized) channel types. Currently: 2.
 529 *
 530 * Enumerated channel types. Currently there are only two link-layer
 531 * channels - Titan fifo and Titan ring. In the future the list will grow.
 532 */
 533enum __vxge_hw_channel_type {
 534        VXGE_HW_CHANNEL_TYPE_UNKNOWN                    = 0,
 535        VXGE_HW_CHANNEL_TYPE_FIFO                       = 1,
 536        VXGE_HW_CHANNEL_TYPE_RING                       = 2,
 537        VXGE_HW_CHANNEL_TYPE_MAX                        = 3
 538};
 539
 540/*
 541 * struct __vxge_hw_channel
 542 * @item: List item; used to maintain a list of open channels.
 543 * @type: Channel type. See enum vxge_hw_channel_type{}.
 544 * @devh: Device handle. HW device object that contains _this_ channel.
 545 * @vph: Virtual path handle. Virtual Path Object that contains _this_ channel.
 546 * @length: Channel length. Currently allocated number of descriptors.
 547 *          The channel length "grows" when more descriptors get allocated.
 548 *          See _hw_mempool_grow.
 549 * @reserve_arr: Reserve array. Contains descriptors that can be reserved
 550 *               by driver for the subsequent send or receive operation.
 551 *               See vxge_hw_fifo_txdl_reserve(),
 552 *               vxge_hw_ring_rxd_reserve().
 553 * @reserve_ptr: Current pointer in the resrve array
 554 * @reserve_top: Reserve top gives the maximum number of dtrs available in
 555 *          reserve array.
 556 * @work_arr: Work array. Contains descriptors posted to the channel.
 557 *            Note that at any point in time @work_arr contains 3 types of
 558 *            descriptors:
 559 *            1) posted but not yet consumed by Titan device;
 560 *            2) consumed but not yet completed;
 561 *            3) completed but not yet freed
 562 *            (via vxge_hw_fifo_txdl_free() or vxge_hw_ring_rxd_free())
 563 * @post_index: Post index. At any point in time points on the
 564 *              position in the channel, which'll contain next to-be-posted
 565 *              descriptor.
 566 * @compl_index: Completion index. At any point in time points on the
 567 *               position in the channel, which will contain next
 568 *               to-be-completed descriptor.
 569 * @free_arr: Free array. Contains completed descriptors that were freed
 570 *            (i.e., handed over back to HW) by driver.
 571 *            See vxge_hw_fifo_txdl_free(), vxge_hw_ring_rxd_free().
 572 * @free_ptr: current pointer in free array
 573 * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize
 574 *                 to store per-operation control information.
 575 * @stats: Pointer to common statistics
 576 * @userdata: Per-channel opaque (void*) user-defined context, which may be
 577 *            driver object, ULP connection, etc.
 578 *            Once channel is open, @userdata is passed back to user via
 579 *            vxge_hw_channel_callback_f.
 580 *
 581 * HW channel object.
 582 *
 583 * See also: enum vxge_hw_channel_type{}, enum vxge_hw_channel_flag
 584 */
 585struct __vxge_hw_channel {
 586        struct list_head                item;
 587        enum __vxge_hw_channel_type     type;
 588        struct __vxge_hw_device         *devh;
 589        struct __vxge_hw_vpath_handle   *vph;
 590        u32                     length;
 591        u32                     vp_id;
 592        void            **reserve_arr;
 593        u32                     reserve_ptr;
 594        u32                     reserve_top;
 595        void            **work_arr;
 596        u32                     post_index ____cacheline_aligned;
 597        u32                     compl_index ____cacheline_aligned;
 598        void            **free_arr;
 599        u32                     free_ptr;
 600        void            **orig_arr;
 601        u32                     per_dtr_space;
 602        void            *userdata;
 603        struct vxge_hw_common_reg       __iomem *common_reg;
 604        u32                     first_vp_id;
 605        struct vxge_hw_vpath_stats_sw_common_info *stats;
 606
 607} ____cacheline_aligned;
 608
 609/*
 610 * struct __vxge_hw_virtualpath - Virtual Path
 611 *
 612 * @vp_id: Virtual path id
 613 * @vp_open: This flag specifies if vxge_hw_vp_open is called from LL Driver
 614 * @hldev: Hal device
 615 * @vp_config: Virtual Path Config
 616 * @vp_reg: VPATH Register map address in BAR0
 617 * @vpmgmt_reg: VPATH_MGMT register map address
 618 * @max_mtu: Max mtu that can be supported
 619 * @vsport_number: vsport attached to this vpath
 620 * @max_kdfc_db: Maximum kernel mode doorbells
 621 * @max_nofl_db: Maximum non offload doorbells
 622 * @tx_intr_num: Interrupt Number associated with the TX
 623
 624 * @ringh: Ring Queue
 625 * @fifoh: FIFO Queue
 626 * @vpath_handles: Virtual Path handles list
 627 * @stats_block: Memory for DMAing stats
 628 * @stats: Vpath statistics
 629 *
 630 * Virtual path structure to encapsulate the data related to a virtual path.
 631 * Virtual paths are allocated by the HW upon getting configuration from the
 632 * driver and inserted into the list of virtual paths.
 633 */
 634struct __vxge_hw_virtualpath {
 635        u32                             vp_id;
 636
 637        u32                             vp_open;
 638#define VXGE_HW_VP_NOT_OPEN     0
 639#define VXGE_HW_VP_OPEN         1
 640
 641        struct __vxge_hw_device         *hldev;
 642        struct vxge_hw_vp_config        *vp_config;
 643        struct vxge_hw_vpath_reg        __iomem *vp_reg;
 644        struct vxge_hw_vpmgmt_reg       __iomem *vpmgmt_reg;
 645        struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db;
 646
 647        u32                             max_mtu;
 648        u32                             vsport_number;
 649        u32                             max_kdfc_db;
 650        u32                             max_nofl_db;
 651
 652        struct __vxge_hw_ring *____cacheline_aligned ringh;
 653        struct __vxge_hw_fifo *____cacheline_aligned fifoh;
 654        struct list_head                vpath_handles;
 655        struct __vxge_hw_blockpool_entry                *stats_block;
 656        struct vxge_hw_vpath_stats_hw_info      *hw_stats;
 657        struct vxge_hw_vpath_stats_hw_info      *hw_stats_sav;
 658        struct vxge_hw_vpath_stats_sw_info      *sw_stats;
 659};
 660
 661/*
 662 * struct __vxge_hw_vpath_handle - List item to store callback information
 663 * @item: List head to keep the item in linked list
 664 * @vpath: Virtual path to which this item belongs
 665 *
 666 * This structure is used to store the callback information.
 667 */
 668struct __vxge_hw_vpath_handle{
 669        struct list_head        item;
 670        struct __vxge_hw_virtualpath    *vpath;
 671};
 672
 673/*
 674 * struct __vxge_hw_device
 675 *
 676 * HW device object.
 677 */
 678/**
 679 * struct __vxge_hw_device  - Hal device object
 680 * @magic: Magic Number
 681 * @device_id: PCI Device Id of the adapter
 682 * @major_revision: PCI Device major revision
 683 * @minor_revision: PCI Device minor revision
 684 * @bar0: BAR0 virtual address.
 685 * @pdev: Physical device handle
 686 * @config: Confguration passed by the LL driver at initialization
 687 * @link_state: Link state
 688 *
 689 * HW device object. Represents Titan adapter
 690 */
 691struct __vxge_hw_device {
 692        u32                             magic;
 693#define VXGE_HW_DEVICE_MAGIC            0x12345678
 694#define VXGE_HW_DEVICE_DEAD             0xDEADDEAD
 695        u16                             device_id;
 696        u8                              major_revision;
 697        u8                              minor_revision;
 698        void __iomem                    *bar0;
 699        struct pci_dev                  *pdev;
 700        struct net_device               *ndev;
 701        struct vxge_hw_device_config    config;
 702        enum vxge_hw_device_link_state  link_state;
 703
 704        struct vxge_hw_uld_cbs          uld_callbacks;
 705
 706        u32                             host_type;
 707        u32                             func_id;
 708        u32                             access_rights;
 709#define VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH      0x1
 710#define VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM     0x2
 711#define VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM     0x4
 712        struct vxge_hw_legacy_reg       __iomem *legacy_reg;
 713        struct vxge_hw_toc_reg          __iomem *toc_reg;
 714        struct vxge_hw_common_reg       __iomem *common_reg;
 715        struct vxge_hw_mrpcim_reg       __iomem *mrpcim_reg;
 716        struct vxge_hw_srpcim_reg       __iomem *srpcim_reg \
 717                                        [VXGE_HW_TITAN_SRPCIM_REG_SPACES];
 718        struct vxge_hw_vpmgmt_reg       __iomem *vpmgmt_reg \
 719                                        [VXGE_HW_TITAN_VPMGMT_REG_SPACES];
 720        struct vxge_hw_vpath_reg        __iomem *vpath_reg \
 721                                        [VXGE_HW_TITAN_VPATH_REG_SPACES];
 722        u8                              __iomem *kdfc;
 723        u8                              __iomem *usdc;
 724        struct __vxge_hw_virtualpath    virtual_paths \
 725                                        [VXGE_HW_MAX_VIRTUAL_PATHS];
 726        u64                             vpath_assignments;
 727        u64                             vpaths_deployed;
 728        u32                             first_vp_id;
 729        u64                             tim_int_mask0[4];
 730        u32                             tim_int_mask1[4];
 731
 732        struct __vxge_hw_blockpool      block_pool;
 733        struct vxge_hw_device_stats     stats;
 734        u32                             debug_module_mask;
 735        u32                             debug_level;
 736        u32                             level_err;
 737        u32                             level_trace;
 738};
 739
 740#define VXGE_HW_INFO_LEN        64
 741/**
 742 * struct vxge_hw_device_hw_info - Device information
 743 * @host_type: Host Type
 744 * @func_id: Function Id
 745 * @vpath_mask: vpath bit mask
 746 * @fw_version: Firmware version
 747 * @fw_date: Firmware Date
 748 * @flash_version: Firmware version
 749 * @flash_date: Firmware Date
 750 * @mac_addrs: Mac addresses for each vpath
 751 * @mac_addr_masks: Mac address masks for each vpath
 752 *
 753 * Returns the vpath mask that has the bits set for each vpath allocated
 754 * for the driver and the first mac address for each vpath
 755 */
 756struct vxge_hw_device_hw_info {
 757        u32             host_type;
 758#define VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION                     0
 759#define VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION                      1
 760#define VXGE_HW_NO_MR_SR_VH0_FUNCTION0                          2
 761#define VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION                   3
 762#define VXGE_HW_MR_SR_VH0_INVALID_CONFIG                        4
 763#define VXGE_HW_SR_VH_FUNCTION0                                 5
 764#define VXGE_HW_SR_VH_VIRTUAL_FUNCTION                          6
 765#define VXGE_HW_VH_NORMAL_FUNCTION                              7
 766        u64             function_mode;
 767#define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION                    0
 768#define VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION                   1
 769#define VXGE_HW_FUNCTION_MODE_SRIOV                             2
 770#define VXGE_HW_FUNCTION_MODE_MRIOV                             3
 771        u32             func_id;
 772        u64             vpath_mask;
 773        struct vxge_hw_device_version fw_version;
 774        struct vxge_hw_device_date    fw_date;
 775        struct vxge_hw_device_version flash_version;
 776        struct vxge_hw_device_date    flash_date;
 777        u8              serial_number[VXGE_HW_INFO_LEN];
 778        u8              part_number[VXGE_HW_INFO_LEN];
 779        u8              product_desc[VXGE_HW_INFO_LEN];
 780        u8 (mac_addrs)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
 781        u8 (mac_addr_masks)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
 782};
 783
 784/**
 785 * struct vxge_hw_device_attr - Device memory spaces.
 786 * @bar0: BAR0 virtual address.
 787 * @pdev: PCI device object.
 788 *
 789 * Device memory spaces. Includes configuration, BAR0 etc. per device
 790 * mapped memories. Also, includes a pointer to OS-specific PCI device object.
 791 */
 792struct vxge_hw_device_attr {
 793        void __iomem            *bar0;
 794        struct pci_dev          *pdev;
 795        struct vxge_hw_uld_cbs  uld_callbacks;
 796};
 797
 798#define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls)        (hldev->link_state = ls)
 799
 800#define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i) {    \
 801        if (i < 16) {                           \
 802                m0[0] |= vxge_vBIT(0x8, (i*4), 4);      \
 803                m0[1] |= vxge_vBIT(0x4, (i*4), 4);      \
 804        }                                       \
 805        else {                                  \
 806                m1[0] = 0x80000000;             \
 807                m1[1] = 0x40000000;             \
 808        }                                       \
 809}
 810
 811#define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i) {  \
 812        if (i < 16) {                                   \
 813                m0[0] &= ~vxge_vBIT(0x8, (i*4), 4);             \
 814                m0[1] &= ~vxge_vBIT(0x4, (i*4), 4);             \
 815        }                                               \
 816        else {                                          \
 817                m1[0] = 0;                              \
 818                m1[1] = 0;                              \
 819        }                                               \
 820}
 821
 822#define VXGE_HW_DEVICE_STATS_PIO_READ(loc, offset) {            \
 823        status = vxge_hw_mrpcim_stats_access(hldev, \
 824                                VXGE_HW_STATS_OP_READ, \
 825                                loc, \
 826                                offset, \
 827                                &val64);                        \
 828                                                                \
 829        if (status != VXGE_HW_OK)                               \
 830                return status;                                          \
 831}
 832
 833#define VXGE_HW_VPATH_STATS_PIO_READ(offset) {                          \
 834        status = __vxge_hw_vpath_stats_access(vpath, \
 835                        VXGE_HW_STATS_OP_READ, \
 836                        offset, \
 837                        &val64);                                        \
 838        if (status != VXGE_HW_OK)                                       \
 839                return status;                                          \
 840}
 841
 842/*
 843 * struct __vxge_hw_ring - Ring channel.
 844 * @channel: Channel "base" of this ring, the common part of all HW
 845 *           channels.
 846 * @mempool: Memory pool, the pool from which descriptors get allocated.
 847 *           (See vxge_hw_mm.h).
 848 * @config: Ring configuration, part of device configuration
 849 *          (see struct vxge_hw_device_config{}).
 850 * @ring_length: Length of the ring
 851 * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
 852 *          as per Titan User Guide.
 853 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Titan spec,
 854 *            1-buffer mode descriptor is 32 byte long, etc.
 855 * @rxd_priv_size: Per RxD size reserved (by HW) for driver to keep
 856 *                 per-descriptor data (e.g., DMA handle for Solaris)
 857 * @per_rxd_space: Per rxd space requested by driver
 858 * @rxds_per_block: Number of descriptors per hardware-defined RxD
 859 *                  block. Depends on the (1-, 3-, 5-) buffer mode.
 860 * @rxdblock_priv_size: Reserved at the end of each RxD block. HW internal
 861 *                      usage. Not to confuse with @rxd_priv_size.
 862 * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
 863 * @callback: Channel completion callback. HW invokes the callback when there
 864 *            are new completions on that channel. In many implementations
 865 *            the @callback executes in the hw interrupt context.
 866 * @rxd_init: Channel's descriptor-initialize callback.
 867 *            See vxge_hw_ring_rxd_init_f{}.
 868 *            If not NULL, HW invokes the callback when opening
 869 *            the ring.
 870 * @rxd_term: Channel's descriptor-terminate callback. If not NULL,
 871 *          HW invokes the callback when closing the corresponding channel.
 872 *          See also vxge_hw_channel_rxd_term_f{}.
 873 * @stats: Statistics for ring
 874 * Ring channel.
 875 *
 876 * Note: The structure is cache line aligned to better utilize
 877 *       CPU cache performance.
 878 */
 879struct __vxge_hw_ring {
 880        struct __vxge_hw_channel                channel;
 881        struct vxge_hw_mempool                  *mempool;
 882        struct vxge_hw_vpath_reg                __iomem *vp_reg;
 883        struct vxge_hw_common_reg               __iomem *common_reg;
 884        u32                                     ring_length;
 885        u32                                     buffer_mode;
 886        u32                                     rxd_size;
 887        u32                                     rxd_priv_size;
 888        u32                                     per_rxd_space;
 889        u32                                     rxds_per_block;
 890        u32                                     rxdblock_priv_size;
 891        u32                                     cmpl_cnt;
 892        u32                                     vp_id;
 893        u32                                     doorbell_cnt;
 894        u32                                     total_db_cnt;
 895        u64                                     rxds_limit;
 896
 897        enum vxge_hw_status (*callback)(
 898                        struct __vxge_hw_ring *ringh,
 899                        void *rxdh,
 900                        u8 t_code,
 901                        void *userdata);
 902
 903        enum vxge_hw_status (*rxd_init)(
 904                        void *rxdh,
 905                        void *userdata);
 906
 907        void (*rxd_term)(
 908                        void *rxdh,
 909                        enum vxge_hw_rxd_state state,
 910                        void *userdata);
 911
 912        struct vxge_hw_vpath_stats_sw_ring_info *stats  ____cacheline_aligned;
 913        struct vxge_hw_ring_config              *config;
 914} ____cacheline_aligned;
 915
 916/**
 917 * enum enum vxge_hw_txdl_state - Descriptor (TXDL) state.
 918 * @VXGE_HW_TXDL_STATE_NONE: Invalid state.
 919 * @VXGE_HW_TXDL_STATE_AVAIL: Descriptor is available for reservation.
 920 * @VXGE_HW_TXDL_STATE_POSTED: Descriptor is posted for processing by the
 921 * device.
 922 * @VXGE_HW_TXDL_STATE_FREED: Descriptor is free and can be reused for
 923 * filling-in and posting later.
 924 *
 925 * Titan/HW descriptor states.
 926 *
 927 */
 928enum vxge_hw_txdl_state {
 929        VXGE_HW_TXDL_STATE_NONE = 0,
 930        VXGE_HW_TXDL_STATE_AVAIL        = 1,
 931        VXGE_HW_TXDL_STATE_POSTED       = 2,
 932        VXGE_HW_TXDL_STATE_FREED        = 3
 933};
 934/*
 935 * struct __vxge_hw_fifo - Fifo.
 936 * @channel: Channel "base" of this fifo, the common part of all HW
 937 *             channels.
 938 * @mempool: Memory pool, from which descriptors get allocated.
 939 * @config: Fifo configuration, part of device configuration
 940 *             (see struct vxge_hw_device_config{}).
 941 * @interrupt_type: Interrupt type to be used
 942 * @no_snoop_bits: See struct vxge_hw_fifo_config{}.
 943 * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
 944 *             on TxDL please refer to Titan UG.
 945 * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
 946 *             per-TxDL HW private space (struct __vxge_hw_fifo_txdl_priv).
 947 * @priv_size: Per-Tx descriptor space reserved for driver
 948 *             usage.
 949 * @per_txdl_space: Per txdl private space for the driver
 950 * @callback: Fifo completion callback. HW invokes the callback when there
 951 *             are new completions on that fifo. In many implementations
 952 *             the @callback executes in the hw interrupt context.
 953 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
 954 *             HW invokes the callback when closing the corresponding fifo.
 955 *             See also vxge_hw_fifo_txdl_term_f{}.
 956 * @stats: Statistics of this fifo
 957 *
 958 * Fifo channel.
 959 * Note: The structure is cache line aligned.
 960 */
 961struct __vxge_hw_fifo {
 962        struct __vxge_hw_channel                channel;
 963        struct vxge_hw_mempool                  *mempool;
 964        struct vxge_hw_fifo_config              *config;
 965        struct vxge_hw_vpath_reg                __iomem *vp_reg;
 966        struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db;
 967        u64                                     interrupt_type;
 968        u32                                     no_snoop_bits;
 969        u32                                     txdl_per_memblock;
 970        u32                                     txdl_size;
 971        u32                                     priv_size;
 972        u32                                     per_txdl_space;
 973        u32                                     vp_id;
 974        u32                                     tx_intr_num;
 975
 976        enum vxge_hw_status (*callback)(
 977                        struct __vxge_hw_fifo *fifo_handle,
 978                        void *txdlh,
 979                        enum vxge_hw_fifo_tcode t_code,
 980                        void *userdata,
 981                        struct sk_buff ***skb_ptr,
 982                        int nr_skb,
 983                        int *more);
 984
 985        void (*txdl_term)(
 986                        void *txdlh,
 987                        enum vxge_hw_txdl_state state,
 988                        void *userdata);
 989
 990        struct vxge_hw_vpath_stats_sw_fifo_info *stats ____cacheline_aligned;
 991} ____cacheline_aligned;
 992
 993/*
 994 * struct __vxge_hw_fifo_txdl_priv - Transmit descriptor HW-private data.
 995 * @dma_addr: DMA (mapped) address of _this_ descriptor.
 996 * @dma_handle: DMA handle used to map the descriptor onto device.
 997 * @dma_offset: Descriptor's offset in the memory block. HW allocates
 998 *       descriptors in memory blocks (see struct vxge_hw_fifo_config{})
 999 *             Each memblock is a contiguous block of DMA-able memory.
1000 * @frags: Total number of fragments (that is, contiguous data buffers)
1001 * carried by this TxDL.
1002 * @align_vaddr_start: Aligned virtual address start
1003 * @align_vaddr: Virtual address of the per-TxDL area in memory used for
1004 *             alignement. Used to place one or more mis-aligned fragments
1005 * @align_dma_addr: DMA address translated from the @align_vaddr.
1006 * @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
1007 * @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
1008 * @align_dma_offset: The current offset into the @align_vaddr area.
1009 * Grows while filling the descriptor, gets reset.
1010 * @align_used_frags: Number of fragments used.
1011 * @alloc_frags: Total number of fragments allocated.
1012 * @unused: TODO
1013 * @next_txdl_priv: (TODO).
1014 * @first_txdp: (TODO).
1015 * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
1016 *             TxDL list.
1017 * @txdlh: Corresponding txdlh to this TxDL.
1018 * @memblock: Pointer to the TxDL memory block or memory page.
1019 *             on the next send operation.
1020 * @dma_object: DMA address and handle of the memory block that contains
1021 *             the descriptor. This member is used only in the "checked"
1022 *             version of the HW (to enforce certain assertions);
1023 *             otherwise it gets compiled out.
1024 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
1025 *
1026 * Per-transmit decsriptor HW-private data. HW uses the space to keep DMA
1027 * information associated with the descriptor. Note that driver can ask HW
1028 * to allocate additional per-descriptor space for its own (driver-specific)
1029 * purposes.
1030 *
1031 * See also: struct vxge_hw_ring_rxd_priv{}.
1032 */
1033struct __vxge_hw_fifo_txdl_priv {
1034        dma_addr_t              dma_addr;
1035        struct pci_dev  *dma_handle;
1036        ptrdiff_t               dma_offset;
1037        u32                             frags;
1038        u8                              *align_vaddr_start;
1039        u8                              *align_vaddr;
1040        dma_addr_t              align_dma_addr;
1041        struct pci_dev  *align_dma_handle;
1042        struct pci_dev  *align_dma_acch;
1043        ptrdiff_t               align_dma_offset;
1044        u32                             align_used_frags;
1045        u32                             alloc_frags;
1046        u32                             unused;
1047        struct __vxge_hw_fifo_txdl_priv *next_txdl_priv;
1048        struct vxge_hw_fifo_txd         *first_txdp;
1049        void                    *memblock;
1050};
1051
1052/*
1053 * struct __vxge_hw_non_offload_db_wrapper - Non-offload Doorbell Wrapper
1054 * @control_0: Bits 0 to 7 - Doorbell type.
1055 *             Bits 8 to 31 - Reserved.
1056 *             Bits 32 to 39 - The highest TxD in this TxDL.
1057 *             Bits 40 to 47 - Reserved.
1058        *              Bits 48 to 55 - Reserved.
1059 *             Bits 56 to 63 - No snoop flags.
1060 * @txdl_ptr:  The starting location of the TxDL in host memory.
1061 *
1062 * Created by the host and written to the adapter via PIO to a Kernel Doorbell
1063 * FIFO. All non-offload doorbell wrapper fields must be written by the host as
1064 * part of a doorbell write. Consumed by the adapter but is not written by the
1065 * adapter.
1066 */
1067struct __vxge_hw_non_offload_db_wrapper {
1068        u64             control_0;
1069#define VXGE_HW_NODBW_GET_TYPE(ctrl0)                   vxge_bVALn(ctrl0, 0, 8)
1070#define VXGE_HW_NODBW_TYPE(val) vxge_vBIT(val, 0, 8)
1071#define VXGE_HW_NODBW_TYPE_NODBW                                0
1072
1073#define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0)        vxge_bVALn(ctrl0, 32, 8)
1074#define VXGE_HW_NODBW_LAST_TXD_NUMBER(val) vxge_vBIT(val, 32, 8)
1075
1076#define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0)               vxge_bVALn(ctrl0, 56, 8)
1077#define VXGE_HW_NODBW_LIST_NO_SNOOP(val) vxge_vBIT(val, 56, 8)
1078#define VXGE_HW_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE         0x2
1079#define VXGE_HW_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ          0x1
1080
1081        u64             txdl_ptr;
1082};
1083
1084/*
1085 * TX Descriptor
1086 */
1087
1088/**
1089 * struct vxge_hw_fifo_txd - Transmit Descriptor
1090 * @control_0: Bits 0 to 6 - Reserved.
1091 *             Bit 7 - List Ownership. This field should be initialized
1092 *             to '1' by the driver before the transmit list pointer is
1093 *             written to the adapter. This field will be set to '0' by the
1094 *             adapter once it has completed transmitting the frame or frames in
1095 *             the list. Note - This field is only valid in TxD0. Additionally,
1096 *             for multi-list sequences, the driver should not release any
1097 *             buffers until the ownership of the last list in the multi-list
1098 *             sequence has been returned to the host.
1099 *             Bits 8 to 11 - Reserved
1100 *             Bits 12 to 15 - Transfer_Code. This field is only valid in
1101 *             TxD0. It is used to describe the status of the transmit data
1102 *             buffer transfer. This field is always overwritten by the
1103 *             adapter, so this field may be initialized to any value.
1104 *             Bits 16 to 17 - Host steering. This field allows the host to
1105 *             override the selection of the physical transmit port.
1106 *             Attention:
1107 *             Normal sounds as if learned from the switch rather than from
1108 *             the aggregation algorythms.
1109 *             00: Normal. Use Destination/MAC Address
1110 *             lookup to determine the transmit port.
1111 *             01: Send on physical Port1.
1112 *             10: Send on physical Port0.
1113        *              11: Send on both ports.
1114 *             Bits 18 to 21 - Reserved
1115 *             Bits 22 to 23 - Gather_Code. This field is set by the host and
1116 *             is used to describe how individual buffers comprise a frame.
1117 *             10: First descriptor of a frame.
1118 *             00: Middle of a multi-descriptor frame.
1119 *             01: Last descriptor of a frame.
1120 *             11: First and last descriptor of a frame (the entire frame
1121 *             resides in a single buffer).
1122 *             For multi-descriptor frames, the only valid gather code sequence
1123 *             is {10, [00], 01}. In other words, the descriptors must be placed
1124 *             in the list in the correct order.
1125 *             Bits 24 to 27 - Reserved
1126 *             Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation
1127 *             definition. Only valid in TxD0. This field allows the host to
1128 *             indicate the Ethernet encapsulation of an outbound LSO packet.
1129 *             00 - classic mode (best guess)
1130 *             01 - LLC
1131 *             10 - SNAP
1132 *             11 - DIX
1133 *             If "classic mode" is selected, the adapter will attempt to
1134 *             decode the frame's Ethernet encapsulation by examining the L/T
1135 *             field as follows:
1136 *             <= 0x05DC LLC/SNAP encoding; must examine DSAP/SSAP to determine
1137 *             if packet is IPv4 or IPv6.
1138 *             0x8870 Jumbo-SNAP encoding.
1139 *             0x0800 IPv4 DIX encoding
1140 *             0x86DD IPv6 DIX encoding
1141 *             others illegal encapsulation
1142 *             Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag.
1143 *             Set to 1 to perform segmentation offload for TCP/UDP.
1144 *             This field is valid only in TxD0.
1145 *             Bits 31 to 33 - Reserved.
1146 *             Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size
1147 *             This field is meaningful only when LSO_Control is non-zero.
1148 *             When LSO_Control is set to TCP_LSO, the single (possibly large)
1149 *             TCP segment described by this TxDL will be sent as a series of
1150 *             TCP segments each of which contains no more than LSO_MSS
1151 *             payload bytes.
1152 *             When LSO_Control is set to UDP_LSO, the single (possibly large)
1153 *             UDP datagram described by this TxDL will be sent as a series of
1154 *             UDP datagrams each of which contains no more than LSO_MSS
1155 *             payload bytes.
1156 *             All outgoing frames from this TxDL will have LSO_MSS bytes of UDP
1157 *             or TCP payload, with the exception of the last, which will have
1158 *             <= LSO_MSS bytes of payload.
1159 *             Bits 48 to 63 - Buffer_Size. Number of valid bytes in the
1160 *             buffer to be read by the adapter. This field is written by the
1161 *             host. A value of 0 is illegal.
1162 *             Bits 32 to 63 - This value is written by the adapter upon
1163 *             completion of a UDP or TCP LSO operation and indicates the number
1164 *             of UDP or TCP payload bytes that were transmitted. 0x0000 will be
1165 *             returned for any non-LSO operation.
1166 * @control_1: Bits 0 to 4 - Reserved.
1167 *             Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum
1168 *             offload. This field is only valid in the first TxD of a frame.
1169 *             Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload.
1170 *             This field is only valid in the first TxD of a frame (the TxD's
1171 *             gather code must be 10 or 11). The driver should only set this
1172 *             bit if it can guarantee that TCP is present.
1173 *             Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload.
1174 *             This field is only valid in the first TxD of a frame (the TxD's
1175 *             gather code must be 10 or 11). The driver should only set this
1176 *             bit if it can guarantee that UDP is present.
1177 *             Bits 8 to 14 - Reserved.
1178 *             Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to
1179 *             instruct the adapter to insert the VLAN tag specified by the
1180 *             Tx_VLAN_Tag field. This field is only valid in the first TxD of
1181 *             a frame.
1182 *             Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag
1183 *             to be inserted into the frame by the adapter (the first two bytes
1184 *             of a VLAN tag are always 0x8100). This field is only valid if the
1185 *             Tx_VLAN_Enable field is set to '1'.
1186 *             Bits 32 to 33 - Reserved.
1187 *             Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt
1188 *             number the frame associated with. This field is written by the
1189 *             host. It is only valid in the first TxD of a frame.
1190 *             Bits 40 to 42 - Reserved.
1191 *             Bit 43 - Set to 1 to exclude the frame from bandwidth metering
1192 *             functions. This field is valid only in the first TxD
1193 *             of a frame.
1194 *             Bits 44 to 45 - Reserved.
1195 *             Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to
1196 *             generate an interrupt as soon as all of the frames in the list
1197 *             have been transmitted. In order to have per-frame interrupts,
1198 *             the driver should place a maximum of one frame per list. This
1199 *             field is only valid in the first TxD of a frame.
1200 *             Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter
1201 *             to count the frame toward the utilization interrupt specified in
1202 *             the Tx_Int_Number field. This field is only valid in the first
1203 *             TxD of a frame.
1204 *             Bits 48 to 63 - Reserved.
1205 * @buffer_pointer: Buffer start address.
1206 * @host_control: Host_Control.Opaque 64bit data stored by driver inside the
1207 *            Titan descriptor prior to posting the latter on the fifo
1208 *            via vxge_hw_fifo_txdl_post().The %host_control is returned as is
1209 *            to the driver with each completed descriptor.
1210 *
1211 * Transmit descriptor (TxD).Fifo descriptor contains configured number
1212 * (list) of TxDs. * For more details please refer to Titan User Guide,
1213 * Section 5.4.2 "Transmit Descriptor (TxD) Format".
1214 */
1215struct vxge_hw_fifo_txd {
1216        u64 control_0;
1217#define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER               vxge_mBIT(7)
1218
1219#define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0)              vxge_bVALn(ctrl0, 12, 4)
1220#define VXGE_HW_FIFO_TXD_T_CODE(val)                    vxge_vBIT(val, 12, 4)
1221#define VXGE_HW_FIFO_TXD_T_CODE_UNUSED          VXGE_HW_FIFO_T_CODE_UNUSED
1222
1223
1224#define VXGE_HW_FIFO_TXD_GATHER_CODE(val)               vxge_vBIT(val, 22, 2)
1225#define VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST      VXGE_HW_FIFO_GATHER_CODE_FIRST
1226#define VXGE_HW_FIFO_TXD_GATHER_CODE_LAST       VXGE_HW_FIFO_GATHER_CODE_LAST
1227
1228
1229#define VXGE_HW_FIFO_TXD_LSO_EN                         vxge_mBIT(30)
1230
1231#define VXGE_HW_FIFO_TXD_LSO_MSS(val)                   vxge_vBIT(val, 34, 14)
1232
1233#define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val)               vxge_vBIT(val, 48, 16)
1234
1235        u64 control_1;
1236#define VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN                 vxge_mBIT(5)
1237#define VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN                  vxge_mBIT(6)
1238#define VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN                  vxge_mBIT(7)
1239#define VXGE_HW_FIFO_TXD_VLAN_ENABLE                    vxge_mBIT(15)
1240
1241#define VXGE_HW_FIFO_TXD_VLAN_TAG(val)                  vxge_vBIT(val, 16, 16)
1242
1243#define VXGE_HW_FIFO_TXD_INT_NUMBER(val)                vxge_vBIT(val, 34, 6)
1244
1245#define VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST              vxge_mBIT(46)
1246#define VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ                 vxge_mBIT(47)
1247
1248        u64 buffer_pointer;
1249
1250        u64 host_control;
1251};
1252
1253/**
1254 * struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring
1255 * @host_control: This field is exclusively for host use and is "readonly"
1256 *             from the adapter's perspective.
1257 * @control_0:Bits 0 to 6 - RTH_Bucket get
1258 *            Bit 7 - Own Descriptor ownership bit. This bit is set to 1
1259 *            by the host, and is set to 0 by the adapter.
1260 *            0 - Host owns RxD and buffer.
1261 *            1 - The adapter owns RxD and buffer.
1262 *            Bit 8 - Fast_Path_Eligible When set, indicates that the
1263 *            received frame meets all of the criteria for fast path processing.
1264 *            The required criteria are as follows:
1265 *            !SYN &
1266 *            (Transfer_Code == "Transfer OK") &
1267 *            (!Is_IP_Fragment) &
1268 *            ((Is_IPv4 & computed_L3_checksum == 0xFFFF) |
1269 *            (Is_IPv6)) &
1270 *            ((Is_TCP & computed_L4_checksum == 0xFFFF) |
1271 *            (Is_UDP & (computed_L4_checksum == 0xFFFF |
1272 *            computed _L4_checksum == 0x0000)))
1273 *            (same meaning for all RxD buffer modes)
1274 *            Bit 9 - L3 Checksum Correct
1275 *            Bit 10 - L4 Checksum Correct
1276 *            Bit 11 - Reserved
1277 *            Bit 12 to 15 - This field is written by the adapter. It is
1278 *            used to report the status of the frame transfer to the host.
1279 *            0x0 - Transfer OK
1280 *            0x4 - RDA Failure During Transfer
1281 *            0x5 - Unparseable Packet, such as unknown IPv6 header.
1282 *            0x6 - Frame integrity error (FCS or ECC).
1283 *            0x7 - Buffer Size Error. The provided buffer(s) were not
1284 *                  appropriately sized and data loss occurred.
1285 *            0x8 - Internal ECC Error. RxD corrupted.
1286 *            0x9 - IPv4 Checksum error
1287 *            0xA - TCP/UDP Checksum error
1288 *            0xF - Unknown Error or Multiple Error. Indicates an
1289 *               unknown problem or that more than one of transfer codes is set.
1290 *            Bit 16 - SYN The adapter sets this field to indicate that
1291 *                the incoming frame contained a TCP segment with its SYN bit
1292 *                set and its ACK bit NOT set. (same meaning for all RxD buffer
1293 *                modes)
1294 *            Bit 17 - Is ICMP
1295 *            Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the
1296 *                Socket Pair Direct Match Table and the frame was steered based
1297 *                on SPDM.
1298 *            Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the
1299 *            Indirection Table and the frame was steered based on hash
1300 *            indirection.
1301 *            Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash
1302 *                type) that was used to calculate the hash.
1303 *            Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN
1304 *                tagged.
1305 *            Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation
1306 *                of the received frame.
1307 *            0x0 - Ethernet DIX
1308 *            0x1 - LLC
1309 *            0x2 - SNAP (includes Jumbo-SNAP)
1310 *            0x3 - IPX
1311 *            Bit 27 - IS_IPV4 Set to '1' if the frame contains an IPv4 packet.
1312 *            Bit 28 - IS_IPV6 Set to '1' if the frame contains an IPv6 packet.
1313 *            Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a fragmented
1314 *            IP packet.
1315 *            Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment.
1316 *            Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message.
1317 *            Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value  that
1318 *            arrived with the frame. If the resulting computed IPv4 header
1319 *            checksum for the frame did not produce the expected 0xFFFF value,
1320 *            then the transfer code would be set to 0x9.
1321 *            Bit 48 to 63 - L4_Checksum[0:15] The TCP/UDP checksum value that
1322 *            arrived with the frame. If the resulting computed TCP/UDP checksum
1323 *            for the frame did not produce the expected 0xFFFF value, then the
1324 *            transfer code would be set to 0xA.
1325 * @control_1:Bits 0 to 1 - Reserved
1326 *            Bits 2 to 15 - Buffer0_Size.This field is set by the host and
1327 *            eventually overwritten by the adapter. The host writes the
1328 *            available buffer size in bytes when it passes the descriptor to
1329 *            the adapter. When a frame is delivered the host, the adapter
1330 *            populates this field with the number of bytes written into the
1331 *            buffer. The largest supported buffer is 16, 383 bytes.
1332 *            Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid if
1333 *            RTH_HASH_TYPE (Control_0, bits 20:23) is nonzero.
1334 *            Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable portion
1335 *            of the VLAN tag, if one was detected by the adapter. This field is
1336 *            populated even if VLAN-tag stripping is enabled.
1337 * @buffer0_ptr: Pointer to buffer. This field is populated by the driver.
1338 *
1339 * One buffer mode RxD for ring structure
1340 */
1341struct vxge_hw_ring_rxd_1 {
1342        u64 host_control;
1343        u64 control_0;
1344#define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0)          vxge_bVALn(ctrl0, 0, 7)
1345
1346#define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER               vxge_mBIT(7)
1347
1348#define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0)  vxge_bVALn(ctrl0, 8, 1)
1349
1350#define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0)    vxge_bVALn(ctrl0, 9, 1)
1351
1352#define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0)    vxge_bVALn(ctrl0, 10, 1)
1353
1354#define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0)              vxge_bVALn(ctrl0, 12, 4)
1355#define VXGE_HW_RING_RXD_T_CODE(val)                    vxge_vBIT(val, 12, 4)
1356
1357#define VXGE_HW_RING_RXD_T_CODE_UNUSED          VXGE_HW_RING_T_CODE_UNUSED
1358
1359#define VXGE_HW_RING_RXD_SYN_GET(ctrl0)         vxge_bVALn(ctrl0, 16, 1)
1360
1361#define VXGE_HW_RING_RXD_IS_ICMP_GET(ctrl0)             vxge_bVALn(ctrl0, 17, 1)
1362
1363#define VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(ctrl0)        vxge_bVALn(ctrl0, 18, 1)
1364
1365#define VXGE_HW_RING_RXD_RTH_IT_HIT_GET(ctrl0)          vxge_bVALn(ctrl0, 19, 1)
1366
1367#define VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(ctrl0)       vxge_bVALn(ctrl0, 20, 4)
1368
1369#define VXGE_HW_RING_RXD_IS_VLAN_GET(ctrl0)             vxge_bVALn(ctrl0, 24, 1)
1370
1371#define VXGE_HW_RING_RXD_ETHER_ENCAP_GET(ctrl0)         vxge_bVALn(ctrl0, 25, 2)
1372
1373#define VXGE_HW_RING_RXD_FRAME_PROTO_GET(ctrl0)         vxge_bVALn(ctrl0, 27, 5)
1374
1375#define VXGE_HW_RING_RXD_L3_CKSUM_GET(ctrl0)    vxge_bVALn(ctrl0, 32, 16)
1376
1377#define VXGE_HW_RING_RXD_L4_CKSUM_GET(ctrl0)    vxge_bVALn(ctrl0, 48, 16)
1378
1379        u64 control_1;
1380
1381#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1)      vxge_bVALn(ctrl1, 2, 14)
1382#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val) vxge_vBIT(val, 2, 14)
1383#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK            vxge_vBIT(0x3FFF, 2, 14)
1384
1385#define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1)    vxge_bVALn(ctrl1, 16, 32)
1386
1387#define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1)    vxge_bVALn(ctrl1, 48, 16)
1388
1389        u64 buffer0_ptr;
1390};
1391
1392enum vxge_hw_rth_algoritms {
1393        RTH_ALG_JENKINS = 0,
1394        RTH_ALG_MS_RSS  = 1,
1395        RTH_ALG_CRC32C  = 2
1396};
1397
1398/**
1399 * struct vxge_hw_rth_hash_types - RTH hash types.
1400 * @hash_type_tcpipv4_en: Enables RTH field type HashTypeTcpIPv4
1401 * @hash_type_ipv4_en: Enables RTH field type HashTypeIPv4
1402 * @hash_type_tcpipv6_en: Enables RTH field type HashTypeTcpIPv6
1403 * @hash_type_ipv6_en: Enables RTH field type HashTypeIPv6
1404 * @hash_type_tcpipv6ex_en: Enables RTH field type HashTypeTcpIPv6Ex
1405 * @hash_type_ipv6ex_en: Enables RTH field type HashTypeIPv6Ex
1406 *
1407 * Used to pass RTH hash types to rts_rts_set.
1408 *
1409 * See also: vxge_hw_vpath_rts_rth_set(), vxge_hw_vpath_rts_rth_get().
1410 */
1411struct vxge_hw_rth_hash_types {
1412        u8 hash_type_tcpipv4_en;
1413        u8 hash_type_ipv4_en;
1414        u8 hash_type_tcpipv6_en;
1415        u8 hash_type_ipv6_en;
1416        u8 hash_type_tcpipv6ex_en;
1417        u8 hash_type_ipv6ex_en;
1418};
1419
1420u32
1421vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh);
1422
1423void vxge_hw_device_debug_set(
1424        struct __vxge_hw_device *devh,
1425        enum vxge_debug_level level,
1426        u32 mask);
1427
1428u32
1429vxge_hw_device_error_level_get(struct __vxge_hw_device *devh);
1430
1431u32
1432vxge_hw_device_trace_level_get(struct __vxge_hw_device *devh);
1433
1434u32
1435vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh);
1436
1437/**
1438 * vxge_hw_ring_rxd_size_get    - Get the size of ring descriptor.
1439 * @buf_mode: Buffer mode (1, 3 or 5)
1440 *
1441 * This function returns the size of RxD for given buffer mode
1442 */
1443static inline u32 vxge_hw_ring_rxd_size_get(u32 buf_mode)
1444{
1445        return sizeof(struct vxge_hw_ring_rxd_1);
1446}
1447
1448/**
1449 * vxge_hw_ring_rxds_per_block_get - Get the number of rxds per block.
1450 * @buf_mode: Buffer mode (1 buffer mode only)
1451 *
1452 * This function returns the number of RxD for RxD block for given buffer mode
1453 */
1454static inline u32 vxge_hw_ring_rxds_per_block_get(u32 buf_mode)
1455{
1456        return (u32)((VXGE_HW_BLOCK_SIZE-16) /
1457                sizeof(struct vxge_hw_ring_rxd_1));
1458}
1459
1460/**
1461 * vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor.
1462 * @rxdh: Descriptor handle.
1463 * @dma_pointer: DMA address of a single receive buffer this descriptor
1464 * should carry. Note that by the time vxge_hw_ring_rxd_1b_set is called,
1465 * the receive buffer should be already mapped to the device
1466 * @size: Size of the receive @dma_pointer buffer.
1467 *
1468 * Prepare 1-buffer-mode Rx     descriptor for posting
1469 * (via vxge_hw_ring_rxd_post()).
1470 *
1471 * This inline helper-function does not return any parameters and always
1472 * succeeds.
1473 *
1474 */
1475static inline
1476void vxge_hw_ring_rxd_1b_set(
1477        void *rxdh,
1478        dma_addr_t dma_pointer,
1479        u32 size)
1480{
1481        struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1482        rxdp->buffer0_ptr = dma_pointer;
1483        rxdp->control_1 &= ~VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK;
1484        rxdp->control_1 |= VXGE_HW_RING_RXD_1_BUFFER0_SIZE(size);
1485}
1486
1487/**
1488 * vxge_hw_ring_rxd_1b_get - Get data from the completed 1-buf
1489 * descriptor.
1490 * @vpath_handle: Virtual Path handle.
1491 * @rxdh: Descriptor handle.
1492 * @dma_pointer: DMA address of a single receive buffer this descriptor
1493 * carries. Returned by HW.
1494 * @pkt_length: Length (in bytes) of the data in the buffer pointed by
1495 *
1496 * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor.
1497 * This inline helper-function uses completed descriptor to populate receive
1498 * buffer pointer and other "out" parameters. The function always succeeds.
1499 *
1500 */
1501static inline
1502void vxge_hw_ring_rxd_1b_get(
1503        struct __vxge_hw_ring *ring_handle,
1504        void *rxdh,
1505        u32 *pkt_length)
1506{
1507        struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1508
1509        *pkt_length =
1510                (u32)VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1);
1511}
1512
1513/**
1514 * vxge_hw_ring_rxd_1b_info_get - Get extended information associated with
1515 * a completed receive descriptor for 1b mode.
1516 * @vpath_handle: Virtual Path handle.
1517 * @rxdh: Descriptor handle.
1518 * @rxd_info: Descriptor information
1519 *
1520 * Retrieve extended information associated with a completed receive descriptor.
1521 *
1522 */
1523static inline
1524void vxge_hw_ring_rxd_1b_info_get(
1525        struct __vxge_hw_ring *ring_handle,
1526        void *rxdh,
1527        struct vxge_hw_ring_rxd_info *rxd_info)
1528{
1529
1530        struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1531        rxd_info->syn_flag =
1532                (u32)VXGE_HW_RING_RXD_SYN_GET(rxdp->control_0);
1533        rxd_info->is_icmp =
1534                (u32)VXGE_HW_RING_RXD_IS_ICMP_GET(rxdp->control_0);
1535        rxd_info->fast_path_eligible =
1536                (u32)VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0);
1537        rxd_info->l3_cksum_valid =
1538                (u32)VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0);
1539        rxd_info->l3_cksum =
1540                (u32)VXGE_HW_RING_RXD_L3_CKSUM_GET(rxdp->control_0);
1541        rxd_info->l4_cksum_valid =
1542                (u32)VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0);
1543        rxd_info->l4_cksum =
1544                (u32)VXGE_HW_RING_RXD_L4_CKSUM_GET(rxdp->control_0);
1545        rxd_info->frame =
1546                (u32)VXGE_HW_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0);
1547        rxd_info->proto =
1548                (u32)VXGE_HW_RING_RXD_FRAME_PROTO_GET(rxdp->control_0);
1549        rxd_info->is_vlan =
1550                (u32)VXGE_HW_RING_RXD_IS_VLAN_GET(rxdp->control_0);
1551        rxd_info->vlan =
1552                (u32)VXGE_HW_RING_RXD_VLAN_TAG_GET(rxdp->control_1);
1553        rxd_info->rth_bucket =
1554                (u32)VXGE_HW_RING_RXD_RTH_BUCKET_GET(rxdp->control_0);
1555        rxd_info->rth_it_hit =
1556                (u32)VXGE_HW_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0);
1557        rxd_info->rth_spdm_hit =
1558                (u32)VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0);
1559        rxd_info->rth_hash_type =
1560                (u32)VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0);
1561        rxd_info->rth_value =
1562                (u32)VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1);
1563}
1564
1565/**
1566 * vxge_hw_ring_rxd_private_get - Get driver private per-descriptor data
1567 *                      of 1b mode 3b mode ring.
1568 * @rxdh: Descriptor handle.
1569 *
1570 * Returns: private driver      info associated with the descriptor.
1571 * driver requests      per-descriptor space via vxge_hw_ring_attr.
1572 *
1573 */
1574static inline void *vxge_hw_ring_rxd_private_get(void *rxdh)
1575{
1576        struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1577        return (void *)(size_t)rxdp->host_control;
1578}
1579
1580/**
1581 * vxge_hw_fifo_txdl_cksum_set_bits - Offload checksum.
1582 * @txdlh: Descriptor handle.
1583 * @cksum_bits: Specifies which checksums are to be offloaded: IPv4,
1584 *              and/or TCP and/or UDP.
1585 *
1586 * Ask Titan to calculate IPv4 & transport checksums for _this_ transmit
1587 * descriptor.
1588 * This API is part of the preparation of the transmit descriptor for posting
1589 * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include
1590 * vxge_hw_fifo_txdl_mss_set(), vxge_hw_fifo_txdl_buffer_set_aligned(),
1591 * and vxge_hw_fifo_txdl_buffer_set().
1592 * All these APIs fill in the fields of the fifo descriptor,
1593 * in accordance with the Titan specification.
1594 *
1595 */
1596static inline void vxge_hw_fifo_txdl_cksum_set_bits(void *txdlh, u64 cksum_bits)
1597{
1598        struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh;
1599        txdp->control_1 |= cksum_bits;
1600}
1601
1602/**
1603 * vxge_hw_fifo_txdl_mss_set - Set MSS.
1604 * @txdlh: Descriptor handle.
1605 * @mss: MSS size for _this_ TCP connection. Passed by TCP stack down to the
1606 *       driver, which in turn inserts the MSS into the @txdlh.
1607 *
1608 * This API is part of the preparation of the transmit descriptor for posting
1609 * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include
1610 * vxge_hw_fifo_txdl_buffer_set(), vxge_hw_fifo_txdl_buffer_set_aligned(),
1611 * and vxge_hw_fifo_txdl_cksum_set_bits().
1612 * All these APIs fill in the fields of the fifo descriptor,
1613 * in accordance with the Titan specification.
1614 *
1615 */
1616static inline void vxge_hw_fifo_txdl_mss_set(void *txdlh, int mss)
1617{
1618        struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh;
1619
1620        txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_EN;
1621        txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_MSS(mss);
1622}
1623
1624/**
1625 * vxge_hw_fifo_txdl_vlan_set - Set VLAN tag.
1626 * @txdlh: Descriptor handle.
1627 * @vlan_tag: 16bit VLAN tag.
1628 *
1629 * Insert VLAN tag into specified transmit descriptor.
1630 * The actual insertion of the tag into outgoing frame is done by the hardware.
1631 */
1632static inline void vxge_hw_fifo_txdl_vlan_set(void *txdlh, u16 vlan_tag)
1633{
1634        struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh;
1635
1636        txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_ENABLE;
1637        txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_TAG(vlan_tag);
1638}
1639
1640/**
1641 * vxge_hw_fifo_txdl_private_get - Retrieve per-descriptor private data.
1642 * @txdlh: Descriptor handle.
1643 *
1644 * Retrieve per-descriptor private data.
1645 * Note that driver requests per-descriptor space via
1646 * struct vxge_hw_fifo_attr passed to
1647 * vxge_hw_vpath_open().
1648 *
1649 * Returns: private driver data associated with the descriptor.
1650 */
1651static inline void *vxge_hw_fifo_txdl_private_get(void *txdlh)
1652{
1653        struct vxge_hw_fifo_txd *txdp  = (struct vxge_hw_fifo_txd *)txdlh;
1654
1655        return (void *)(size_t)txdp->host_control;
1656}
1657
1658/**
1659 * struct vxge_hw_ring_attr - Ring open "template".
1660 * @callback: Ring completion callback. HW invokes the callback when there
1661 *            are new completions on that ring. In many implementations
1662 *            the @callback executes in the hw interrupt context.
1663 * @rxd_init: Ring's descriptor-initialize callback.
1664 *            See vxge_hw_ring_rxd_init_f{}.
1665 *            If not NULL, HW invokes the callback when opening
1666 *            the ring.
1667 * @rxd_term: Ring's descriptor-terminate callback. If not NULL,
1668 *          HW invokes the callback when closing the corresponding ring.
1669 *          See also vxge_hw_ring_rxd_term_f{}.
1670 * @userdata: User-defined "context" of _that_ ring. Passed back to the
1671 *            user as one of the @callback, @rxd_init, and @rxd_term arguments.
1672 * @per_rxd_space: If specified (i.e., greater than zero): extra space
1673 *              reserved by HW per each receive descriptor.
1674 *              Can be used to store
1675 *              and retrieve on completion, information specific
1676 *              to the driver.
1677 *
1678 * Ring open "template". User fills the structure with ring
1679 * attributes and passes it to vxge_hw_vpath_open().
1680 */
1681struct vxge_hw_ring_attr {
1682        enum vxge_hw_status (*callback)(
1683                        struct __vxge_hw_ring *ringh,
1684                        void *rxdh,
1685                        u8 t_code,
1686                        void *userdata);
1687
1688        enum vxge_hw_status (*rxd_init)(
1689                        void *rxdh,
1690                        void *userdata);
1691
1692        void (*rxd_term)(
1693                        void *rxdh,
1694                        enum vxge_hw_rxd_state state,
1695                        void *userdata);
1696
1697        void            *userdata;
1698        u32             per_rxd_space;
1699};
1700
1701/**
1702 * function vxge_hw_fifo_callback_f - FIFO callback.
1703 * @vpath_handle: Virtual path whose Fifo "containing" 1 or more completed
1704 *             descriptors.
1705 * @txdlh: First completed descriptor.
1706 * @txdl_priv: Pointer to per txdl space allocated
1707 * @t_code: Transfer code, as per Titan User Guide.
1708 *          Returned by HW.
1709 * @host_control: Opaque 64bit data stored by driver inside the Titan
1710 *            descriptor prior to posting the latter on the fifo
1711 *            via vxge_hw_fifo_txdl_post(). The @host_control is returned
1712 *            as is to the driver with each completed descriptor.
1713 * @userdata: Opaque per-fifo data specified at fifo open
1714 *            time, via vxge_hw_vpath_open().
1715 *
1716 * Fifo completion callback (type declaration). A single per-fifo
1717 * callback is specified at fifo open time, via
1718 * vxge_hw_vpath_open(). Typically gets called as part of the processing
1719 * of the Interrupt Service Routine.
1720 *
1721 * Fifo callback gets called by HW if, and only if, there is at least
1722 * one new completion on a given fifo. Upon processing the first @txdlh driver
1723 * is _supposed_ to continue consuming completions using:
1724 *    - vxge_hw_fifo_txdl_next_completed()
1725 *
1726 * Note that failure to process new completions in a timely fashion
1727 * leads to VXGE_HW_INF_OUT_OF_DESCRIPTORS condition.
1728 *
1729 * Non-zero @t_code means failure to process transmit descriptor.
1730 *
1731 * In the "transmit" case the failure could happen, for instance, when the
1732 * link is down, in which case Titan completes the descriptor because it
1733 * is not able to send the data out.
1734 *
1735 * For details please refer to Titan User Guide.
1736 *
1737 * See also: vxge_hw_fifo_txdl_next_completed(), vxge_hw_fifo_txdl_term_f{}.
1738 */
1739/**
1740 * function vxge_hw_fifo_txdl_term_f - Terminate descriptor callback.
1741 * @txdlh: First completed descriptor.
1742 * @txdl_priv: Pointer to per txdl space allocated
1743 * @state: One of the enum vxge_hw_txdl_state{} enumerated states.
1744 * @userdata: Per-fifo user data (a.k.a. context) specified at
1745 * fifo open time, via vxge_hw_vpath_open().
1746 *
1747 * Terminate descriptor callback. Unless NULL is specified in the
1748 * struct vxge_hw_fifo_attr{} structure passed to vxge_hw_vpath_open()),
1749 * HW invokes the callback as part of closing fifo, prior to
1750 * de-allocating the ring and associated data structures
1751 * (including descriptors).
1752 * driver should utilize the callback to (for instance) unmap
1753 * and free DMA data buffers associated with the posted (state =
1754 * VXGE_HW_TXDL_STATE_POSTED) descriptors,
1755 * as well as other relevant cleanup functions.
1756 *
1757 * See also: struct vxge_hw_fifo_attr{}
1758 */
1759/**
1760 * struct vxge_hw_fifo_attr - Fifo open "template".
1761 * @callback: Fifo completion callback. HW invokes the callback when there
1762 *            are new completions on that fifo. In many implementations
1763 *            the @callback executes in the hw interrupt context.
1764 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
1765 *          HW invokes the callback when closing the corresponding fifo.
1766 *          See also vxge_hw_fifo_txdl_term_f{}.
1767 * @userdata: User-defined "context" of _that_ fifo. Passed back to the
1768 *            user as one of the @callback, and @txdl_term arguments.
1769 * @per_txdl_space: If specified (i.e., greater than zero): extra space
1770 *              reserved by HW per each transmit descriptor. Can be used to
1771 *              store, and retrieve on completion, information specific
1772 *              to the driver.
1773 *
1774 * Fifo open "template". User fills the structure with fifo
1775 * attributes and passes it to vxge_hw_vpath_open().
1776 */
1777struct vxge_hw_fifo_attr {
1778
1779        enum vxge_hw_status (*callback)(
1780                        struct __vxge_hw_fifo *fifo_handle,
1781                        void *txdlh,
1782                        enum vxge_hw_fifo_tcode t_code,
1783                        void *userdata,
1784                        struct sk_buff ***skb_ptr,
1785                        int nr_skb, int *more);
1786
1787        void (*txdl_term)(
1788                        void *txdlh,
1789                        enum vxge_hw_txdl_state state,
1790                        void *userdata);
1791
1792        void            *userdata;
1793        u32             per_txdl_space;
1794};
1795
1796/**
1797 * struct vxge_hw_vpath_attr - Attributes of virtual path
1798 * @vp_id: Identifier of Virtual Path
1799 * @ring_attr: Attributes of ring for non-offload receive
1800 * @fifo_attr: Attributes of fifo for non-offload transmit
1801 *
1802 * Attributes of virtual path.  This structure is passed as parameter
1803 * to the vxge_hw_vpath_open() routine to set the attributes of ring and fifo.
1804 */
1805struct vxge_hw_vpath_attr {
1806        u32                             vp_id;
1807        struct vxge_hw_ring_attr        ring_attr;
1808        struct vxge_hw_fifo_attr        fifo_attr;
1809};
1810
1811enum vxge_hw_status
1812__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1813                        struct __vxge_hw_blockpool  *blockpool,
1814                        u32 pool_size,
1815                        u32 pool_max);
1816
1817void
1818__vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool  *blockpool);
1819
1820struct __vxge_hw_blockpool_entry *
1821__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *hldev,
1822                        u32 size);
1823
1824void
1825__vxge_hw_blockpool_block_free(struct __vxge_hw_device *hldev,
1826                        struct __vxge_hw_blockpool_entry *entry);
1827
1828void *
1829__vxge_hw_blockpool_malloc(struct __vxge_hw_device *hldev,
1830                        u32 size,
1831                        struct vxge_hw_mempool_dma *dma_object);
1832
1833void
1834__vxge_hw_blockpool_free(struct __vxge_hw_device *hldev,
1835                        void *memblock,
1836                        u32 size,
1837                        struct vxge_hw_mempool_dma *dma_object);
1838
1839enum vxge_hw_status
1840__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config);
1841
1842enum vxge_hw_status
1843__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config);
1844
1845enum vxge_hw_status
1846vxge_hw_mgmt_device_config(struct __vxge_hw_device *devh,
1847                struct vxge_hw_device_config    *dev_config, int size);
1848
1849enum vxge_hw_status __devinit vxge_hw_device_hw_info_get(
1850        void __iomem *bar0,
1851        struct vxge_hw_device_hw_info *hw_info);
1852
1853enum vxge_hw_status
1854__vxge_hw_vpath_fw_ver_get(
1855        u32     vp_id,
1856        struct vxge_hw_vpath_reg __iomem *vpath_reg,
1857        struct vxge_hw_device_hw_info *hw_info);
1858
1859enum vxge_hw_status
1860__vxge_hw_vpath_card_info_get(
1861        u32 vp_id,
1862        struct vxge_hw_vpath_reg __iomem *vpath_reg,
1863        struct vxge_hw_device_hw_info *hw_info);
1864
1865enum vxge_hw_status __devinit vxge_hw_device_config_default_get(
1866        struct vxge_hw_device_config *device_config);
1867
1868/**
1869 * vxge_hw_device_link_state_get - Get link state.
1870 * @devh: HW device handle.
1871 *
1872 * Get link state.
1873 * Returns: link state.
1874 */
1875static inline
1876enum vxge_hw_device_link_state vxge_hw_device_link_state_get(
1877        struct __vxge_hw_device *devh)
1878{
1879        return devh->link_state;
1880}
1881
1882void vxge_hw_device_terminate(struct __vxge_hw_device *devh);
1883
1884const u8 *
1885vxge_hw_device_serial_number_get(struct __vxge_hw_device *devh);
1886
1887u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *devh);
1888
1889const u8 *
1890vxge_hw_device_product_name_get(struct __vxge_hw_device *devh);
1891
1892enum vxge_hw_status __devinit vxge_hw_device_initialize(
1893        struct __vxge_hw_device **devh,
1894        struct vxge_hw_device_attr *attr,
1895        struct vxge_hw_device_config *device_config);
1896
1897enum vxge_hw_status vxge_hw_device_getpause_data(
1898         struct __vxge_hw_device *devh,
1899         u32 port,
1900         u32 *tx,
1901         u32 *rx);
1902
1903enum vxge_hw_status vxge_hw_device_setpause_data(
1904        struct __vxge_hw_device *devh,
1905        u32 port,
1906        u32 tx,
1907        u32 rx);
1908
1909static inline void *vxge_os_dma_malloc(struct pci_dev *pdev,
1910                        unsigned long size,
1911                        struct pci_dev **p_dmah,
1912                        struct pci_dev **p_dma_acch)
1913{
1914        gfp_t flags;
1915        void *vaddr;
1916        unsigned long misaligned = 0;
1917        *p_dma_acch = *p_dmah = NULL;
1918
1919        if (in_interrupt())
1920                flags = GFP_ATOMIC | GFP_DMA;
1921        else
1922                flags = GFP_KERNEL | GFP_DMA;
1923
1924        size += VXGE_CACHE_LINE_SIZE;
1925
1926        vaddr = kmalloc((size), flags);
1927        if (vaddr == NULL)
1928                return vaddr;
1929        misaligned = (unsigned long)VXGE_ALIGN(*((u64 *)&vaddr),
1930                                VXGE_CACHE_LINE_SIZE);
1931        *(unsigned long *)p_dma_acch = misaligned;
1932        vaddr = (void *)((u8 *)vaddr + misaligned);
1933        return vaddr;
1934}
1935
1936extern void vxge_hw_blockpool_block_add(
1937                        struct __vxge_hw_device *devh,
1938                        void *block_addr,
1939                        u32 length,
1940                        struct pci_dev *dma_h,
1941                        struct pci_dev *acc_handle);
1942
1943static inline void vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh,
1944                                        unsigned long size)
1945{
1946        gfp_t flags;
1947        void *vaddr;
1948
1949        if (in_interrupt())
1950                flags = GFP_ATOMIC | GFP_DMA;
1951        else
1952                flags = GFP_KERNEL | GFP_DMA;
1953
1954        vaddr = kmalloc((size), flags);
1955
1956        vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
1957}
1958
1959static inline void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr,
1960                        struct pci_dev **p_dma_acch)
1961{
1962        unsigned long misaligned = *(unsigned long *)p_dma_acch;
1963        u8 *tmp = (u8 *)vaddr;
1964        tmp -= misaligned;
1965        kfree((void *)tmp);
1966}
1967
1968/*
1969 * __vxge_hw_mempool_item_priv - will return pointer on per item private space
1970 */
1971static inline void*
1972__vxge_hw_mempool_item_priv(
1973        struct vxge_hw_mempool *mempool,
1974        u32 memblock_idx,
1975        void *item,
1976        u32 *memblock_item_idx)
1977{
1978        ptrdiff_t offset;
1979        void *memblock = mempool->memblocks_arr[memblock_idx];
1980
1981
1982        offset = (u32)((u8 *)item - (u8 *)memblock);
1983        vxge_assert(offset >= 0 && (u32)offset < mempool->memblock_size);
1984
1985        (*memblock_item_idx) = (u32) offset / mempool->item_size;
1986        vxge_assert((*memblock_item_idx) < mempool->items_per_memblock);
1987
1988        return (u8 *)mempool->memblocks_priv_arr[memblock_idx] +
1989                            (*memblock_item_idx) * mempool->items_priv_size;
1990}
1991
1992enum vxge_hw_status
1993__vxge_hw_mempool_grow(
1994        struct vxge_hw_mempool *mempool,
1995        u32 num_allocate,
1996        u32 *num_allocated);
1997
1998struct vxge_hw_mempool*
1999__vxge_hw_mempool_create(
2000        struct __vxge_hw_device *devh,
2001        u32 memblock_size,
2002        u32 item_size,
2003        u32 private_size,
2004        u32 items_initial,
2005        u32 items_max,
2006        struct vxge_hw_mempool_cbs *mp_callback,
2007        void *userdata);
2008
2009struct __vxge_hw_channel*
2010__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2011                        enum __vxge_hw_channel_type type, u32 length,
2012                        u32 per_dtr_space, void *userdata);
2013
2014void
2015__vxge_hw_channel_free(
2016        struct __vxge_hw_channel *channel);
2017
2018enum vxge_hw_status
2019__vxge_hw_channel_initialize(
2020        struct __vxge_hw_channel *channel);
2021
2022enum vxge_hw_status
2023__vxge_hw_channel_reset(
2024        struct __vxge_hw_channel *channel);
2025
2026/*
2027 * __vxge_hw_fifo_txdl_priv - Return the max fragments allocated
2028 * for the fifo.
2029 * @fifo: Fifo
2030 * @txdp: Poniter to a TxD
2031 */
2032static inline struct __vxge_hw_fifo_txdl_priv *
2033__vxge_hw_fifo_txdl_priv(
2034        struct __vxge_hw_fifo *fifo,
2035        struct vxge_hw_fifo_txd *txdp)
2036{
2037        return (struct __vxge_hw_fifo_txdl_priv *)
2038                        (((char *)((ulong)txdp->host_control)) +
2039                                fifo->per_txdl_space);
2040}
2041
2042enum vxge_hw_status vxge_hw_vpath_open(
2043        struct __vxge_hw_device *devh,
2044        struct vxge_hw_vpath_attr *attr,
2045        struct __vxge_hw_vpath_handle **vpath_handle);
2046
2047enum vxge_hw_status
2048__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog);
2049
2050enum vxge_hw_status vxge_hw_vpath_close(
2051        struct __vxge_hw_vpath_handle *vpath_handle);
2052
2053enum vxge_hw_status
2054vxge_hw_vpath_reset(
2055        struct __vxge_hw_vpath_handle *vpath_handle);
2056
2057enum vxge_hw_status
2058vxge_hw_vpath_recover_from_reset(
2059        struct __vxge_hw_vpath_handle *vpath_handle);
2060
2061void
2062vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp);
2063
2064enum vxge_hw_status
2065vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ringh);
2066
2067enum vxge_hw_status vxge_hw_vpath_mtu_set(
2068        struct __vxge_hw_vpath_handle *vpath_handle,
2069        u32 new_mtu);
2070
2071enum vxge_hw_status vxge_hw_vpath_stats_enable(
2072        struct __vxge_hw_vpath_handle *vpath_handle);
2073
2074enum vxge_hw_status
2075__vxge_hw_vpath_stats_access(
2076        struct __vxge_hw_virtualpath    *vpath,
2077        u32                     operation,
2078        u32                     offset,
2079        u64                     *stat);
2080
2081enum vxge_hw_status
2082__vxge_hw_vpath_xmac_tx_stats_get(
2083        struct __vxge_hw_virtualpath    *vpath,
2084        struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats);
2085
2086enum vxge_hw_status
2087__vxge_hw_vpath_xmac_rx_stats_get(
2088        struct __vxge_hw_virtualpath    *vpath,
2089        struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats);
2090
2091enum vxge_hw_status
2092__vxge_hw_vpath_stats_get(
2093        struct __vxge_hw_virtualpath *vpath,
2094        struct vxge_hw_vpath_stats_hw_info *hw_stats);
2095
2096void
2097vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp);
2098
2099enum vxge_hw_status
2100__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config);
2101
2102void
2103__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev);
2104
2105enum vxge_hw_status
2106__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg);
2107
2108enum vxge_hw_status
2109__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg);
2110
2111enum vxge_hw_status
2112__vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
2113        struct vxge_hw_vpath_reg __iomem *vpath_reg);
2114
2115enum vxge_hw_status
2116__vxge_hw_device_register_poll(
2117        void __iomem    *reg,
2118        u64 mask, u32 max_millis);
2119
2120#ifndef readq
2121static inline u64 readq(void __iomem *addr)
2122{
2123        u64 ret = 0;
2124        ret = readl(addr + 4);
2125        ret <<= 32;
2126        ret |= readl(addr);
2127
2128        return ret;
2129}
2130#endif
2131
2132#ifndef writeq
2133static inline void writeq(u64 val, void __iomem *addr)
2134{
2135        writel((u32) (val), addr);
2136        writel((u32) (val >> 32), (addr + 4));
2137}
2138#endif
2139
2140static inline void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
2141{
2142        writel(val, addr + 4);
2143}
2144
2145static inline void __vxge_hw_pio_mem_write32_lower(u32 val, void __iomem *addr)
2146{
2147        writel(val, addr);
2148}
2149
2150static inline enum vxge_hw_status
2151__vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
2152                          u64 mask, u32 max_millis)
2153{
2154        enum vxge_hw_status status = VXGE_HW_OK;
2155
2156        __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
2157        wmb();
2158        __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
2159        wmb();
2160
2161        status = __vxge_hw_device_register_poll(addr, mask, max_millis);
2162        return status;
2163}
2164
2165struct vxge_hw_toc_reg __iomem *
2166__vxge_hw_device_toc_get(void __iomem *bar0);
2167
2168enum vxge_hw_status
2169__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev);
2170
2171void
2172__vxge_hw_device_id_get(struct __vxge_hw_device *hldev);
2173
2174void
2175__vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev);
2176
2177enum vxge_hw_status
2178vxge_hw_device_flick_link_led(struct __vxge_hw_device *devh, u64 on_off);
2179
2180enum vxge_hw_status
2181__vxge_hw_device_initialize(struct __vxge_hw_device *hldev);
2182
2183enum vxge_hw_status
2184__vxge_hw_vpath_pci_read(
2185        struct __vxge_hw_virtualpath    *vpath,
2186        u32                     phy_func_0,
2187        u32                     offset,
2188        u32                     *val);
2189
2190enum vxge_hw_status
2191__vxge_hw_vpath_addr_get(
2192        u32 vp_id,
2193        struct vxge_hw_vpath_reg __iomem *vpath_reg,
2194        u8 (macaddr)[ETH_ALEN],
2195        u8 (macaddr_mask)[ETH_ALEN]);
2196
2197u32
2198__vxge_hw_vpath_func_id_get(
2199        u32 vp_id, struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg);
2200
2201enum vxge_hw_status
2202__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath);
2203
2204/**
2205 * vxge_debug
2206 * @level: level of debug verbosity.
2207 * @mask: mask for the debug
2208 * @buf: Circular buffer for tracing
2209 * @fmt: printf like format string
2210 *
2211 * Provides logging facilities. Can be customized on per-module
2212 * basis or/and with debug levels. Input parameters, except
2213 * module and level, are the same as posix printf. This function
2214 * may be compiled out if DEBUG macro was never defined.
2215 * See also: enum vxge_debug_level{}.
2216 */
2217
2218#define vxge_trace_aux(level, mask, fmt, ...) \
2219{\
2220                vxge_os_vaprintf(level, mask, fmt, __VA_ARGS__);\
2221}
2222
2223#define vxge_debug(module, level, mask, fmt, ...) { \
2224if ((level >= VXGE_TRACE && ((module & VXGE_DEBUG_TRACE_MASK) == module)) || \
2225        (level >= VXGE_ERR && ((module & VXGE_DEBUG_ERR_MASK) == module))) {\
2226        if ((mask & VXGE_DEBUG_MASK) == mask)\
2227                vxge_trace_aux(level, mask, fmt, __VA_ARGS__); \
2228} \
2229}
2230
2231#if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK)
2232#define vxge_debug_ll(level, mask, fmt, ...) \
2233{\
2234        vxge_debug(VXGE_COMPONENT_LL, level, mask, fmt, __VA_ARGS__);\
2235}
2236
2237#else
2238#define vxge_debug_ll(level, mask, fmt, ...)
2239#endif
2240
2241enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
2242                        struct __vxge_hw_vpath_handle **vpath_handles,
2243                        u32 vpath_count,
2244                        u8 *mtable,
2245                        u8 *itable,
2246                        u32 itable_size);
2247
2248enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
2249        struct __vxge_hw_vpath_handle *vpath_handle,
2250        enum vxge_hw_rth_algoritms algorithm,
2251        struct vxge_hw_rth_hash_types *hash_type,
2252        u16 bucket_size);
2253
2254#endif
2255