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14#ifndef VXGE_CONFIG_H
15#define VXGE_CONFIG_H
16#include <linux/list.h>
17
18#ifndef VXGE_CACHE_LINE_SIZE
19#define VXGE_CACHE_LINE_SIZE 128
20#endif
21
22#define vxge_os_vaprintf(level, mask, fmt, ...) { \
23 char buff[255]; \
24 snprintf(buff, 255, fmt, __VA_ARGS__); \
25 printk(buff); \
26 printk("\n"); \
27}
28
29#ifndef VXGE_ALIGN
30#define VXGE_ALIGN(adrs, size) \
31 (((size) - (((u64)adrs) & ((size)-1))) & ((size)-1))
32#endif
33
34#define VXGE_HW_MIN_MTU 68
35#define VXGE_HW_MAX_MTU 9600
36#define VXGE_HW_DEFAULT_MTU 1500
37
38#ifdef VXGE_DEBUG_ASSERT
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49
50#define vxge_assert(test) { \
51 if (!(test)) \
52 vxge_os_bug("bad cond: "#test" at %s:%d\n", \
53 __FILE__, __LINE__); }
54#else
55#define vxge_assert(test)
56#endif
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70enum vxge_debug_level {
71 VXGE_NONE = 0,
72 VXGE_TRACE = 1,
73 VXGE_ERR = 2
74};
75
76#define NULL_VPID 0xFFFFFFFF
77#ifdef CONFIG_VXGE_DEBUG_TRACE_ALL
78#define VXGE_DEBUG_MODULE_MASK 0xffffffff
79#define VXGE_DEBUG_TRACE_MASK 0xffffffff
80#define VXGE_DEBUG_ERR_MASK 0xffffffff
81#define VXGE_DEBUG_MASK 0x000001ff
82#else
83#define VXGE_DEBUG_MODULE_MASK 0x20000000
84#define VXGE_DEBUG_TRACE_MASK 0x20000000
85#define VXGE_DEBUG_ERR_MASK 0x20000000
86#define VXGE_DEBUG_MASK 0x00000001
87#endif
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97#define VXGE_COMPONENT_LL 0x20000000
98#define VXGE_COMPONENT_ALL 0xffffffff
99
100#define VXGE_HW_BASE_INF 100
101#define VXGE_HW_BASE_ERR 200
102#define VXGE_HW_BASE_BADCFG 300
103
104enum vxge_hw_status {
105 VXGE_HW_OK = 0,
106 VXGE_HW_FAIL = 1,
107 VXGE_HW_PENDING = 2,
108 VXGE_HW_COMPLETIONS_REMAIN = 3,
109
110 VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS = VXGE_HW_BASE_INF + 1,
111 VXGE_HW_INF_OUT_OF_DESCRIPTORS = VXGE_HW_BASE_INF + 2,
112
113 VXGE_HW_ERR_INVALID_HANDLE = VXGE_HW_BASE_ERR + 1,
114 VXGE_HW_ERR_OUT_OF_MEMORY = VXGE_HW_BASE_ERR + 2,
115 VXGE_HW_ERR_VPATH_NOT_AVAILABLE = VXGE_HW_BASE_ERR + 3,
116 VXGE_HW_ERR_VPATH_NOT_OPEN = VXGE_HW_BASE_ERR + 4,
117 VXGE_HW_ERR_WRONG_IRQ = VXGE_HW_BASE_ERR + 5,
118 VXGE_HW_ERR_SWAPPER_CTRL = VXGE_HW_BASE_ERR + 6,
119 VXGE_HW_ERR_INVALID_MTU_SIZE = VXGE_HW_BASE_ERR + 7,
120 VXGE_HW_ERR_INVALID_INDEX = VXGE_HW_BASE_ERR + 8,
121 VXGE_HW_ERR_INVALID_TYPE = VXGE_HW_BASE_ERR + 9,
122 VXGE_HW_ERR_INVALID_OFFSET = VXGE_HW_BASE_ERR + 10,
123 VXGE_HW_ERR_INVALID_DEVICE = VXGE_HW_BASE_ERR + 11,
124 VXGE_HW_ERR_VERSION_CONFLICT = VXGE_HW_BASE_ERR + 12,
125 VXGE_HW_ERR_INVALID_PCI_INFO = VXGE_HW_BASE_ERR + 13,
126 VXGE_HW_ERR_INVALID_TCODE = VXGE_HW_BASE_ERR + 14,
127 VXGE_HW_ERR_INVALID_BLOCK_SIZE = VXGE_HW_BASE_ERR + 15,
128 VXGE_HW_ERR_INVALID_STATE = VXGE_HW_BASE_ERR + 16,
129 VXGE_HW_ERR_PRIVILAGED_OPEARATION = VXGE_HW_BASE_ERR + 17,
130 VXGE_HW_ERR_INVALID_PORT = VXGE_HW_BASE_ERR + 18,
131 VXGE_HW_ERR_FIFO = VXGE_HW_BASE_ERR + 19,
132 VXGE_HW_ERR_VPATH = VXGE_HW_BASE_ERR + 20,
133 VXGE_HW_ERR_CRITICAL = VXGE_HW_BASE_ERR + 21,
134 VXGE_HW_ERR_SLOT_FREEZE = VXGE_HW_BASE_ERR + 22,
135
136 VXGE_HW_BADCFG_RING_INDICATE_MAX_PKTS = VXGE_HW_BASE_BADCFG + 1,
137 VXGE_HW_BADCFG_FIFO_BLOCKS = VXGE_HW_BASE_BADCFG + 2,
138 VXGE_HW_BADCFG_VPATH_MTU = VXGE_HW_BASE_BADCFG + 3,
139 VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG = VXGE_HW_BASE_BADCFG + 4,
140 VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH = VXGE_HW_BASE_BADCFG + 5,
141 VXGE_HW_BADCFG_INTR_MODE = VXGE_HW_BASE_BADCFG + 6,
142 VXGE_HW_BADCFG_RTS_MAC_EN = VXGE_HW_BASE_BADCFG + 7,
143
144 VXGE_HW_EOF_TRACE_BUF = -1
145};
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154enum vxge_hw_device_link_state {
155 VXGE_HW_LINK_NONE,
156 VXGE_HW_LINK_DOWN,
157 VXGE_HW_LINK_UP
158};
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170#define VXGE_HW_FW_STRLEN 32
171struct vxge_hw_device_date {
172 u32 day;
173 u32 month;
174 u32 year;
175 char date[VXGE_HW_FW_STRLEN];
176};
177
178struct vxge_hw_device_version {
179 u32 major;
180 u32 minor;
181 u32 build;
182 char version[VXGE_HW_FW_STRLEN];
183};
184
185u64
186__vxge_hw_vpath_pci_func_mode_get(
187 u32 vp_id,
188 struct vxge_hw_vpath_reg __iomem *vpath_reg);
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214struct vxge_hw_fifo_config {
215 u32 enable;
216#define VXGE_HW_FIFO_ENABLE 1
217#define VXGE_HW_FIFO_DISABLE 0
218
219 u32 fifo_blocks;
220#define VXGE_HW_MIN_FIFO_BLOCKS 2
221#define VXGE_HW_MAX_FIFO_BLOCKS 128
222
223 u32 max_frags;
224#define VXGE_HW_MIN_FIFO_FRAGS 1
225#define VXGE_HW_MAX_FIFO_FRAGS 256
226
227 u32 memblock_size;
228#define VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE VXGE_HW_BLOCK_SIZE
229#define VXGE_HW_MAX_FIFO_MEMBLOCK_SIZE 131072
230#define VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE 8096
231
232 u32 alignment_size;
233#define VXGE_HW_MIN_FIFO_ALIGNMENT_SIZE 0
234#define VXGE_HW_MAX_FIFO_ALIGNMENT_SIZE 65536
235#define VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE VXGE_CACHE_LINE_SIZE
236
237 u32 intr;
238#define VXGE_HW_FIFO_QUEUE_INTR_ENABLE 1
239#define VXGE_HW_FIFO_QUEUE_INTR_DISABLE 0
240#define VXGE_HW_FIFO_QUEUE_INTR_DEFAULT 0
241
242 u32 no_snoop_bits;
243#define VXGE_HW_FIFO_NO_SNOOP_DISABLED 0
244#define VXGE_HW_FIFO_NO_SNOOP_TXD 1
245#define VXGE_HW_FIFO_NO_SNOOP_FRM 2
246#define VXGE_HW_FIFO_NO_SNOOP_ALL 3
247#define VXGE_HW_FIFO_NO_SNOOP_DEFAULT 0
248
249};
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275struct vxge_hw_ring_config {
276 u32 enable;
277#define VXGE_HW_RING_ENABLE 1
278#define VXGE_HW_RING_DISABLE 0
279#define VXGE_HW_RING_DEFAULT 1
280
281 u32 ring_blocks;
282#define VXGE_HW_MIN_RING_BLOCKS 1
283#define VXGE_HW_MAX_RING_BLOCKS 128
284#define VXGE_HW_DEF_RING_BLOCKS 2
285
286 u32 buffer_mode;
287#define VXGE_HW_RING_RXD_BUFFER_MODE_1 1
288#define VXGE_HW_RING_RXD_BUFFER_MODE_3 3
289#define VXGE_HW_RING_RXD_BUFFER_MODE_5 5
290#define VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT 1
291
292 u32 scatter_mode;
293#define VXGE_HW_RING_SCATTER_MODE_A 0
294#define VXGE_HW_RING_SCATTER_MODE_B 1
295#define VXGE_HW_RING_SCATTER_MODE_C 2
296#define VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT 0xffffffff
297
298 u64 rxds_limit;
299#define VXGE_HW_DEF_RING_RXDS_LIMIT 44
300};
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323struct vxge_hw_vp_config {
324 u32 vp_id;
325
326#define VXGE_HW_VPATH_PRIORITY_MIN 0
327#define VXGE_HW_VPATH_PRIORITY_MAX 16
328#define VXGE_HW_VPATH_PRIORITY_DEFAULT 0
329
330 u32 min_bandwidth;
331#define VXGE_HW_VPATH_BANDWIDTH_MIN 0
332#define VXGE_HW_VPATH_BANDWIDTH_MAX 100
333#define VXGE_HW_VPATH_BANDWIDTH_DEFAULT 0
334
335 struct vxge_hw_ring_config ring;
336 struct vxge_hw_fifo_config fifo;
337 struct vxge_hw_tim_intr_config tti;
338 struct vxge_hw_tim_intr_config rti;
339
340 u32 mtu;
341#define VXGE_HW_VPATH_MIN_INITIAL_MTU VXGE_HW_MIN_MTU
342#define VXGE_HW_VPATH_MAX_INITIAL_MTU VXGE_HW_MAX_MTU
343#define VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU 0xffffffff
344
345 u32 rpa_strip_vlan_tag;
346#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE 1
347#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE 0
348#define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT 0xffffffff
349
350};
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379struct vxge_hw_device_config {
380 u32 dma_blockpool_initial;
381 u32 dma_blockpool_max;
382#define VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE 0
383#define VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE 0
384#define VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE 4
385#define VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE 4096
386
387#define VXGE_HW_MAX_PAYLOAD_SIZE_512 2
388
389 u32 intr_mode;
390#define VXGE_HW_INTR_MODE_IRQLINE 0
391#define VXGE_HW_INTR_MODE_MSIX 1
392#define VXGE_HW_INTR_MODE_MSIX_ONE_SHOT 2
393
394#define VXGE_HW_INTR_MODE_DEF 0
395
396 u32 rth_en;
397#define VXGE_HW_RTH_DISABLE 0
398#define VXGE_HW_RTH_ENABLE 1
399#define VXGE_HW_RTH_DEFAULT 0
400
401 u32 rth_it_type;
402#define VXGE_HW_RTH_IT_TYPE_SOLO_IT 0
403#define VXGE_HW_RTH_IT_TYPE_MULTI_IT 1
404#define VXGE_HW_RTH_IT_TYPE_DEFAULT 0
405
406 u32 rts_mac_en;
407#define VXGE_HW_RTS_MAC_DISABLE 0
408#define VXGE_HW_RTS_MAC_ENABLE 1
409#define VXGE_HW_RTS_MAC_DEFAULT 0
410
411 struct vxge_hw_vp_config vp_config[VXGE_HW_MAX_VIRTUAL_PATHS];
412
413 u32 device_poll_millis;
414#define VXGE_HW_MIN_DEVICE_POLL_MILLIS 1
415#define VXGE_HW_MAX_DEVICE_POLL_MILLIS 100000
416#define VXGE_HW_DEF_DEVICE_POLL_MILLIS 1000
417
418};
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471struct vxge_hw_uld_cbs {
472
473 void (*link_up)(struct __vxge_hw_device *devh);
474 void (*link_down)(struct __vxge_hw_device *devh);
475 void (*crit_err)(struct __vxge_hw_device *devh,
476 enum vxge_hw_event type, u64 ext_data);
477};
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491struct __vxge_hw_blockpool_entry {
492 struct list_head item;
493 u32 length;
494 void *memblock;
495 dma_addr_t dma_addr;
496 struct pci_dev *dma_handle;
497 struct pci_dev *acc_handle;
498};
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512struct __vxge_hw_blockpool {
513 struct __vxge_hw_device *hldev;
514 u32 block_size;
515 u32 pool_size;
516 u32 pool_max;
517 u32 req_out;
518 struct list_head free_block_list;
519 struct list_head free_entry_list;
520};
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533enum __vxge_hw_channel_type {
534 VXGE_HW_CHANNEL_TYPE_UNKNOWN = 0,
535 VXGE_HW_CHANNEL_TYPE_FIFO = 1,
536 VXGE_HW_CHANNEL_TYPE_RING = 2,
537 VXGE_HW_CHANNEL_TYPE_MAX = 3
538};
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585struct __vxge_hw_channel {
586 struct list_head item;
587 enum __vxge_hw_channel_type type;
588 struct __vxge_hw_device *devh;
589 struct __vxge_hw_vpath_handle *vph;
590 u32 length;
591 u32 vp_id;
592 void **reserve_arr;
593 u32 reserve_ptr;
594 u32 reserve_top;
595 void **work_arr;
596 u32 post_index ____cacheline_aligned;
597 u32 compl_index ____cacheline_aligned;
598 void **free_arr;
599 u32 free_ptr;
600 void **orig_arr;
601 u32 per_dtr_space;
602 void *userdata;
603 struct vxge_hw_common_reg __iomem *common_reg;
604 u32 first_vp_id;
605 struct vxge_hw_vpath_stats_sw_common_info *stats;
606
607} ____cacheline_aligned;
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634struct __vxge_hw_virtualpath {
635 u32 vp_id;
636
637 u32 vp_open;
638#define VXGE_HW_VP_NOT_OPEN 0
639#define VXGE_HW_VP_OPEN 1
640
641 struct __vxge_hw_device *hldev;
642 struct vxge_hw_vp_config *vp_config;
643 struct vxge_hw_vpath_reg __iomem *vp_reg;
644 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
645 struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db;
646
647 u32 max_mtu;
648 u32 vsport_number;
649 u32 max_kdfc_db;
650 u32 max_nofl_db;
651
652 struct __vxge_hw_ring *____cacheline_aligned ringh;
653 struct __vxge_hw_fifo *____cacheline_aligned fifoh;
654 struct list_head vpath_handles;
655 struct __vxge_hw_blockpool_entry *stats_block;
656 struct vxge_hw_vpath_stats_hw_info *hw_stats;
657 struct vxge_hw_vpath_stats_hw_info *hw_stats_sav;
658 struct vxge_hw_vpath_stats_sw_info *sw_stats;
659};
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668struct __vxge_hw_vpath_handle{
669 struct list_head item;
670 struct __vxge_hw_virtualpath *vpath;
671};
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691struct __vxge_hw_device {
692 u32 magic;
693#define VXGE_HW_DEVICE_MAGIC 0x12345678
694#define VXGE_HW_DEVICE_DEAD 0xDEADDEAD
695 u16 device_id;
696 u8 major_revision;
697 u8 minor_revision;
698 void __iomem *bar0;
699 struct pci_dev *pdev;
700 struct net_device *ndev;
701 struct vxge_hw_device_config config;
702 enum vxge_hw_device_link_state link_state;
703
704 struct vxge_hw_uld_cbs uld_callbacks;
705
706 u32 host_type;
707 u32 func_id;
708 u32 access_rights;
709#define VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH 0x1
710#define VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM 0x2
711#define VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM 0x4
712 struct vxge_hw_legacy_reg __iomem *legacy_reg;
713 struct vxge_hw_toc_reg __iomem *toc_reg;
714 struct vxge_hw_common_reg __iomem *common_reg;
715 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
716 struct vxge_hw_srpcim_reg __iomem *srpcim_reg \
717 [VXGE_HW_TITAN_SRPCIM_REG_SPACES];
718 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg \
719 [VXGE_HW_TITAN_VPMGMT_REG_SPACES];
720 struct vxge_hw_vpath_reg __iomem *vpath_reg \
721 [VXGE_HW_TITAN_VPATH_REG_SPACES];
722 u8 __iomem *kdfc;
723 u8 __iomem *usdc;
724 struct __vxge_hw_virtualpath virtual_paths \
725 [VXGE_HW_MAX_VIRTUAL_PATHS];
726 u64 vpath_assignments;
727 u64 vpaths_deployed;
728 u32 first_vp_id;
729 u64 tim_int_mask0[4];
730 u32 tim_int_mask1[4];
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732 struct __vxge_hw_blockpool block_pool;
733 struct vxge_hw_device_stats stats;
734 u32 debug_module_mask;
735 u32 debug_level;
736 u32 level_err;
737 u32 level_trace;
738};
739
740#define VXGE_HW_INFO_LEN 64
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756struct vxge_hw_device_hw_info {
757 u32 host_type;
758#define VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION 0
759#define VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION 1
760#define VXGE_HW_NO_MR_SR_VH0_FUNCTION0 2
761#define VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION 3
762#define VXGE_HW_MR_SR_VH0_INVALID_CONFIG 4
763#define VXGE_HW_SR_VH_FUNCTION0 5
764#define VXGE_HW_SR_VH_VIRTUAL_FUNCTION 6
765#define VXGE_HW_VH_NORMAL_FUNCTION 7
766 u64 function_mode;
767#define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION 0
768#define VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION 1
769#define VXGE_HW_FUNCTION_MODE_SRIOV 2
770#define VXGE_HW_FUNCTION_MODE_MRIOV 3
771 u32 func_id;
772 u64 vpath_mask;
773 struct vxge_hw_device_version fw_version;
774 struct vxge_hw_device_date fw_date;
775 struct vxge_hw_device_version flash_version;
776 struct vxge_hw_device_date flash_date;
777 u8 serial_number[VXGE_HW_INFO_LEN];
778 u8 part_number[VXGE_HW_INFO_LEN];
779 u8 product_desc[VXGE_HW_INFO_LEN];
780 u8 (mac_addrs)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
781 u8 (mac_addr_masks)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
782};
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792struct vxge_hw_device_attr {
793 void __iomem *bar0;
794 struct pci_dev *pdev;
795 struct vxge_hw_uld_cbs uld_callbacks;
796};
797
798#define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls) (hldev->link_state = ls)
799
800#define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i) { \
801 if (i < 16) { \
802 m0[0] |= vxge_vBIT(0x8, (i*4), 4); \
803 m0[1] |= vxge_vBIT(0x4, (i*4), 4); \
804 } \
805 else { \
806 m1[0] = 0x80000000; \
807 m1[1] = 0x40000000; \
808 } \
809}
810
811#define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i) { \
812 if (i < 16) { \
813 m0[0] &= ~vxge_vBIT(0x8, (i*4), 4); \
814 m0[1] &= ~vxge_vBIT(0x4, (i*4), 4); \
815 } \
816 else { \
817 m1[0] = 0; \
818 m1[1] = 0; \
819 } \
820}
821
822#define VXGE_HW_DEVICE_STATS_PIO_READ(loc, offset) { \
823 status = vxge_hw_mrpcim_stats_access(hldev, \
824 VXGE_HW_STATS_OP_READ, \
825 loc, \
826 offset, \
827 &val64); \
828 \
829 if (status != VXGE_HW_OK) \
830 return status; \
831}
832
833#define VXGE_HW_VPATH_STATS_PIO_READ(offset) { \
834 status = __vxge_hw_vpath_stats_access(vpath, \
835 VXGE_HW_STATS_OP_READ, \
836 offset, \
837 &val64); \
838 if (status != VXGE_HW_OK) \
839 return status; \
840}
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879struct __vxge_hw_ring {
880 struct __vxge_hw_channel channel;
881 struct vxge_hw_mempool *mempool;
882 struct vxge_hw_vpath_reg __iomem *vp_reg;
883 struct vxge_hw_common_reg __iomem *common_reg;
884 u32 ring_length;
885 u32 buffer_mode;
886 u32 rxd_size;
887 u32 rxd_priv_size;
888 u32 per_rxd_space;
889 u32 rxds_per_block;
890 u32 rxdblock_priv_size;
891 u32 cmpl_cnt;
892 u32 vp_id;
893 u32 doorbell_cnt;
894 u32 total_db_cnt;
895 u64 rxds_limit;
896
897 enum vxge_hw_status (*callback)(
898 struct __vxge_hw_ring *ringh,
899 void *rxdh,
900 u8 t_code,
901 void *userdata);
902
903 enum vxge_hw_status (*rxd_init)(
904 void *rxdh,
905 void *userdata);
906
907 void (*rxd_term)(
908 void *rxdh,
909 enum vxge_hw_rxd_state state,
910 void *userdata);
911
912 struct vxge_hw_vpath_stats_sw_ring_info *stats ____cacheline_aligned;
913 struct vxge_hw_ring_config *config;
914} ____cacheline_aligned;
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928enum vxge_hw_txdl_state {
929 VXGE_HW_TXDL_STATE_NONE = 0,
930 VXGE_HW_TXDL_STATE_AVAIL = 1,
931 VXGE_HW_TXDL_STATE_POSTED = 2,
932 VXGE_HW_TXDL_STATE_FREED = 3
933};
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960
961struct __vxge_hw_fifo {
962 struct __vxge_hw_channel channel;
963 struct vxge_hw_mempool *mempool;
964 struct vxge_hw_fifo_config *config;
965 struct vxge_hw_vpath_reg __iomem *vp_reg;
966 struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db;
967 u64 interrupt_type;
968 u32 no_snoop_bits;
969 u32 txdl_per_memblock;
970 u32 txdl_size;
971 u32 priv_size;
972 u32 per_txdl_space;
973 u32 vp_id;
974 u32 tx_intr_num;
975
976 enum vxge_hw_status (*callback)(
977 struct __vxge_hw_fifo *fifo_handle,
978 void *txdlh,
979 enum vxge_hw_fifo_tcode t_code,
980 void *userdata,
981 struct sk_buff ***skb_ptr,
982 int nr_skb,
983 int *more);
984
985 void (*txdl_term)(
986 void *txdlh,
987 enum vxge_hw_txdl_state state,
988 void *userdata);
989
990 struct vxge_hw_vpath_stats_sw_fifo_info *stats ____cacheline_aligned;
991} ____cacheline_aligned;
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1033struct __vxge_hw_fifo_txdl_priv {
1034 dma_addr_t dma_addr;
1035 struct pci_dev *dma_handle;
1036 ptrdiff_t dma_offset;
1037 u32 frags;
1038 u8 *align_vaddr_start;
1039 u8 *align_vaddr;
1040 dma_addr_t align_dma_addr;
1041 struct pci_dev *align_dma_handle;
1042 struct pci_dev *align_dma_acch;
1043 ptrdiff_t align_dma_offset;
1044 u32 align_used_frags;
1045 u32 alloc_frags;
1046 u32 unused;
1047 struct __vxge_hw_fifo_txdl_priv *next_txdl_priv;
1048 struct vxge_hw_fifo_txd *first_txdp;
1049 void *memblock;
1050};
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1067struct __vxge_hw_non_offload_db_wrapper {
1068 u64 control_0;
1069#define VXGE_HW_NODBW_GET_TYPE(ctrl0) vxge_bVALn(ctrl0, 0, 8)
1070#define VXGE_HW_NODBW_TYPE(val) vxge_vBIT(val, 0, 8)
1071#define VXGE_HW_NODBW_TYPE_NODBW 0
1072
1073#define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0) vxge_bVALn(ctrl0, 32, 8)
1074#define VXGE_HW_NODBW_LAST_TXD_NUMBER(val) vxge_vBIT(val, 32, 8)
1075
1076#define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0) vxge_bVALn(ctrl0, 56, 8)
1077#define VXGE_HW_NODBW_LIST_NO_SNOOP(val) vxge_vBIT(val, 56, 8)
1078#define VXGE_HW_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE 0x2
1079#define VXGE_HW_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ 0x1
1080
1081 u64 txdl_ptr;
1082};
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1215struct vxge_hw_fifo_txd {
1216 u64 control_0;
1217#define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER vxge_mBIT(7)
1218
1219#define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4)
1220#define VXGE_HW_FIFO_TXD_T_CODE(val) vxge_vBIT(val, 12, 4)
1221#define VXGE_HW_FIFO_TXD_T_CODE_UNUSED VXGE_HW_FIFO_T_CODE_UNUSED
1222
1223
1224#define VXGE_HW_FIFO_TXD_GATHER_CODE(val) vxge_vBIT(val, 22, 2)
1225#define VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST VXGE_HW_FIFO_GATHER_CODE_FIRST
1226#define VXGE_HW_FIFO_TXD_GATHER_CODE_LAST VXGE_HW_FIFO_GATHER_CODE_LAST
1227
1228
1229#define VXGE_HW_FIFO_TXD_LSO_EN vxge_mBIT(30)
1230
1231#define VXGE_HW_FIFO_TXD_LSO_MSS(val) vxge_vBIT(val, 34, 14)
1232
1233#define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val) vxge_vBIT(val, 48, 16)
1234
1235 u64 control_1;
1236#define VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN vxge_mBIT(5)
1237#define VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN vxge_mBIT(6)
1238#define VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN vxge_mBIT(7)
1239#define VXGE_HW_FIFO_TXD_VLAN_ENABLE vxge_mBIT(15)
1240
1241#define VXGE_HW_FIFO_TXD_VLAN_TAG(val) vxge_vBIT(val, 16, 16)
1242
1243#define VXGE_HW_FIFO_TXD_INT_NUMBER(val) vxge_vBIT(val, 34, 6)
1244
1245#define VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST vxge_mBIT(46)
1246#define VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ vxge_mBIT(47)
1247
1248 u64 buffer_pointer;
1249
1250 u64 host_control;
1251};
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1341struct vxge_hw_ring_rxd_1 {
1342 u64 host_control;
1343 u64 control_0;
1344#define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0) vxge_bVALn(ctrl0, 0, 7)
1345
1346#define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER vxge_mBIT(7)
1347
1348#define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) vxge_bVALn(ctrl0, 8, 1)
1349
1350#define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 9, 1)
1351
1352#define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 10, 1)
1353
1354#define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4)
1355#define VXGE_HW_RING_RXD_T_CODE(val) vxge_vBIT(val, 12, 4)
1356
1357#define VXGE_HW_RING_RXD_T_CODE_UNUSED VXGE_HW_RING_T_CODE_UNUSED
1358
1359#define VXGE_HW_RING_RXD_SYN_GET(ctrl0) vxge_bVALn(ctrl0, 16, 1)
1360
1361#define VXGE_HW_RING_RXD_IS_ICMP_GET(ctrl0) vxge_bVALn(ctrl0, 17, 1)
1362
1363#define VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 18, 1)
1364
1365#define VXGE_HW_RING_RXD_RTH_IT_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 19, 1)
1366
1367#define VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) vxge_bVALn(ctrl0, 20, 4)
1368
1369#define VXGE_HW_RING_RXD_IS_VLAN_GET(ctrl0) vxge_bVALn(ctrl0, 24, 1)
1370
1371#define VXGE_HW_RING_RXD_ETHER_ENCAP_GET(ctrl0) vxge_bVALn(ctrl0, 25, 2)
1372
1373#define VXGE_HW_RING_RXD_FRAME_PROTO_GET(ctrl0) vxge_bVALn(ctrl0, 27, 5)
1374
1375#define VXGE_HW_RING_RXD_L3_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 32, 16)
1376
1377#define VXGE_HW_RING_RXD_L4_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 48, 16)
1378
1379 u64 control_1;
1380
1381#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) vxge_bVALn(ctrl1, 2, 14)
1382#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val) vxge_vBIT(val, 2, 14)
1383#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK vxge_vBIT(0x3FFF, 2, 14)
1384
1385#define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) vxge_bVALn(ctrl1, 16, 32)
1386
1387#define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1) vxge_bVALn(ctrl1, 48, 16)
1388
1389 u64 buffer0_ptr;
1390};
1391
1392enum vxge_hw_rth_algoritms {
1393 RTH_ALG_JENKINS = 0,
1394 RTH_ALG_MS_RSS = 1,
1395 RTH_ALG_CRC32C = 2
1396};
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1411struct vxge_hw_rth_hash_types {
1412 u8 hash_type_tcpipv4_en;
1413 u8 hash_type_ipv4_en;
1414 u8 hash_type_tcpipv6_en;
1415 u8 hash_type_ipv6_en;
1416 u8 hash_type_tcpipv6ex_en;
1417 u8 hash_type_ipv6ex_en;
1418};
1419
1420u32
1421vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh);
1422
1423void vxge_hw_device_debug_set(
1424 struct __vxge_hw_device *devh,
1425 enum vxge_debug_level level,
1426 u32 mask);
1427
1428u32
1429vxge_hw_device_error_level_get(struct __vxge_hw_device *devh);
1430
1431u32
1432vxge_hw_device_trace_level_get(struct __vxge_hw_device *devh);
1433
1434u32
1435vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh);
1436
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1443static inline u32 vxge_hw_ring_rxd_size_get(u32 buf_mode)
1444{
1445 return sizeof(struct vxge_hw_ring_rxd_1);
1446}
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1454static inline u32 vxge_hw_ring_rxds_per_block_get(u32 buf_mode)
1455{
1456 return (u32)((VXGE_HW_BLOCK_SIZE-16) /
1457 sizeof(struct vxge_hw_ring_rxd_1));
1458}
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1475static inline
1476void vxge_hw_ring_rxd_1b_set(
1477 void *rxdh,
1478 dma_addr_t dma_pointer,
1479 u32 size)
1480{
1481 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1482 rxdp->buffer0_ptr = dma_pointer;
1483 rxdp->control_1 &= ~VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK;
1484 rxdp->control_1 |= VXGE_HW_RING_RXD_1_BUFFER0_SIZE(size);
1485}
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1500
1501static inline
1502void vxge_hw_ring_rxd_1b_get(
1503 struct __vxge_hw_ring *ring_handle,
1504 void *rxdh,
1505 u32 *pkt_length)
1506{
1507 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1508
1509 *pkt_length =
1510 (u32)VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1);
1511}
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1522
1523static inline
1524void vxge_hw_ring_rxd_1b_info_get(
1525 struct __vxge_hw_ring *ring_handle,
1526 void *rxdh,
1527 struct vxge_hw_ring_rxd_info *rxd_info)
1528{
1529
1530 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1531 rxd_info->syn_flag =
1532 (u32)VXGE_HW_RING_RXD_SYN_GET(rxdp->control_0);
1533 rxd_info->is_icmp =
1534 (u32)VXGE_HW_RING_RXD_IS_ICMP_GET(rxdp->control_0);
1535 rxd_info->fast_path_eligible =
1536 (u32)VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0);
1537 rxd_info->l3_cksum_valid =
1538 (u32)VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0);
1539 rxd_info->l3_cksum =
1540 (u32)VXGE_HW_RING_RXD_L3_CKSUM_GET(rxdp->control_0);
1541 rxd_info->l4_cksum_valid =
1542 (u32)VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0);
1543 rxd_info->l4_cksum =
1544 (u32)VXGE_HW_RING_RXD_L4_CKSUM_GET(rxdp->control_0);
1545 rxd_info->frame =
1546 (u32)VXGE_HW_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0);
1547 rxd_info->proto =
1548 (u32)VXGE_HW_RING_RXD_FRAME_PROTO_GET(rxdp->control_0);
1549 rxd_info->is_vlan =
1550 (u32)VXGE_HW_RING_RXD_IS_VLAN_GET(rxdp->control_0);
1551 rxd_info->vlan =
1552 (u32)VXGE_HW_RING_RXD_VLAN_TAG_GET(rxdp->control_1);
1553 rxd_info->rth_bucket =
1554 (u32)VXGE_HW_RING_RXD_RTH_BUCKET_GET(rxdp->control_0);
1555 rxd_info->rth_it_hit =
1556 (u32)VXGE_HW_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0);
1557 rxd_info->rth_spdm_hit =
1558 (u32)VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0);
1559 rxd_info->rth_hash_type =
1560 (u32)VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0);
1561 rxd_info->rth_value =
1562 (u32)VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1);
1563}
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1574static inline void *vxge_hw_ring_rxd_private_get(void *rxdh)
1575{
1576 struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1577 return (void *)(size_t)rxdp->host_control;
1578}
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1596static inline void vxge_hw_fifo_txdl_cksum_set_bits(void *txdlh, u64 cksum_bits)
1597{
1598 struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh;
1599 txdp->control_1 |= cksum_bits;
1600}
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1616static inline void vxge_hw_fifo_txdl_mss_set(void *txdlh, int mss)
1617{
1618 struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh;
1619
1620 txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_EN;
1621 txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_MSS(mss);
1622}
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1631
1632static inline void vxge_hw_fifo_txdl_vlan_set(void *txdlh, u16 vlan_tag)
1633{
1634 struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh;
1635
1636 txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_ENABLE;
1637 txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_TAG(vlan_tag);
1638}
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1651static inline void *vxge_hw_fifo_txdl_private_get(void *txdlh)
1652{
1653 struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh;
1654
1655 return (void *)(size_t)txdp->host_control;
1656}
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1681struct vxge_hw_ring_attr {
1682 enum vxge_hw_status (*callback)(
1683 struct __vxge_hw_ring *ringh,
1684 void *rxdh,
1685 u8 t_code,
1686 void *userdata);
1687
1688 enum vxge_hw_status (*rxd_init)(
1689 void *rxdh,
1690 void *userdata);
1691
1692 void (*rxd_term)(
1693 void *rxdh,
1694 enum vxge_hw_rxd_state state,
1695 void *userdata);
1696
1697 void *userdata;
1698 u32 per_rxd_space;
1699};
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1775
1776
1777struct vxge_hw_fifo_attr {
1778
1779 enum vxge_hw_status (*callback)(
1780 struct __vxge_hw_fifo *fifo_handle,
1781 void *txdlh,
1782 enum vxge_hw_fifo_tcode t_code,
1783 void *userdata,
1784 struct sk_buff ***skb_ptr,
1785 int nr_skb, int *more);
1786
1787 void (*txdl_term)(
1788 void *txdlh,
1789 enum vxge_hw_txdl_state state,
1790 void *userdata);
1791
1792 void *userdata;
1793 u32 per_txdl_space;
1794};
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805struct vxge_hw_vpath_attr {
1806 u32 vp_id;
1807 struct vxge_hw_ring_attr ring_attr;
1808 struct vxge_hw_fifo_attr fifo_attr;
1809};
1810
1811enum vxge_hw_status
1812__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1813 struct __vxge_hw_blockpool *blockpool,
1814 u32 pool_size,
1815 u32 pool_max);
1816
1817void
1818__vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool);
1819
1820struct __vxge_hw_blockpool_entry *
1821__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *hldev,
1822 u32 size);
1823
1824void
1825__vxge_hw_blockpool_block_free(struct __vxge_hw_device *hldev,
1826 struct __vxge_hw_blockpool_entry *entry);
1827
1828void *
1829__vxge_hw_blockpool_malloc(struct __vxge_hw_device *hldev,
1830 u32 size,
1831 struct vxge_hw_mempool_dma *dma_object);
1832
1833void
1834__vxge_hw_blockpool_free(struct __vxge_hw_device *hldev,
1835 void *memblock,
1836 u32 size,
1837 struct vxge_hw_mempool_dma *dma_object);
1838
1839enum vxge_hw_status
1840__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config);
1841
1842enum vxge_hw_status
1843__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config);
1844
1845enum vxge_hw_status
1846vxge_hw_mgmt_device_config(struct __vxge_hw_device *devh,
1847 struct vxge_hw_device_config *dev_config, int size);
1848
1849enum vxge_hw_status __devinit vxge_hw_device_hw_info_get(
1850 void __iomem *bar0,
1851 struct vxge_hw_device_hw_info *hw_info);
1852
1853enum vxge_hw_status
1854__vxge_hw_vpath_fw_ver_get(
1855 u32 vp_id,
1856 struct vxge_hw_vpath_reg __iomem *vpath_reg,
1857 struct vxge_hw_device_hw_info *hw_info);
1858
1859enum vxge_hw_status
1860__vxge_hw_vpath_card_info_get(
1861 u32 vp_id,
1862 struct vxge_hw_vpath_reg __iomem *vpath_reg,
1863 struct vxge_hw_device_hw_info *hw_info);
1864
1865enum vxge_hw_status __devinit vxge_hw_device_config_default_get(
1866 struct vxge_hw_device_config *device_config);
1867
1868
1869
1870
1871
1872
1873
1874
1875static inline
1876enum vxge_hw_device_link_state vxge_hw_device_link_state_get(
1877 struct __vxge_hw_device *devh)
1878{
1879 return devh->link_state;
1880}
1881
1882void vxge_hw_device_terminate(struct __vxge_hw_device *devh);
1883
1884const u8 *
1885vxge_hw_device_serial_number_get(struct __vxge_hw_device *devh);
1886
1887u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *devh);
1888
1889const u8 *
1890vxge_hw_device_product_name_get(struct __vxge_hw_device *devh);
1891
1892enum vxge_hw_status __devinit vxge_hw_device_initialize(
1893 struct __vxge_hw_device **devh,
1894 struct vxge_hw_device_attr *attr,
1895 struct vxge_hw_device_config *device_config);
1896
1897enum vxge_hw_status vxge_hw_device_getpause_data(
1898 struct __vxge_hw_device *devh,
1899 u32 port,
1900 u32 *tx,
1901 u32 *rx);
1902
1903enum vxge_hw_status vxge_hw_device_setpause_data(
1904 struct __vxge_hw_device *devh,
1905 u32 port,
1906 u32 tx,
1907 u32 rx);
1908
1909static inline void *vxge_os_dma_malloc(struct pci_dev *pdev,
1910 unsigned long size,
1911 struct pci_dev **p_dmah,
1912 struct pci_dev **p_dma_acch)
1913{
1914 gfp_t flags;
1915 void *vaddr;
1916 unsigned long misaligned = 0;
1917 *p_dma_acch = *p_dmah = NULL;
1918
1919 if (in_interrupt())
1920 flags = GFP_ATOMIC | GFP_DMA;
1921 else
1922 flags = GFP_KERNEL | GFP_DMA;
1923
1924 size += VXGE_CACHE_LINE_SIZE;
1925
1926 vaddr = kmalloc((size), flags);
1927 if (vaddr == NULL)
1928 return vaddr;
1929 misaligned = (unsigned long)VXGE_ALIGN(*((u64 *)&vaddr),
1930 VXGE_CACHE_LINE_SIZE);
1931 *(unsigned long *)p_dma_acch = misaligned;
1932 vaddr = (void *)((u8 *)vaddr + misaligned);
1933 return vaddr;
1934}
1935
1936extern void vxge_hw_blockpool_block_add(
1937 struct __vxge_hw_device *devh,
1938 void *block_addr,
1939 u32 length,
1940 struct pci_dev *dma_h,
1941 struct pci_dev *acc_handle);
1942
1943static inline void vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh,
1944 unsigned long size)
1945{
1946 gfp_t flags;
1947 void *vaddr;
1948
1949 if (in_interrupt())
1950 flags = GFP_ATOMIC | GFP_DMA;
1951 else
1952 flags = GFP_KERNEL | GFP_DMA;
1953
1954 vaddr = kmalloc((size), flags);
1955
1956 vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
1957}
1958
1959static inline void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr,
1960 struct pci_dev **p_dma_acch)
1961{
1962 unsigned long misaligned = *(unsigned long *)p_dma_acch;
1963 u8 *tmp = (u8 *)vaddr;
1964 tmp -= misaligned;
1965 kfree((void *)tmp);
1966}
1967
1968
1969
1970
1971static inline void*
1972__vxge_hw_mempool_item_priv(
1973 struct vxge_hw_mempool *mempool,
1974 u32 memblock_idx,
1975 void *item,
1976 u32 *memblock_item_idx)
1977{
1978 ptrdiff_t offset;
1979 void *memblock = mempool->memblocks_arr[memblock_idx];
1980
1981
1982 offset = (u32)((u8 *)item - (u8 *)memblock);
1983 vxge_assert(offset >= 0 && (u32)offset < mempool->memblock_size);
1984
1985 (*memblock_item_idx) = (u32) offset / mempool->item_size;
1986 vxge_assert((*memblock_item_idx) < mempool->items_per_memblock);
1987
1988 return (u8 *)mempool->memblocks_priv_arr[memblock_idx] +
1989 (*memblock_item_idx) * mempool->items_priv_size;
1990}
1991
1992enum vxge_hw_status
1993__vxge_hw_mempool_grow(
1994 struct vxge_hw_mempool *mempool,
1995 u32 num_allocate,
1996 u32 *num_allocated);
1997
1998struct vxge_hw_mempool*
1999__vxge_hw_mempool_create(
2000 struct __vxge_hw_device *devh,
2001 u32 memblock_size,
2002 u32 item_size,
2003 u32 private_size,
2004 u32 items_initial,
2005 u32 items_max,
2006 struct vxge_hw_mempool_cbs *mp_callback,
2007 void *userdata);
2008
2009struct __vxge_hw_channel*
2010__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2011 enum __vxge_hw_channel_type type, u32 length,
2012 u32 per_dtr_space, void *userdata);
2013
2014void
2015__vxge_hw_channel_free(
2016 struct __vxge_hw_channel *channel);
2017
2018enum vxge_hw_status
2019__vxge_hw_channel_initialize(
2020 struct __vxge_hw_channel *channel);
2021
2022enum vxge_hw_status
2023__vxge_hw_channel_reset(
2024 struct __vxge_hw_channel *channel);
2025
2026
2027
2028
2029
2030
2031
2032static inline struct __vxge_hw_fifo_txdl_priv *
2033__vxge_hw_fifo_txdl_priv(
2034 struct __vxge_hw_fifo *fifo,
2035 struct vxge_hw_fifo_txd *txdp)
2036{
2037 return (struct __vxge_hw_fifo_txdl_priv *)
2038 (((char *)((ulong)txdp->host_control)) +
2039 fifo->per_txdl_space);
2040}
2041
2042enum vxge_hw_status vxge_hw_vpath_open(
2043 struct __vxge_hw_device *devh,
2044 struct vxge_hw_vpath_attr *attr,
2045 struct __vxge_hw_vpath_handle **vpath_handle);
2046
2047enum vxge_hw_status
2048__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog);
2049
2050enum vxge_hw_status vxge_hw_vpath_close(
2051 struct __vxge_hw_vpath_handle *vpath_handle);
2052
2053enum vxge_hw_status
2054vxge_hw_vpath_reset(
2055 struct __vxge_hw_vpath_handle *vpath_handle);
2056
2057enum vxge_hw_status
2058vxge_hw_vpath_recover_from_reset(
2059 struct __vxge_hw_vpath_handle *vpath_handle);
2060
2061void
2062vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp);
2063
2064enum vxge_hw_status
2065vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ringh);
2066
2067enum vxge_hw_status vxge_hw_vpath_mtu_set(
2068 struct __vxge_hw_vpath_handle *vpath_handle,
2069 u32 new_mtu);
2070
2071enum vxge_hw_status vxge_hw_vpath_stats_enable(
2072 struct __vxge_hw_vpath_handle *vpath_handle);
2073
2074enum vxge_hw_status
2075__vxge_hw_vpath_stats_access(
2076 struct __vxge_hw_virtualpath *vpath,
2077 u32 operation,
2078 u32 offset,
2079 u64 *stat);
2080
2081enum vxge_hw_status
2082__vxge_hw_vpath_xmac_tx_stats_get(
2083 struct __vxge_hw_virtualpath *vpath,
2084 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats);
2085
2086enum vxge_hw_status
2087__vxge_hw_vpath_xmac_rx_stats_get(
2088 struct __vxge_hw_virtualpath *vpath,
2089 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats);
2090
2091enum vxge_hw_status
2092__vxge_hw_vpath_stats_get(
2093 struct __vxge_hw_virtualpath *vpath,
2094 struct vxge_hw_vpath_stats_hw_info *hw_stats);
2095
2096void
2097vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp);
2098
2099enum vxge_hw_status
2100__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config);
2101
2102void
2103__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev);
2104
2105enum vxge_hw_status
2106__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg);
2107
2108enum vxge_hw_status
2109__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg);
2110
2111enum vxge_hw_status
2112__vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
2113 struct vxge_hw_vpath_reg __iomem *vpath_reg);
2114
2115enum vxge_hw_status
2116__vxge_hw_device_register_poll(
2117 void __iomem *reg,
2118 u64 mask, u32 max_millis);
2119
2120#ifndef readq
2121static inline u64 readq(void __iomem *addr)
2122{
2123 u64 ret = 0;
2124 ret = readl(addr + 4);
2125 ret <<= 32;
2126 ret |= readl(addr);
2127
2128 return ret;
2129}
2130#endif
2131
2132#ifndef writeq
2133static inline void writeq(u64 val, void __iomem *addr)
2134{
2135 writel((u32) (val), addr);
2136 writel((u32) (val >> 32), (addr + 4));
2137}
2138#endif
2139
2140static inline void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
2141{
2142 writel(val, addr + 4);
2143}
2144
2145static inline void __vxge_hw_pio_mem_write32_lower(u32 val, void __iomem *addr)
2146{
2147 writel(val, addr);
2148}
2149
2150static inline enum vxge_hw_status
2151__vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
2152 u64 mask, u32 max_millis)
2153{
2154 enum vxge_hw_status status = VXGE_HW_OK;
2155
2156 __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
2157 wmb();
2158 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
2159 wmb();
2160
2161 status = __vxge_hw_device_register_poll(addr, mask, max_millis);
2162 return status;
2163}
2164
2165struct vxge_hw_toc_reg __iomem *
2166__vxge_hw_device_toc_get(void __iomem *bar0);
2167
2168enum vxge_hw_status
2169__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev);
2170
2171void
2172__vxge_hw_device_id_get(struct __vxge_hw_device *hldev);
2173
2174void
2175__vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev);
2176
2177enum vxge_hw_status
2178vxge_hw_device_flick_link_led(struct __vxge_hw_device *devh, u64 on_off);
2179
2180enum vxge_hw_status
2181__vxge_hw_device_initialize(struct __vxge_hw_device *hldev);
2182
2183enum vxge_hw_status
2184__vxge_hw_vpath_pci_read(
2185 struct __vxge_hw_virtualpath *vpath,
2186 u32 phy_func_0,
2187 u32 offset,
2188 u32 *val);
2189
2190enum vxge_hw_status
2191__vxge_hw_vpath_addr_get(
2192 u32 vp_id,
2193 struct vxge_hw_vpath_reg __iomem *vpath_reg,
2194 u8 (macaddr)[ETH_ALEN],
2195 u8 (macaddr_mask)[ETH_ALEN]);
2196
2197u32
2198__vxge_hw_vpath_func_id_get(
2199 u32 vp_id, struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg);
2200
2201enum vxge_hw_status
2202__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath);
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218#define vxge_trace_aux(level, mask, fmt, ...) \
2219{\
2220 vxge_os_vaprintf(level, mask, fmt, __VA_ARGS__);\
2221}
2222
2223#define vxge_debug(module, level, mask, fmt, ...) { \
2224if ((level >= VXGE_TRACE && ((module & VXGE_DEBUG_TRACE_MASK) == module)) || \
2225 (level >= VXGE_ERR && ((module & VXGE_DEBUG_ERR_MASK) == module))) {\
2226 if ((mask & VXGE_DEBUG_MASK) == mask)\
2227 vxge_trace_aux(level, mask, fmt, __VA_ARGS__); \
2228} \
2229}
2230
2231#if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK)
2232#define vxge_debug_ll(level, mask, fmt, ...) \
2233{\
2234 vxge_debug(VXGE_COMPONENT_LL, level, mask, fmt, __VA_ARGS__);\
2235}
2236
2237#else
2238#define vxge_debug_ll(level, mask, fmt, ...)
2239#endif
2240
2241enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
2242 struct __vxge_hw_vpath_handle **vpath_handles,
2243 u32 vpath_count,
2244 u8 *mtable,
2245 u8 *itable,
2246 u32 itable_size);
2247
2248enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
2249 struct __vxge_hw_vpath_handle *vpath_handle,
2250 enum vxge_hw_rth_algoritms algorithm,
2251 struct vxge_hw_rth_hash_types *hash_type,
2252 u16 bucket_size);
2253
2254#endif
2255