LXR linux/drivers/net/wan/hd64572.c

   1/*
   2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux
   3 *
   4 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License
   8 * as published by the Free Software Foundation.
   9 *
  10 * Source of information: HD64572 SCA-II User's Manual
  11 *
  12 * We use the following SCA memory map:
  13 *
  14 * Packet buffer descriptor rings - starting from card->rambase:
  15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
  16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
  17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
  18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
  19 *
  20 * Packet data buffers - starting from card->rambase + buff_offset:
  21 * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers
  22 * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers
  23 * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers (if used)
  24 * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers (if used)
  25 */
  26
  27#include <linux/bitops.h>
  28#include <linux/errno.h>
  29#include <linux/fcntl.h>
  30#include <linux/hdlc.h>
  31#include <linux/in.h>
  32#include <linux/init.h>
  33#include <linux/interrupt.h>
  34#include <linux/ioport.h>
  35#include <linux/jiffies.h>
  36#include <linux/kernel.h>
  37#include <linux/module.h>
  38#include <linux/netdevice.h>
  39#include <linux/skbuff.h>
  40#include <linux/slab.h>
  41#include <linux/string.h>
  42#include <linux/types.h>
  43#include <asm/io.h>
  44#include <asm/system.h>
  45#include <asm/uaccess.h>
  46#include "hd64572.h"
  47
  48#define NAPI_WEIGHT             16
  49
  50#define get_msci(port)    (port->chan ?   MSCI1_OFFSET :   MSCI0_OFFSET)
  51#define get_dmac_rx(port) (port->chan ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
  52#define get_dmac_tx(port) (port->chan ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
  53
  54#define sca_in(reg, card)            readb(card->scabase + (reg))
  55#define sca_out(value, reg, card)    writeb(value, card->scabase + (reg))
  56#define sca_inw(reg, card)           readw(card->scabase + (reg))
  57#define sca_outw(value, reg, card)   writew(value, card->scabase + (reg))
  58#define sca_inl(reg, card)           readl(card->scabase + (reg))
  59#define sca_outl(value, reg, card)   writel(value, card->scabase + (reg))
  60
  61static int sca_poll(struct napi_struct *napi, int budget);
  62
  63static inline port_t* dev_to_port(struct net_device *dev)
  64{
  65        return dev_to_hdlc(dev)->priv;
  66}
  67
  68static inline void enable_intr(port_t *port)
  69{
  70        /* enable DMIB and MSCI RXINTA interrupts */
  71        sca_outl(sca_inl(IER0, port->card) |
  72                 (port->chan ? 0x08002200 : 0x00080022), IER0, port->card);
  73}
  74
  75static inline void disable_intr(port_t *port)
  76{
  77        sca_outl(sca_inl(IER0, port->card) &
  78                 (port->chan ? 0x00FF00FF : 0xFF00FF00), IER0, port->card);
  79}
  80
  81static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
  82{
  83        u16 rx_buffs = port->card->rx_ring_buffers;
  84        u16 tx_buffs = port->card->tx_ring_buffers;
  85
  86        desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
  87        return port->chan * (rx_buffs + tx_buffs) + transmit * rx_buffs + desc;
  88}
  89
  90
  91static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
  92{
  93        /* Descriptor offset always fits in 16 bits */
  94        return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
  95}
  96
  97
  98static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
  99                                             int transmit)
 100{
 101        return (pkt_desc __iomem *)(port->card->rambase +
 102                                    desc_offset(port, desc, transmit));
 103}
 104
 105
 106static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
 107{
 108        return port->card->buff_offset +
 109                desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
 110}
 111
 112
 113static inline void sca_set_carrier(port_t *port)
 114{
 115        if (!(sca_in(get_msci(port) + ST3, port->card) & ST3_DCD)) {
 116#ifdef DEBUG_LINK
 117                printk(KERN_DEBUG "%s: sca_set_carrier on\n",
 118                       port->netdev.name);
 119#endif
 120                netif_carrier_on(port->netdev);
 121        } else {
 122#ifdef DEBUG_LINK
 123                printk(KERN_DEBUG "%s: sca_set_carrier off\n",
 124                       port->netdev.name);
 125#endif
 126                netif_carrier_off(port->netdev);
 127        }
 128}
 129
 130
 131static void sca_init_port(port_t *port)
 132{
 133        card_t *card = port->card;
 134        u16 dmac_rx = get_dmac_rx(port), dmac_tx = get_dmac_tx(port);
 135        int transmit, i;
 136
 137        port->rxin = 0;
 138        port->txin = 0;
 139        port->txlast = 0;
 140
 141        for (transmit = 0; transmit < 2; transmit++) {
 142                u16 buffs = transmit ? card->tx_ring_buffers
 143                        : card->rx_ring_buffers;
 144
 145                for (i = 0; i < buffs; i++) {
 146                        pkt_desc __iomem *desc = desc_address(port, i, transmit);
 147                        u16 chain_off = desc_offset(port, i + 1, transmit);
 148                        u32 buff_off = buffer_offset(port, i, transmit);
 149
 150                        writel(chain_off, &desc->cp);
 151                        writel(buff_off, &desc->bp);
 152                        writew(0, &desc->len);
 153                        writeb(0, &desc->stat);
 154                }
 155        }
 156
 157        /* DMA disable - to halt state */
 158        sca_out(0, DSR_RX(port->chan), card);
 159        sca_out(0, DSR_TX(port->chan), card);
 160
 161        /* software ABORT - to initial state */
 162        sca_out(DCR_ABORT, DCR_RX(port->chan), card);
 163        sca_out(DCR_ABORT, DCR_TX(port->chan), card);
 164
 165        /* current desc addr */
 166        sca_outl(desc_offset(port, 0, 0), dmac_rx + CDAL, card);
 167        sca_outl(desc_offset(port, card->tx_ring_buffers - 1, 0),
 168                 dmac_rx + EDAL, card);
 169        sca_outl(desc_offset(port, 0, 1), dmac_tx + CDAL, card);
 170        sca_outl(desc_offset(port, 0, 1), dmac_tx + EDAL, card);
 171
 172        /* clear frame end interrupt counter */
 173        sca_out(DCR_CLEAR_EOF, DCR_RX(port->chan), card);
 174        sca_out(DCR_CLEAR_EOF, DCR_TX(port->chan), card);
 175
 176        /* Receive */
 177        sca_outw(HDLC_MAX_MRU, dmac_rx + BFLL, card); /* set buffer length */
 178        sca_out(0x14, DMR_RX(port->chan), card); /* Chain mode, Multi-frame */
 179        sca_out(DIR_EOME, DIR_RX(port->chan), card); /* enable interrupts */
 180        sca_out(DSR_DE, DSR_RX(port->chan), card); /* DMA enable */
 181
 182        /* Transmit */
 183        sca_out(0x14, DMR_TX(port->chan), card); /* Chain mode, Multi-frame */
 184        sca_out(DIR_EOME, DIR_TX(port->chan), card); /* enable interrupts */
 185
 186        sca_set_carrier(port);
 187        netif_napi_add(port->netdev, &port->napi, sca_poll, NAPI_WEIGHT);
 188}
 189
 190
 191/* MSCI interrupt service */
 192static inline void sca_msci_intr(port_t *port)
 193{
 194        u16 msci = get_msci(port);
 195        card_t* card = port->card;
 196
 197        if (sca_in(msci + ST1, card) & ST1_CDCD) {
 198                /* Reset MSCI CDCD status bit */
 199                sca_out(ST1_CDCD, msci + ST1, card);
 200                sca_set_carrier(port);
 201        }
 202}
 203
 204
 205static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
 206                          u16 rxin)
 207{
 208        struct net_device *dev = port->netdev;
 209        struct sk_buff *skb;
 210        u16 len;
 211        u32 buff;
 212
 213        len = readw(&desc->len);
 214        skb = dev_alloc_skb(len);
 215        if (!skb) {
 216                dev->stats.rx_dropped++;
 217                return;
 218        }
 219
 220        buff = buffer_offset(port, rxin, 0);
 221        memcpy_fromio(skb->data, card->rambase + buff, len);
 222
 223        skb_put(skb, len);
 224#ifdef DEBUG_PKT
 225        printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
 226        debug_frame(skb);
 227#endif
 228        dev->stats.rx_packets++;
 229        dev->stats.rx_bytes += skb->len;
 230        skb->protocol = hdlc_type_trans(skb, dev);
 231        netif_receive_skb(skb);
 232}
 233
 234
 235/* Receive DMA service */
 236static inline int sca_rx_done(port_t *port, int budget)
 237{
 238        struct net_device *dev = port->netdev;
 239        u16 dmac = get_dmac_rx(port);
 240        card_t *card = port->card;
 241        u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */
 242        int received = 0;
 243
 244        /* Reset DSR status bits */
 245        sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
 246                DSR_RX(port->chan), card);
 247
 248        if (stat & DSR_BOF)
 249                /* Dropped one or more frames */
 250                dev->stats.rx_over_errors++;
 251
 252        while (received < budget) {
 253                u32 desc_off = desc_offset(port, port->rxin, 0);
 254                pkt_desc __iomem *desc;
 255                u32 cda = sca_inl(dmac + CDAL, card);
 256
 257                if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
 258                        break;  /* No frame received */
 259
 260                desc = desc_address(port, port->rxin, 0);
 261                stat = readb(&desc->stat);
 262                if (!(stat & ST_RX_EOM))
 263                        port->rxpart = 1; /* partial frame received */
 264                else if ((stat & ST_ERROR_MASK) || port->rxpart) {
 265                        dev->stats.rx_errors++;
 266                        if (stat & ST_RX_OVERRUN)
 267                                dev->stats.rx_fifo_errors++;
 268                        else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
 269                                          ST_RX_RESBIT)) || port->rxpart)
 270                                dev->stats.rx_frame_errors++;
 271                        else if (stat & ST_RX_CRC)
 272                                dev->stats.rx_crc_errors++;
 273                        if (stat & ST_RX_EOM)
 274                                port->rxpart = 0; /* received last fragment */
 275                } else {
 276                        sca_rx(card, port, desc, port->rxin);
 277                        received++;
 278                }
 279
 280                /* Set new error descriptor address */
 281                sca_outl(desc_off, dmac + EDAL, card);
 282                port->rxin = (port->rxin + 1) % card->rx_ring_buffers;
 283        }
 284
 285        /* make sure RX DMA is enabled */
 286        sca_out(DSR_DE, DSR_RX(port->chan), card);
 287        return received;
 288}
 289
 290
 291/* Transmit DMA service */
 292static inline void sca_tx_done(port_t *port)
 293{
 294        struct net_device *dev = port->netdev;
 295        card_t* card = port->card;
 296        u8 stat;
 297
 298        spin_lock(&port->lock);
 299
 300        stat = sca_in(DSR_TX(port->chan), card); /* read DMA Status */
 301
 302        /* Reset DSR status bits */
 303        sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
 304                DSR_TX(port->chan), card);
 305
 306        while (1) {
 307                pkt_desc __iomem *desc = desc_address(port, port->txlast, 1);
 308                u8 stat = readb(&desc->stat);
 309
 310                if (!(stat & ST_TX_OWNRSHP))
 311                        break; /* not yet transmitted */
 312                if (stat & ST_TX_UNDRRUN) {
 313                        dev->stats.tx_errors++;
 314                        dev->stats.tx_fifo_errors++;
 315                } else {
 316                        dev->stats.tx_packets++;
 317                        dev->stats.tx_bytes += readw(&desc->len);
 318                }
 319                writeb(0, &desc->stat); /* Free descriptor */
 320                port->txlast = (port->txlast + 1) % card->tx_ring_buffers;
 321        }
 322
 323        netif_wake_queue(dev);
 324        spin_unlock(&port->lock);
 325}
 326
 327
 328static int sca_poll(struct napi_struct *napi, int budget)
 329{
 330        port_t *port = container_of(napi, port_t, napi);
 331        u32 isr0 = sca_inl(ISR0, port->card);
 332        int received = 0;
 333
 334        if (isr0 & (port->chan ? 0x08000000 : 0x00080000))
 335                sca_msci_intr(port);
 336
 337        if (isr0 & (port->chan ? 0x00002000 : 0x00000020))
 338                sca_tx_done(port);
 339
 340        if (isr0 & (port->chan ? 0x00000200 : 0x00000002))
 341                received = sca_rx_done(port, budget);
 342
 343        if (received < budget) {
 344                napi_complete(napi);
 345                enable_intr(port);
 346        }
 347
 348        return received;
 349}
 350
 351static irqreturn_t sca_intr(int irq, void *dev_id)
 352{
 353        card_t *card = dev_id;
 354        u32 isr0 = sca_inl(ISR0, card);
 355        int i, handled = 0;
 356
 357        for (i = 0; i < 2; i++) {
 358                port_t *port = get_port(card, i);
 359                if (port && (isr0 & (i ? 0x08002200 : 0x00080022))) {
 360                        handled = 1;
 361                        disable_intr(port);
 362                        napi_schedule(&port->napi);
 363                }
 364        }
 365
 366        return IRQ_RETVAL(handled);
 367}
 368
 369
 370static void sca_set_port(port_t *port)
 371{
 372        card_t* card = port->card;
 373        u16 msci = get_msci(port);
 374        u8 md2 = sca_in(msci + MD2, card);
 375        unsigned int tmc, br = 10, brv = 1024;
 376
 377
 378        if (port->settings.clock_rate > 0) {
 379                /* Try lower br for better accuracy*/
 380                do {
 381                        br--;
 382                        brv >>= 1; /* brv = 2^9 = 512 max in specs */
 383
 384                        /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
 385                        tmc = CLOCK_BASE / brv / port->settings.clock_rate;
 386                }while (br > 1 && tmc <= 128);
 387
 388                if (tmc < 1) {
 389                        tmc = 1;
 390                        br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
 391                        brv = 1;
 392                } else if (tmc > 255)
 393                        tmc = 256; /* tmc=0 means 256 - low baud rates */
 394
 395                port->settings.clock_rate = CLOCK_BASE / brv / tmc;
 396        } else {
 397                br = 9; /* Minimum clock rate */
 398                tmc = 256;      /* 8bit = 0 */
 399                port->settings.clock_rate = CLOCK_BASE / (256 * 512);
 400        }
 401
 402        port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
 403        port->txs = (port->txs & ~CLK_BRG_MASK) | br;
 404        port->tmc = tmc;
 405
 406        /* baud divisor - time constant*/
 407        sca_out(port->tmc, msci + TMCR, card);
 408        sca_out(port->tmc, msci + TMCT, card);
 409
 410        /* Set BRG bits */
 411        sca_out(port->rxs, msci + RXS, card);
 412        sca_out(port->txs, msci + TXS, card);
 413
 414        if (port->settings.loopback)
 415                md2 |= MD2_LOOPBACK;
 416        else
 417                md2 &= ~MD2_LOOPBACK;
 418
 419        sca_out(md2, msci + MD2, card);
 420
 421}
 422
 423
 424static void sca_open(struct net_device *dev)
 425{
 426        port_t *port = dev_to_port(dev);
 427        card_t* card = port->card;
 428        u16 msci = get_msci(port);
 429        u8 md0, md2;
 430
 431        switch(port->encoding) {
 432        case ENCODING_NRZ:      md2 = MD2_NRZ;          break;
 433        case ENCODING_NRZI:     md2 = MD2_NRZI;         break;
 434        case ENCODING_FM_MARK:  md2 = MD2_FM_MARK;      break;
 435        case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE;     break;
 436        default:                md2 = MD2_MANCHESTER;
 437        }
 438
 439        if (port->settings.loopback)
 440                md2 |= MD2_LOOPBACK;
 441
 442        switch(port->parity) {
 443        case PARITY_CRC16_PR0:       md0 = MD0_HDLC | MD0_CRC_16_0;  break;
 444        case PARITY_CRC16_PR1:       md0 = MD0_HDLC | MD0_CRC_16;    break;
 445        case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
 446        case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU;   break;
 447        default:                     md0 = MD0_HDLC | MD0_CRC_NONE;
 448        }
 449
 450        sca_out(CMD_RESET, msci + CMD, card);
 451        sca_out(md0, msci + MD0, card);
 452        sca_out(0x00, msci + MD1, card); /* no address field check */
 453        sca_out(md2, msci + MD2, card);
 454        sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
 455        /* Skip the rest of underrun frame */
 456        sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
 457        sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
 458        sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
 459        sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
 460        sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
 461        sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
 462
 463/* We're using the following interrupts:
 464   - RXINTA (DCD changes only)
 465   - DMIB (EOM - single frame transfer complete)
 466*/
 467        sca_outl(IE0_RXINTA | IE0_CDCD, msci + IE0, card);
 468
 469        sca_out(port->tmc, msci + TMCR, card);
 470        sca_out(port->tmc, msci + TMCT, card);
 471        sca_out(port->rxs, msci + RXS, card);
 472        sca_out(port->txs, msci + TXS, card);
 473        sca_out(CMD_TX_ENABLE, msci + CMD, card);
 474        sca_out(CMD_RX_ENABLE, msci + CMD, card);
 475
 476        sca_set_carrier(port);
 477        enable_intr(port);
 478        napi_enable(&port->napi);
 479        netif_start_queue(dev);
 480}
 481
 482
 483static void sca_close(struct net_device *dev)
 484{
 485        port_t *port = dev_to_port(dev);
 486
 487        /* reset channel */
 488        sca_out(CMD_RESET, get_msci(port) + CMD, port->card);
 489        disable_intr(port);
 490        napi_disable(&port->napi);
 491        netif_stop_queue(dev);
 492}
 493
 494
 495static int sca_attach(struct net_device *dev, unsigned short encoding,
 496                      unsigned short parity)
 497{
 498        if (encoding != ENCODING_NRZ &&
 499            encoding != ENCODING_NRZI &&
 500            encoding != ENCODING_FM_MARK &&
 501            encoding != ENCODING_FM_SPACE &&
 502            encoding != ENCODING_MANCHESTER)
 503                return -EINVAL;
 504
 505        if (parity != PARITY_NONE &&
 506            parity != PARITY_CRC16_PR0 &&
 507            parity != PARITY_CRC16_PR1 &&
 508            parity != PARITY_CRC32_PR1_CCITT &&
 509            parity != PARITY_CRC16_PR1_CCITT)
 510                return -EINVAL;
 511
 512        dev_to_port(dev)->encoding = encoding;
 513        dev_to_port(dev)->parity = parity;
 514        return 0;
 515}
 516
 517
 518#ifdef DEBUG_RINGS
 519static void sca_dump_rings(struct net_device *dev)
 520{
 521        port_t *port = dev_to_port(dev);
 522        card_t *card = port->card;
 523        u16 cnt;
 524
 525        printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
 526               sca_inl(get_dmac_rx(port) + CDAL, card),
 527               sca_inl(get_dmac_rx(port) + EDAL, card),
 528               sca_in(DSR_RX(port->chan), card), port->rxin,
 529               sca_in(DSR_RX(port->chan), card) & DSR_DE ? "" : "in");
 530        for (cnt = 0; cnt < port->card->rx_ring_buffers; cnt++)
 531                printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
 532        printk(KERN_CONT "\n");
 533
 534        printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
 535               "last=%u %sactive",
 536               sca_inl(get_dmac_tx(port) + CDAL, card),
 537               sca_inl(get_dmac_tx(port) + EDAL, card),
 538               sca_in(DSR_TX(port->chan), card), port->txin, port->txlast,
 539               sca_in(DSR_TX(port->chan), card) & DSR_DE ? "" : "in");
 540
 541        for (cnt = 0; cnt < port->card->tx_ring_buffers; cnt++)
 542                printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
 543        printk("\n");
 544
 545        printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x,"
 546               " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n",
 547               sca_in(get_msci(port) + MD0, card),
 548               sca_in(get_msci(port) + MD1, card),
 549               sca_in(get_msci(port) + MD2, card),
 550               sca_in(get_msci(port) + ST0, card),
 551               sca_in(get_msci(port) + ST1, card),
 552               sca_in(get_msci(port) + ST2, card),
 553               sca_in(get_msci(port) + ST3, card),
 554               sca_in(get_msci(port) + ST4, card),
 555               sca_in(get_msci(port) + FST, card),
 556               sca_in(get_msci(port) + CST0, card),
 557               sca_in(get_msci(port) + CST1, card));
 558
 559        printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
 560               sca_inl(ISR0, card), sca_inl(ISR1, card));
 561}
 562#endif /* DEBUG_RINGS */
 563
 564
 565static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
 566{
 567        port_t *port = dev_to_port(dev);
 568        card_t *card = port->card;
 569        pkt_desc __iomem *desc;
 570        u32 buff, len;
 571
 572        spin_lock_irq(&port->lock);
 573
 574        desc = desc_address(port, port->txin + 1, 1);
 575        BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
 576
 577#ifdef DEBUG_PKT
 578        printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
 579        debug_frame(skb);
 580#endif
 581
 582        desc = desc_address(port, port->txin, 1);
 583        buff = buffer_offset(port, port->txin, 1);
 584        len = skb->len;
 585        memcpy_toio(card->rambase + buff, skb->data, len);
 586
 587        writew(len, &desc->len);
 588        writeb(ST_TX_EOM, &desc->stat);
 589        dev->trans_start = jiffies;
 590
 591        port->txin = (port->txin + 1) % card->tx_ring_buffers;
 592        sca_outl(desc_offset(port, port->txin, 1),
 593                 get_dmac_tx(port) + EDAL, card);
 594
 595        sca_out(DSR_DE, DSR_TX(port->chan), card); /* Enable TX DMA */
 596
 597        desc = desc_address(port, port->txin + 1, 1);
 598        if (readb(&desc->stat)) /* allow 1 packet gap */
 599                netif_stop_queue(dev);
 600
 601        spin_unlock_irq(&port->lock);
 602
 603        dev_kfree_skb(skb);
 604        return NETDEV_TX_OK;
 605}
 606
 607
 608static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase,
 609                                    u32 ramsize)
 610{
 611        /* Round RAM size to 32 bits, fill from end to start */
 612        u32 i = ramsize &= ~3;
 613
 614        do {
 615                i -= 4;
 616                writel(i ^ 0x12345678, rambase + i);
 617        } while (i > 0);
 618
 619        for (i = 0; i < ramsize ; i += 4) {
 620                if (readl(rambase + i) != (i ^ 0x12345678))
 621                        break;
 622        }
 623
 624        return i;
 625}
 626
 627
 628static void __devinit sca_init(card_t *card, int wait_states)
 629{
 630        sca_out(wait_states, WCRL, card); /* Wait Control */
 631        sca_out(wait_states, WCRM, card);
 632        sca_out(wait_states, WCRH, card);
 633
 634        sca_out(0, DMER, card); /* DMA Master disable */
 635        sca_out(0x03, PCR, card); /* DMA priority */
 636        sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
 637        sca_out(0, DSR_TX(0), card);
 638        sca_out(0, DSR_RX(1), card);
 639        sca_out(0, DSR_TX(1), card);
 640        sca_out(DMER_DME, DMER, card); /* DMA Master enable */
 641}
 642