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39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/mm.h>
42#include <linux/net.h>
43#include <linux/skbuff.h>
44#include <linux/netdevice.h>
45#include <linux/if_arp.h>
46#include <linux/delay.h>
47#include <linux/hdlc.h>
48#include <linux/ioport.h>
49#include <linux/init.h>
50#include <asm/dma.h>
51#include <asm/io.h>
52#define RT_LOCK
53#define RT_UNLOCK
54#include <linux/spinlock.h>
55
56#include "z85230.h"
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75static inline int z8530_read_port(unsigned long p)
76{
77 u8 r=inb(Z8530_PORT_OF(p));
78 if(p&Z8530_PORT_SLEEP)
79 udelay(5);
80 return r;
81}
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99static inline void z8530_write_port(unsigned long p, u8 d)
100{
101 outb(d,Z8530_PORT_OF(p));
102 if(p&Z8530_PORT_SLEEP)
103 udelay(5);
104}
105
106
107
108static void z8530_rx_done(struct z8530_channel *c);
109static void z8530_tx_done(struct z8530_channel *c);
110
111
112
113
114
115
116
117
118
119
120
121
122
123static inline u8 read_zsreg(struct z8530_channel *c, u8 reg)
124{
125 if(reg)
126 z8530_write_port(c->ctrlio, reg);
127 return z8530_read_port(c->ctrlio);
128}
129
130
131
132
133
134
135
136
137
138static inline u8 read_zsdata(struct z8530_channel *c)
139{
140 u8 r;
141 r=z8530_read_port(c->dataio);
142 return r;
143}
144
145
146
147
148
149
150
151
152
153
154
155
156
157static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val)
158{
159 if(reg)
160 z8530_write_port(c->ctrlio, reg);
161 z8530_write_port(c->ctrlio, val);
162
163}
164
165
166
167
168
169
170
171
172
173static inline void write_zsctrl(struct z8530_channel *c, u8 val)
174{
175 z8530_write_port(c->ctrlio, val);
176}
177
178
179
180
181
182
183
184
185
186
187static inline void write_zsdata(struct z8530_channel *c, u8 val)
188{
189 z8530_write_port(c->dataio, val);
190}
191
192
193
194
195
196u8 z8530_dead_port[]=
197{
198 255
199};
200
201EXPORT_SYMBOL(z8530_dead_port);
202
203
204
205
206
207
208
209
210
211
212
213u8 z8530_hdlc_kilostream[]=
214{
215 4, SYNC_ENAB|SDLC|X1CLK,
216 2, 0,
217 1, 0,
218 3, ENT_HM|RxCRC_ENAB|Rx8,
219 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
220 9, 0,
221 6, 0xFF,
222 7, FLAG,
223 10, ABUNDER|NRZ|CRCPS,
224 11, TCTRxCP,
225 14, DISDPLL,
226 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
227 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
228 9, NV|MIE|NORESET,
229 255
230};
231
232EXPORT_SYMBOL(z8530_hdlc_kilostream);
233
234
235
236
237
238u8 z8530_hdlc_kilostream_85230[]=
239{
240 4, SYNC_ENAB|SDLC|X1CLK,
241 2, 0,
242 1, 0,
243 3, ENT_HM|RxCRC_ENAB|Rx8,
244 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
245 9, 0,
246 6, 0xFF,
247 7, FLAG,
248 10, ABUNDER|NRZ|CRCPS,
249 11, TCTRxCP,
250 14, DISDPLL,
251 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
252 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
253 9, NV|MIE|NORESET,
254 23, 3,
255
256 255
257};
258
259EXPORT_SYMBOL(z8530_hdlc_kilostream_85230);
260
261
262
263
264
265
266
267
268
269
270
271
272
273static void z8530_flush_fifo(struct z8530_channel *c)
274{
275 read_zsreg(c, R1);
276 read_zsreg(c, R1);
277 read_zsreg(c, R1);
278 read_zsreg(c, R1);
279 if(c->dev->type==Z85230)
280 {
281 read_zsreg(c, R1);
282 read_zsreg(c, R1);
283 read_zsreg(c, R1);
284 read_zsreg(c, R1);
285 }
286}
287
288
289
290
291
292
293
294
295
296
297
298
299static void z8530_rtsdtr(struct z8530_channel *c, int set)
300{
301 if (set)
302 c->regs[5] |= (RTS | DTR);
303 else
304 c->regs[5] &= ~(RTS | DTR);
305 write_zsreg(c, R5, c->regs[5]);
306}
307
308
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329
330
331
332static void z8530_rx(struct z8530_channel *c)
333{
334 u8 ch,stat;
335
336 while(1)
337 {
338
339 if(!(read_zsreg(c, R0)&1))
340 break;
341 ch=read_zsdata(c);
342 stat=read_zsreg(c, R1);
343
344
345
346
347 if(c->count < c->max)
348 {
349 *c->dptr++=ch;
350 c->count++;
351 }
352
353 if(stat&END_FR)
354 {
355
356
357
358
359 if(stat&(Rx_OVR|CRC_ERR))
360 {
361
362 if(c->skb)
363 c->dptr=c->skb->data;
364 c->count=0;
365 if(stat&Rx_OVR)
366 {
367 printk(KERN_WARNING "%s: overrun\n", c->dev->name);
368 c->rx_overrun++;
369 }
370 if(stat&CRC_ERR)
371 {
372 c->rx_crc_err++;
373
374 }
375
376 }
377 else
378 {
379
380
381
382
383 z8530_rx_done(c);
384 write_zsctrl(c, RES_Rx_CRC);
385 }
386 }
387 }
388
389
390
391 write_zsctrl(c, ERR_RES);
392 write_zsctrl(c, RES_H_IUS);
393}
394
395
396
397
398
399
400
401
402
403
404
405
406static void z8530_tx(struct z8530_channel *c)
407{
408 while(c->txcount) {
409
410 if(!(read_zsreg(c, R0)&4))
411 return;
412 c->txcount--;
413
414
415
416 write_zsreg(c, R8, *c->tx_ptr++);
417 write_zsctrl(c, RES_H_IUS);
418
419 if(c->txcount==0)
420 {
421 write_zsctrl(c, RES_EOM_L);
422 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
423 }
424 }
425
426
427
428
429
430
431 write_zsctrl(c, RES_Tx_P);
432
433 z8530_tx_done(c);
434 write_zsctrl(c, RES_H_IUS);
435}
436
437
438
439
440
441
442
443
444
445
446
447static void z8530_status(struct z8530_channel *chan)
448{
449 u8 status, altered;
450
451 status = read_zsreg(chan, R0);
452 altered = chan->status ^ status;
453
454 chan->status = status;
455
456 if (status & TxEOM) {
457
458 chan->netdevice->stats.tx_fifo_errors++;
459 write_zsctrl(chan, ERR_RES);
460 z8530_tx_done(chan);
461 }
462
463 if (altered & chan->dcdcheck)
464 {
465 if (status & chan->dcdcheck) {
466 printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
467 write_zsreg(chan, R3, chan->regs[3] | RxENABLE);
468 if (chan->netdevice)
469 netif_carrier_on(chan->netdevice);
470 } else {
471 printk(KERN_INFO "%s: DCD lost\n", chan->dev->name);
472 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE);
473 z8530_flush_fifo(chan);
474 if (chan->netdevice)
475 netif_carrier_off(chan->netdevice);
476 }
477
478 }
479 write_zsctrl(chan, RES_EXT_INT);
480 write_zsctrl(chan, RES_H_IUS);
481}
482
483struct z8530_irqhandler z8530_sync =
484{
485 z8530_rx,
486 z8530_tx,
487 z8530_status
488};
489
490EXPORT_SYMBOL(z8530_sync);
491
492
493
494
495
496
497
498
499
500
501
502static void z8530_dma_rx(struct z8530_channel *chan)
503{
504 if(chan->rxdma_on)
505 {
506
507 u8 status;
508
509 read_zsreg(chan, R7);
510 read_zsreg(chan, R6);
511
512 status=read_zsreg(chan, R1);
513
514 if(status&END_FR)
515 {
516 z8530_rx_done(chan);
517 }
518 write_zsctrl(chan, ERR_RES);
519 write_zsctrl(chan, RES_H_IUS);
520 }
521 else
522 {
523
524 z8530_rx(chan);
525 }
526}
527
528
529
530
531
532
533
534
535
536static void z8530_dma_tx(struct z8530_channel *chan)
537{
538 if(!chan->dma_tx)
539 {
540 printk(KERN_WARNING "Hey who turned the DMA off?\n");
541 z8530_tx(chan);
542 return;
543 }
544
545 printk(KERN_ERR "DMA tx - bogus event!\n");
546 z8530_tx(chan);
547}
548
549
550
551
552
553
554
555
556
557
558
559static void z8530_dma_status(struct z8530_channel *chan)
560{
561 u8 status, altered;
562
563 status=read_zsreg(chan, R0);
564 altered=chan->status^status;
565
566 chan->status=status;
567
568
569 if(chan->dma_tx)
570 {
571 if(status&TxEOM)
572 {
573 unsigned long flags;
574
575 flags=claim_dma_lock();
576 disable_dma(chan->txdma);
577 clear_dma_ff(chan->txdma);
578 chan->txdma_on=0;
579 release_dma_lock(flags);
580 z8530_tx_done(chan);
581 }
582 }
583
584 if (altered & chan->dcdcheck)
585 {
586 if (status & chan->dcdcheck) {
587 printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
588 write_zsreg(chan, R3, chan->regs[3] | RxENABLE);
589 if (chan->netdevice)
590 netif_carrier_on(chan->netdevice);
591 } else {
592 printk(KERN_INFO "%s:DCD lost\n", chan->dev->name);
593 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE);
594 z8530_flush_fifo(chan);
595 if (chan->netdevice)
596 netif_carrier_off(chan->netdevice);
597 }
598 }
599
600 write_zsctrl(chan, RES_EXT_INT);
601 write_zsctrl(chan, RES_H_IUS);
602}
603
604static struct z8530_irqhandler z8530_dma_sync = {
605 z8530_dma_rx,
606 z8530_dma_tx,
607 z8530_dma_status
608};
609
610static struct z8530_irqhandler z8530_txdma_sync = {
611 z8530_rx,
612 z8530_dma_tx,
613 z8530_dma_status
614};
615
616
617
618
619
620
621
622
623
624
625
626static void z8530_rx_clear(struct z8530_channel *c)
627{
628
629
630
631 u8 stat;
632
633 read_zsdata(c);
634 stat=read_zsreg(c, R1);
635
636 if(stat&END_FR)
637 write_zsctrl(c, RES_Rx_CRC);
638
639
640
641 write_zsctrl(c, ERR_RES);
642 write_zsctrl(c, RES_H_IUS);
643}
644
645
646
647
648
649
650
651
652
653
654static void z8530_tx_clear(struct z8530_channel *c)
655{
656 write_zsctrl(c, RES_Tx_P);
657 write_zsctrl(c, RES_H_IUS);
658}
659
660
661
662
663
664
665
666
667
668
669static void z8530_status_clear(struct z8530_channel *chan)
670{
671 u8 status=read_zsreg(chan, R0);
672 if(status&TxEOM)
673 write_zsctrl(chan, ERR_RES);
674 write_zsctrl(chan, RES_EXT_INT);
675 write_zsctrl(chan, RES_H_IUS);
676}
677
678struct z8530_irqhandler z8530_nop=
679{
680 z8530_rx_clear,
681 z8530_tx_clear,
682 z8530_status_clear
683};
684
685
686EXPORT_SYMBOL(z8530_nop);
687
688
689
690
691
692
693
694
695
696
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698
699
700
701
702
703
704irqreturn_t z8530_interrupt(int irq, void *dev_id)
705{
706 struct z8530_dev *dev=dev_id;
707 u8 uninitialized_var(intr);
708 static volatile int locker=0;
709 int work=0;
710 struct z8530_irqhandler *irqs;
711
712 if(locker)
713 {
714 printk(KERN_ERR "IRQ re-enter\n");
715 return IRQ_NONE;
716 }
717 locker=1;
718
719 spin_lock(&dev->lock);
720
721 while(++work<5000)
722 {
723
724 intr = read_zsreg(&dev->chanA, R3);
725 if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))
726 break;
727
728
729
730
731
732
733
734 irqs=dev->chanA.irqs;
735
736 if(intr & (CHARxIP|CHATxIP|CHAEXT))
737 {
738 if(intr&CHARxIP)
739 irqs->rx(&dev->chanA);
740 if(intr&CHATxIP)
741 irqs->tx(&dev->chanA);
742 if(intr&CHAEXT)
743 irqs->status(&dev->chanA);
744 }
745
746 irqs=dev->chanB.irqs;
747
748 if(intr & (CHBRxIP|CHBTxIP|CHBEXT))
749 {
750 if(intr&CHBRxIP)
751 irqs->rx(&dev->chanB);
752 if(intr&CHBTxIP)
753 irqs->tx(&dev->chanB);
754 if(intr&CHBEXT)
755 irqs->status(&dev->chanB);
756 }
757 }
758 spin_unlock(&dev->lock);
759 if(work==5000)
760 printk(KERN_ERR "%s: interrupt jammed - abort(0x%X)!\n", dev->name, intr);
761
762 locker=0;
763 return IRQ_HANDLED;
764}
765
766EXPORT_SYMBOL(z8530_interrupt);
767
768static char reg_init[16]=
769{
770 0,0,0,0,
771 0,0,0,0,
772 0,0,0,0,
773 0x55,0,0,0
774};
775
776
777
778
779
780
781
782
783
784
785
786int z8530_sync_open(struct net_device *dev, struct z8530_channel *c)
787{
788 unsigned long flags;
789
790 spin_lock_irqsave(c->lock, flags);
791
792 c->sync = 1;
793 c->mtu = dev->mtu+64;
794 c->count = 0;
795 c->skb = NULL;
796 c->skb2 = NULL;
797 c->irqs = &z8530_sync;
798
799
800 z8530_rx_done(c);
801 z8530_rx_done(c);
802 z8530_rtsdtr(c,1);
803 c->dma_tx = 0;
804 c->regs[R1]|=TxINT_ENAB;
805 write_zsreg(c, R1, c->regs[R1]);
806 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
807
808 spin_unlock_irqrestore(c->lock, flags);
809 return 0;
810}
811
812
813EXPORT_SYMBOL(z8530_sync_open);
814
815
816
817
818
819
820
821
822
823
824int z8530_sync_close(struct net_device *dev, struct z8530_channel *c)
825{
826 u8 chk;
827 unsigned long flags;
828
829 spin_lock_irqsave(c->lock, flags);
830 c->irqs = &z8530_nop;
831 c->max = 0;
832 c->sync = 0;
833
834 chk=read_zsreg(c,R0);
835 write_zsreg(c, R3, c->regs[R3]);
836 z8530_rtsdtr(c,0);
837
838 spin_unlock_irqrestore(c->lock, flags);
839 return 0;
840}
841
842EXPORT_SYMBOL(z8530_sync_close);
843
844
845
846
847
848
849
850
851
852
853
854int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
855{
856 unsigned long cflags, dflags;
857
858 c->sync = 1;
859 c->mtu = dev->mtu+64;
860 c->count = 0;
861 c->skb = NULL;
862 c->skb2 = NULL;
863
864
865
866 c->rxdma_on = 0;
867 c->txdma_on = 0;
868
869
870
871
872
873
874
875 if(c->mtu > PAGE_SIZE/2)
876 return -EMSGSIZE;
877
878 c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
879 if(c->rx_buf[0]==NULL)
880 return -ENOBUFS;
881 c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2;
882
883 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
884 if(c->tx_dma_buf[0]==NULL)
885 {
886 free_page((unsigned long)c->rx_buf[0]);
887 c->rx_buf[0]=NULL;
888 return -ENOBUFS;
889 }
890 c->tx_dma_buf[1]=c->tx_dma_buf[0]+PAGE_SIZE/2;
891
892 c->tx_dma_used=0;
893 c->dma_tx = 1;
894 c->dma_num=0;
895 c->dma_ready=1;
896
897
898
899
900
901 spin_lock_irqsave(c->lock, cflags);
902
903
904
905
906
907 c->regs[R14]|= DTRREQ;
908 write_zsreg(c, R14, c->regs[R14]);
909
910 c->regs[R1]&= ~TxINT_ENAB;
911 write_zsreg(c, R1, c->regs[R1]);
912
913
914
915
916
917 c->regs[R1]|= WT_FN_RDYFN;
918 c->regs[R1]|= WT_RDY_RT;
919 c->regs[R1]|= INT_ERR_Rx;
920 c->regs[R1]&= ~TxINT_ENAB;
921 write_zsreg(c, R1, c->regs[R1]);
922 c->regs[R1]|= WT_RDY_ENAB;
923 write_zsreg(c, R1, c->regs[R1]);
924
925
926
927
928
929
930
931
932
933 dflags=claim_dma_lock();
934
935 disable_dma(c->rxdma);
936 clear_dma_ff(c->rxdma);
937 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
938 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0]));
939 set_dma_count(c->rxdma, c->mtu);
940 enable_dma(c->rxdma);
941
942 disable_dma(c->txdma);
943 clear_dma_ff(c->txdma);
944 set_dma_mode(c->txdma, DMA_MODE_WRITE);
945 disable_dma(c->txdma);
946
947 release_dma_lock(dflags);
948
949
950
951
952
953 c->rxdma_on = 1;
954 c->txdma_on = 1;
955 c->tx_dma_used = 1;
956
957 c->irqs = &z8530_dma_sync;
958 z8530_rtsdtr(c,1);
959 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
960
961 spin_unlock_irqrestore(c->lock, cflags);
962
963 return 0;
964}
965
966EXPORT_SYMBOL(z8530_sync_dma_open);
967
968
969
970
971
972
973
974
975
976
977int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c)
978{
979 u8 chk;
980 unsigned long flags;
981
982 c->irqs = &z8530_nop;
983 c->max = 0;
984 c->sync = 0;
985
986
987
988
989
990 flags=claim_dma_lock();
991 disable_dma(c->rxdma);
992 clear_dma_ff(c->rxdma);
993
994 c->rxdma_on = 0;
995
996 disable_dma(c->txdma);
997 clear_dma_ff(c->txdma);
998 release_dma_lock(flags);
999
1000 c->txdma_on = 0;
1001 c->tx_dma_used = 0;
1002
1003 spin_lock_irqsave(c->lock, flags);
1004
1005
1006
1007
1008
1009 c->regs[R1]&= ~WT_RDY_ENAB;
1010 write_zsreg(c, R1, c->regs[R1]);
1011 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1012 c->regs[R1]|= INT_ALL_Rx;
1013 write_zsreg(c, R1, c->regs[R1]);
1014 c->regs[R14]&= ~DTRREQ;
1015 write_zsreg(c, R14, c->regs[R14]);
1016
1017 if(c->rx_buf[0])
1018 {
1019 free_page((unsigned long)c->rx_buf[0]);
1020 c->rx_buf[0]=NULL;
1021 }
1022 if(c->tx_dma_buf[0])
1023 {
1024 free_page((unsigned long)c->tx_dma_buf[0]);
1025 c->tx_dma_buf[0]=NULL;
1026 }
1027 chk=read_zsreg(c,R0);
1028 write_zsreg(c, R3, c->regs[R3]);
1029 z8530_rtsdtr(c,0);
1030
1031 spin_unlock_irqrestore(c->lock, flags);
1032
1033 return 0;
1034}
1035
1036EXPORT_SYMBOL(z8530_sync_dma_close);
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
1049{
1050 unsigned long cflags, dflags;
1051
1052 printk("Opening sync interface for TX-DMA\n");
1053 c->sync = 1;
1054 c->mtu = dev->mtu+64;
1055 c->count = 0;
1056 c->skb = NULL;
1057 c->skb2 = NULL;
1058
1059
1060
1061
1062
1063
1064
1065 if(c->mtu > PAGE_SIZE/2)
1066 return -EMSGSIZE;
1067
1068 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
1069 if(c->tx_dma_buf[0]==NULL)
1070 return -ENOBUFS;
1071
1072 c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2;
1073
1074
1075 spin_lock_irqsave(c->lock, cflags);
1076
1077
1078
1079
1080
1081 z8530_rx_done(c);
1082 z8530_rx_done(c);
1083
1084
1085
1086
1087
1088 c->rxdma_on = 0;
1089 c->txdma_on = 0;
1090
1091 c->tx_dma_used=0;
1092 c->dma_num=0;
1093 c->dma_ready=1;
1094 c->dma_tx = 1;
1095
1096
1097
1098
1099
1100
1101
1102
1103 c->regs[R14]|= DTRREQ;
1104 write_zsreg(c, R14, c->regs[R14]);
1105
1106 c->regs[R1]&= ~TxINT_ENAB;
1107 write_zsreg(c, R1, c->regs[R1]);
1108
1109
1110
1111
1112
1113 dflags = claim_dma_lock();
1114
1115 disable_dma(c->txdma);
1116 clear_dma_ff(c->txdma);
1117 set_dma_mode(c->txdma, DMA_MODE_WRITE);
1118 disable_dma(c->txdma);
1119
1120 release_dma_lock(dflags);
1121
1122
1123
1124
1125
1126 c->rxdma_on = 0;
1127 c->txdma_on = 1;
1128 c->tx_dma_used = 1;
1129
1130 c->irqs = &z8530_txdma_sync;
1131 z8530_rtsdtr(c,1);
1132 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1133 spin_unlock_irqrestore(c->lock, cflags);
1134
1135 return 0;
1136}
1137
1138EXPORT_SYMBOL(z8530_sync_txdma_open);
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c)
1150{
1151 unsigned long dflags, cflags;
1152 u8 chk;
1153
1154
1155 spin_lock_irqsave(c->lock, cflags);
1156
1157 c->irqs = &z8530_nop;
1158 c->max = 0;
1159 c->sync = 0;
1160
1161
1162
1163
1164
1165 dflags = claim_dma_lock();
1166
1167 disable_dma(c->txdma);
1168 clear_dma_ff(c->txdma);
1169 c->txdma_on = 0;
1170 c->tx_dma_used = 0;
1171
1172 release_dma_lock(dflags);
1173
1174
1175
1176
1177
1178 c->regs[R1]&= ~WT_RDY_ENAB;
1179 write_zsreg(c, R1, c->regs[R1]);
1180 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1181 c->regs[R1]|= INT_ALL_Rx;
1182 write_zsreg(c, R1, c->regs[R1]);
1183 c->regs[R14]&= ~DTRREQ;
1184 write_zsreg(c, R14, c->regs[R14]);
1185
1186 if(c->tx_dma_buf[0])
1187 {
1188 free_page((unsigned long)c->tx_dma_buf[0]);
1189 c->tx_dma_buf[0]=NULL;
1190 }
1191 chk=read_zsreg(c,R0);
1192 write_zsreg(c, R3, c->regs[R3]);
1193 z8530_rtsdtr(c,0);
1194
1195 spin_unlock_irqrestore(c->lock, cflags);
1196 return 0;
1197}
1198
1199
1200EXPORT_SYMBOL(z8530_sync_txdma_close);
1201
1202
1203
1204
1205
1206
1207
1208static char *z8530_type_name[]={
1209 "Z8530",
1210 "Z85C30",
1211 "Z85230"
1212};
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225void z8530_describe(struct z8530_dev *dev, char *mapping, unsigned long io)
1226{
1227 printk(KERN_INFO "%s: %s found at %s 0x%lX, IRQ %d.\n",
1228 dev->name,
1229 z8530_type_name[dev->type],
1230 mapping,
1231 Z8530_PORT_OF(io),
1232 dev->irq);
1233}
1234
1235EXPORT_SYMBOL(z8530_describe);
1236
1237
1238
1239
1240
1241static inline int do_z8530_init(struct z8530_dev *dev)
1242{
1243
1244
1245 dev->chanA.irqs=&z8530_nop;
1246 dev->chanB.irqs=&z8530_nop;
1247 dev->chanA.dcdcheck=DCD;
1248 dev->chanB.dcdcheck=DCD;
1249
1250
1251 write_zsreg(&dev->chanA, R9, 0xC0);
1252 udelay(200);
1253
1254 write_zsreg(&dev->chanA, R12, 0xAA);
1255 if(read_zsreg(&dev->chanA, R12)!=0xAA)
1256 return -ENODEV;
1257 write_zsreg(&dev->chanA, R12, 0x55);
1258 if(read_zsreg(&dev->chanA, R12)!=0x55)
1259 return -ENODEV;
1260
1261 dev->type=Z8530;
1262
1263
1264
1265
1266
1267 write_zsreg(&dev->chanA, R15, 0x01);
1268
1269
1270
1271
1272
1273
1274 if(read_zsreg(&dev->chanA, R15)==0x01)
1275 {
1276
1277
1278 write_zsreg(&dev->chanA, R8, 0);
1279 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP)
1280 dev->type = Z85230;
1281 else
1282 dev->type = Z85C30;
1283 }
1284
1285
1286
1287
1288
1289
1290
1291 write_zsreg(&dev->chanA, R15, 0);
1292
1293
1294
1295
1296
1297 memcpy(dev->chanA.regs, reg_init, 16);
1298 memcpy(dev->chanB.regs, reg_init ,16);
1299
1300 return 0;
1301}
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320int z8530_init(struct z8530_dev *dev)
1321{
1322 unsigned long flags;
1323 int ret;
1324
1325
1326 spin_lock_init(&dev->lock);
1327 dev->chanA.lock = &dev->lock;
1328 dev->chanB.lock = &dev->lock;
1329
1330 spin_lock_irqsave(&dev->lock, flags);
1331 ret = do_z8530_init(dev);
1332 spin_unlock_irqrestore(&dev->lock, flags);
1333
1334 return ret;
1335}
1336
1337
1338EXPORT_SYMBOL(z8530_init);
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351int z8530_shutdown(struct z8530_dev *dev)
1352{
1353 unsigned long flags;
1354
1355
1356 spin_lock_irqsave(&dev->lock, flags);
1357 dev->chanA.irqs=&z8530_nop;
1358 dev->chanB.irqs=&z8530_nop;
1359 write_zsreg(&dev->chanA, R9, 0xC0);
1360
1361 udelay(100);
1362 spin_unlock_irqrestore(&dev->lock, flags);
1363 return 0;
1364}
1365
1366EXPORT_SYMBOL(z8530_shutdown);
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379int z8530_channel_load(struct z8530_channel *c, u8 *rtable)
1380{
1381 unsigned long flags;
1382
1383 spin_lock_irqsave(c->lock, flags);
1384
1385 while(*rtable!=255)
1386 {
1387 int reg=*rtable++;
1388 if(reg>0x0F)
1389 write_zsreg(c, R15, c->regs[15]|1);
1390 write_zsreg(c, reg&0x0F, *rtable);
1391 if(reg>0x0F)
1392 write_zsreg(c, R15, c->regs[15]&~1);
1393 c->regs[reg]=*rtable++;
1394 }
1395 c->rx_function=z8530_null_rx;
1396 c->skb=NULL;
1397 c->tx_skb=NULL;
1398 c->tx_next_skb=NULL;
1399 c->mtu=1500;
1400 c->max=0;
1401 c->count=0;
1402 c->status=read_zsreg(c, R0);
1403 c->sync=1;
1404 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1405
1406 spin_unlock_irqrestore(c->lock, flags);
1407 return 0;
1408}
1409
1410EXPORT_SYMBOL(z8530_channel_load);
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427static void z8530_tx_begin(struct z8530_channel *c)
1428{
1429 unsigned long flags;
1430 if(c->tx_skb)
1431 return;
1432
1433 c->tx_skb=c->tx_next_skb;
1434 c->tx_next_skb=NULL;
1435 c->tx_ptr=c->tx_next_ptr;
1436
1437 if(c->tx_skb==NULL)
1438 {
1439
1440 if(c->dma_tx)
1441 {
1442 flags=claim_dma_lock();
1443 disable_dma(c->txdma);
1444
1445
1446
1447 if (get_dma_residue(c->txdma))
1448 {
1449 c->netdevice->stats.tx_dropped++;
1450 c->netdevice->stats.tx_fifo_errors++;
1451 }
1452 release_dma_lock(flags);
1453 }
1454 c->txcount=0;
1455 }
1456 else
1457 {
1458 c->txcount=c->tx_skb->len;
1459
1460
1461 if(c->dma_tx)
1462 {
1463
1464
1465
1466
1467
1468
1469
1470 flags=claim_dma_lock();
1471 disable_dma(c->txdma);
1472
1473
1474
1475
1476
1477
1478 if(c->dev->type!=Z85230)
1479 {
1480 write_zsctrl(c, RES_Tx_CRC);
1481 write_zsctrl(c, RES_EOM_L);
1482 }
1483 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
1484 clear_dma_ff(c->txdma);
1485 set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr));
1486 set_dma_count(c->txdma, c->txcount);
1487 enable_dma(c->txdma);
1488 release_dma_lock(flags);
1489 write_zsctrl(c, RES_EOM_L);
1490 write_zsreg(c, R5, c->regs[R5]|TxENAB);
1491 }
1492 else
1493 {
1494
1495
1496 write_zsreg(c, R10, c->regs[10]);
1497 write_zsctrl(c, RES_Tx_CRC);
1498
1499 while(c->txcount && (read_zsreg(c,R0)&Tx_BUF_EMP))
1500 {
1501 write_zsreg(c, R8, *c->tx_ptr++);
1502 c->txcount--;
1503 }
1504
1505 }
1506 }
1507
1508
1509
1510 netif_wake_queue(c->netdevice);
1511}
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524static void z8530_tx_done(struct z8530_channel *c)
1525{
1526 struct sk_buff *skb;
1527
1528
1529 if (c->tx_skb == NULL)
1530 return;
1531
1532 skb = c->tx_skb;
1533 c->tx_skb = NULL;
1534 z8530_tx_begin(c);
1535 c->netdevice->stats.tx_packets++;
1536 c->netdevice->stats.tx_bytes += skb->len;
1537 dev_kfree_skb_irq(skb);
1538}
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb)
1550{
1551 dev_kfree_skb_any(skb);
1552}
1553
1554EXPORT_SYMBOL(z8530_null_rx);
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569static void z8530_rx_done(struct z8530_channel *c)
1570{
1571 struct sk_buff *skb;
1572 int ct;
1573
1574
1575
1576
1577
1578 if(c->rxdma_on)
1579 {
1580
1581
1582
1583
1584
1585 int ready=c->dma_ready;
1586 unsigned char *rxb=c->rx_buf[c->dma_num];
1587 unsigned long flags;
1588
1589
1590
1591
1592
1593 flags=claim_dma_lock();
1594
1595 disable_dma(c->rxdma);
1596 clear_dma_ff(c->rxdma);
1597 c->rxdma_on=0;
1598 ct=c->mtu-get_dma_residue(c->rxdma);
1599 if(ct<0)
1600 ct=2;
1601 c->dma_ready=0;
1602
1603
1604
1605
1606
1607
1608 if(ready)
1609 {
1610 c->dma_num^=1;
1611 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
1612 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num]));
1613 set_dma_count(c->rxdma, c->mtu);
1614 c->rxdma_on = 1;
1615 enable_dma(c->rxdma);
1616
1617
1618 write_zsreg(c, R0, RES_Rx_CRC);
1619 }
1620 else
1621
1622
1623 printk(KERN_WARNING "%s: DMA flip overrun!\n",
1624 c->netdevice->name);
1625
1626 release_dma_lock(flags);
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636 skb = dev_alloc_skb(ct);
1637 if (skb == NULL) {
1638 c->netdevice->stats.rx_dropped++;
1639 printk(KERN_WARNING "%s: Memory squeeze.\n",
1640 c->netdevice->name);
1641 } else {
1642 skb_put(skb, ct);
1643 skb_copy_to_linear_data(skb, rxb, ct);
1644 c->netdevice->stats.rx_packets++;
1645 c->netdevice->stats.rx_bytes += ct;
1646 }
1647 c->dma_ready = 1;
1648 } else {
1649 RT_LOCK;
1650 skb = c->skb;
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664 ct=c->count;
1665
1666 c->skb = c->skb2;
1667 c->count = 0;
1668 c->max = c->mtu;
1669 if (c->skb) {
1670 c->dptr = c->skb->data;
1671 c->max = c->mtu;
1672 } else {
1673 c->count = 0;
1674 c->max = 0;
1675 }
1676 RT_UNLOCK;
1677
1678 c->skb2 = dev_alloc_skb(c->mtu);
1679 if (c->skb2 == NULL)
1680 printk(KERN_WARNING "%s: memory squeeze.\n",
1681 c->netdevice->name);
1682 else
1683 skb_put(c->skb2, c->mtu);
1684 c->netdevice->stats.rx_packets++;
1685 c->netdevice->stats.rx_bytes += ct;
1686 }
1687
1688
1689
1690 if (skb) {
1691 skb_trim(skb, ct);
1692 c->rx_function(c, skb);
1693 } else {
1694 c->netdevice->stats.rx_dropped++;
1695 printk(KERN_ERR "%s: Lost a frame\n", c->netdevice->name);
1696 }
1697}
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707static inline int spans_boundary(struct sk_buff *skb)
1708{
1709 unsigned long a=(unsigned long)skb->data;
1710 a^=(a+skb->len);
1711 if(a&0x00010000)
1712 return 1;
1713 return 0;
1714}
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
1731{
1732 unsigned long flags;
1733
1734 netif_stop_queue(c->netdevice);
1735 if(c->tx_next_skb)
1736 return NETDEV_TX_BUSY;
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746 if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb)))
1747 {
1748
1749
1750
1751
1752
1753
1754
1755 c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used];
1756 c->tx_dma_used^=1;
1757 skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len);
1758 }
1759 else
1760 c->tx_next_ptr=skb->data;
1761 RT_LOCK;
1762 c->tx_next_skb=skb;
1763 RT_UNLOCK;
1764
1765 spin_lock_irqsave(c->lock, flags);
1766 z8530_tx_begin(c);
1767 spin_unlock_irqrestore(c->lock, flags);
1768
1769 return NETDEV_TX_OK;
1770}
1771
1772EXPORT_SYMBOL(z8530_queue_xmit);
1773
1774
1775
1776
1777static const char banner[] __initdata =
1778 KERN_INFO "Generic Z85C30/Z85230 interface driver v0.02\n";
1779
1780static int __init z85230_init_driver(void)
1781{
1782 printk(banner);
1783 return 0;
1784}
1785module_init(z85230_init_driver);
1786
1787static void __exit z85230_cleanup_driver(void)
1788{
1789}
1790module_exit(z85230_cleanup_driver);
1791
1792MODULE_AUTHOR("Red Hat Inc.");
1793MODULE_DESCRIPTION("Z85x30 synchronous driver core");
1794MODULE_LICENSE("GPL");
1795