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17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
28#include "reg.h"
29#include "phy.h"
30
31#include "../regd.h"
32
33#define ATHEROS_VENDOR_ID 0x168c
34#define AR5416_DEVID_PCI 0x0023
35#define AR5416_DEVID_PCIE 0x0024
36#define AR9160_DEVID_PCI 0x0027
37#define AR9280_DEVID_PCI 0x0029
38#define AR9280_DEVID_PCIE 0x002a
39#define AR9285_DEVID_PCIE 0x002b
40#define AR5416_AR9100_DEVID 0x000b
41#define AR_SUBVENDOR_ID_NOG 0x0e11
42#define AR_SUBVENDOR_ID_NEW_A 0x7065
43#define AR5416_MAGIC 0x19641014
44
45#define AR5416_DEVID_AR9287_PCI 0x002D
46#define AR5416_DEVID_AR9287_PCIE 0x002E
47
48#define AR9280_COEX2WIRE_SUBSYSID 0x309b
49#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
50#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
51
52
53#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
54#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
55
56#define SM(_v, _f) (((_v) << _f##_S) & _f)
57#define MS(_v, _f) (((_v) & _f) >> _f##_S)
58#define REG_RMW(_a, _r, _set, _clr) \
59 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
60#define REG_RMW_FIELD(_a, _r, _f, _v) \
61 REG_WRITE(_a, _r, \
62 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
63#define REG_SET_BIT(_a, _r, _f) \
64 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
65#define REG_CLR_BIT(_a, _r, _f) \
66 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
67
68#define DO_DELAY(x) do { \
69 if ((++(x) % 64) == 0) \
70 udelay(1); \
71 } while (0)
72
73#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
74 int r; \
75 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
76 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
77 INI_RA((iniarray), r, (column))); \
78 DO_DELAY(regWr); \
79 } \
80 } while (0)
81
82#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
83#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
84#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
85#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
86#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
87#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
88#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
89
90#define AR_GPIOD_MASK 0x00001FFF
91#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
92
93#define BASE_ACTIVATE_DELAY 100
94#define RTC_PLL_SETTLE_DELAY 1000
95#define COEF_SCALE_S 24
96#define HT40_CHANNEL_CENTER_SHIFT 10
97
98#define ATH9K_ANTENNA0_CHAINMASK 0x1
99#define ATH9K_ANTENNA1_CHAINMASK 0x2
100
101#define ATH9K_NUM_DMA_DEBUG_REGS 8
102#define ATH9K_NUM_QUEUES 10
103
104#define MAX_RATE_POWER 63
105#define AH_WAIT_TIMEOUT 100000
106#define AH_TSF_WRITE_TIMEOUT 100
107#define AH_TIME_QUANTUM 10
108#define AR_KEYTABLE_SIZE 128
109#define POWER_UP_TIME 10000
110#define SPUR_RSSI_THRESH 40
111
112#define CAB_TIMEOUT_VAL 10
113#define BEACON_TIMEOUT_VAL 10
114#define MIN_BEACON_TIMEOUT_VAL 1
115#define SLEEP_SLOP 3
116
117#define INIT_CONFIG_STATUS 0x00000000
118#define INIT_RSSI_THR 0x00000700
119#define INIT_BCON_CNTRL_REG 0x00000000
120
121#define TU_TO_USEC(_tu) ((_tu) << 10)
122
123enum wireless_mode {
124 ATH9K_MODE_11A = 0,
125 ATH9K_MODE_11G,
126 ATH9K_MODE_11NA_HT20,
127 ATH9K_MODE_11NG_HT20,
128 ATH9K_MODE_11NA_HT40PLUS,
129 ATH9K_MODE_11NA_HT40MINUS,
130 ATH9K_MODE_11NG_HT40PLUS,
131 ATH9K_MODE_11NG_HT40MINUS,
132 ATH9K_MODE_MAX,
133};
134
135enum ath9k_ant_setting {
136 ATH9K_ANT_VARIABLE = 0,
137 ATH9K_ANT_FIXED_A,
138 ATH9K_ANT_FIXED_B
139};
140
141enum ath9k_hw_caps {
142 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
143 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
144 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
145 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
146 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
147 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
148 ATH9K_HW_CAP_VEOL = BIT(6),
149 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
150 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
151 ATH9K_HW_CAP_HT = BIT(9),
152 ATH9K_HW_CAP_GTT = BIT(10),
153 ATH9K_HW_CAP_FASTCC = BIT(11),
154 ATH9K_HW_CAP_RFSILENT = BIT(12),
155 ATH9K_HW_CAP_CST = BIT(13),
156 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
157 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
158 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
159};
160
161enum ath9k_capability_type {
162 ATH9K_CAP_CIPHER = 0,
163 ATH9K_CAP_TKIP_MIC,
164 ATH9K_CAP_TKIP_SPLIT,
165 ATH9K_CAP_DIVERSITY,
166 ATH9K_CAP_TXPOW,
167 ATH9K_CAP_MCAST_KEYSRCH,
168 ATH9K_CAP_DS
169};
170
171struct ath9k_hw_capabilities {
172 u32 hw_caps;
173 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX);
174 u16 total_queues;
175 u16 keycache_size;
176 u16 low_5ghz_chan, high_5ghz_chan;
177 u16 low_2ghz_chan, high_2ghz_chan;
178 u16 rts_aggr_limit;
179 u8 tx_chainmask;
180 u8 rx_chainmask;
181 u16 tx_triglevel_max;
182 u16 reg_cap;
183 u8 num_gpio_pins;
184 u8 num_antcfg_2ghz;
185 u8 num_antcfg_5ghz;
186};
187
188struct ath9k_ops_config {
189 int dma_beacon_response_time;
190 int sw_beacon_response_time;
191 int additional_swba_backoff;
192 int ack_6mb;
193 int cwm_ignore_extcca;
194 u8 pcie_powersave_enable;
195 u8 pcie_clock_req;
196 u32 pcie_waen;
197 u8 analog_shiftreg;
198 u8 ht_enable;
199 u32 ofdm_trig_low;
200 u32 ofdm_trig_high;
201 u32 cck_trig_high;
202 u32 cck_trig_low;
203 u32 enable_ani;
204 enum ath9k_ant_setting diversity_control;
205 u16 antenna_switch_swap;
206 int serialize_regmode;
207 bool intr_mitigation;
208#define SPUR_DISABLE 0
209#define SPUR_ENABLE_IOCTL 1
210#define SPUR_ENABLE_EEPROM 2
211#define AR_EEPROM_MODAL_SPURS 5
212#define AR_SPUR_5413_1 1640
213#define AR_SPUR_5413_2 1200
214#define AR_NO_SPUR 0x8000
215#define AR_BASE_FREQ_2GHZ 2300
216#define AR_BASE_FREQ_5GHZ 4900
217#define AR_SPUR_FEEQ_BOUND_HT40 19
218#define AR_SPUR_FEEQ_BOUND_HT20 10
219 int spurmode;
220 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
221};
222
223enum ath9k_int {
224 ATH9K_INT_RX = 0x00000001,
225 ATH9K_INT_RXDESC = 0x00000002,
226 ATH9K_INT_RXNOFRM = 0x00000008,
227 ATH9K_INT_RXEOL = 0x00000010,
228 ATH9K_INT_RXORN = 0x00000020,
229 ATH9K_INT_TX = 0x00000040,
230 ATH9K_INT_TXDESC = 0x00000080,
231 ATH9K_INT_TIM_TIMER = 0x00000100,
232 ATH9K_INT_TXURN = 0x00000800,
233 ATH9K_INT_MIB = 0x00001000,
234 ATH9K_INT_RXPHY = 0x00004000,
235 ATH9K_INT_RXKCM = 0x00008000,
236 ATH9K_INT_SWBA = 0x00010000,
237 ATH9K_INT_BMISS = 0x00040000,
238 ATH9K_INT_BNR = 0x00100000,
239 ATH9K_INT_TIM = 0x00200000,
240 ATH9K_INT_DTIM = 0x00400000,
241 ATH9K_INT_DTIMSYNC = 0x00800000,
242 ATH9K_INT_GPIO = 0x01000000,
243 ATH9K_INT_CABEND = 0x02000000,
244 ATH9K_INT_TSFOOR = 0x04000000,
245 ATH9K_INT_GENTIMER = 0x08000000,
246 ATH9K_INT_CST = 0x10000000,
247 ATH9K_INT_GTT = 0x20000000,
248 ATH9K_INT_FATAL = 0x40000000,
249 ATH9K_INT_GLOBAL = 0x80000000,
250 ATH9K_INT_BMISC = ATH9K_INT_TIM |
251 ATH9K_INT_DTIM |
252 ATH9K_INT_DTIMSYNC |
253 ATH9K_INT_TSFOOR |
254 ATH9K_INT_CABEND,
255 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
256 ATH9K_INT_RXDESC |
257 ATH9K_INT_RXEOL |
258 ATH9K_INT_RXORN |
259 ATH9K_INT_TXURN |
260 ATH9K_INT_TXDESC |
261 ATH9K_INT_MIB |
262 ATH9K_INT_RXPHY |
263 ATH9K_INT_RXKCM |
264 ATH9K_INT_SWBA |
265 ATH9K_INT_BMISS |
266 ATH9K_INT_GPIO,
267 ATH9K_INT_NOCARD = 0xffffffff
268};
269
270#define CHANNEL_CW_INT 0x00002
271#define CHANNEL_CCK 0x00020
272#define CHANNEL_OFDM 0x00040
273#define CHANNEL_2GHZ 0x00080
274#define CHANNEL_5GHZ 0x00100
275#define CHANNEL_PASSIVE 0x00200
276#define CHANNEL_DYN 0x00400
277#define CHANNEL_HALF 0x04000
278#define CHANNEL_QUARTER 0x08000
279#define CHANNEL_HT20 0x10000
280#define CHANNEL_HT40PLUS 0x20000
281#define CHANNEL_HT40MINUS 0x40000
282
283#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
284#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
285#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
286#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
287#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
288#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
289#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
290#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
291#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
292#define CHANNEL_ALL \
293 (CHANNEL_OFDM| \
294 CHANNEL_CCK| \
295 CHANNEL_2GHZ | \
296 CHANNEL_5GHZ | \
297 CHANNEL_HT20 | \
298 CHANNEL_HT40PLUS | \
299 CHANNEL_HT40MINUS)
300
301struct ath9k_channel {
302 struct ieee80211_channel *chan;
303 u16 channel;
304 u32 channelFlags;
305 u32 chanmode;
306 int32_t CalValid;
307 bool oneTimeCalsDone;
308 int8_t iCoff;
309 int8_t qCoff;
310 int16_t rawNoiseFloor;
311};
312
313#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
314 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
315 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
316 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
317#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
318#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
319#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
320#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
321#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
322#define IS_CHAN_A_5MHZ_SPACED(_c) \
323 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
324 (((_c)->channel % 20) != 0) && \
325 (((_c)->channel % 10) != 0))
326
327
328#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
329#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
330 ((_c)->chanmode == CHANNEL_G_HT20))
331#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
332 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
333 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
334 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
335#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
336
337enum ath9k_power_mode {
338 ATH9K_PM_AWAKE = 0,
339 ATH9K_PM_FULL_SLEEP,
340 ATH9K_PM_NETWORK_SLEEP,
341 ATH9K_PM_UNDEFINED
342};
343
344enum ath9k_tp_scale {
345 ATH9K_TP_SCALE_MAX = 0,
346 ATH9K_TP_SCALE_50,
347 ATH9K_TP_SCALE_25,
348 ATH9K_TP_SCALE_12,
349 ATH9K_TP_SCALE_MIN
350};
351
352enum ser_reg_mode {
353 SER_REG_MODE_OFF = 0,
354 SER_REG_MODE_ON = 1,
355 SER_REG_MODE_AUTO = 2,
356};
357
358struct ath9k_beacon_state {
359 u32 bs_nexttbtt;
360 u32 bs_nextdtim;
361 u32 bs_intval;
362#define ATH9K_BEACON_PERIOD 0x0000ffff
363#define ATH9K_BEACON_ENA 0x00800000
364#define ATH9K_BEACON_RESET_TSF 0x01000000
365#define ATH9K_TSFOOR_THRESHOLD 0x00004240
366 u32 bs_dtimperiod;
367 u16 bs_cfpperiod;
368 u16 bs_cfpmaxduration;
369 u32 bs_cfpnext;
370 u16 bs_timoffset;
371 u16 bs_bmissthreshold;
372 u32 bs_sleepduration;
373 u32 bs_tsfoor_threshold;
374};
375
376struct chan_centers {
377 u16 synth_center;
378 u16 ctl_center;
379 u16 ext_center;
380};
381
382enum {
383 ATH9K_RESET_POWER_ON,
384 ATH9K_RESET_WARM,
385 ATH9K_RESET_COLD,
386};
387
388struct ath9k_hw_version {
389 u32 magic;
390 u16 devid;
391 u16 subvendorid;
392 u32 macVersion;
393 u16 macRev;
394 u16 phyRev;
395 u16 analog5GhzRev;
396 u16 analog2GhzRev;
397 u16 subsysid;
398};
399
400
401
402#define ATH_MAX_GEN_TIMER 16
403
404#define AR_GENTMR_BIT(_index) (1 << (_index))
405
406
407
408
409
410#define debruijn32 0x077CB531UL
411
412struct ath_gen_timer_configuration {
413 u32 next_addr;
414 u32 period_addr;
415 u32 mode_addr;
416 u32 mode_mask;
417};
418
419struct ath_gen_timer {
420 void (*trigger)(void *arg);
421 void (*overflow)(void *arg);
422 void *arg;
423 u8 index;
424};
425
426struct ath_gen_timer_table {
427 u32 gen_timer_index[32];
428 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
429 union {
430 unsigned long timer_bits;
431 u16 val;
432 } timer_mask;
433};
434
435struct ath_hw {
436 struct ath_softc *ah_sc;
437 struct ath9k_hw_version hw_version;
438 struct ath9k_ops_config config;
439 struct ath9k_hw_capabilities caps;
440 struct ath9k_channel channels[38];
441 struct ath9k_channel *curchan;
442
443 union {
444 struct ar5416_eeprom_def def;
445 struct ar5416_eeprom_4k map4k;
446 struct ar9287_eeprom map9287;
447 } eeprom;
448 const struct eeprom_ops *eep_ops;
449 enum ath9k_eep_map eep_map;
450
451 bool sw_mgmt_crypto;
452 bool is_pciexpress;
453 u8 macaddr[ETH_ALEN];
454 u16 tx_trig_level;
455 u16 rfsilent;
456 u32 rfkill_gpio;
457 u32 rfkill_polarity;
458 u32 ah_flags;
459
460 bool htc_reset_init;
461
462 enum nl80211_iftype opmode;
463 enum ath9k_power_mode power_mode;
464
465 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
466 struct ath9k_pacal_info pacal_info;
467 struct ar5416Stats stats;
468 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
469
470 int16_t curchan_rad_index;
471 u32 mask_reg;
472 u32 txok_interrupt_mask;
473 u32 txerr_interrupt_mask;
474 u32 txdesc_interrupt_mask;
475 u32 txeol_interrupt_mask;
476 u32 txurn_interrupt_mask;
477 bool chip_fullsleep;
478 u32 atim_window;
479
480
481 enum ath9k_cal_types supp_cals;
482 struct ath9k_cal_list iq_caldata;
483 struct ath9k_cal_list adcgain_caldata;
484 struct ath9k_cal_list adcdc_calinitdata;
485 struct ath9k_cal_list adcdc_caldata;
486 struct ath9k_cal_list *cal_list;
487 struct ath9k_cal_list *cal_list_last;
488 struct ath9k_cal_list *cal_list_curr;
489#define totalPowerMeasI meas0.unsign
490#define totalPowerMeasQ meas1.unsign
491#define totalIqCorrMeas meas2.sign
492#define totalAdcIOddPhase meas0.unsign
493#define totalAdcIEvenPhase meas1.unsign
494#define totalAdcQOddPhase meas2.unsign
495#define totalAdcQEvenPhase meas3.unsign
496#define totalAdcDcOffsetIOddPhase meas0.sign
497#define totalAdcDcOffsetIEvenPhase meas1.sign
498#define totalAdcDcOffsetQOddPhase meas2.sign
499#define totalAdcDcOffsetQEvenPhase meas3.sign
500 union {
501 u32 unsign[AR5416_MAX_CHAINS];
502 int32_t sign[AR5416_MAX_CHAINS];
503 } meas0;
504 union {
505 u32 unsign[AR5416_MAX_CHAINS];
506 int32_t sign[AR5416_MAX_CHAINS];
507 } meas1;
508 union {
509 u32 unsign[AR5416_MAX_CHAINS];
510 int32_t sign[AR5416_MAX_CHAINS];
511 } meas2;
512 union {
513 u32 unsign[AR5416_MAX_CHAINS];
514 int32_t sign[AR5416_MAX_CHAINS];
515 } meas3;
516 u16 cal_samples;
517
518 u32 sta_id1_defaults;
519 u32 misc_mode;
520 enum {
521 AUTO_32KHZ,
522 USE_32KHZ,
523 DONT_USE_32KHZ,
524 } enable_32kHz_clock;
525
526
527 u32 *analogBank0Data;
528 u32 *analogBank1Data;
529 u32 *analogBank2Data;
530 u32 *analogBank3Data;
531 u32 *analogBank6Data;
532 u32 *analogBank6TPCData;
533 u32 *analogBank7Data;
534 u32 *addac5416_21;
535 u32 *bank6Temp;
536
537 int16_t txpower_indexoffset;
538 u32 beacon_interval;
539 u32 slottime;
540 u32 acktimeout;
541 u32 ctstimeout;
542 u32 globaltxtimeout;
543 u8 gbeacon_rate;
544
545
546 u32 proc_phyerr;
547 u32 aniperiod;
548 struct ar5416AniState *curani;
549 struct ar5416AniState ani[255];
550 int totalSizeDesired[5];
551 int coarse_high[5];
552 int coarse_low[5];
553 int firpwr[5];
554 enum ath9k_ani_cmd ani_function;
555
556 u32 intr_txqs;
557 enum ath9k_ht_extprotspacing extprotspacing;
558 u8 txchainmask;
559 u8 rxchainmask;
560
561 u32 originalGain[22];
562 int initPDADC;
563 int PDADCdelta;
564 u8 led_pin;
565
566 struct ar5416IniArray iniModes;
567 struct ar5416IniArray iniCommon;
568 struct ar5416IniArray iniBank0;
569 struct ar5416IniArray iniBB_RfGain;
570 struct ar5416IniArray iniBank1;
571 struct ar5416IniArray iniBank2;
572 struct ar5416IniArray iniBank3;
573 struct ar5416IniArray iniBank6;
574 struct ar5416IniArray iniBank6TPC;
575 struct ar5416IniArray iniBank7;
576 struct ar5416IniArray iniAddac;
577 struct ar5416IniArray iniPcieSerdes;
578 struct ar5416IniArray iniModesAdditional;
579 struct ar5416IniArray iniModesRxGain;
580 struct ar5416IniArray iniModesTxGain;
581
582 u32 intr_gen_timer_trigger;
583 u32 intr_gen_timer_thresh;
584 struct ath_gen_timer_table hw_gen_timers;
585};
586
587
588const char *ath9k_hw_probe(u16 vendorid, u16 devid);
589void ath9k_hw_detach(struct ath_hw *ah);
590int ath9k_hw_init(struct ath_hw *ah);
591void ath9k_hw_rf_free(struct ath_hw *ah);
592int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
593 bool bChannelChange);
594void ath9k_hw_fill_cap_info(struct ath_hw *ah);
595bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
596 u32 capability, u32 *result);
597bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
598 u32 capability, u32 setting, int *status);
599
600
601bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
602bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
603bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
604 const struct ath9k_keyval *k,
605 const u8 *mac);
606bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
607
608
609void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
610u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
611void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
612 u32 ah_signal_type);
613void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
614u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
615void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
616bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
617 enum ath9k_ant_setting settings,
618 struct ath9k_channel *chan,
619 u8 *tx_chainmask, u8 *rx_chainmask,
620 u8 *antenna_cfgd);
621
622
623bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
624u32 ath9k_hw_reverse_bits(u32 val, u32 n);
625bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
626u16 ath9k_hw_computetxtime(struct ath_hw *ah,
627 const struct ath_rate_table *rates,
628 u32 frameLen, u16 rateix, bool shortPreamble);
629void ath9k_hw_get_channel_centers(struct ath_hw *ah,
630 struct ath9k_channel *chan,
631 struct chan_centers *centers);
632u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
633void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
634bool ath9k_hw_phy_disable(struct ath_hw *ah);
635bool ath9k_hw_disable(struct ath_hw *ah);
636void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
637void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
638void ath9k_hw_setopmode(struct ath_hw *ah);
639void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
640void ath9k_hw_setbssidmask(struct ath_softc *sc);
641void ath9k_hw_write_associd(struct ath_softc *sc);
642u64 ath9k_hw_gettsf64(struct ath_hw *ah);
643void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
644void ath9k_hw_reset_tsf(struct ath_hw *ah);
645void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
646bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
647void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
648void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
649void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
650 const struct ath9k_beacon_state *bs);
651bool ath9k_hw_setpower(struct ath_hw *ah,
652 enum ath9k_power_mode mode);
653void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
654
655
656bool ath9k_hw_intrpend(struct ath_hw *ah);
657bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
658enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
659
660
661struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
662 void (*trigger)(void *),
663 void (*overflow)(void *),
664 void *arg,
665 u8 timer_index);
666void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer,
667 u32 timer_next, u32 timer_period);
668void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
669void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
670void ath_gen_timer_isr(struct ath_hw *hw);
671u32 ath9k_hw_gettsf32(struct ath_hw *ah);
672
673#define ATH_PCIE_CAP_LINK_CTRL 0x70
674#define ATH_PCIE_CAP_LINK_L0S 1
675#define ATH_PCIE_CAP_LINK_L1 2
676
677void ath_pcie_aspm_disable(struct ath_softc *sc);
678#endif
679
