1#ifndef B43_H_
2#define B43_H_
3
4#include <linux/kernel.h>
5#include <linux/spinlock.h>
6#include <linux/interrupt.h>
7#include <linux/hw_random.h>
8#include <linux/ssb/ssb.h>
9#include <net/mac80211.h>
10
11#include "debugfs.h"
12#include "leds.h"
13#include "rfkill.h"
14#include "lo.h"
15#include "phy_common.h"
16
17
18
19
20#define B43_SUPPORTED_FIRMWARE_ID "FW13"
21
22
23#ifdef CONFIG_B43_DEBUG
24# define B43_DEBUG 1
25#else
26# define B43_DEBUG 0
27#endif
28
29#define B43_RX_MAX_SSI 60
30
31
32#define B43_MMIO_DMA0_REASON 0x20
33#define B43_MMIO_DMA0_IRQ_MASK 0x24
34#define B43_MMIO_DMA1_REASON 0x28
35#define B43_MMIO_DMA1_IRQ_MASK 0x2C
36#define B43_MMIO_DMA2_REASON 0x30
37#define B43_MMIO_DMA2_IRQ_MASK 0x34
38#define B43_MMIO_DMA3_REASON 0x38
39#define B43_MMIO_DMA3_IRQ_MASK 0x3C
40#define B43_MMIO_DMA4_REASON 0x40
41#define B43_MMIO_DMA4_IRQ_MASK 0x44
42#define B43_MMIO_DMA5_REASON 0x48
43#define B43_MMIO_DMA5_IRQ_MASK 0x4C
44#define B43_MMIO_MACCTL 0x120
45#define B43_MMIO_MACCMD 0x124
46#define B43_MMIO_GEN_IRQ_REASON 0x128
47#define B43_MMIO_GEN_IRQ_MASK 0x12C
48#define B43_MMIO_RAM_CONTROL 0x130
49#define B43_MMIO_RAM_DATA 0x134
50#define B43_MMIO_PS_STATUS 0x140
51#define B43_MMIO_RADIO_HWENABLED_HI 0x158
52#define B43_MMIO_SHM_CONTROL 0x160
53#define B43_MMIO_SHM_DATA 0x164
54#define B43_MMIO_SHM_DATA_UNALIGNED 0x166
55#define B43_MMIO_XMITSTAT_0 0x170
56#define B43_MMIO_XMITSTAT_1 0x174
57#define B43_MMIO_REV3PLUS_TSF_LOW 0x180
58#define B43_MMIO_REV3PLUS_TSF_HIGH 0x184
59#define B43_MMIO_TSF_CFP_REP 0x188
60#define B43_MMIO_TSF_CFP_START 0x18C
61#define B43_MMIO_TSF_CFP_MAXDUR 0x190
62
63
64#define B43_MMIO_DMA32_BASE0 0x200
65#define B43_MMIO_DMA32_BASE1 0x220
66#define B43_MMIO_DMA32_BASE2 0x240
67#define B43_MMIO_DMA32_BASE3 0x260
68#define B43_MMIO_DMA32_BASE4 0x280
69#define B43_MMIO_DMA32_BASE5 0x2A0
70
71#define B43_MMIO_DMA64_BASE0 0x200
72#define B43_MMIO_DMA64_BASE1 0x240
73#define B43_MMIO_DMA64_BASE2 0x280
74#define B43_MMIO_DMA64_BASE3 0x2C0
75#define B43_MMIO_DMA64_BASE4 0x300
76#define B43_MMIO_DMA64_BASE5 0x340
77
78
79#define B43_MMIO_PIO_BASE0 0x300
80#define B43_MMIO_PIO_BASE1 0x310
81#define B43_MMIO_PIO_BASE2 0x320
82#define B43_MMIO_PIO_BASE3 0x330
83#define B43_MMIO_PIO_BASE4 0x340
84#define B43_MMIO_PIO_BASE5 0x350
85#define B43_MMIO_PIO_BASE6 0x360
86#define B43_MMIO_PIO_BASE7 0x370
87
88#define B43_MMIO_PIO11_BASE0 0x200
89#define B43_MMIO_PIO11_BASE1 0x240
90#define B43_MMIO_PIO11_BASE2 0x280
91#define B43_MMIO_PIO11_BASE3 0x2C0
92#define B43_MMIO_PIO11_BASE4 0x300
93#define B43_MMIO_PIO11_BASE5 0x340
94
95#define B43_MMIO_PHY_VER 0x3E0
96#define B43_MMIO_PHY_RADIO 0x3E2
97#define B43_MMIO_PHY0 0x3E6
98#define B43_MMIO_ANTENNA 0x3E8
99#define B43_MMIO_CHANNEL 0x3F0
100#define B43_MMIO_CHANNEL_EXT 0x3F4
101#define B43_MMIO_RADIO_CONTROL 0x3F6
102#define B43_MMIO_RADIO_DATA_HIGH 0x3F8
103#define B43_MMIO_RADIO_DATA_LOW 0x3FA
104#define B43_MMIO_PHY_CONTROL 0x3FC
105#define B43_MMIO_PHY_DATA 0x3FE
106#define B43_MMIO_MACFILTER_CONTROL 0x420
107#define B43_MMIO_MACFILTER_DATA 0x422
108#define B43_MMIO_RCMTA_COUNT 0x43C
109#define B43_MMIO_RADIO_HWENABLED_LO 0x49A
110#define B43_MMIO_GPIO_CONTROL 0x49C
111#define B43_MMIO_GPIO_MASK 0x49E
112#define B43_MMIO_TSF_CFP_START_LOW 0x604
113#define B43_MMIO_TSF_CFP_START_HIGH 0x606
114#define B43_MMIO_TSF_CFP_PRETBTT 0x612
115#define B43_MMIO_TSF_0 0x632
116#define B43_MMIO_TSF_1 0x634
117#define B43_MMIO_TSF_2 0x636
118#define B43_MMIO_TSF_3 0x638
119#define B43_MMIO_RNG 0x65A
120#define B43_MMIO_IFSCTL 0x688
121#define B43_MMIO_IFSCTL_USE_EDCF 0x0004
122#define B43_MMIO_POWERUP_DELAY 0x6A8
123#define B43_MMIO_BTCOEX_CTL 0x6B4
124#define B43_MMIO_BTCOEX_STAT 0x6B6
125#define B43_MMIO_BTCOEX_TXCTL 0x6B8
126
127
128#define B43_BFL_BTCOEXIST 0x0001
129#define B43_BFL_PACTRL 0x0002
130#define B43_BFL_AIRLINEMODE 0x0004
131#define B43_BFL_RSSI 0x0008
132#define B43_BFL_ENETSPI 0x0010
133#define B43_BFL_XTAL_NOSLOW 0x0020
134#define B43_BFL_CCKHIPWR 0x0040
135#define B43_BFL_ENETADM 0x0080
136#define B43_BFL_ENETVLAN 0x0100
137#define B43_BFL_AFTERBURNER 0x0200
138#define B43_BFL_NOPCI 0x0400
139#define B43_BFL_FEM 0x0800
140#define B43_BFL_EXTLNA 0x1000
141#define B43_BFL_HGPA 0x2000
142#define B43_BFL_BTCMOD 0x4000
143#define B43_BFL_ALTIQ 0x8000
144
145
146#define B43_BFH_NOPA 0x0001
147#define B43_BFH_RSSIINV 0x0002
148#define B43_BFH_PAREF 0x0004
149#define B43_BFH_3TSWITCH 0x0008
150
151#define B43_BFH_PHASESHIFT 0x0010
152#define B43_BFH_BUCKBOOST 0x0020
153#define B43_BFH_FEM_BT 0x0040
154
155
156
157#define B43_GPIO_CONTROL 0x6c
158
159
160enum {
161 B43_SHM_UCODE,
162 B43_SHM_SHARED,
163 B43_SHM_SCRATCH,
164 B43_SHM_HW,
165 B43_SHM_RCMTA,
166};
167
168#define B43_SHM_AUTOINC_R 0x0200
169#define B43_SHM_AUTOINC_W 0x0100
170#define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
171 B43_SHM_AUTOINC_W)
172
173
174#define B43_SHM_SH_WLCOREREV 0x0016
175#define B43_SHM_SH_PCTLWDPOS 0x0008
176#define B43_SHM_SH_RXPADOFF 0x0034
177#define B43_SHM_SH_FWCAPA 0x0042
178#define B43_SHM_SH_PHYVER 0x0050
179#define B43_SHM_SH_PHYTYPE 0x0052
180#define B43_SHM_SH_ANTSWAP 0x005C
181#define B43_SHM_SH_HOSTFLO 0x005E
182#define B43_SHM_SH_HOSTFMI 0x0060
183#define B43_SHM_SH_HOSTFHI 0x0062
184#define B43_SHM_SH_RFATT 0x0064
185#define B43_SHM_SH_RADAR 0x0066
186#define B43_SHM_SH_PHYTXNOI 0x006E
187#define B43_SHM_SH_RFRXSP1 0x0072
188#define B43_SHM_SH_CHAN 0x00A0
189#define B43_SHM_SH_CHAN_5GHZ 0x0100
190#define B43_SHM_SH_BCMCFIFOID 0x0108
191
192#define B43_SHM_SH_TSSI_CCK 0x0058
193#define B43_SHM_SH_TSSI_OFDM_A 0x0068
194#define B43_SHM_SH_TSSI_OFDM_G 0x0070
195#define B43_TSSI_MAX 0x7F
196
197#define B43_SHM_SH_SIZE01 0x0098
198#define B43_SHM_SH_SIZE23 0x009A
199#define B43_SHM_SH_SIZE45 0x009C
200#define B43_SHM_SH_SIZE67 0x009E
201
202#define B43_SHM_SH_JSSI0 0x0088
203#define B43_SHM_SH_JSSI1 0x008A
204#define B43_SHM_SH_JSSIAUX 0x008C
205
206#define B43_SHM_SH_DEFAULTIV 0x003C
207#define B43_SHM_SH_NRRXTRANS 0x003E
208#define B43_SHM_SH_KTP 0x0056
209#define B43_SHM_SH_TKIPTSCTTAK 0x0318
210#define B43_SHM_SH_KEYIDXBLOCK 0x05D4
211#define B43_SHM_SH_PSM 0x05F4
212
213#define B43_SHM_SH_EDCFSTAT 0x000E
214#define B43_SHM_SH_TXFCUR 0x0030
215#define B43_SHM_SH_EDCFQ 0x0240
216
217#define B43_SHM_SH_SLOTT 0x0010
218#define B43_SHM_SH_DTIMPER 0x0012
219#define B43_SHM_SH_NOSLPZNATDTIM 0x004C
220
221#define B43_SHM_SH_BTL0 0x0018
222#define B43_SHM_SH_BTL1 0x001A
223#define B43_SHM_SH_BTSFOFF 0x001C
224#define B43_SHM_SH_TIMBPOS 0x001E
225#define B43_SHM_SH_DTIMP 0x0012
226#define B43_SHM_SH_MCASTCOOKIE 0x00A8
227#define B43_SHM_SH_SFFBLIM 0x0044
228#define B43_SHM_SH_LFFBLIM 0x0046
229#define B43_SHM_SH_BEACPHYCTL 0x0054
230#define B43_SHM_SH_EXTNPHYCTL 0x00B0
231
232#define B43_SHM_SH_ACKCTSPHYCTL 0x0022
233
234#define B43_SHM_SH_PRSSID 0x0160
235#define B43_SHM_SH_PRSSIDLEN 0x0048
236#define B43_SHM_SH_PRTLEN 0x004A
237#define B43_SHM_SH_PRMAXTIME 0x0074
238#define B43_SHM_SH_PRPHYCTL 0x0188
239
240#define B43_SHM_SH_OFDMDIRECT 0x01C0
241#define B43_SHM_SH_OFDMBASIC 0x01E0
242#define B43_SHM_SH_CCKDIRECT 0x0200
243#define B43_SHM_SH_CCKBASIC 0x0220
244
245#define B43_SHM_SH_UCODEREV 0x0000
246#define B43_SHM_SH_UCODEPATCH 0x0002
247#define B43_SHM_SH_UCODEDATE 0x0004
248#define B43_SHM_SH_UCODETIME 0x0006
249#define B43_SHM_SH_UCODESTAT 0x0040
250#define B43_SHM_SH_UCODESTAT_INVALID 0
251#define B43_SHM_SH_UCODESTAT_INIT 1
252#define B43_SHM_SH_UCODESTAT_ACTIVE 2
253#define B43_SHM_SH_UCODESTAT_SUSP 3
254#define B43_SHM_SH_UCODESTAT_SLEEP 4
255#define B43_SHM_SH_MAXBFRAMES 0x0080
256#define B43_SHM_SH_SPUWKUP 0x0094
257#define B43_SHM_SH_PRETBTT 0x0096
258
259
260#define B43_SHM_SC_MINCONT 0x0003
261#define B43_SHM_SC_MAXCONT 0x0004
262#define B43_SHM_SC_CURCONT 0x0005
263#define B43_SHM_SC_SRLIMIT 0x0006
264#define B43_SHM_SC_LRLIMIT 0x0007
265#define B43_SHM_SC_DTIMC 0x0008
266#define B43_SHM_SC_BTL0LEN 0x0015
267#define B43_SHM_SC_BTL1LEN 0x0016
268#define B43_SHM_SC_SCFB 0x0017
269#define B43_SHM_SC_LCFB 0x0018
270
271
272#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
273#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
274
275
276#define B43_HF_ANTDIVHELP 0x000000000001ULL
277#define B43_HF_SYMW 0x000000000002ULL
278#define B43_HF_RXPULLW 0x000000000004ULL
279#define B43_HF_CCKBOOST 0x000000000008ULL
280#define B43_HF_BTCOEX 0x000000000010ULL
281#define B43_HF_GDCW 0x000000000020ULL
282#define B43_HF_OFDMPABOOST 0x000000000040ULL
283#define B43_HF_ACPR 0x000000000080ULL
284#define B43_HF_EDCF 0x000000000100ULL
285#define B43_HF_TSSIRPSMW 0x000000000200ULL
286#define B43_HF_20IN40IQW 0x000000000200ULL
287#define B43_HF_DSCRQ 0x000000000400ULL
288#define B43_HF_ACIW 0x000000000800ULL
289#define B43_HF_2060W 0x000000001000ULL
290#define B43_HF_RADARW 0x000000002000ULL
291#define B43_HF_USEDEFKEYS 0x000000004000ULL
292#define B43_HF_AFTERBURNER 0x000000008000ULL
293#define B43_HF_BT4PRIOCOEX 0x000000010000ULL
294#define B43_HF_FWKUP 0x000000020000ULL
295#define B43_HF_VCORECALC 0x000000040000ULL
296#define B43_HF_PCISCW 0x000000080000ULL
297#define B43_HF_4318TSSI 0x000000200000ULL
298#define B43_HF_FBCMCFIFO 0x000000400000ULL
299#define B43_HF_HWPCTL 0x000000800000ULL
300#define B43_HF_BTCOEXALT 0x000001000000ULL
301#define B43_HF_TXBTCHECK 0x000002000000ULL
302#define B43_HF_SKCFPUP 0x000004000000ULL
303#define B43_HF_N40W 0x000008000000ULL
304#define B43_HF_ANTSEL 0x000020000000ULL
305#define B43_HF_BT3COEXT 0x000020000000ULL
306#define B43_HF_BTCANT 0x000040000000ULL
307#define B43_HF_ANTSELEN 0x000100000000ULL
308#define B43_HF_ANTSELMODE 0x000200000000ULL
309#define B43_HF_MLADVW 0x001000000000ULL
310#define B43_HF_PR45960W 0x080000000000ULL
311
312
313#define B43_FWCAPA_HWCRYPTO 0x0001
314#define B43_FWCAPA_QOS 0x0002
315
316
317#define B43_MACFILTER_SELF 0x0000
318#define B43_MACFILTER_BSSID 0x0003
319
320
321#define B43_PCTL_IN 0xB0
322#define B43_PCTL_OUT 0xB4
323#define B43_PCTL_OUTENABLE 0xB8
324#define B43_PCTL_XTAL_POWERUP 0x40
325#define B43_PCTL_PLL_POWERDOWN 0x80
326
327
328#define B43_PCTL_CLK_FAST 0x00
329#define B43_PCTL_CLK_SLOW 0x01
330#define B43_PCTL_CLK_DYNAMIC 0x02
331
332#define B43_PCTL_FORCE_SLOW 0x0800
333#define B43_PCTL_FORCE_PLL 0x1000
334#define B43_PCTL_DYN_XTAL 0x2000
335
336
337#define B43_PHYTYPE_A 0x00
338#define B43_PHYTYPE_B 0x01
339#define B43_PHYTYPE_G 0x02
340#define B43_PHYTYPE_N 0x04
341#define B43_PHYTYPE_LP 0x05
342
343
344#define B43_PHY_ILT_A_CTRL 0x0072
345#define B43_PHY_ILT_A_DATA1 0x0073
346#define B43_PHY_ILT_A_DATA2 0x0074
347#define B43_PHY_G_LO_CONTROL 0x0810
348#define B43_PHY_ILT_G_CTRL 0x0472
349#define B43_PHY_ILT_G_DATA1 0x0473
350#define B43_PHY_ILT_G_DATA2 0x0474
351#define B43_PHY_A_PCTL 0x007B
352#define B43_PHY_G_PCTL 0x0029
353#define B43_PHY_A_CRS 0x0029
354#define B43_PHY_RADIO_BITFIELD 0x0401
355#define B43_PHY_G_CRS 0x0429
356#define B43_PHY_NRSSILT_CTRL 0x0803
357#define B43_PHY_NRSSILT_DATA 0x0804
358
359
360#define B43_RADIOCTL_ID 0x01
361
362
363#define B43_MACCTL_ENABLED 0x00000001
364#define B43_MACCTL_PSM_RUN 0x00000002
365#define B43_MACCTL_PSM_JMP0 0x00000004
366#define B43_MACCTL_SHM_ENABLED 0x00000100
367#define B43_MACCTL_SHM_UPPER 0x00000200
368#define B43_MACCTL_IHR_ENABLED 0x00000400
369#define B43_MACCTL_PSM_DBG 0x00002000
370#define B43_MACCTL_GPOUTSMSK 0x0000C000
371#define B43_MACCTL_BE 0x00010000
372#define B43_MACCTL_INFRA 0x00020000
373#define B43_MACCTL_AP 0x00040000
374#define B43_MACCTL_RADIOLOCK 0x00080000
375#define B43_MACCTL_BEACPROMISC 0x00100000
376#define B43_MACCTL_KEEP_BADPLCP 0x00200000
377#define B43_MACCTL_KEEP_CTL 0x00400000
378#define B43_MACCTL_KEEP_BAD 0x00800000
379#define B43_MACCTL_PROMISC 0x01000000
380#define B43_MACCTL_HWPS 0x02000000
381#define B43_MACCTL_AWAKE 0x04000000
382#define B43_MACCTL_CLOSEDNET 0x08000000
383#define B43_MACCTL_TBTTHOLD 0x10000000
384#define B43_MACCTL_DISCTXSTAT 0x20000000
385#define B43_MACCTL_DISCPMQ 0x40000000
386#define B43_MACCTL_GMODE 0x80000000
387
388
389#define B43_MACCMD_BEACON0_VALID 0x00000001
390#define B43_MACCMD_BEACON1_VALID 0x00000002
391#define B43_MACCMD_DFQ_VALID 0x00000004
392#define B43_MACCMD_CCA 0x00000008
393#define B43_MACCMD_BGNOISE 0x00000010
394
395
396#define B43_TMSLOW_GMODE 0x20000000
397#define B43_TMSLOW_PHYCLKSPEED 0x00C00000
398#define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x00000000
399#define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x00400000
400#define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000
401#define B43_TMSLOW_PLLREFSEL 0x00200000
402#define B43_TMSLOW_MACPHYCLKEN 0x00100000
403#define B43_TMSLOW_PHYRESET 0x00080000
404#define B43_TMSLOW_PHYCLKEN 0x00040000
405
406
407#define B43_TMSHIGH_DUALBAND_PHY 0x00080000
408#define B43_TMSHIGH_FCLOCK 0x00040000
409#define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000
410#define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000
411
412
413#define B43_IRQ_MAC_SUSPENDED 0x00000001
414#define B43_IRQ_BEACON 0x00000002
415#define B43_IRQ_TBTT_INDI 0x00000004
416#define B43_IRQ_BEACON_TX_OK 0x00000008
417#define B43_IRQ_BEACON_CANCEL 0x00000010
418#define B43_IRQ_ATIM_END 0x00000020
419#define B43_IRQ_PMQ 0x00000040
420#define B43_IRQ_PIO_WORKAROUND 0x00000100
421#define B43_IRQ_MAC_TXERR 0x00000200
422#define B43_IRQ_PHY_TXERR 0x00000800
423#define B43_IRQ_PMEVENT 0x00001000
424#define B43_IRQ_TIMER0 0x00002000
425#define B43_IRQ_TIMER1 0x00004000
426#define B43_IRQ_DMA 0x00008000
427#define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
428#define B43_IRQ_CCA_MEASURE_OK 0x00020000
429#define B43_IRQ_NOISESAMPLE_OK 0x00040000
430#define B43_IRQ_UCODE_DEBUG 0x08000000
431#define B43_IRQ_RFKILL 0x10000000
432#define B43_IRQ_TX_OK 0x20000000
433#define B43_IRQ_PHY_G_CHANGED 0x40000000
434#define B43_IRQ_TIMEOUT 0x80000000
435
436#define B43_IRQ_ALL 0xFFFFFFFF
437#define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
438 B43_IRQ_ATIM_END | \
439 B43_IRQ_PMQ | \
440 B43_IRQ_MAC_TXERR | \
441 B43_IRQ_PHY_TXERR | \
442 B43_IRQ_DMA | \
443 B43_IRQ_TXFIFO_FLUSH_OK | \
444 B43_IRQ_NOISESAMPLE_OK | \
445 B43_IRQ_UCODE_DEBUG | \
446 B43_IRQ_RFKILL | \
447 B43_IRQ_TX_OK)
448
449
450#define B43_DEBUGIRQ_REASON_REG 63
451
452#define B43_DEBUGIRQ_PANIC 0
453#define B43_DEBUGIRQ_DUMP_SHM 1
454#define B43_DEBUGIRQ_DUMP_REGS 2
455#define B43_DEBUGIRQ_MARKER 3
456#define B43_DEBUGIRQ_ACK 0xFFFF
457
458
459#define B43_MARKER_ID_REG 2
460#define B43_MARKER_LINE_REG 3
461
462
463#define B43_FWPANIC_REASON_REG 3
464
465#define B43_FWPANIC_DIE 0
466#define B43_FWPANIC_RESTART 1
467
468
469#define B43_WATCHDOG_REG 1
470
471
472
473
474#define B43_CCK_RATE_1MB 0x02
475#define B43_CCK_RATE_2MB 0x04
476#define B43_CCK_RATE_5MB 0x0B
477#define B43_CCK_RATE_11MB 0x16
478#define B43_OFDM_RATE_6MB 0x0C
479#define B43_OFDM_RATE_9MB 0x12
480#define B43_OFDM_RATE_12MB 0x18
481#define B43_OFDM_RATE_18MB 0x24
482#define B43_OFDM_RATE_24MB 0x30
483#define B43_OFDM_RATE_36MB 0x48
484#define B43_OFDM_RATE_48MB 0x60
485#define B43_OFDM_RATE_54MB 0x6C
486
487#define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
488
489#define B43_DEFAULT_SHORT_RETRY_LIMIT 7
490#define B43_DEFAULT_LONG_RETRY_LIMIT 4
491
492#define B43_PHY_TX_BADNESS_LIMIT 1000
493
494
495#define B43_SEC_KEYSIZE 16
496
497#define B43_NR_GROUP_KEYS 4
498
499#define B43_NR_PAIRWISE_KEYS 50
500
501enum {
502 B43_SEC_ALGO_NONE = 0,
503 B43_SEC_ALGO_WEP40,
504 B43_SEC_ALGO_TKIP,
505 B43_SEC_ALGO_AES,
506 B43_SEC_ALGO_WEP104,
507 B43_SEC_ALGO_AES_LEGACY,
508};
509
510struct b43_dmaring;
511
512
513#define B43_FW_TYPE_UCODE 'u'
514#define B43_FW_TYPE_PCM 'p'
515#define B43_FW_TYPE_IV 'i'
516struct b43_fw_header {
517
518 u8 type;
519
520 u8 ver;
521 u8 __padding[2];
522
523
524 __be32 size;
525} __attribute__((__packed__));
526
527
528#define B43_IV_OFFSET_MASK 0x7FFF
529#define B43_IV_32BIT 0x8000
530struct b43_iv {
531 __be16 offset_size;
532 union {
533 __be16 d16;
534 __be32 d32;
535 } data __attribute__((__packed__));
536} __attribute__((__packed__));
537
538
539
540struct b43_dma {
541 struct b43_dmaring *tx_ring_AC_BK;
542 struct b43_dmaring *tx_ring_AC_BE;
543 struct b43_dmaring *tx_ring_AC_VI;
544 struct b43_dmaring *tx_ring_AC_VO;
545 struct b43_dmaring *tx_ring_mcast;
546
547 struct b43_dmaring *rx_ring;
548};
549
550struct b43_pio_txqueue;
551struct b43_pio_rxqueue;
552
553
554struct b43_pio {
555 struct b43_pio_txqueue *tx_queue_AC_BK;
556 struct b43_pio_txqueue *tx_queue_AC_BE;
557 struct b43_pio_txqueue *tx_queue_AC_VI;
558 struct b43_pio_txqueue *tx_queue_AC_VO;
559 struct b43_pio_txqueue *tx_queue_mcast;
560
561 struct b43_pio_rxqueue *rx_queue;
562};
563
564
565struct b43_noise_calculation {
566 bool calculation_running;
567 u8 nr_samples;
568 s8 samples[8][4];
569};
570
571struct b43_stats {
572 u8 link_noise;
573};
574
575struct b43_key {
576
577
578
579 struct ieee80211_key_conf *keyconf;
580 u8 algorithm;
581};
582
583
584#define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
585 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
586#define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
587#define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
588#define B43_QOS_VIDEO B43_QOS_PARAMS(2)
589#define B43_QOS_VOICE B43_QOS_PARAMS(3)
590
591
592#define B43_NR_QOSPARAMS 16
593enum {
594 B43_QOSPARAM_TXOP = 0,
595 B43_QOSPARAM_CWMIN,
596 B43_QOSPARAM_CWMAX,
597 B43_QOSPARAM_CWCUR,
598 B43_QOSPARAM_AIFS,
599 B43_QOSPARAM_BSLOTS,
600 B43_QOSPARAM_REGGAP,
601 B43_QOSPARAM_STATUS,
602};
603
604
605struct b43_qos_params {
606
607 struct ieee80211_tx_queue_params p;
608};
609
610struct b43_wl;
611
612
613enum b43_firmware_file_type {
614 B43_FWTYPE_PROPRIETARY,
615 B43_FWTYPE_OPENSOURCE,
616 B43_NR_FWTYPES,
617};
618
619
620struct b43_request_fw_context {
621
622 struct b43_wldev *dev;
623
624 enum b43_firmware_file_type req_type;
625
626 char errors[B43_NR_FWTYPES][128];
627
628 char fwname[64];
629
630
631 int fatal_failure;
632};
633
634
635struct b43_firmware_file {
636 const char *filename;
637 const struct firmware *data;
638
639
640
641
642
643
644 enum b43_firmware_file_type type;
645};
646
647
648struct b43_firmware {
649
650 struct b43_firmware_file ucode;
651
652 struct b43_firmware_file pcm;
653
654 struct b43_firmware_file initvals;
655
656 struct b43_firmware_file initvals_band;
657
658
659 u16 rev;
660
661 u16 patch;
662
663
664
665 bool opensource;
666
667
668
669 bool pcm_request_failed;
670};
671
672
673enum {
674 B43_STAT_UNINIT = 0,
675 B43_STAT_INITIALIZED = 1,
676 B43_STAT_STARTED = 2,
677};
678#define b43_status(wldev) atomic_read(&(wldev)->__init_status)
679#define b43_set_status(wldev, stat) do { \
680 atomic_set(&(wldev)->__init_status, (stat)); \
681 smp_wmb(); \
682 } while (0)
683
684
685struct b43_wldev {
686 struct ssb_device *dev;
687 struct b43_wl *wl;
688
689
690
691 atomic_t __init_status;
692
693 bool bad_frames_preempt;
694 bool dfq_valid;
695 bool radio_hw_enable;
696 bool qos_enabled;
697 bool hwcrypto_enabled;
698
699
700 struct b43_phy phy;
701
702 union {
703
704 struct b43_dma dma;
705
706 struct b43_pio pio;
707 };
708
709
710 bool __using_pio_transfers;
711
712
713 struct b43_stats stats;
714
715
716 u32 irq_reason;
717 u32 dma_reason[6];
718
719 u32 irq_mask;
720
721
722 struct b43_noise_calculation noisecalc;
723
724 int mac_suspended;
725
726
727 struct delayed_work periodic_work;
728 unsigned int periodic_state;
729
730 struct work_struct restart_work;
731
732
733 u16 ktp;
734 struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS];
735
736
737 struct b43_firmware fw;
738
739
740 struct list_head list;
741
742
743#ifdef CONFIG_B43_DEBUG
744 struct b43_dfsentry *dfsentry;
745 unsigned int irq_count;
746 unsigned int irq_bit_count[32];
747 unsigned int tx_count;
748 unsigned int rx_count;
749#endif
750};
751
752
753
754
755
756#include "xmit.h"
757
758
759struct b43_wl {
760
761 struct b43_wldev *current_dev;
762
763 struct ieee80211_hw *hw;
764
765
766 struct mutex mutex;
767
768
769 spinlock_t hardirq_lock;
770
771
772
773
774
775
776 u16 mac80211_initially_registered_queues;
777
778
779
780
781
782 struct ieee80211_vif *vif;
783
784 u8 mac_addr[ETH_ALEN];
785
786 u8 bssid[ETH_ALEN];
787
788 int if_type;
789
790 bool operating;
791
792 unsigned int filter_flags;
793
794 struct ieee80211_low_level_stats ieee_stats;
795
796#ifdef CONFIG_B43_HWRNG
797 struct hwrng rng;
798 bool rng_initialized;
799 char rng_name[30 + 1];
800#endif
801
802
803 struct list_head devlist;
804 u8 nr_devs;
805
806 bool radiotap_enabled;
807 bool radio_enabled;
808
809
810 struct sk_buff *current_beacon;
811 bool beacon0_uploaded;
812 bool beacon1_uploaded;
813 bool beacon_templates_virgin;
814 struct work_struct beacon_update_trigger;
815
816
817 struct b43_qos_params qos_params[4];
818
819
820
821
822 struct work_struct txpower_adjust_work;
823
824
825 struct work_struct tx_work;
826
827 struct sk_buff_head tx_queue;
828
829
830 struct b43_leds leds;
831
832#ifdef CONFIG_B43_PIO
833
834
835
836 struct b43_rxhdr_fw4 rxhdr;
837 struct b43_txhdr txhdr;
838 u8 rx_tail[4];
839 u8 tx_tail[4];
840#endif
841};
842
843static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
844{
845 return hw->priv;
846}
847
848static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
849{
850 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
851 return ssb_get_drvdata(ssb_dev);
852}
853
854
855static inline int b43_is_mode(struct b43_wl *wl, int type)
856{
857 return (wl->operating && wl->if_type == type);
858}
859
860
861
862
863
864static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
865{
866 return wl->hw->conf.channel->band;
867}
868
869static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
870{
871 return ssb_read16(dev->dev, offset);
872}
873
874static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
875{
876 ssb_write16(dev->dev, offset, value);
877}
878
879static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
880{
881 return ssb_read32(dev->dev, offset);
882}
883
884static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
885{
886 ssb_write32(dev->dev, offset, value);
887}
888
889static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
890{
891#ifdef CONFIG_B43_PIO
892 return dev->__using_pio_transfers;
893#else
894 return 0;
895#endif
896}
897
898#ifdef CONFIG_B43_FORCE_PIO
899# define B43_FORCE_PIO 1
900#else
901# define B43_FORCE_PIO 0
902#endif
903
904
905
906void b43info(struct b43_wl *wl, const char *fmt, ...)
907 __attribute__ ((format(printf, 2, 3)));
908void b43err(struct b43_wl *wl, const char *fmt, ...)
909 __attribute__ ((format(printf, 2, 3)));
910void b43warn(struct b43_wl *wl, const char *fmt, ...)
911 __attribute__ ((format(printf, 2, 3)));
912void b43dbg(struct b43_wl *wl, const char *fmt, ...)
913 __attribute__ ((format(printf, 2, 3)));
914
915
916
917
918#if B43_DEBUG
919# define B43_WARN_ON(x) WARN_ON(x)
920#else
921static inline bool __b43_warn_on_dummy(bool x) { return x; }
922# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
923#endif
924
925
926#define INT_TO_Q52(i) ((i) << 2)
927
928#define Q52_TO_INT(q52) ((q52) >> 2)
929
930#define Q52_FMT "%u.%u"
931#define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
932
933#endif
934