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29#include "b43.h"
30#include "phy_g.h"
31#include "phy_common.h"
32#include "lo.h"
33#include "main.h"
34
35#include <linux/bitrev.h>
36
37
38static const s8 b43_tssi2dbm_g_table[] = {
39 77, 77, 77, 76,
40 76, 76, 75, 75,
41 74, 74, 73, 73,
42 73, 72, 72, 71,
43 71, 70, 70, 69,
44 68, 68, 67, 67,
45 66, 65, 65, 64,
46 63, 63, 62, 61,
47 60, 59, 58, 57,
48 56, 55, 54, 53,
49 52, 50, 49, 47,
50 45, 43, 40, 37,
51 33, 28, 22, 14,
52 5, -7, -20, -20,
53 -20, -20, -20, -20,
54 -20, -20, -20, -20,
55};
56
57static const u8 b43_radio_channel_codes_bg[] = {
58 12, 17, 22, 27,
59 32, 37, 42, 47,
60 52, 57, 62, 67,
61 72, 84,
62};
63
64
65static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
66
67
68#define bitrev4(tmp) (bitrev8(tmp) >> 4)
69
70
71
72static inline u16 channel2freq_bg(u8 channel)
73{
74 B43_WARN_ON(!(channel >= 1 && channel <= 14));
75
76 return b43_radio_channel_codes_bg[channel - 1];
77}
78
79static void generate_rfatt_list(struct b43_wldev *dev,
80 struct b43_rfatt_list *list)
81{
82 struct b43_phy *phy = &dev->phy;
83
84
85 static const struct b43_rfatt rfatt_0[] = {
86 {.att = 3,.with_padmix = 0,},
87 {.att = 1,.with_padmix = 0,},
88 {.att = 5,.with_padmix = 0,},
89 {.att = 7,.with_padmix = 0,},
90 {.att = 9,.with_padmix = 0,},
91 {.att = 2,.with_padmix = 0,},
92 {.att = 0,.with_padmix = 0,},
93 {.att = 4,.with_padmix = 0,},
94 {.att = 6,.with_padmix = 0,},
95 {.att = 8,.with_padmix = 0,},
96 {.att = 1,.with_padmix = 1,},
97 {.att = 2,.with_padmix = 1,},
98 {.att = 3,.with_padmix = 1,},
99 {.att = 4,.with_padmix = 1,},
100 };
101
102 static const struct b43_rfatt rfatt_1[] = {
103 {.att = 2,.with_padmix = 1,},
104 {.att = 4,.with_padmix = 1,},
105 {.att = 6,.with_padmix = 1,},
106 {.att = 8,.with_padmix = 1,},
107 {.att = 10,.with_padmix = 1,},
108 {.att = 12,.with_padmix = 1,},
109 {.att = 14,.with_padmix = 1,},
110 };
111
112 static const struct b43_rfatt rfatt_2[] = {
113 {.att = 0,.with_padmix = 1,},
114 {.att = 2,.with_padmix = 1,},
115 {.att = 4,.with_padmix = 1,},
116 {.att = 6,.with_padmix = 1,},
117 {.att = 8,.with_padmix = 1,},
118 {.att = 9,.with_padmix = 1,},
119 {.att = 9,.with_padmix = 1,},
120 };
121
122 if (!b43_has_hardware_pctl(dev)) {
123
124 list->list = rfatt_0;
125 list->len = ARRAY_SIZE(rfatt_0);
126 list->min_val = 0;
127 list->max_val = 9;
128 return;
129 }
130 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
131
132 list->list = rfatt_1;
133 list->len = ARRAY_SIZE(rfatt_1);
134 list->min_val = 0;
135 list->max_val = 14;
136 return;
137 }
138
139 list->list = rfatt_2;
140 list->len = ARRAY_SIZE(rfatt_2);
141 list->min_val = 0;
142 list->max_val = 9;
143}
144
145static void generate_bbatt_list(struct b43_wldev *dev,
146 struct b43_bbatt_list *list)
147{
148 static const struct b43_bbatt bbatt_0[] = {
149 {.att = 0,},
150 {.att = 1,},
151 {.att = 2,},
152 {.att = 3,},
153 {.att = 4,},
154 {.att = 5,},
155 {.att = 6,},
156 {.att = 7,},
157 {.att = 8,},
158 };
159
160 list->list = bbatt_0;
161 list->len = ARRAY_SIZE(bbatt_0);
162 list->min_val = 0;
163 list->max_val = 8;
164}
165
166static void b43_shm_clear_tssi(struct b43_wldev *dev)
167{
168 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
169 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
170 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
171 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
172}
173
174
175static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
176{
177 struct b43_phy *phy = &dev->phy;
178
179 might_sleep();
180
181 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
182
183 return;
184 }
185
186 if (channel <= 10) {
187 b43_write16(dev, B43_MMIO_CHANNEL,
188 channel2freq_bg(channel + 4));
189 } else {
190 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
191 }
192 msleep(1);
193 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
194}
195
196
197void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
198 u16 baseband_attenuation)
199{
200 struct b43_phy *phy = &dev->phy;
201
202 if (phy->analog == 0) {
203 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
204 & 0xFFF0) |
205 baseband_attenuation);
206 } else if (phy->analog > 1) {
207 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2));
208 } else {
209 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3));
210 }
211}
212
213
214static void b43_set_txpower_g(struct b43_wldev *dev,
215 const struct b43_bbatt *bbatt,
216 const struct b43_rfatt *rfatt, u8 tx_control)
217{
218 struct b43_phy *phy = &dev->phy;
219 struct b43_phy_g *gphy = phy->g;
220 struct b43_txpower_lo_control *lo = gphy->lo_control;
221 u16 bb, rf;
222 u16 tx_bias, tx_magn;
223
224 bb = bbatt->att;
225 rf = rfatt->att;
226 tx_bias = lo->tx_bias;
227 tx_magn = lo->tx_magn;
228 if (unlikely(tx_bias == 0xFF))
229 tx_bias = 0;
230
231
232
233 gphy->tx_control = tx_control;
234 memmove(&gphy->rfatt, rfatt, sizeof(*rfatt));
235 gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
236 memmove(&gphy->bbatt, bbatt, sizeof(*bbatt));
237
238 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
239 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
240 "rfatt(%u), tx_control(0x%02X), "
241 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
242 bb, rf, tx_control, tx_bias, tx_magn);
243 }
244
245 b43_gphy_set_baseband_attenuation(dev, bb);
246 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
247 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
248 b43_radio_write16(dev, 0x43,
249 (rf & 0x000F) | (tx_control & 0x0070));
250 } else {
251 b43_radio_maskset(dev, 0x43, 0xFFF0, (rf & 0x000F));
252 b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070));
253 }
254 if (has_tx_magnification(phy)) {
255 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
256 } else {
257 b43_radio_maskset(dev, 0x52, 0xFFF0, (tx_bias & 0x000F));
258 }
259 b43_lo_g_adjust(dev);
260}
261
262
263static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
264{
265 struct b43_phy_g *gphy = dev->phy.g;
266 int i;
267 u16 value;
268
269 for (i = 0; i < 32; i++)
270 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]);
271 for (i = 32; i < 64; i++)
272 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]);
273 for (i = 0; i < 64; i += 2) {
274 value = (u16) gphy->tssi2dbm[i];
275 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8;
276 b43_phy_write(dev, 0x380 + (i / 2), value);
277 }
278}
279
280
281static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
282{
283 struct b43_phy *phy = &dev->phy;
284 struct b43_phy_g *gphy = phy->g;
285 struct b43_txpower_lo_control *lo = gphy->lo_control;
286 u16 nr_written = 0;
287 u16 tmp;
288 u8 rf, bb;
289
290 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
291 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
292 if (nr_written >= 0x40)
293 return;
294 tmp = lo->bbatt_list.list[bb].att;
295 tmp <<= 8;
296 if (phy->radio_rev == 8)
297 tmp |= 0x50;
298 else
299 tmp |= 0x40;
300 tmp |= lo->rfatt_list.list[rf].att;
301 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
302 nr_written++;
303 }
304 }
305}
306
307static void b43_set_all_gains(struct b43_wldev *dev,
308 s16 first, s16 second, s16 third)
309{
310 struct b43_phy *phy = &dev->phy;
311 u16 i;
312 u16 start = 0x08, end = 0x18;
313 u16 tmp;
314 u16 table;
315
316 if (phy->rev <= 1) {
317 start = 0x10;
318 end = 0x20;
319 }
320
321 table = B43_OFDMTAB_GAINX;
322 if (phy->rev <= 1)
323 table = B43_OFDMTAB_GAINX_R1;
324 for (i = 0; i < 4; i++)
325 b43_ofdmtab_write16(dev, table, i, first);
326
327 for (i = start; i < end; i++)
328 b43_ofdmtab_write16(dev, table, i, second);
329
330 if (third != -1) {
331 tmp = ((u16) third << 14) | ((u16) third << 6);
332 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp);
333 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp);
334 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp);
335 }
336 b43_dummy_transmission(dev, false, true);
337}
338
339static void b43_set_original_gains(struct b43_wldev *dev)
340{
341 struct b43_phy *phy = &dev->phy;
342 u16 i, tmp;
343 u16 table;
344 u16 start = 0x0008, end = 0x0018;
345
346 if (phy->rev <= 1) {
347 start = 0x0010;
348 end = 0x0020;
349 }
350
351 table = B43_OFDMTAB_GAINX;
352 if (phy->rev <= 1)
353 table = B43_OFDMTAB_GAINX_R1;
354 for (i = 0; i < 4; i++) {
355 tmp = (i & 0xFFFC);
356 tmp |= (i & 0x0001) << 1;
357 tmp |= (i & 0x0002) >> 1;
358
359 b43_ofdmtab_write16(dev, table, i, tmp);
360 }
361
362 for (i = start; i < end; i++)
363 b43_ofdmtab_write16(dev, table, i, i - start);
364
365 b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040);
366 b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040);
367 b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000);
368 b43_dummy_transmission(dev, false, true);
369}
370
371
372static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
373{
374 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
375 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
376}
377
378
379static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
380{
381 u16 val;
382
383 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
384 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
385
386 return (s16) val;
387}
388
389
390static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
391{
392 u16 i;
393 s16 tmp;
394
395 for (i = 0; i < 64; i++) {
396 tmp = b43_nrssi_hw_read(dev, i);
397 tmp -= val;
398 tmp = clamp_val(tmp, -32, 31);
399 b43_nrssi_hw_write(dev, i, tmp);
400 }
401}
402
403
404static void b43_nrssi_mem_update(struct b43_wldev *dev)
405{
406 struct b43_phy_g *gphy = dev->phy.g;
407 s16 i, delta;
408 s32 tmp;
409
410 delta = 0x1F - gphy->nrssi[0];
411 for (i = 0; i < 64; i++) {
412 tmp = (i - delta) * gphy->nrssislope;
413 tmp /= 0x10000;
414 tmp += 0x3A;
415 tmp = clamp_val(tmp, 0, 0x3F);
416 gphy->nrssi_lt[i] = tmp;
417 }
418}
419
420static void b43_calc_nrssi_offset(struct b43_wldev *dev)
421{
422 struct b43_phy *phy = &dev->phy;
423 u16 backup[20] = { 0 };
424 s16 v47F;
425 u16 i;
426 u16 saved = 0xFFFF;
427
428 backup[0] = b43_phy_read(dev, 0x0001);
429 backup[1] = b43_phy_read(dev, 0x0811);
430 backup[2] = b43_phy_read(dev, 0x0812);
431 if (phy->rev != 1) {
432 backup[3] = b43_phy_read(dev, 0x0814);
433 backup[4] = b43_phy_read(dev, 0x0815);
434 }
435 backup[5] = b43_phy_read(dev, 0x005A);
436 backup[6] = b43_phy_read(dev, 0x0059);
437 backup[7] = b43_phy_read(dev, 0x0058);
438 backup[8] = b43_phy_read(dev, 0x000A);
439 backup[9] = b43_phy_read(dev, 0x0003);
440 backup[10] = b43_radio_read16(dev, 0x007A);
441 backup[11] = b43_radio_read16(dev, 0x0043);
442
443 b43_phy_mask(dev, 0x0429, 0x7FFF);
444 b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000);
445 b43_phy_set(dev, 0x0811, 0x000C);
446 b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004);
447 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2));
448 if (phy->rev >= 6) {
449 backup[12] = b43_phy_read(dev, 0x002E);
450 backup[13] = b43_phy_read(dev, 0x002F);
451 backup[14] = b43_phy_read(dev, 0x080F);
452 backup[15] = b43_phy_read(dev, 0x0810);
453 backup[16] = b43_phy_read(dev, 0x0801);
454 backup[17] = b43_phy_read(dev, 0x0060);
455 backup[18] = b43_phy_read(dev, 0x0014);
456 backup[19] = b43_phy_read(dev, 0x0478);
457
458 b43_phy_write(dev, 0x002E, 0);
459 b43_phy_write(dev, 0x002F, 0);
460 b43_phy_write(dev, 0x080F, 0);
461 b43_phy_write(dev, 0x0810, 0);
462 b43_phy_set(dev, 0x0478, 0x0100);
463 b43_phy_set(dev, 0x0801, 0x0040);
464 b43_phy_set(dev, 0x0060, 0x0040);
465 b43_phy_set(dev, 0x0014, 0x0200);
466 }
467 b43_radio_set(dev, 0x007A, 0x0070);
468 b43_radio_set(dev, 0x007A, 0x0080);
469 udelay(30);
470
471 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
472 if (v47F >= 0x20)
473 v47F -= 0x40;
474 if (v47F == 31) {
475 for (i = 7; i >= 4; i--) {
476 b43_radio_write16(dev, 0x007B, i);
477 udelay(20);
478 v47F =
479 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
480 if (v47F >= 0x20)
481 v47F -= 0x40;
482 if (v47F < 31 && saved == 0xFFFF)
483 saved = i;
484 }
485 if (saved == 0xFFFF)
486 saved = 4;
487 } else {
488 b43_radio_mask(dev, 0x007A, 0x007F);
489 if (phy->rev != 1) {
490 b43_phy_set(dev, 0x0814, 0x0001);
491 b43_phy_mask(dev, 0x0815, 0xFFFE);
492 }
493 b43_phy_set(dev, 0x0811, 0x000C);
494 b43_phy_set(dev, 0x0812, 0x000C);
495 b43_phy_set(dev, 0x0811, 0x0030);
496 b43_phy_set(dev, 0x0812, 0x0030);
497 b43_phy_write(dev, 0x005A, 0x0480);
498 b43_phy_write(dev, 0x0059, 0x0810);
499 b43_phy_write(dev, 0x0058, 0x000D);
500 if (phy->rev == 0) {
501 b43_phy_write(dev, 0x0003, 0x0122);
502 } else {
503 b43_phy_set(dev, 0x000A, 0x2000);
504 }
505 if (phy->rev != 1) {
506 b43_phy_set(dev, 0x0814, 0x0004);
507 b43_phy_mask(dev, 0x0815, 0xFFFB);
508 }
509 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
510 b43_radio_set(dev, 0x007A, 0x000F);
511 b43_set_all_gains(dev, 3, 0, 1);
512 b43_radio_maskset(dev, 0x0043, 0x00F0, 0x000F);
513 udelay(30);
514 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
515 if (v47F >= 0x20)
516 v47F -= 0x40;
517 if (v47F == -32) {
518 for (i = 0; i < 4; i++) {
519 b43_radio_write16(dev, 0x007B, i);
520 udelay(20);
521 v47F =
522 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
523 0x003F);
524 if (v47F >= 0x20)
525 v47F -= 0x40;
526 if (v47F > -31 && saved == 0xFFFF)
527 saved = i;
528 }
529 if (saved == 0xFFFF)
530 saved = 3;
531 } else
532 saved = 0;
533 }
534 b43_radio_write16(dev, 0x007B, saved);
535
536 if (phy->rev >= 6) {
537 b43_phy_write(dev, 0x002E, backup[12]);
538 b43_phy_write(dev, 0x002F, backup[13]);
539 b43_phy_write(dev, 0x080F, backup[14]);
540 b43_phy_write(dev, 0x0810, backup[15]);
541 }
542 if (phy->rev != 1) {
543 b43_phy_write(dev, 0x0814, backup[3]);
544 b43_phy_write(dev, 0x0815, backup[4]);
545 }
546 b43_phy_write(dev, 0x005A, backup[5]);
547 b43_phy_write(dev, 0x0059, backup[6]);
548 b43_phy_write(dev, 0x0058, backup[7]);
549 b43_phy_write(dev, 0x000A, backup[8]);
550 b43_phy_write(dev, 0x0003, backup[9]);
551 b43_radio_write16(dev, 0x0043, backup[11]);
552 b43_radio_write16(dev, 0x007A, backup[10]);
553 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
554 b43_phy_set(dev, 0x0429, 0x8000);
555 b43_set_original_gains(dev);
556 if (phy->rev >= 6) {
557 b43_phy_write(dev, 0x0801, backup[16]);
558 b43_phy_write(dev, 0x0060, backup[17]);
559 b43_phy_write(dev, 0x0014, backup[18]);
560 b43_phy_write(dev, 0x0478, backup[19]);
561 }
562 b43_phy_write(dev, 0x0001, backup[0]);
563 b43_phy_write(dev, 0x0812, backup[2]);
564 b43_phy_write(dev, 0x0811, backup[1]);
565}
566
567static void b43_calc_nrssi_slope(struct b43_wldev *dev)
568{
569 struct b43_phy *phy = &dev->phy;
570 struct b43_phy_g *gphy = phy->g;
571 u16 backup[18] = { 0 };
572 u16 tmp;
573 s16 nrssi0, nrssi1;
574
575 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
576
577 if (phy->radio_rev >= 9)
578 return;
579 if (phy->radio_rev == 8)
580 b43_calc_nrssi_offset(dev);
581
582 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
583 b43_phy_mask(dev, 0x0802, 0xFFFC);
584 backup[7] = b43_read16(dev, 0x03E2);
585 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
586 backup[0] = b43_radio_read16(dev, 0x007A);
587 backup[1] = b43_radio_read16(dev, 0x0052);
588 backup[2] = b43_radio_read16(dev, 0x0043);
589 backup[3] = b43_phy_read(dev, 0x0015);
590 backup[4] = b43_phy_read(dev, 0x005A);
591 backup[5] = b43_phy_read(dev, 0x0059);
592 backup[6] = b43_phy_read(dev, 0x0058);
593 backup[8] = b43_read16(dev, 0x03E6);
594 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
595 if (phy->rev >= 3) {
596 backup[10] = b43_phy_read(dev, 0x002E);
597 backup[11] = b43_phy_read(dev, 0x002F);
598 backup[12] = b43_phy_read(dev, 0x080F);
599 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
600 backup[14] = b43_phy_read(dev, 0x0801);
601 backup[15] = b43_phy_read(dev, 0x0060);
602 backup[16] = b43_phy_read(dev, 0x0014);
603 backup[17] = b43_phy_read(dev, 0x0478);
604 b43_phy_write(dev, 0x002E, 0);
605 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
606 switch (phy->rev) {
607 case 4:
608 case 6:
609 case 7:
610 b43_phy_set(dev, 0x0478, 0x0100);
611 b43_phy_set(dev, 0x0801, 0x0040);
612 break;
613 case 3:
614 case 5:
615 b43_phy_mask(dev, 0x0801, 0xFFBF);
616 break;
617 }
618 b43_phy_set(dev, 0x0060, 0x0040);
619 b43_phy_set(dev, 0x0014, 0x0200);
620 }
621 b43_radio_set(dev, 0x007A, 0x0070);
622 b43_set_all_gains(dev, 0, 8, 0);
623 b43_radio_mask(dev, 0x007A, 0x00F7);
624 if (phy->rev >= 2) {
625 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030);
626 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010);
627 }
628 b43_radio_set(dev, 0x007A, 0x0080);
629 udelay(20);
630
631 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
632 if (nrssi0 >= 0x0020)
633 nrssi0 -= 0x0040;
634
635 b43_radio_mask(dev, 0x007A, 0x007F);
636 if (phy->rev >= 2) {
637 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
638 }
639
640 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
641 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
642 | 0x2000);
643 b43_radio_set(dev, 0x007A, 0x000F);
644 b43_phy_write(dev, 0x0015, 0xF330);
645 if (phy->rev >= 2) {
646 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020);
647 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020);
648 }
649
650 b43_set_all_gains(dev, 3, 0, 1);
651 if (phy->radio_rev == 8) {
652 b43_radio_write16(dev, 0x0043, 0x001F);
653 } else {
654 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
655 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
656 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
657 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
658 }
659 b43_phy_write(dev, 0x005A, 0x0480);
660 b43_phy_write(dev, 0x0059, 0x0810);
661 b43_phy_write(dev, 0x0058, 0x000D);
662 udelay(20);
663 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
664 if (nrssi1 >= 0x0020)
665 nrssi1 -= 0x0040;
666 if (nrssi0 == nrssi1)
667 gphy->nrssislope = 0x00010000;
668 else
669 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
670 if (nrssi0 >= -4) {
671 gphy->nrssi[0] = nrssi1;
672 gphy->nrssi[1] = nrssi0;
673 }
674 if (phy->rev >= 3) {
675 b43_phy_write(dev, 0x002E, backup[10]);
676 b43_phy_write(dev, 0x002F, backup[11]);
677 b43_phy_write(dev, 0x080F, backup[12]);
678 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
679 }
680 if (phy->rev >= 2) {
681 b43_phy_mask(dev, 0x0812, 0xFFCF);
682 b43_phy_mask(dev, 0x0811, 0xFFCF);
683 }
684
685 b43_radio_write16(dev, 0x007A, backup[0]);
686 b43_radio_write16(dev, 0x0052, backup[1]);
687 b43_radio_write16(dev, 0x0043, backup[2]);
688 b43_write16(dev, 0x03E2, backup[7]);
689 b43_write16(dev, 0x03E6, backup[8]);
690 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
691 b43_phy_write(dev, 0x0015, backup[3]);
692 b43_phy_write(dev, 0x005A, backup[4]);
693 b43_phy_write(dev, 0x0059, backup[5]);
694 b43_phy_write(dev, 0x0058, backup[6]);
695 b43_synth_pu_workaround(dev, phy->channel);
696 b43_phy_set(dev, 0x0802, (0x0001 | 0x0002));
697 b43_set_original_gains(dev);
698 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
699 if (phy->rev >= 3) {
700 b43_phy_write(dev, 0x0801, backup[14]);
701 b43_phy_write(dev, 0x0060, backup[15]);
702 b43_phy_write(dev, 0x0014, backup[16]);
703 b43_phy_write(dev, 0x0478, backup[17]);
704 }
705 b43_nrssi_mem_update(dev);
706 b43_calc_nrssi_threshold(dev);
707}
708
709static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
710{
711 struct b43_phy *phy = &dev->phy;
712 struct b43_phy_g *gphy = phy->g;
713 s32 a, b;
714 s16 tmp16;
715 u16 tmp_u16;
716
717 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
718
719 if (!phy->gmode ||
720 !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
721 tmp16 = b43_nrssi_hw_read(dev, 0x20);
722 if (tmp16 >= 0x20)
723 tmp16 -= 0x40;
724 if (tmp16 < 3) {
725 b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB);
726 } else {
727 b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED);
728 }
729 } else {
730 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) {
731 a = 0xE;
732 b = 0xA;
733 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) {
734 a = 0x13;
735 b = 0x12;
736 } else {
737 a = 0xE;
738 b = 0x11;
739 }
740
741 a = a * (gphy->nrssi[1] - gphy->nrssi[0]);
742 a += (gphy->nrssi[0] << 6);
743 if (a < 32)
744 a += 31;
745 else
746 a += 32;
747 a = a >> 6;
748 a = clamp_val(a, -31, 31);
749
750 b = b * (gphy->nrssi[1] - gphy->nrssi[0]);
751 b += (gphy->nrssi[0] << 6);
752 if (b < 32)
753 b += 31;
754 else
755 b += 32;
756 b = b >> 6;
757 b = clamp_val(b, -31, 31);
758
759 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
760 tmp_u16 |= ((u32) b & 0x0000003F);
761 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
762 b43_phy_write(dev, 0x048A, tmp_u16);
763 }
764}
765
766
767
768
769
770static void _stack_save(u32 *_stackptr, size_t *stackidx,
771 u8 id, u16 offset, u16 value)
772{
773 u32 *stackptr = &(_stackptr[*stackidx]);
774
775 B43_WARN_ON(offset & 0xF000);
776 B43_WARN_ON(id & 0xF0);
777 *stackptr = offset;
778 *stackptr |= ((u32) id) << 12;
779 *stackptr |= ((u32) value) << 16;
780 (*stackidx)++;
781 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
782}
783
784static u16 _stack_restore(u32 *stackptr, u8 id, u16 offset)
785{
786 size_t i;
787
788 B43_WARN_ON(offset & 0xF000);
789 B43_WARN_ON(id & 0xF0);
790 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
791 if ((*stackptr & 0x00000FFF) != offset)
792 continue;
793 if (((*stackptr & 0x0000F000) >> 12) != id)
794 continue;
795 return ((*stackptr & 0xFFFF0000) >> 16);
796 }
797 B43_WARN_ON(1);
798
799 return 0;
800}
801
802#define phy_stacksave(offset) \
803 do { \
804 _stack_save(stack, &stackidx, 0x1, (offset), \
805 b43_phy_read(dev, (offset))); \
806 } while (0)
807#define phy_stackrestore(offset) \
808 do { \
809 b43_phy_write(dev, (offset), \
810 _stack_restore(stack, 0x1, \
811 (offset))); \
812 } while (0)
813#define radio_stacksave(offset) \
814 do { \
815 _stack_save(stack, &stackidx, 0x2, (offset), \
816 b43_radio_read16(dev, (offset))); \
817 } while (0)
818#define radio_stackrestore(offset) \
819 do { \
820 b43_radio_write16(dev, (offset), \
821 _stack_restore(stack, 0x2, \
822 (offset))); \
823 } while (0)
824#define ofdmtab_stacksave(table, offset) \
825 do { \
826 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
827 b43_ofdmtab_read16(dev, (table), (offset))); \
828 } while (0)
829#define ofdmtab_stackrestore(table, offset) \
830 do { \
831 b43_ofdmtab_write16(dev, (table), (offset), \
832 _stack_restore(stack, 0x3, \
833 (offset)|(table))); \
834 } while (0)
835
836static void
837b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
838{
839 struct b43_phy *phy = &dev->phy;
840 struct b43_phy_g *gphy = phy->g;
841 u16 tmp, flipped;
842 size_t stackidx = 0;
843 u32 *stack = gphy->interfstack;
844
845 switch (mode) {
846 case B43_INTERFMODE_NONWLAN:
847 if (phy->rev != 1) {
848 b43_phy_set(dev, 0x042B, 0x0800);
849 b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000);
850 break;
851 }
852 radio_stacksave(0x0078);
853 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
854 B43_WARN_ON(tmp > 15);
855 flipped = bitrev4(tmp);
856 if (flipped < 10 && flipped >= 8)
857 flipped = 7;
858 else if (flipped >= 10)
859 flipped -= 3;
860 flipped = (bitrev4(flipped) << 1) | 0x0020;
861 b43_radio_write16(dev, 0x0078, flipped);
862
863 b43_calc_nrssi_threshold(dev);
864
865 phy_stacksave(0x0406);
866 b43_phy_write(dev, 0x0406, 0x7E28);
867
868 b43_phy_set(dev, 0x042B, 0x0800);
869 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000);
870
871 phy_stacksave(0x04A0);
872 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008);
873 phy_stacksave(0x04A1);
874 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605);
875 phy_stacksave(0x04A2);
876 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204);
877 phy_stacksave(0x04A8);
878 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803);
879 phy_stacksave(0x04AB);
880 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605);
881
882 phy_stacksave(0x04A7);
883 b43_phy_write(dev, 0x04A7, 0x0002);
884 phy_stacksave(0x04A3);
885 b43_phy_write(dev, 0x04A3, 0x287A);
886 phy_stacksave(0x04A9);
887 b43_phy_write(dev, 0x04A9, 0x2027);
888 phy_stacksave(0x0493);
889 b43_phy_write(dev, 0x0493, 0x32F5);
890 phy_stacksave(0x04AA);
891 b43_phy_write(dev, 0x04AA, 0x2027);
892 phy_stacksave(0x04AC);
893 b43_phy_write(dev, 0x04AC, 0x32F5);
894 break;
895 case B43_INTERFMODE_MANUALWLAN:
896 if (b43_phy_read(dev, 0x0033) & 0x0800)
897 break;
898
899 gphy->aci_enable = 1;
900
901 phy_stacksave(B43_PHY_RADIO_BITFIELD);
902 phy_stacksave(B43_PHY_G_CRS);
903 if (phy->rev < 2) {
904 phy_stacksave(0x0406);
905 } else {
906 phy_stacksave(0x04C0);
907 phy_stacksave(0x04C1);
908 }
909 phy_stacksave(0x0033);
910 phy_stacksave(0x04A7);
911 phy_stacksave(0x04A3);
912 phy_stacksave(0x04A9);
913 phy_stacksave(0x04AA);
914 phy_stacksave(0x04AC);
915 phy_stacksave(0x0493);
916 phy_stacksave(0x04A1);
917 phy_stacksave(0x04A0);
918 phy_stacksave(0x04A2);
919 phy_stacksave(0x048A);
920 phy_stacksave(0x04A8);
921 phy_stacksave(0x04AB);
922 if (phy->rev == 2) {
923 phy_stacksave(0x04AD);
924 phy_stacksave(0x04AE);
925 } else if (phy->rev >= 3) {
926 phy_stacksave(0x04AD);
927 phy_stacksave(0x0415);
928 phy_stacksave(0x0416);
929 phy_stacksave(0x0417);
930 ofdmtab_stacksave(0x1A00, 0x2);
931 ofdmtab_stacksave(0x1A00, 0x3);
932 }
933 phy_stacksave(0x042B);
934 phy_stacksave(0x048C);
935
936 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000);
937 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002);
938
939 b43_phy_write(dev, 0x0033, 0x0800);
940 b43_phy_write(dev, 0x04A3, 0x2027);
941 b43_phy_write(dev, 0x04A9, 0x1CA8);
942 b43_phy_write(dev, 0x0493, 0x287A);
943 b43_phy_write(dev, 0x04AA, 0x1CA8);
944 b43_phy_write(dev, 0x04AC, 0x287A);
945
946 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A);
947 b43_phy_write(dev, 0x04A7, 0x000D);
948
949 if (phy->rev < 2) {
950 b43_phy_write(dev, 0x0406, 0xFF0D);
951 } else if (phy->rev == 2) {
952 b43_phy_write(dev, 0x04C0, 0xFFFF);
953 b43_phy_write(dev, 0x04C1, 0x00A9);
954 } else {
955 b43_phy_write(dev, 0x04C0, 0x00C1);
956 b43_phy_write(dev, 0x04C1, 0x0059);
957 }
958
959 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800);
960 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015);
961 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000);
962 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00);
963 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000);
964 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800);
965 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010);
966 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005);
967 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010);
968 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006);
969 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800);
970 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500);
971 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B);
972
973 if (phy->rev >= 3) {
974 b43_phy_mask(dev, 0x048A, (u16)~0x8000);
975 b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8);
976 b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8);
977 b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D);
978 } else {
979 b43_phy_set(dev, 0x048A, 0x1000);
980 b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000);
981 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
982 }
983 if (phy->rev >= 2) {
984 b43_phy_set(dev, 0x042B, 0x0800);
985 }
986 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200);
987 if (phy->rev == 2) {
988 b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F);
989 b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300);
990 } else if (phy->rev >= 6) {
991 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
992 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
993 b43_phy_mask(dev, 0x04AD, 0x00FF);
994 }
995 b43_calc_nrssi_slope(dev);
996 break;
997 default:
998 B43_WARN_ON(1);
999 }
1000}
1001
1002static void
1003b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
1004{
1005 struct b43_phy *phy = &dev->phy;
1006 struct b43_phy_g *gphy = phy->g;
1007 u32 *stack = gphy->interfstack;
1008
1009 switch (mode) {
1010 case B43_INTERFMODE_NONWLAN:
1011 if (phy->rev != 1) {
1012 b43_phy_mask(dev, 0x042B, ~0x0800);
1013 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1014 break;
1015 }
1016 radio_stackrestore(0x0078);
1017 b43_calc_nrssi_threshold(dev);
1018 phy_stackrestore(0x0406);
1019 b43_phy_mask(dev, 0x042B, ~0x0800);
1020 if (!dev->bad_frames_preempt) {
1021 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11));
1022 }
1023 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1024 phy_stackrestore(0x04A0);
1025 phy_stackrestore(0x04A1);
1026 phy_stackrestore(0x04A2);
1027 phy_stackrestore(0x04A8);
1028 phy_stackrestore(0x04AB);
1029 phy_stackrestore(0x04A7);
1030 phy_stackrestore(0x04A3);
1031 phy_stackrestore(0x04A9);
1032 phy_stackrestore(0x0493);
1033 phy_stackrestore(0x04AA);
1034 phy_stackrestore(0x04AC);
1035 break;
1036 case B43_INTERFMODE_MANUALWLAN:
1037 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
1038 break;
1039
1040 gphy->aci_enable = 0;
1041
1042 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
1043 phy_stackrestore(B43_PHY_G_CRS);
1044 phy_stackrestore(0x0033);
1045 phy_stackrestore(0x04A3);
1046 phy_stackrestore(0x04A9);
1047 phy_stackrestore(0x0493);
1048 phy_stackrestore(0x04AA);
1049 phy_stackrestore(0x04AC);
1050 phy_stackrestore(0x04A0);
1051 phy_stackrestore(0x04A7);
1052 if (phy->rev >= 2) {
1053 phy_stackrestore(0x04C0);
1054 phy_stackrestore(0x04C1);
1055 } else
1056 phy_stackrestore(0x0406);
1057 phy_stackrestore(0x04A1);
1058 phy_stackrestore(0x04AB);
1059 phy_stackrestore(0x04A8);
1060 if (phy->rev == 2) {
1061 phy_stackrestore(0x04AD);
1062 phy_stackrestore(0x04AE);
1063 } else if (phy->rev >= 3) {
1064 phy_stackrestore(0x04AD);
1065 phy_stackrestore(0x0415);
1066 phy_stackrestore(0x0416);
1067 phy_stackrestore(0x0417);
1068 ofdmtab_stackrestore(0x1A00, 0x2);
1069 ofdmtab_stackrestore(0x1A00, 0x3);
1070 }
1071 phy_stackrestore(0x04A2);
1072 phy_stackrestore(0x048A);
1073 phy_stackrestore(0x042B);
1074 phy_stackrestore(0x048C);
1075 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
1076 b43_calc_nrssi_slope(dev);
1077 break;
1078 default:
1079 B43_WARN_ON(1);
1080 }
1081}
1082
1083#undef phy_stacksave
1084#undef phy_stackrestore
1085#undef radio_stacksave
1086#undef radio_stackrestore
1087#undef ofdmtab_stacksave
1088#undef ofdmtab_stackrestore
1089
1090static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
1091{
1092 u16 reg, index, ret;
1093
1094 static const u8 rcc_table[] = {
1095 0x02, 0x03, 0x01, 0x0F,
1096 0x06, 0x07, 0x05, 0x0F,
1097 0x0A, 0x0B, 0x09, 0x0F,
1098 0x0E, 0x0F, 0x0D, 0x0F,
1099 };
1100
1101 reg = b43_radio_read16(dev, 0x60);
1102 index = (reg & 0x001E) >> 1;
1103 ret = rcc_table[index] << 1;
1104 ret |= (reg & 0x0001);
1105 ret |= 0x0020;
1106
1107 return ret;
1108}
1109
1110#define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
1111static u16 radio2050_rfover_val(struct b43_wldev *dev,
1112 u16 phy_register, unsigned int lpd)
1113{
1114 struct b43_phy *phy = &dev->phy;
1115 struct b43_phy_g *gphy = phy->g;
1116 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
1117
1118 if (!phy->gmode)
1119 return 0;
1120
1121 if (has_loopback_gain(phy)) {
1122 int max_lb_gain = gphy->max_lb_gain;
1123 u16 extlna;
1124 u16 i;
1125
1126 if (phy->radio_rev == 8)
1127 max_lb_gain += 0x3E;
1128 else
1129 max_lb_gain += 0x26;
1130 if (max_lb_gain >= 0x46) {
1131 extlna = 0x3000;
1132 max_lb_gain -= 0x46;
1133 } else if (max_lb_gain >= 0x3A) {
1134 extlna = 0x1000;
1135 max_lb_gain -= 0x3A;
1136 } else if (max_lb_gain >= 0x2E) {
1137 extlna = 0x2000;
1138 max_lb_gain -= 0x2E;
1139 } else {
1140 extlna = 0;
1141 max_lb_gain -= 0x10;
1142 }
1143
1144 for (i = 0; i < 16; i++) {
1145 max_lb_gain -= (i * 6);
1146 if (max_lb_gain < 6)
1147 break;
1148 }
1149
1150 if ((phy->rev < 7) ||
1151 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1152 if (phy_register == B43_PHY_RFOVER) {
1153 return 0x1B3;
1154 } else if (phy_register == B43_PHY_RFOVERVAL) {
1155 extlna |= (i << 8);
1156 switch (lpd) {
1157 case LPD(0, 1, 1):
1158 return 0x0F92;
1159 case LPD(0, 0, 1):
1160 case LPD(1, 0, 1):
1161 return (0x0092 | extlna);
1162 case LPD(1, 0, 0):
1163 return (0x0093 | extlna);
1164 }
1165 B43_WARN_ON(1);
1166 }
1167 B43_WARN_ON(1);
1168 } else {
1169 if (phy_register == B43_PHY_RFOVER) {
1170 return 0x9B3;
1171 } else if (phy_register == B43_PHY_RFOVERVAL) {
1172 if (extlna)
1173 extlna |= 0x8000;
1174 extlna |= (i << 8);
1175 switch (lpd) {
1176 case LPD(0, 1, 1):
1177 return 0x8F92;
1178 case LPD(0, 0, 1):
1179 return (0x8092 | extlna);
1180 case LPD(1, 0, 1):
1181 return (0x2092 | extlna);
1182 case LPD(1, 0, 0):
1183 return (0x2093 | extlna);
1184 }
1185 B43_WARN_ON(1);
1186 }
1187 B43_WARN_ON(1);
1188 }
1189 } else {
1190 if ((phy->rev < 7) ||
1191 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1192 if (phy_register == B43_PHY_RFOVER) {
1193 return 0x1B3;
1194 } else if (phy_register == B43_PHY_RFOVERVAL) {
1195 switch (lpd) {
1196 case LPD(0, 1, 1):
1197 return 0x0FB2;
1198 case LPD(0, 0, 1):
1199 return 0x00B2;
1200 case LPD(1, 0, 1):
1201 return 0x30B2;
1202 case LPD(1, 0, 0):
1203 return 0x30B3;
1204 }
1205 B43_WARN_ON(1);
1206 }
1207 B43_WARN_ON(1);
1208 } else {
1209 if (phy_register == B43_PHY_RFOVER) {
1210 return 0x9B3;
1211 } else if (phy_register == B43_PHY_RFOVERVAL) {
1212 switch (lpd) {
1213 case LPD(0, 1, 1):
1214 return 0x8FB2;
1215 case LPD(0, 0, 1):
1216 return 0x80B2;
1217 case LPD(1, 0, 1):
1218 return 0x20B2;
1219 case LPD(1, 0, 0):
1220 return 0x20B3;
1221 }
1222 B43_WARN_ON(1);
1223 }
1224 B43_WARN_ON(1);
1225 }
1226 }
1227 return 0;
1228}
1229
1230struct init2050_saved_values {
1231
1232 u16 reg_3EC;
1233 u16 reg_3E6;
1234 u16 reg_3F4;
1235
1236 u16 radio_43;
1237 u16 radio_51;
1238 u16 radio_52;
1239
1240 u16 phy_pgactl;
1241 u16 phy_cck_5A;
1242 u16 phy_cck_59;
1243 u16 phy_cck_58;
1244 u16 phy_cck_30;
1245 u16 phy_rfover;
1246 u16 phy_rfoverval;
1247 u16 phy_analogover;
1248 u16 phy_analogoverval;
1249 u16 phy_crs0;
1250 u16 phy_classctl;
1251 u16 phy_lo_mask;
1252 u16 phy_lo_ctl;
1253 u16 phy_syncctl;
1254};
1255
1256static u16 b43_radio_init2050(struct b43_wldev *dev)
1257{
1258 struct b43_phy *phy = &dev->phy;
1259 struct init2050_saved_values sav;
1260 u16 rcc;
1261 u16 radio78;
1262 u16 ret;
1263 u16 i, j;
1264 u32 tmp1 = 0, tmp2 = 0;
1265
1266 memset(&sav, 0, sizeof(sav));
1267
1268 sav.radio_43 = b43_radio_read16(dev, 0x43);
1269 sav.radio_51 = b43_radio_read16(dev, 0x51);
1270 sav.radio_52 = b43_radio_read16(dev, 0x52);
1271 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
1272 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1273 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
1274 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
1275
1276 if (phy->type == B43_PHYTYPE_B) {
1277 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
1278 sav.reg_3EC = b43_read16(dev, 0x3EC);
1279
1280 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
1281 b43_write16(dev, 0x3EC, 0x3F3F);
1282 } else if (phy->gmode || phy->rev >= 2) {
1283 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
1284 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1285 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1286 sav.phy_analogoverval =
1287 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1288 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
1289 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1290
1291 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003);
1292 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC);
1293 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF);
1294 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC);
1295 if (has_loopback_gain(phy)) {
1296 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1297 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
1298
1299 if (phy->rev >= 3)
1300 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1301 else
1302 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1303 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1304 }
1305
1306 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1307 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1308 LPD(0, 1, 1)));
1309 b43_phy_write(dev, B43_PHY_RFOVER,
1310 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
1311 }
1312 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1313
1314 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1315 b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F);
1316 sav.reg_3E6 = b43_read16(dev, 0x3E6);
1317 sav.reg_3F4 = b43_read16(dev, 0x3F4);
1318
1319 if (phy->analog == 0) {
1320 b43_write16(dev, 0x03E6, 0x0122);
1321 } else {
1322 if (phy->analog >= 2) {
1323 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40);
1324 }
1325 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1326 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
1327 }
1328
1329 rcc = b43_radio_core_calibration_value(dev);
1330
1331 if (phy->type == B43_PHYTYPE_B)
1332 b43_radio_write16(dev, 0x78, 0x26);
1333 if (phy->gmode || phy->rev >= 2) {
1334 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1335 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1336 LPD(0, 1, 1)));
1337 }
1338 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
1339 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
1340 if (phy->gmode || phy->rev >= 2) {
1341 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1342 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1343 LPD(0, 0, 1)));
1344 }
1345 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
1346 b43_radio_set(dev, 0x51, 0x0004);
1347 if (phy->radio_rev == 8) {
1348 b43_radio_write16(dev, 0x43, 0x1F);
1349 } else {
1350 b43_radio_write16(dev, 0x52, 0);
1351 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x0009);
1352 }
1353 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1354
1355 for (i = 0; i < 16; i++) {
1356 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
1357 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1358 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1359 if (phy->gmode || phy->rev >= 2) {
1360 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1361 radio2050_rfover_val(dev,
1362 B43_PHY_RFOVERVAL,
1363 LPD(1, 0, 1)));
1364 }
1365 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1366 udelay(10);
1367 if (phy->gmode || phy->rev >= 2) {
1368 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1369 radio2050_rfover_val(dev,
1370 B43_PHY_RFOVERVAL,
1371 LPD(1, 0, 1)));
1372 }
1373 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1374 udelay(10);
1375 if (phy->gmode || phy->rev >= 2) {
1376 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1377 radio2050_rfover_val(dev,
1378 B43_PHY_RFOVERVAL,
1379 LPD(1, 0, 0)));
1380 }
1381 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1382 udelay(20);
1383 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1384 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1385 if (phy->gmode || phy->rev >= 2) {
1386 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1387 radio2050_rfover_val(dev,
1388 B43_PHY_RFOVERVAL,
1389 LPD(1, 0, 1)));
1390 }
1391 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1392 }
1393 udelay(10);
1394
1395 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1396 tmp1++;
1397 tmp1 >>= 9;
1398
1399 for (i = 0; i < 16; i++) {
1400 radio78 = (bitrev4(i) << 1) | 0x0020;
1401 b43_radio_write16(dev, 0x78, radio78);
1402 udelay(10);
1403 for (j = 0; j < 16; j++) {
1404 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
1405 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1406 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1407 if (phy->gmode || phy->rev >= 2) {
1408 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1409 radio2050_rfover_val(dev,
1410 B43_PHY_RFOVERVAL,
1411 LPD(1, 0,
1412 1)));
1413 }
1414 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1415 udelay(10);
1416 if (phy->gmode || phy->rev >= 2) {
1417 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1418 radio2050_rfover_val(dev,
1419 B43_PHY_RFOVERVAL,
1420 LPD(1, 0,
1421 1)));
1422 }
1423 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1424 udelay(10);
1425 if (phy->gmode || phy->rev >= 2) {
1426 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1427 radio2050_rfover_val(dev,
1428 B43_PHY_RFOVERVAL,
1429 LPD(1, 0,
1430 0)));
1431 }
1432 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1433 udelay(10);
1434 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1435 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1436 if (phy->gmode || phy->rev >= 2) {
1437 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1438 radio2050_rfover_val(dev,
1439 B43_PHY_RFOVERVAL,
1440 LPD(1, 0,
1441 1)));
1442 }
1443 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1444 }
1445 tmp2++;
1446 tmp2 >>= 8;
1447 if (tmp1 < tmp2)
1448 break;
1449 }
1450
1451
1452 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
1453 b43_radio_write16(dev, 0x51, sav.radio_51);
1454 b43_radio_write16(dev, 0x52, sav.radio_52);
1455 b43_radio_write16(dev, 0x43, sav.radio_43);
1456 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
1457 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
1458 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
1459 b43_write16(dev, 0x3E6, sav.reg_3E6);
1460 if (phy->analog != 0)
1461 b43_write16(dev, 0x3F4, sav.reg_3F4);
1462 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
1463 b43_synth_pu_workaround(dev, phy->channel);
1464 if (phy->type == B43_PHYTYPE_B) {
1465 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
1466 b43_write16(dev, 0x3EC, sav.reg_3EC);
1467 } else if (phy->gmode) {
1468 b43_write16(dev, B43_MMIO_PHY_RADIO,
1469 b43_read16(dev, B43_MMIO_PHY_RADIO)
1470 & 0x7FFF);
1471 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
1472 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
1473 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
1474 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1475 sav.phy_analogoverval);
1476 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
1477 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
1478 if (has_loopback_gain(phy)) {
1479 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
1480 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
1481 }
1482 }
1483 if (i > 15)
1484 ret = radio78;
1485 else
1486 ret = rcc;
1487
1488 return ret;
1489}
1490
1491static void b43_phy_initb5(struct b43_wldev *dev)
1492{
1493 struct ssb_bus *bus = dev->dev->bus;
1494 struct b43_phy *phy = &dev->phy;
1495 struct b43_phy_g *gphy = phy->g;
1496 u16 offset, value;
1497 u8 old_channel;
1498
1499 if (phy->analog == 1) {
1500 b43_radio_set(dev, 0x007A, 0x0050);
1501 }
1502 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1503 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1504 value = 0x2120;
1505 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1506 b43_phy_write(dev, offset, value);
1507 value += 0x202;
1508 }
1509 }
1510 b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700);
1511 if (phy->radio_ver == 0x2050)
1512 b43_phy_write(dev, 0x0038, 0x0667);
1513
1514 if (phy->gmode || phy->rev >= 2) {
1515 if (phy->radio_ver == 0x2050) {
1516 b43_radio_set(dev, 0x007A, 0x0020);
1517 b43_radio_set(dev, 0x0051, 0x0004);
1518 }
1519 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1520
1521 b43_phy_set(dev, 0x0802, 0x0100);
1522 b43_phy_set(dev, 0x042B, 0x2000);
1523
1524 b43_phy_write(dev, 0x001C, 0x186A);
1525
1526 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900);
1527 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064);
1528 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A);
1529 }
1530
1531 if (dev->bad_frames_preempt) {
1532 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11));
1533 }
1534
1535 if (phy->analog == 1) {
1536 b43_phy_write(dev, 0x0026, 0xCE00);
1537 b43_phy_write(dev, 0x0021, 0x3763);
1538 b43_phy_write(dev, 0x0022, 0x1BC3);
1539 b43_phy_write(dev, 0x0023, 0x06F9);
1540 b43_phy_write(dev, 0x0024, 0x037E);
1541 } else
1542 b43_phy_write(dev, 0x0026, 0xCC00);
1543 b43_phy_write(dev, 0x0030, 0x00C6);
1544 b43_write16(dev, 0x03EC, 0x3F22);
1545
1546 if (phy->analog == 1)
1547 b43_phy_write(dev, 0x0020, 0x3E1C);
1548 else
1549 b43_phy_write(dev, 0x0020, 0x301C);
1550
1551 if (phy->analog == 0)
1552 b43_write16(dev, 0x03E4, 0x3000);
1553
1554 old_channel = phy->channel;
1555
1556 b43_gphy_channel_switch(dev, 7, 0);
1557
1558 if (phy->radio_ver != 0x2050) {
1559 b43_radio_write16(dev, 0x0075, 0x0080);
1560 b43_radio_write16(dev, 0x0079, 0x0081);
1561 }
1562
1563 b43_radio_write16(dev, 0x0050, 0x0020);
1564 b43_radio_write16(dev, 0x0050, 0x0023);
1565
1566 if (phy->radio_ver == 0x2050) {
1567 b43_radio_write16(dev, 0x0050, 0x0020);
1568 b43_radio_write16(dev, 0x005A, 0x0070);
1569 }
1570
1571 b43_radio_write16(dev, 0x005B, 0x007B);
1572 b43_radio_write16(dev, 0x005C, 0x00B0);
1573
1574 b43_radio_set(dev, 0x007A, 0x0007);
1575
1576 b43_gphy_channel_switch(dev, old_channel, 0);
1577
1578 b43_phy_write(dev, 0x0014, 0x0080);
1579 b43_phy_write(dev, 0x0032, 0x00CA);
1580 b43_phy_write(dev, 0x002A, 0x88A3);
1581
1582 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1583
1584 if (phy->radio_ver == 0x2050)
1585 b43_radio_write16(dev, 0x005D, 0x000D);
1586
1587 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1588}
1589
1590static void b43_phy_initb6(struct b43_wldev *dev)
1591{
1592 struct b43_phy *phy = &dev->phy;
1593 struct b43_phy_g *gphy = phy->g;
1594 u16 offset, val;
1595 u8 old_channel;
1596
1597 b43_phy_write(dev, 0x003E, 0x817A);
1598 b43_radio_write16(dev, 0x007A,
1599 (b43_radio_read16(dev, 0x007A) | 0x0058));
1600 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1601 b43_radio_write16(dev, 0x51, 0x37);
1602 b43_radio_write16(dev, 0x52, 0x70);
1603 b43_radio_write16(dev, 0x53, 0xB3);
1604 b43_radio_write16(dev, 0x54, 0x9B);
1605 b43_radio_write16(dev, 0x5A, 0x88);
1606 b43_radio_write16(dev, 0x5B, 0x88);
1607 b43_radio_write16(dev, 0x5D, 0x88);
1608 b43_radio_write16(dev, 0x5E, 0x88);
1609 b43_radio_write16(dev, 0x7D, 0x88);
1610 b43_hf_write(dev, b43_hf_read(dev)
1611 | B43_HF_TSSIRPSMW);
1612 }
1613 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7);
1614 if (phy->radio_rev == 8) {
1615 b43_radio_write16(dev, 0x51, 0);
1616 b43_radio_write16(dev, 0x52, 0x40);
1617 b43_radio_write16(dev, 0x53, 0xB7);
1618 b43_radio_write16(dev, 0x54, 0x98);
1619 b43_radio_write16(dev, 0x5A, 0x88);
1620 b43_radio_write16(dev, 0x5B, 0x6B);
1621 b43_radio_write16(dev, 0x5C, 0x0F);
1622 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1623 b43_radio_write16(dev, 0x5D, 0xFA);
1624 b43_radio_write16(dev, 0x5E, 0xD8);
1625 } else {
1626 b43_radio_write16(dev, 0x5D, 0xF5);
1627 b43_radio_write16(dev, 0x5E, 0xB8);
1628 }
1629 b43_radio_write16(dev, 0x0073, 0x0003);
1630 b43_radio_write16(dev, 0x007D, 0x00A8);
1631 b43_radio_write16(dev, 0x007C, 0x0001);
1632 b43_radio_write16(dev, 0x007E, 0x0008);
1633 }
1634 val = 0x1E1F;
1635 for (offset = 0x0088; offset < 0x0098; offset++) {
1636 b43_phy_write(dev, offset, val);
1637 val -= 0x0202;
1638 }
1639 val = 0x3E3F;
1640 for (offset = 0x0098; offset < 0x00A8; offset++) {
1641 b43_phy_write(dev, offset, val);
1642 val -= 0x0202;
1643 }
1644 val = 0x2120;
1645 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1646 b43_phy_write(dev, offset, (val & 0x3F3F));
1647 val += 0x0202;
1648 }
1649 if (phy->type == B43_PHYTYPE_G) {
1650 b43_radio_set(dev, 0x007A, 0x0020);
1651 b43_radio_set(dev, 0x0051, 0x0004);
1652 b43_phy_set(dev, 0x0802, 0x0100);
1653 b43_phy_set(dev, 0x042B, 0x2000);
1654 b43_phy_write(dev, 0x5B, 0);
1655 b43_phy_write(dev, 0x5C, 0);
1656 }
1657
1658 old_channel = phy->channel;
1659 if (old_channel >= 8)
1660 b43_gphy_channel_switch(dev, 1, 0);
1661 else
1662 b43_gphy_channel_switch(dev, 13, 0);
1663
1664 b43_radio_write16(dev, 0x0050, 0x0020);
1665 b43_radio_write16(dev, 0x0050, 0x0023);
1666 udelay(40);
1667 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1668 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1669 | 0x0002));
1670 b43_radio_write16(dev, 0x50, 0x20);
1671 }
1672 if (phy->radio_rev <= 2) {
1673 b43_radio_write16(dev, 0x7C, 0x20);
1674 b43_radio_write16(dev, 0x5A, 0x70);
1675 b43_radio_write16(dev, 0x5B, 0x7B);
1676 b43_radio_write16(dev, 0x5C, 0xB0);
1677 }
1678 b43_radio_maskset(dev, 0x007A, 0x00F8, 0x0007);
1679
1680 b43_gphy_channel_switch(dev, old_channel, 0);
1681
1682 b43_phy_write(dev, 0x0014, 0x0200);
1683 if (phy->radio_rev >= 6)
1684 b43_phy_write(dev, 0x2A, 0x88C2);
1685 else
1686 b43_phy_write(dev, 0x2A, 0x8AC0);
1687 b43_phy_write(dev, 0x0038, 0x0668);
1688 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1689 if (phy->radio_rev <= 5) {
1690 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003);
1691 }
1692 if (phy->radio_rev <= 2)
1693 b43_radio_write16(dev, 0x005D, 0x000D);
1694
1695 if (phy->analog == 4) {
1696 b43_write16(dev, 0x3E4, 9);
1697 b43_phy_mask(dev, 0x61, 0x0FFF);
1698 } else {
1699 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004);
1700 }
1701 if (phy->type == B43_PHYTYPE_B)
1702 B43_WARN_ON(1);
1703 else if (phy->type == B43_PHYTYPE_G)
1704 b43_write16(dev, 0x03E6, 0x0);
1705}
1706
1707static void b43_calc_loopback_gain(struct b43_wldev *dev)
1708{
1709 struct b43_phy *phy = &dev->phy;
1710 struct b43_phy_g *gphy = phy->g;
1711 u16 backup_phy[16] = { 0 };
1712 u16 backup_radio[3];
1713 u16 backup_bband;
1714 u16 i, j, loop_i_max;
1715 u16 trsw_rx;
1716 u16 loop1_outer_done, loop1_inner_done;
1717
1718 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1719 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1720 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1721 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1722 if (phy->rev != 1) {
1723 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1724 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1725 }
1726 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1727 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1728 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1729 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1730 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1731 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1732 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1733 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1734 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1735 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1736 backup_bband = gphy->bbatt.att;
1737 backup_radio[0] = b43_radio_read16(dev, 0x52);
1738 backup_radio[1] = b43_radio_read16(dev, 0x43);
1739 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1740
1741 b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF);
1742 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000);
1743 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002);
1744 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD);
1745 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001);
1746 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE);
1747 if (phy->rev != 1) {
1748 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001);
1749 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE);
1750 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002);
1751 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD);
1752 }
1753 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C);
1754 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C);
1755 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030);
1756 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10);
1757
1758 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1759 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1760 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1761
1762 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000);
1763 if (phy->rev != 1) {
1764 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004);
1765 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB);
1766 }
1767 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40);
1768
1769 if (phy->radio_rev == 8) {
1770 b43_radio_write16(dev, 0x43, 0x000F);
1771 } else {
1772 b43_radio_write16(dev, 0x52, 0);
1773 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x9);
1774 }
1775 b43_gphy_set_baseband_attenuation(dev, 11);
1776
1777 if (phy->rev >= 3)
1778 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1779 else
1780 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1781 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1782
1783 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01);
1784 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800);
1785
1786 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1787 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
1788
1789 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1790 if (phy->rev >= 7) {
1791 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800);
1792 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000);
1793 }
1794 }
1795 b43_radio_mask(dev, 0x7A, 0x00F7);
1796
1797 j = 0;
1798 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1799 for (i = 0; i < loop_i_max; i++) {
1800 for (j = 0; j < 16; j++) {
1801 b43_radio_write16(dev, 0x43, i);
1802 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1803 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1804 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1805 udelay(20);
1806 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1807 goto exit_loop1;
1808 }
1809 }
1810 exit_loop1:
1811 loop1_outer_done = i;
1812 loop1_inner_done = j;
1813 if (j >= 8) {
1814 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30);
1815 trsw_rx = 0x1B;
1816 for (j = j - 8; j < 16; j++) {
1817 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1818 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1819 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1820 udelay(20);
1821 trsw_rx -= 3;
1822 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1823 goto exit_loop2;
1824 }
1825 } else
1826 trsw_rx = 0x18;
1827 exit_loop2:
1828
1829 if (phy->rev != 1) {
1830 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1831 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1832 }
1833 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1834 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1835 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1836 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1837 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1838 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1839 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1840 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1841 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1842
1843 b43_gphy_set_baseband_attenuation(dev, backup_bband);
1844
1845 b43_radio_write16(dev, 0x52, backup_radio[0]);
1846 b43_radio_write16(dev, 0x43, backup_radio[1]);
1847 b43_radio_write16(dev, 0x7A, backup_radio[2]);
1848
1849 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1850 udelay(10);
1851 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1852 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1853 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1854 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1855
1856 gphy->max_lb_gain =
1857 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1858 gphy->trsw_rx_gain = trsw_rx * 2;
1859}
1860
1861static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
1862{
1863 struct b43_phy *phy = &dev->phy;
1864
1865 if (!b43_has_hardware_pctl(dev)) {
1866 b43_phy_write(dev, 0x047A, 0xC111);
1867 return;
1868 }
1869
1870 b43_phy_mask(dev, 0x0036, 0xFEFF);
1871 b43_phy_write(dev, 0x002F, 0x0202);
1872 b43_phy_set(dev, 0x047C, 0x0002);
1873 b43_phy_set(dev, 0x047A, 0xF000);
1874 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
1875 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1876 b43_phy_set(dev, 0x005D, 0x8000);
1877 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1878 b43_phy_write(dev, 0x002E, 0xC07F);
1879 b43_phy_set(dev, 0x0036, 0x0400);
1880 } else {
1881 b43_phy_set(dev, 0x0036, 0x0200);
1882 b43_phy_set(dev, 0x0036, 0x0400);
1883 b43_phy_mask(dev, 0x005D, 0x7FFF);
1884 b43_phy_mask(dev, 0x004F, 0xFFFE);
1885 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1886 b43_phy_write(dev, 0x002E, 0xC07F);
1887 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1888 }
1889}
1890
1891
1892static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
1893{
1894 struct b43_phy *phy = &dev->phy;
1895 struct b43_phy_g *gphy = phy->g;
1896
1897 if (!b43_has_hardware_pctl(dev)) {
1898
1899 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
1900 return;
1901 }
1902
1903 b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1904 b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1905 b43_gphy_tssi_power_lt_init(dev);
1906 b43_gphy_gain_lt_init(dev);
1907 b43_phy_mask(dev, 0x0060, 0xFFBF);
1908 b43_phy_write(dev, 0x0014, 0x0000);
1909
1910 B43_WARN_ON(phy->rev < 6);
1911 b43_phy_set(dev, 0x0478, 0x0800);
1912 b43_phy_mask(dev, 0x0478, 0xFEFF);
1913 b43_phy_mask(dev, 0x0801, 0xFFBF);
1914
1915 b43_gphy_dc_lt_init(dev, 1);
1916
1917
1918 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
1919}
1920
1921
1922static void b43_phy_init_pctl(struct b43_wldev *dev)
1923{
1924 struct ssb_bus *bus = dev->dev->bus;
1925 struct b43_phy *phy = &dev->phy;
1926 struct b43_phy_g *gphy = phy->g;
1927 struct b43_rfatt old_rfatt;
1928 struct b43_bbatt old_bbatt;
1929 u8 old_tx_control = 0;
1930
1931 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
1932
1933 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1934 (bus->boardinfo.type == SSB_BOARD_BU4306))
1935 return;
1936
1937 b43_phy_write(dev, 0x0028, 0x8018);
1938
1939
1940 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
1941 & 0xFFDF);
1942
1943 if (!phy->gmode)
1944 return;
1945 b43_hardware_pctl_early_init(dev);
1946 if (gphy->cur_idle_tssi == 0) {
1947 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
1948 b43_radio_maskset(dev, 0x0076, 0x00F7, 0x0084);
1949 } else {
1950 struct b43_rfatt rfatt;
1951 struct b43_bbatt bbatt;
1952
1953 memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt));
1954 memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt));
1955 old_tx_control = gphy->tx_control;
1956
1957 bbatt.att = 11;
1958 if (phy->radio_rev == 8) {
1959 rfatt.att = 15;
1960 rfatt.with_padmix = 1;
1961 } else {
1962 rfatt.att = 9;
1963 rfatt.with_padmix = 0;
1964 }
1965 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
1966 }
1967 b43_dummy_transmission(dev, false, true);
1968 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
1969 if (B43_DEBUG) {
1970
1971 if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) {
1972 b43dbg(dev->wl,
1973 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
1974 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
1975 "adjustment.\n", gphy->cur_idle_tssi,
1976 gphy->tgt_idle_tssi);
1977 gphy->cur_idle_tssi = 0;
1978 }
1979 }
1980 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
1981 b43_radio_mask(dev, 0x0076, 0xFF7B);
1982 } else {
1983 b43_set_txpower_g(dev, &old_bbatt,
1984 &old_rfatt, old_tx_control);
1985 }
1986 }
1987 b43_hardware_pctl_init_gphy(dev);
1988 b43_shm_clear_tssi(dev);
1989}
1990
1991static void b43_phy_initg(struct b43_wldev *dev)
1992{
1993 struct b43_phy *phy = &dev->phy;
1994 struct b43_phy_g *gphy = phy->g;
1995 u16 tmp;
1996
1997 if (phy->rev == 1)
1998 b43_phy_initb5(dev);
1999 else
2000 b43_phy_initb6(dev);
2001
2002 if (phy->rev >= 2 || phy->gmode)
2003 b43_phy_inita(dev);
2004
2005 if (phy->rev >= 2) {
2006 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
2007 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
2008 }
2009 if (phy->rev == 2) {
2010 b43_phy_write(dev, B43_PHY_RFOVER, 0);
2011 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2012 }
2013 if (phy->rev > 5) {
2014 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
2015 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2016 }
2017 if (phy->gmode || phy->rev >= 2) {
2018 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
2019 tmp &= B43_PHYVER_VERSION;
2020 if (tmp == 3 || tmp == 5) {
2021 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
2022 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2023 }
2024 if (tmp == 5) {
2025 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00);
2026 }
2027 }
2028 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
2029 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
2030 if (phy->radio_rev == 8) {
2031 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80);
2032 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4);
2033 }
2034 if (has_loopback_gain(phy))
2035 b43_calc_loopback_gain(dev);
2036
2037 if (phy->radio_rev != 8) {
2038 if (gphy->initval == 0xFFFF)
2039 gphy->initval = b43_radio_init2050(dev);
2040 else
2041 b43_radio_write16(dev, 0x0078, gphy->initval);
2042 }
2043 b43_lo_g_init(dev);
2044 if (has_tx_magnification(phy)) {
2045 b43_radio_write16(dev, 0x52,
2046 (b43_radio_read16(dev, 0x52) & 0xFF00)
2047 | gphy->lo_control->tx_bias | gphy->
2048 lo_control->tx_magn);
2049 } else {
2050 b43_radio_maskset(dev, 0x52, 0xFFF0, gphy->lo_control->tx_bias);
2051 }
2052 if (phy->rev >= 6) {
2053 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12));
2054 }
2055 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2056 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2057 else
2058 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
2059 if (phy->rev < 2)
2060 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
2061 else
2062 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
2063 if (phy->gmode || phy->rev >= 2) {
2064 b43_lo_g_adjust(dev);
2065 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2066 }
2067
2068 if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2069
2070
2071
2072
2073
2074
2075 b43_nrssi_hw_update(dev, 0xFFFF);
2076 b43_calc_nrssi_threshold(dev);
2077 } else if (phy->gmode || phy->rev >= 2) {
2078 if (gphy->nrssi[0] == -1000) {
2079 B43_WARN_ON(gphy->nrssi[1] != -1000);
2080 b43_calc_nrssi_slope(dev);
2081 } else
2082 b43_calc_nrssi_threshold(dev);
2083 }
2084 if (phy->radio_rev == 8)
2085 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
2086 b43_phy_init_pctl(dev);
2087
2088
2089
2090 if ((dev->dev->bus->chip_id == 0x4306
2091 && dev->dev->bus->chip_package == 2) || 0) {
2092 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF);
2093 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF);
2094 }
2095}
2096
2097void b43_gphy_channel_switch(struct b43_wldev *dev,
2098 unsigned int channel,
2099 bool synthetic_pu_workaround)
2100{
2101 if (synthetic_pu_workaround)
2102 b43_synth_pu_workaround(dev, channel);
2103
2104 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2105
2106 if (channel == 14) {
2107 if (dev->dev->bus->sprom.country_code ==
2108 SSB_SPROM1CCODE_JAPAN)
2109 b43_hf_write(dev,
2110 b43_hf_read(dev) & ~B43_HF_ACPR);
2111 else
2112 b43_hf_write(dev,
2113 b43_hf_read(dev) | B43_HF_ACPR);
2114 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2115 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2116 | (1 << 11));
2117 } else {
2118 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2119 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2120 & 0xF7BF);
2121 }
2122}
2123
2124static void default_baseband_attenuation(struct b43_wldev *dev,
2125 struct b43_bbatt *bb)
2126{
2127 struct b43_phy *phy = &dev->phy;
2128
2129 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
2130 bb->att = 0;
2131 else
2132 bb->att = 2;
2133}
2134
2135static void default_radio_attenuation(struct b43_wldev *dev,
2136 struct b43_rfatt *rf)
2137{
2138 struct ssb_bus *bus = dev->dev->bus;
2139 struct b43_phy *phy = &dev->phy;
2140
2141 rf->with_padmix = 0;
2142
2143 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
2144 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
2145 if (bus->boardinfo.rev < 0x43) {
2146 rf->att = 2;
2147 return;
2148 } else if (bus->boardinfo.rev < 0x51) {
2149 rf->att = 3;
2150 return;
2151 }
2152 }
2153
2154 if (phy->type == B43_PHYTYPE_A) {
2155 rf->att = 0x60;
2156 return;
2157 }
2158
2159 switch (phy->radio_ver) {
2160 case 0x2053:
2161 switch (phy->radio_rev) {
2162 case 1:
2163 rf->att = 6;
2164 return;
2165 }
2166 break;
2167 case 0x2050:
2168 switch (phy->radio_rev) {
2169 case 0:
2170 rf->att = 5;
2171 return;
2172 case 1:
2173 if (phy->type == B43_PHYTYPE_G) {
2174 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2175 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2176 && bus->boardinfo.rev >= 30)
2177 rf->att = 3;
2178 else if (bus->boardinfo.vendor ==
2179 SSB_BOARDVENDOR_BCM
2180 && bus->boardinfo.type ==
2181 SSB_BOARD_BU4306)
2182 rf->att = 3;
2183 else
2184 rf->att = 1;
2185 } else {
2186 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2187 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2188 && bus->boardinfo.rev >= 30)
2189 rf->att = 7;
2190 else
2191 rf->att = 6;
2192 }
2193 return;
2194 case 2:
2195 if (phy->type == B43_PHYTYPE_G) {
2196 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2197 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2198 && bus->boardinfo.rev >= 30)
2199 rf->att = 3;
2200 else if (bus->boardinfo.vendor ==
2201 SSB_BOARDVENDOR_BCM
2202 && bus->boardinfo.type ==
2203 SSB_BOARD_BU4306)
2204 rf->att = 5;
2205 else if (bus->chip_id == 0x4320)
2206 rf->att = 4;
2207 else
2208 rf->att = 3;
2209 } else
2210 rf->att = 6;
2211 return;
2212 case 3:
2213 rf->att = 5;
2214 return;
2215 case 4:
2216 case 5:
2217 rf->att = 1;
2218 return;
2219 case 6:
2220 case 7:
2221 rf->att = 5;
2222 return;
2223 case 8:
2224 rf->att = 0xA;
2225 rf->with_padmix = 1;
2226 return;
2227 case 9:
2228 default:
2229 rf->att = 5;
2230 return;
2231 }
2232 }
2233 rf->att = 5;
2234}
2235
2236static u16 default_tx_control(struct b43_wldev *dev)
2237{
2238 struct b43_phy *phy = &dev->phy;
2239
2240 if (phy->radio_ver != 0x2050)
2241 return 0;
2242 if (phy->radio_rev == 1)
2243 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
2244 if (phy->radio_rev < 6)
2245 return B43_TXCTL_PA2DB;
2246 if (phy->radio_rev == 8)
2247 return B43_TXCTL_TXMIX;
2248 return 0;
2249}
2250
2251static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel)
2252{
2253 struct b43_phy *phy = &dev->phy;
2254 struct b43_phy_g *gphy = phy->g;
2255 u8 ret = 0;
2256 u16 saved, rssi, temp;
2257 int i, j = 0;
2258
2259 saved = b43_phy_read(dev, 0x0403);
2260 b43_switch_channel(dev, channel);
2261 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2262 if (gphy->aci_hw_rssi)
2263 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2264 else
2265 rssi = saved & 0x3F;
2266
2267 if (rssi > 32)
2268 rssi -= 64;
2269 for (i = 0; i < 100; i++) {
2270 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2271 if (temp > 32)
2272 temp -= 64;
2273 if (temp < rssi)
2274 j++;
2275 if (j >= 20)
2276 ret = 1;
2277 }
2278 b43_phy_write(dev, 0x0403, saved);
2279
2280 return ret;
2281}
2282
2283static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2284{
2285 struct b43_phy *phy = &dev->phy;
2286 u8 ret[13];
2287 unsigned int channel = phy->channel;
2288 unsigned int i, j, start, end;
2289
2290 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2291 return 0;
2292
2293 b43_phy_lock(dev);
2294 b43_radio_lock(dev);
2295 b43_phy_mask(dev, 0x0802, 0xFFFC);
2296 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
2297 b43_set_all_gains(dev, 3, 8, 1);
2298
2299 start = (channel - 5 > 0) ? channel - 5 : 1;
2300 end = (channel + 5 < 14) ? channel + 5 : 13;
2301
2302 for (i = start; i <= end; i++) {
2303 if (abs(channel - i) > 2)
2304 ret[i - 1] = b43_gphy_aci_detect(dev, i);
2305 }
2306 b43_switch_channel(dev, channel);
2307 b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003);
2308 b43_phy_mask(dev, 0x0403, 0xFFF8);
2309 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
2310 b43_set_original_gains(dev);
2311 for (i = 0; i < 13; i++) {
2312 if (!ret[i])
2313 continue;
2314 end = (i + 5 < 13) ? i + 5 : 13;
2315 for (j = i; j < end; j++)
2316 ret[j] = 1;
2317 }
2318 b43_radio_unlock(dev);
2319 b43_phy_unlock(dev);
2320
2321 return ret[channel - 1];
2322}
2323
2324static s32 b43_tssi2dbm_ad(s32 num, s32 den)
2325{
2326 if (num < 0)
2327 return num / den;
2328 else
2329 return (num + den / 2) / den;
2330}
2331
2332static s8 b43_tssi2dbm_entry(s8 entry[], u8 index,
2333 s16 pab0, s16 pab1, s16 pab2)
2334{
2335 s32 m1, m2, f = 256, q, delta;
2336 s8 i = 0;
2337
2338 m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2339 m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2340 do {
2341 if (i > 15)
2342 return -EINVAL;
2343 q = b43_tssi2dbm_ad(f * 4096 -
2344 b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2345 delta = abs(q - f);
2346 f = q;
2347 i++;
2348 } while (delta >= 2);
2349 entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2350 return 0;
2351}
2352
2353u8 *b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
2354 s16 pab0, s16 pab1, s16 pab2)
2355{
2356 unsigned int i;
2357 u8 *tab;
2358 int err;
2359
2360 tab = kmalloc(64, GFP_KERNEL);
2361 if (!tab) {
2362 b43err(dev->wl, "Could not allocate memory "
2363 "for tssi2dbm table\n");
2364 return NULL;
2365 }
2366 for (i = 0; i < 64; i++) {
2367 err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2);
2368 if (err) {
2369 b43err(dev->wl, "Could not generate "
2370 "tssi2dBm table\n");
2371 kfree(tab);
2372 return NULL;
2373 }
2374 }
2375
2376 return tab;
2377}
2378
2379
2380static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2381{
2382 struct b43_phy *phy = &dev->phy;
2383 struct b43_phy_g *gphy = phy->g;
2384 s16 pab0, pab1, pab2;
2385
2386 pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
2387 pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
2388 pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
2389
2390 B43_WARN_ON((dev->dev->bus->chip_id == 0x4301) &&
2391 (phy->radio_ver != 0x2050));
2392
2393 gphy->dyn_tssi_tbl = 0;
2394
2395 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2396 pab0 != -1 && pab1 != -1 && pab2 != -1) {
2397
2398 if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
2399 (s8) dev->dev->bus->sprom.itssi_bg != -1) {
2400 gphy->tgt_idle_tssi =
2401 (s8) (dev->dev->bus->sprom.itssi_bg);
2402 } else
2403 gphy->tgt_idle_tssi = 62;
2404 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
2405 pab1, pab2);
2406 if (!gphy->tssi2dbm)
2407 return -ENOMEM;
2408 gphy->dyn_tssi_tbl = 1;
2409 } else {
2410
2411 gphy->tgt_idle_tssi = 52;
2412 gphy->tssi2dbm = b43_tssi2dbm_g_table;
2413 }
2414
2415 return 0;
2416}
2417
2418static int b43_gphy_op_allocate(struct b43_wldev *dev)
2419{
2420 struct b43_phy_g *gphy;
2421 struct b43_txpower_lo_control *lo;
2422 int err;
2423
2424 gphy = kzalloc(sizeof(*gphy), GFP_KERNEL);
2425 if (!gphy) {
2426 err = -ENOMEM;
2427 goto error;
2428 }
2429 dev->phy.g = gphy;
2430
2431 lo = kzalloc(sizeof(*lo), GFP_KERNEL);
2432 if (!lo) {
2433 err = -ENOMEM;
2434 goto err_free_gphy;
2435 }
2436 gphy->lo_control = lo;
2437
2438 err = b43_gphy_init_tssi2dbm_table(dev);
2439 if (err)
2440 goto err_free_lo;
2441
2442 return 0;
2443
2444err_free_lo:
2445 kfree(lo);
2446err_free_gphy:
2447 kfree(gphy);
2448error:
2449 return err;
2450}
2451
2452static void b43_gphy_op_prepare_structs(struct b43_wldev *dev)
2453{
2454 struct b43_phy *phy = &dev->phy;
2455 struct b43_phy_g *gphy = phy->g;
2456 const void *tssi2dbm;
2457 int tgt_idle_tssi;
2458 struct b43_txpower_lo_control *lo;
2459 unsigned int i;
2460
2461
2462
2463 tssi2dbm = gphy->tssi2dbm;
2464 tgt_idle_tssi = gphy->tgt_idle_tssi;
2465
2466 lo = gphy->lo_control;
2467
2468
2469 memset(gphy, 0, sizeof(*gphy));
2470
2471
2472 gphy->tssi2dbm = tssi2dbm;
2473 gphy->tgt_idle_tssi = tgt_idle_tssi;
2474 gphy->lo_control = lo;
2475
2476 memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig));
2477
2478
2479 for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++)
2480 gphy->nrssi[i] = -1000;
2481 for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++)
2482 gphy->nrssi_lt[i] = i;
2483
2484 gphy->lofcal = 0xFFFF;
2485 gphy->initval = 0xFFFF;
2486
2487 gphy->interfmode = B43_INTERFMODE_NONE;
2488
2489
2490 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
2491
2492 gphy->average_tssi = 0xFF;
2493
2494
2495 lo->tx_bias = 0xFF;
2496 INIT_LIST_HEAD(&lo->calib_list);
2497}
2498
2499static void b43_gphy_op_free(struct b43_wldev *dev)
2500{
2501 struct b43_phy *phy = &dev->phy;
2502 struct b43_phy_g *gphy = phy->g;
2503
2504 kfree(gphy->lo_control);
2505
2506 if (gphy->dyn_tssi_tbl)
2507 kfree(gphy->tssi2dbm);
2508 gphy->dyn_tssi_tbl = 0;
2509 gphy->tssi2dbm = NULL;
2510
2511 kfree(gphy);
2512 dev->phy.g = NULL;
2513}
2514
2515static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev)
2516{
2517 struct b43_phy *phy = &dev->phy;
2518 struct b43_phy_g *gphy = phy->g;
2519 struct b43_txpower_lo_control *lo = gphy->lo_control;
2520
2521 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2522
2523 default_baseband_attenuation(dev, &gphy->bbatt);
2524 default_radio_attenuation(dev, &gphy->rfatt);
2525 gphy->tx_control = (default_tx_control(dev) << 4);
2526 generate_rfatt_list(dev, &lo->rfatt_list);
2527 generate_bbatt_list(dev, &lo->bbatt_list);
2528
2529
2530 b43_read32(dev, B43_MMIO_MACCTL);
2531
2532 if (phy->rev == 1) {
2533
2534
2535 phy->gmode = 0;
2536 b43_wireless_core_reset(dev, 0);
2537 b43_phy_initg(dev);
2538 phy->gmode = 1;
2539 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
2540 }
2541
2542 return 0;
2543}
2544
2545static int b43_gphy_op_init(struct b43_wldev *dev)
2546{
2547 b43_phy_initg(dev);
2548
2549 return 0;
2550}
2551
2552static void b43_gphy_op_exit(struct b43_wldev *dev)
2553{
2554 b43_lo_g_cleanup(dev);
2555}
2556
2557static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
2558{
2559 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2560 return b43_read16(dev, B43_MMIO_PHY_DATA);
2561}
2562
2563static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2564{
2565 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2566 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2567}
2568
2569static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2570{
2571
2572 B43_WARN_ON(reg == 1);
2573
2574 reg |= 0x80;
2575
2576 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2577 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2578}
2579
2580static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2581{
2582
2583 B43_WARN_ON(reg == 1);
2584
2585 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2586 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2587}
2588
2589static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev)
2590{
2591 return (dev->phy.rev >= 6);
2592}
2593
2594static void b43_gphy_op_software_rfkill(struct b43_wldev *dev,
2595 bool blocked)
2596{
2597 struct b43_phy *phy = &dev->phy;
2598 struct b43_phy_g *gphy = phy->g;
2599 unsigned int channel;
2600
2601 might_sleep();
2602
2603 if (!blocked) {
2604
2605 if (phy->radio_on)
2606 return;
2607
2608 b43_phy_write(dev, 0x0015, 0x8000);
2609 b43_phy_write(dev, 0x0015, 0xCC00);
2610 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
2611 if (gphy->radio_off_context.valid) {
2612
2613 b43_phy_write(dev, B43_PHY_RFOVER,
2614 gphy->radio_off_context.rfover);
2615 b43_phy_write(dev, B43_PHY_RFOVERVAL,
2616 gphy->radio_off_context.rfoverval);
2617 gphy->radio_off_context.valid = 0;
2618 }
2619 channel = phy->channel;
2620 b43_gphy_channel_switch(dev, 6, 1);
2621 b43_gphy_channel_switch(dev, channel, 0);
2622 } else {
2623
2624 u16 rfover, rfoverval;
2625
2626 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
2627 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
2628 gphy->radio_off_context.rfover = rfover;
2629 gphy->radio_off_context.rfoverval = rfoverval;
2630 gphy->radio_off_context.valid = 1;
2631 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
2632 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
2633 }
2634}
2635
2636static int b43_gphy_op_switch_channel(struct b43_wldev *dev,
2637 unsigned int new_channel)
2638{
2639 if ((new_channel < 1) || (new_channel > 14))
2640 return -EINVAL;
2641 b43_gphy_channel_switch(dev, new_channel, 0);
2642
2643 return 0;
2644}
2645
2646static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev)
2647{
2648 return 1;
2649}
2650
2651static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2652{
2653 struct b43_phy *phy = &dev->phy;
2654 u16 tmp;
2655 int autodiv = 0;
2656
2657 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2658 autodiv = 1;
2659
2660 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
2661
2662 b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT,
2663 (autodiv ? B43_ANTENNA_AUTO1 : antenna) <<
2664 B43_PHY_BBANDCFG_RXANT_SHIFT);
2665
2666 if (autodiv) {
2667 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2668 if (antenna == B43_ANTENNA_AUTO1)
2669 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2670 else
2671 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2672 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2673 }
2674
2675 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2676 if (autodiv)
2677 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2678 else
2679 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2680 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2681
2682 if (autodiv)
2683 b43_phy_set(dev, B43_PHY_ANTWRSETT, B43_PHY_ANTWRSETT_ARXDIV);
2684 else {
2685 b43_phy_mask(dev, B43_PHY_ANTWRSETT,
2686 B43_PHY_ANTWRSETT_ARXDIV);
2687 }
2688
2689 if (phy->rev >= 2) {
2690 b43_phy_set(dev, B43_PHY_OFDM61, B43_PHY_OFDM61_10);
2691 b43_phy_maskset(dev, B43_PHY_DIVSRCHGAINBACK, 0xFF00, 0x15);
2692
2693 if (phy->rev == 2)
2694 b43_phy_write(dev, B43_PHY_ADIVRELATED, 8);
2695 else
2696 b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8);
2697 }
2698 if (phy->rev >= 6)
2699 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2700
2701 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
2702}
2703
2704static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev,
2705 enum b43_interference_mitigation mode)
2706{
2707 struct b43_phy *phy = &dev->phy;
2708 struct b43_phy_g *gphy = phy->g;
2709 int currentmode;
2710
2711 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2712 if ((phy->rev == 0) || (!phy->gmode))
2713 return -ENODEV;
2714
2715 gphy->aci_wlan_automatic = 0;
2716 switch (mode) {
2717 case B43_INTERFMODE_AUTOWLAN:
2718 gphy->aci_wlan_automatic = 1;
2719 if (gphy->aci_enable)
2720 mode = B43_INTERFMODE_MANUALWLAN;
2721 else
2722 mode = B43_INTERFMODE_NONE;
2723 break;
2724 case B43_INTERFMODE_NONE:
2725 case B43_INTERFMODE_NONWLAN:
2726 case B43_INTERFMODE_MANUALWLAN:
2727 break;
2728 default:
2729 return -EINVAL;
2730 }
2731
2732 currentmode = gphy->interfmode;
2733 if (currentmode == mode)
2734 return 0;
2735 if (currentmode != B43_INTERFMODE_NONE)
2736 b43_radio_interference_mitigation_disable(dev, currentmode);
2737
2738 if (mode == B43_INTERFMODE_NONE) {
2739 gphy->aci_enable = 0;
2740 gphy->aci_hw_rssi = 0;
2741 } else
2742 b43_radio_interference_mitigation_enable(dev, mode);
2743 gphy->interfmode = mode;
2744
2745 return 0;
2746}
2747
2748
2749
2750
2751static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
2752{
2753 struct b43_phy_g *gphy = dev->phy.g;
2754 s8 dbm;
2755 s32 tmp;
2756
2757 tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi);
2758 tmp = clamp_val(tmp, 0x00, 0x3F);
2759 dbm = gphy->tssi2dbm[tmp];
2760
2761 return dbm;
2762}
2763
2764static void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
2765 int *_bbatt, int *_rfatt)
2766{
2767 int rfatt = *_rfatt;
2768 int bbatt = *_bbatt;
2769 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
2770
2771
2772
2773
2774
2775 const int rf_min = lo->rfatt_list.min_val;
2776 const int rf_max = lo->rfatt_list.max_val;
2777 const int bb_min = lo->bbatt_list.min_val;
2778 const int bb_max = lo->bbatt_list.max_val;
2779
2780 while (1) {
2781 if (rfatt > rf_max && bbatt > bb_max - 4)
2782 break;
2783 if (rfatt < rf_min && bbatt < bb_min + 4)
2784 break;
2785 if (bbatt > bb_max && rfatt > rf_max - 1)
2786 break;
2787 if (bbatt < bb_min && rfatt < rf_min + 1)
2788 break;
2789
2790 if (bbatt > bb_max) {
2791 bbatt -= 4;
2792 rfatt += 1;
2793 continue;
2794 }
2795 if (bbatt < bb_min) {
2796 bbatt += 4;
2797 rfatt -= 1;
2798 continue;
2799 }
2800 if (rfatt > rf_max) {
2801 rfatt -= 1;
2802 bbatt += 4;
2803 continue;
2804 }
2805 if (rfatt < rf_min) {
2806 rfatt += 1;
2807 bbatt -= 4;
2808 continue;
2809 }
2810 break;
2811 }
2812
2813 *_rfatt = clamp_val(rfatt, rf_min, rf_max);
2814 *_bbatt = clamp_val(bbatt, bb_min, bb_max);
2815}
2816
2817static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev)
2818{
2819 struct b43_phy *phy = &dev->phy;
2820 struct b43_phy_g *gphy = phy->g;
2821 int rfatt, bbatt;
2822 u8 tx_control;
2823
2824 b43_mac_suspend(dev);
2825
2826
2827 bbatt = gphy->bbatt.att;
2828 bbatt += gphy->bbatt_delta;
2829 rfatt = gphy->rfatt.att;
2830 rfatt += gphy->rfatt_delta;
2831
2832 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2833 tx_control = gphy->tx_control;
2834 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2835 if (rfatt <= 1) {
2836 if (tx_control == 0) {
2837 tx_control =
2838 B43_TXCTL_PA2DB |
2839 B43_TXCTL_TXMIX;
2840 rfatt += 2;
2841 bbatt += 2;
2842 } else if (dev->dev->bus->sprom.
2843 boardflags_lo &
2844 B43_BFL_PACTRL) {
2845 bbatt += 4 * (rfatt - 2);
2846 rfatt = 2;
2847 }
2848 } else if (rfatt > 4 && tx_control) {
2849 tx_control = 0;
2850 if (bbatt < 3) {
2851 rfatt -= 3;
2852 bbatt += 2;
2853 } else {
2854 rfatt -= 2;
2855 bbatt -= 2;
2856 }
2857 }
2858 }
2859
2860 gphy->tx_control = tx_control;
2861 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2862 gphy->rfatt.att = rfatt;
2863 gphy->bbatt.att = bbatt;
2864
2865 if (b43_debug(dev, B43_DBG_XMITPOWER))
2866 b43dbg(dev->wl, "Adjusting TX power\n");
2867
2868
2869 b43_phy_lock(dev);
2870 b43_radio_lock(dev);
2871 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt,
2872 gphy->tx_control);
2873 b43_radio_unlock(dev);
2874 b43_phy_unlock(dev);
2875
2876 b43_mac_enable(dev);
2877}
2878
2879static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev,
2880 bool ignore_tssi)
2881{
2882 struct b43_phy *phy = &dev->phy;
2883 struct b43_phy_g *gphy = phy->g;
2884 unsigned int average_tssi;
2885 int cck_result, ofdm_result;
2886 int estimated_pwr, desired_pwr, pwr_adjust;
2887 int rfatt_delta, bbatt_delta;
2888 unsigned int max_pwr;
2889
2890
2891 cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK);
2892 ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G);
2893 if ((cck_result < 0) && (ofdm_result < 0)) {
2894
2895 if (!ignore_tssi)
2896 goto no_adjustment_needed;
2897 cck_result = 0;
2898 ofdm_result = 0;
2899 }
2900 if (cck_result < 0)
2901 average_tssi = ofdm_result;
2902 else if (ofdm_result < 0)
2903 average_tssi = cck_result;
2904 else
2905 average_tssi = (cck_result + ofdm_result) / 2;
2906
2907 if (likely(gphy->average_tssi != 0xFF))
2908 average_tssi = (average_tssi + gphy->average_tssi) / 2;
2909 gphy->average_tssi = average_tssi;
2910 B43_WARN_ON(average_tssi >= B43_TSSI_MAX);
2911
2912
2913 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi);
2914
2915 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2916 max_pwr = dev->dev->bus->sprom.maxpwr_bg;
2917 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2918 max_pwr -= 3;
2919 if (unlikely(max_pwr >= INT_TO_Q52(30))) {
2920 b43warn(dev->wl,
2921 "Invalid max-TX-power value in SPROM.\n");
2922 max_pwr = INT_TO_Q52(20);
2923 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
2924 }
2925
2926
2927 if (phy->desired_txpower < 0)
2928 desired_pwr = INT_TO_Q52(0);
2929 else
2930 desired_pwr = INT_TO_Q52(phy->desired_txpower);
2931
2932 desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
2933 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2934 b43dbg(dev->wl,
2935 "[TX power] current = " Q52_FMT
2936 " dBm, desired = " Q52_FMT
2937 " dBm, max = " Q52_FMT "\n",
2938 Q52_ARG(estimated_pwr),
2939 Q52_ARG(desired_pwr),
2940 Q52_ARG(max_pwr));
2941 }
2942
2943
2944 pwr_adjust = desired_pwr - estimated_pwr;
2945 if (pwr_adjust == 0)
2946 goto no_adjustment_needed;
2947
2948
2949 rfatt_delta = ((pwr_adjust + 7) / 8);
2950
2951 rfatt_delta = -rfatt_delta;
2952
2953
2954 bbatt_delta = pwr_adjust / 2;
2955
2956 bbatt_delta = -bbatt_delta;
2957
2958
2959 bbatt_delta -= 4 * rfatt_delta;
2960
2961#if B43_DEBUG
2962 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2963 int dbm = pwr_adjust < 0 ? -pwr_adjust : pwr_adjust;
2964 b43dbg(dev->wl,
2965 "[TX power deltas] %s" Q52_FMT " dBm => "
2966 "bbatt-delta = %d, rfatt-delta = %d\n",
2967 (pwr_adjust < 0 ? "-" : ""), Q52_ARG(dbm),
2968 bbatt_delta, rfatt_delta);
2969 }
2970#endif
2971
2972
2973 if ((rfatt_delta == 0) && (bbatt_delta == 0))
2974 goto no_adjustment_needed;
2975
2976
2977 gphy->bbatt_delta = bbatt_delta;
2978 gphy->rfatt_delta = rfatt_delta;
2979
2980
2981 return B43_TXPWR_RES_NEED_ADJUST;
2982
2983no_adjustment_needed:
2984 return B43_TXPWR_RES_DONE;
2985}
2986
2987static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev)
2988{
2989 struct b43_phy *phy = &dev->phy;
2990 struct b43_phy_g *gphy = phy->g;
2991
2992 b43_mac_suspend(dev);
2993
2994 if (gphy->aci_enable && gphy->aci_wlan_automatic) {
2995 if (!gphy->aci_enable && 1 ) {
2996 if (0 ) {
2997 phy->ops->interf_mitigation(dev,
2998 B43_INTERFMODE_MANUALWLAN);
2999 }
3000 } else if (0 ) {
3001 if ( !b43_gphy_aci_scan(dev))
3002 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3003 }
3004 } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN &&
3005 phy->rev == 1) {
3006
3007 }
3008 b43_lo_g_maintanance_work(dev);
3009 b43_mac_enable(dev);
3010}
3011
3012static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3013{
3014 struct b43_phy *phy = &dev->phy;
3015
3016 if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI))
3017 return;
3018
3019 b43_mac_suspend(dev);
3020 b43_calc_nrssi_slope(dev);
3021 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
3022 u8 old_chan = phy->channel;
3023
3024
3025 if (old_chan >= 8)
3026 b43_switch_channel(dev, 1);
3027 else
3028 b43_switch_channel(dev, 13);
3029 b43_switch_channel(dev, old_chan);
3030 }
3031 b43_mac_enable(dev);
3032}
3033
3034const struct b43_phy_operations b43_phyops_g = {
3035 .allocate = b43_gphy_op_allocate,
3036 .free = b43_gphy_op_free,
3037 .prepare_structs = b43_gphy_op_prepare_structs,
3038 .prepare_hardware = b43_gphy_op_prepare_hardware,
3039 .init = b43_gphy_op_init,
3040 .exit = b43_gphy_op_exit,
3041 .phy_read = b43_gphy_op_read,
3042 .phy_write = b43_gphy_op_write,
3043 .radio_read = b43_gphy_op_radio_read,
3044 .radio_write = b43_gphy_op_radio_write,
3045 .supports_hwpctl = b43_gphy_op_supports_hwpctl,
3046 .software_rfkill = b43_gphy_op_software_rfkill,
3047 .switch_analog = b43_phyop_switch_analog_generic,
3048 .switch_channel = b43_gphy_op_switch_channel,
3049 .get_default_chan = b43_gphy_op_get_default_chan,
3050 .set_rx_antenna = b43_gphy_op_set_rx_antenna,
3051 .interf_mitigation = b43_gphy_op_interf_mitigation,
3052 .recalc_txpower = b43_gphy_op_recalc_txpower,
3053 .adjust_txpower = b43_gphy_op_adjust_txpower,
3054 .pwork_15sec = b43_gphy_op_pwork_15sec,
3055 .pwork_60sec = b43_gphy_op_pwork_60sec,
3056};
3057
