1#ifndef B43_NPHY_H_ 2#define B43_NPHY_H_ 3 4#include "phy_common.h" 5 6 7/* N-PHY registers. */ 8 9#define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */ 10#define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */ 11#define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */ 12#define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */ 13#define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */ 14#define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */ 15#define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ 16#define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */ 17#define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */ 18#define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */ 19#define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */ 20#define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */ 21 22#define B43_NPHY_C1_DESPWR B43_PHY_N(0x018) /* Core 1 desired power */ 23#define B43_NPHY_C1_CCK_DESPWR B43_PHY_N(0x019) /* Core 1 CCK desired power */ 24#define B43_NPHY_C1_BCLIPBKOFF B43_PHY_N(0x01A) /* Core 1 barely clip backoff */ 25#define B43_NPHY_C1_CCK_BCLIPBKOFF B43_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */ 26#define B43_NPHY_C1_CGAINI B43_PHY_N(0x01C) /* Core 1 compute gain info */ 27#define B43_NPHY_C1_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ 28#define B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT 0 29#define B43_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */ 30#define B43_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT 5 31#define B43_NPHY_C1_CGAINI_GAINSTEP 0x1C00 /* Gain step */ 32#define B43_NPHY_C1_CGAINI_GAINSTEP_SHIFT 10 33#define B43_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */ 34#define B43_NPHY_C1_CCK_CGAINI B43_PHY_N(0x01D) /* Core 1 CCK compute gain info */ 35#define B43_NPHY_C1_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ 36#define B43_NPHY_C1_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */ 37#define B43_NPHY_C1_MINMAX_GAIN B43_PHY_N(0x01E) /* Core 1 min/max gain */ 38#define B43_NPHY_C1_MINGAIN 0x00FF /* Minimum gain */ 39#define B43_NPHY_C1_MINGAIN_SHIFT 0 40#define B43_NPHY_C1_MAXGAIN 0xFF00 /* Maximum gain */ 41#define B43_NPHY_C1_MAXGAIN_SHIFT 8 42#define B43_NPHY_C1_CCK_MINMAX_GAIN B43_PHY_N(0x01F) /* Core 1 CCK min/max gain */ 43#define B43_NPHY_C1_CCK_MINGAIN 0x00FF /* Minimum gain */ 44#define B43_NPHY_C1_CCK_MINGAIN_SHIFT 0 45#define B43_NPHY_C1_CCK_MAXGAIN 0xFF00 /* Maximum gain */ 46#define B43_NPHY_C1_CCK_MAXGAIN_SHIFT 8 47#define B43_NPHY_C1_INITGAIN B43_PHY_N(0x020) /* Core 1 initial gain code */ 48#define B43_NPHY_C1_INITGAIN_EXTLNA 0x0001 /* External LNA index */ 49#define B43_NPHY_C1_INITGAIN_LNA 0x0006 /* LNA index */ 50#define B43_NPHY_C1_INITGAIN_LNAIDX_SHIFT 1 51#define B43_NPHY_C1_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */ 52#define B43_NPHY_C1_INITGAIN_HPVGA1_SHIFT 3 53#define B43_NPHY_C1_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */ 54#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7 55#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ 56#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */ 57#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */ 58#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */ 59#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */ 60#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */ 61#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */ 62#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */ 63#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */ 64#define B43_NPHY_C1_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */ 65#define B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT 0 66#define B43_NPHY_C1_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */ 67#define B43_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT 6 68#define B43_NPHY_C1_W1THRES B43_PHY_N(0x028) /* Core 1 W1 threshold */ 69#define B43_NPHY_C1_EDTHRES B43_PHY_N(0x029) /* Core 1 ED threshold */ 70#define B43_NPHY_C1_SMSIGTHRES B43_PHY_N(0x02A) /* Core 1 small sig threshold */ 71#define B43_NPHY_C1_NBCLIPTHRES B43_PHY_N(0x02B) /* Core 1 NB clip threshold */ 72#define B43_NPHY_C1_CLIP1THRES B43_PHY_N(0x02C) /* Core 1 clip1 threshold */ 73#define B43_NPHY_C1_CLIP2THRES B43_PHY_N(0x02D) /* Core 1 clip2 threshold */ 74 75#define B43_NPHY_C2_DESPWR B43_PHY_N(0x02E) /* Core 2 desired power */ 76#define B43_NPHY_C2_CCK_DESPWR B43_PHY_N(0x02F) /* Core 2 CCK desired power */ 77#define B43_NPHY_C2_BCLIPBKOFF B43_PHY_N(0x030) /* Core 2 barely clip backoff */ 78#define B43_NPHY_C2_CCK_BCLIPBKOFF B43_PHY_N(0x031) /* Core 2 CCK barely clip backoff */ 79#define B43_NPHY_C2_CGAINI B43_PHY_N(0x032) /* Core 2 compute gain info */ 80#define B43_NPHY_C2_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ 81#define B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT 0 82#define B43_NPHY_C2_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */ 83#define B43_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT 5 84#define B43_NPHY_C2_CGAINI_GAINSTEP 0x1C00 /* Gain step */ 85#define B43_NPHY_C2_CGAINI_GAINSTEP_SHIFT 10 86#define B43_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */ 87#define B43_NPHY_C2_CCK_CGAINI B43_PHY_N(0x033) /* Core 2 CCK compute gain info */ 88#define B43_NPHY_C2_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ 89#define B43_NPHY_C2_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */ 90#define B43_NPHY_C2_MINMAX_GAIN B43_PHY_N(0x034) /* Core 2 min/max gain */ 91#define B43_NPHY_C2_MINGAIN 0x00FF /* Minimum gain */ 92#define B43_NPHY_C2_MINGAIN_SHIFT 0 93#define B43_NPHY_C2_MAXGAIN 0xFF00 /* Maximum gain */ 94#define B43_NPHY_C2_MAXGAIN_SHIFT 8 95#define B43_NPHY_C2_CCK_MINMAX_GAIN B43_PHY_N(0x035) /* Core 2 CCK min/max gain */ 96#define B43_NPHY_C2_CCK_MINGAIN 0x00FF /* Minimum gain */ 97#define B43_NPHY_C2_CCK_MINGAIN_SHIFT 0 98#define B43_NPHY_C2_CCK_MAXGAIN 0xFF00 /* Maximum gain */ 99#define B43_NPHY_C2_CCK_MAXGAIN_SHIFT 8 100#define B43_NPHY_C2_INITGAIN B43_PHY_N(0x036) /* Core 2 initial gain code */ 101#define B43_NPHY_C2_INITGAIN_EXTLNA 0x0001 /* External LNA index */ 102#define B43_NPHY_C2_INITGAIN_LNA 0x0006 /* LNA index */ 103#define B43_NPHY_C2_INITGAIN_LNAIDX_SHIFT 1 104#define B43_NPHY_C2_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */ 105#define B43_NPHY_C2_INITGAIN_HPVGA1_SHIFT 3 106#define B43_NPHY_C2_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */ 107#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7 108#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */ 109#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */ 110#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */ 111#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */ 112#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */ 113#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */ 114#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */ 115#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */ 116#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */ 117#define B43_NPHY_C2_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */ 118#define B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT 0 119#define B43_NPHY_C2_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */ 120#define B43_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT 6 121#define B43_NPHY_C2_W1THRES B43_PHY_N(0x03E) /* Core 2 W1 threshold */ 122#define B43_NPHY_C2_EDTHRES B43_PHY_N(0x03F) /* Core 2 ED threshold */ 123#define B43_NPHY_C2_SMSIGTHRES B43_PHY_N(0x040) /* Core 2 small sig threshold */ 124#define B43_NPHY_C2_NBCLIPTHRES B43_PHY_N(0x041) /* Core 2 NB clip threshold */ 125#define B43_NPHY_C2_CLIP1THRES B43_PHY_N(0x042) /* Core 2 clip1 threshold */ 126#define B43_NPHY_C2_CLIP2THRES B43_PHY_N(0x043) /* Core 2 clip2 threshold */ 127 128#define B43_NPHY_CRS_THRES1 B43_PHY_N(0x044) /* CRS threshold 1 */ 129#define B43_NPHY_CRS_THRES2 B43_PHY_N(0x045) /* CRS threshold 2 */ 130#define B43_NPHY_CRS_THRES3 B43_PHY_N(0x046) /* CRS threshold 3 */ 131#define B43_NPHY_CRSCTL B43_PHY_N(0x047) /* CRS control */ 132#define B43_NPHY_DCFADDR B43_PHY_N(0x048) /* DC filter address */ 133#define B43_NPHY_RXF20_NUM0 B43_PHY_N(0x049) /* RX filter 20 numerator 0 */ 134#define B43_NPHY_RXF20_NUM1 B43_PHY_N(0x04A) /* RX filter 20 numerator 1 */ 135#define B43_NPHY_RXF20_NUM2 B43_PHY_N(0x04B) /* RX filter 20 numerator 2 */ 136#define B43_NPHY_RXF20_DENOM0 B43_PHY_N(0x04C) /* RX filter 20 denominator 0 */ 137#define B43_NPHY_RXF20_DENOM1 B43_PHY_N(0x04D) /* RX filter 20 denominator 1 */ 138#define B43_NPHY_RXF20_NUM10 B43_PHY_N(0x04E) /* RX filter 20 numerator 10 */ 139#define B43_NPHY_RXF20_NUM11 B43_PHY_N(0x04F) /* RX filter 20 numerator 11 */ 140#define B43_NPHY_RXF20_NUM12 B43_PHY_N(0x050) /* RX filter 20 numerator 12 */ 141#define B43_NPHY_RXF20_DENOM10 B43_PHY_N(0x051) /* RX filter 20 denominator 10 */ 142#define B43_NPHY_RXF20_DENOM11 B43_PHY_N(0x052) /* RX filter 20 denominator 11 */ 143#define B43_NPHY_RXF40_NUM0 B43_PHY_N(0x053) /* RX filter 40 numerator 0 */ 144#define B43_NPHY_RXF40_NUM1 B43_PHY_N(0x054) /* RX filter 40 numerator 1 */ 145#define B43_NPHY_RXF40_NUM2 B43_PHY_N(0x055) /* RX filter 40 numerator 2 */ 146#define B43_NPHY_RXF40_DENOM0 B43_PHY_N(0x056) /* RX filter 40 denominator 0 */ 147#define B43_NPHY_RXF40_DENOM1 B43_PHY_N(0x057) /* RX filter 40 denominator 1 */ 148#define B43_NPHY_RXF40_NUM10 B43_PHY_N(0x058) /* RX filter 40 numerator 10 */ 149#define B43_NPHY_RXF40_NUM11 B43_PHY_N(0x059) /* RX filter 40 numerator 11 */ 150#define B43_NPHY_RXF40_NUM12 B43_PHY_N(0x05A) /* RX filter 40 numerator 12 */ 151#define B43_NPHY_RXF40_DENOM10 B43_PHY_N(0x05B) /* RX filter 40 denominator 10 */ 152#define B43_NPHY_RXF40_DENOM11 B43_PHY_N(0x05C) /* RX filter 40 denominator 11 */ 153#define B43_NPHY_PPROC_RSTLEN B43_PHY_N(0x060) /* Packet processing reset length */ 154#define B43_NPHY_INITCARR_DLEN B43_PHY_N(0x061) /* Initial carrier detection length */ 155#define B43_NPHY_CLIP1CARR_DLEN B43_PHY_N(0x062) /* Clip1 carrier detection length */ 156#define B43_NPHY_CLIP2CARR_DLEN B43_PHY_N(0x063) /* Clip2 carrier detection length */ 157#define B43_NPHY_INITGAIN_SLEN B43_PHY_N(0x064) /* Initial gain settle length */ 158#define B43_NPHY_CLIP1GAIN_SLEN B43_PHY_N(0x065) /* Clip1 gain settle length */ 159#define B43_NPHY_CLIP2GAIN_SLEN B43_PHY_N(0x066) /* Clip2 gain settle length */ 160#define B43_NPHY_PACKGAIN_SLEN B43_PHY_N(0x067) /* Packet gain settle length */ 161#define B43_NPHY_CARRSRC_TLEN B43_PHY_N(0x068) /* Carrier search timeout length */ 162#define B43_NPHY_TISRC_TLEN B43_PHY_N(0x069) /* Timing search timeout length */ 163#define B43_NPHY_ENDROP_TLEN B43_PHY_N(0x06A) /* Energy drop timeout length */ 164#define B43_NPHY_CLIP1_NBDWELL_LEN B43_PHY_N(0x06B) /* Clip1 NB dwell length */ 165#define B43_NPHY_CLIP2_NBDWELL_LEN B43_PHY_N(0x06C) /* Clip2 NB dwell length */ 166#define B43_NPHY_W1CLIP1_DWELL_LEN B43_PHY_N(0x06D) /* W1 clip1 dwell length */ 167#define B43_NPHY_W1CLIP2_DWELL_LEN B43_PHY_N(0x06E) /* W1 clip2 dwell length */ 168#define B43_NPHY_W2CLIP1_DWELL_LEN B43_PHY_N(0x06F) /* W2 clip1 dwell length */ 169#define B43_NPHY_PLOAD_CSENSE_EXTLEN B43_PHY_N(0x070) /* Payload carrier sense extension length */ 170#define B43_NPHY_EDROP_CSENSE_EXTLEN B43_PHY_N(0x071) /* Energy drop carrier sense extension length */ 171#define B43_NPHY_TABLE_ADDR B43_PHY_N(0x072) /* Table address */ 172#define B43_NPHY_TABLE_DATALO B43_PHY_N(0x073) /* Table data low */ 173#define B43_NPHY_TABLE_DATAHI B43_PHY_N(0x074) /* Table data high */ 174#define B43_NPHY_WWISE_LENIDX B43_PHY_N(0x075) /* WWiSE length index */ 175#define B43_NPHY_TGNSYNC_LENIDX B43_PHY_N(0x076) /* TGNsync length index */ 176#define B43_NPHY_TXMACIF_HOLDOFF B43_PHY_N(0x077) /* TX MAC IF Hold off */ 177#define B43_NPHY_RFCTL_CMD B43_PHY_N(0x078) /* RF control (command) */ 178#define B43_NPHY_RFCTL_CMD_START 0x0001 /* Start sequence */ 179#define B43_NPHY_RFCTL_CMD_RXTX 0x0002 /* RX/TX */ 180#define B43_NPHY_RFCTL_CMD_CORESEL 0x0038 /* Core select */ 181#define B43_NPHY_RFCTL_CMD_CORESEL_SHIFT 3 182#define B43_NPHY_RFCTL_CMD_PORFORCE 0x0040 /* POR force */ 183#define B43_NPHY_RFCTL_CMD_OEPORFORCE 0x0080 /* OE POR force */ 184#define B43_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */ 185#define B43_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */ 186#define B43_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */ 187#define B43_NPHY_RFCTL_CMD_EN 0x0800 /* Radio enabled */ 188#define B43_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */ 189#define B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12 190#define B43_NPHY_RFCTL_RSSIO1 B43_PHY_N(0x07A) /* RF control (RSSI others 1) */ 191#define B43_NPHY_RFCTL_RSSIO1_RXPD 0x0001 /* RX PD */ 192#define B43_NPHY_RFCTL_RSSIO1_TXPD 0x0002 /* TX PD */ 193#define B43_NPHY_RFCTL_RSSIO1_PAPD 0x0004 /* PA PD */ 194#define B43_NPHY_RFCTL_RSSIO1_RSSICTL 0x0030 /* RSSI control */ 195#define B43_NPHY_RFCTL_RSSIO1_LPFBW 0x00C0 /* LPF bandwidth */ 196#define B43_NPHY_RFCTL_RSSIO1_HPFBWHI 0x0100 /* HPF bandwidth high */ 197#define B43_NPHY_RFCTL_RSSIO1_HIQDISCO 0x0200 /* HIQ dis core */ 198#define B43_NPHY_RFCTL_RXG1 B43_PHY_N(0x07B) /* RF control (RX gain 1) */ 199#define B43_NPHY_RFCTL_TXG1 B43_PHY_N(0x07C) /* RF control (TX gain 1) */ 200#define B43_NPHY_RFCTL_RSSIO2 B43_PHY_N(0x07D) /* RF control (RSSI others 2) */ 201#define B43_NPHY_RFCTL_RSSIO2_RXPD 0x0001 /* RX PD */ 202#define B43_NPHY_RFCTL_RSSIO2_TXPD 0x0002 /* TX PD */ 203#define B43_NPHY_RFCTL_RSSIO2_PAPD 0x0004 /* PA PD */ 204#define B43_NPHY_RFCTL_RSSIO2_RSSICTL 0x0030 /* RSSI control */ 205#define B43_NPHY_RFCTL_RSSIO2_LPFBW 0x00C0 /* LPF bandwidth */ 206#define B43_NPHY_RFCTL_RSSIO2_HPFBWHI 0x0100 /* HPF bandwidth high */ 207#define B43_NPHY_RFCTL_RSSIO2_HIQDISCO 0x0200 /* HIQ dis core */ 208#define B43_NPHY_RFCTL_RXG2 B43_PHY_N(0x07E) /* RF control (RX gain 2) */ 209#define B43_NPHY_RFCTL_TXG2 B43_PHY_N(0x07F) /* RF control (TX gain 2) */ 210#define B43_NPHY_RFCTL_RSSIO3 B43_PHY_N(0x080) /* RF control (RSSI others 3) */ 211#define B43_NPHY_RFCTL_RSSIO3_RXPD 0x0001 /* RX PD */ 212#define B43_NPHY_RFCTL_RSSIO3_TXPD 0x0002 /* TX PD */ 213#define B43_NPHY_RFCTL_RSSIO3_PAPD 0x0004 /* PA PD */ 214#define B43_NPHY_RFCTL_RSSIO3_RSSICTL 0x0030 /* RSSI control */ 215#define B43_NPHY_RFCTL_RSSIO3_LPFBW 0x00C0 /* LPF bandwidth */ 216#define B43_NPHY_RFCTL_RSSIO3_HPFBWHI 0x0100 /* HPF bandwidth high */ 217#define B43_NPHY_RFCTL_RSSIO3_HIQDISCO 0x0200 /* HIQ dis core */ 218#define B43_NPHY_RFCTL_RXG3 B43_PHY_N(0x081) /* RF control (RX gain 3) */ 219#define B43_NPHY_RFCTL_TXG3 B43_PHY_N(0x082) /* RF control (TX gain 3) */ 220#define B43_NPHY_RFCTL_RSSIO4 B43_PHY_N(0x083) /* RF control (RSSI others 4) */ 221#define B43_NPHY_RFCTL_RSSIO4_RXPD 0x0001 /* RX PD */ 222#define B43_NPHY_RFCTL_RSSIO4_TXPD 0x0002 /* TX PD */ 223#define B43_NPHY_RFCTL_RSSIO4_PAPD 0x0004 /* PA PD */ 224#define B43_NPHY_RFCTL_RSSIO4_RSSICTL 0x0030 /* RSSI control */ 225#define B43_NPHY_RFCTL_RSSIO4_LPFBW 0x00C0 /* LPF bandwidth */ 226#define B43_NPHY_RFCTL_RSSIO4_HPFBWHI 0x0100 /* HPF bandwidth high */ 227#define B43_NPHY_RFCTL_RSSIO4_HIQDISCO 0x0200 /* HIQ dis core */ 228#define B43_NPHY_RFCTL_RXG4 B43_PHY_N(0x084) /* RF control (RX gain 4) */ 229#define B43_NPHY_RFCTL_TXG4 B43_PHY_N(0x085) /* RF control (TX gain 4) */ 230#define B43_NPHY_C1_TXIQ_COMP_OFF B43_PHY_N(0x087) /* Core 1 TX I/Q comp offset */ 231#define B43_NPHY_C2_TXIQ_COMP_OFF B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */ 232#define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */ 233#define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */ 234#define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scram signal control */ 235#define B43_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */ 236#define B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0 237#define B43_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */ 238#define B43_NPHY_SCRAM_SIGCTL_SICE 0x0100 /* Scram index control enable */ 239#define B43_NPHY_SCRAM_SIGCTL_START 0xFE00 /* Scram start bit */ 240#define B43_NPHY_SCRAM_SIGCTL_START_SHIFT 9 241#define B43_NPHY_RFCTL_INTC1 B43_PHY_N(0x091) /* RF control (intc 1) */ 242#define B43_NPHY_RFCTL_INTC2 B43_PHY_N(0x092) /* RF control (intc 2) */ 243#define B43_NPHY_RFCTL_INTC3 B43_PHY_N(0x093) /* RF control (intc 3) */ 244#define B43_NPHY_RFCTL_INTC4 B43_PHY_N(0x094) /* RF control (intc 4) */ 245#define B43_NPHY_NRDTO_WWISE B43_PHY_N(0x095) /* # datatones WWiSE */ 246#define B43_NPHY_NRDTO_TGNSYNC B43_PHY_N(0x096) /* # datatones TGNsync */ 247#define B43_NPHY_SIGFMOD_WWISE B43_PHY_N(0x097) /* Signal field mod WWiSE */ 248#define B43_NPHY_LEG_SIGFMOD_11N B43_PHY_N(0x098) /* Legacy signal field mod 11n */ 249#define B43_NPHY_HT_SIGFMOD_11N B43_PHY_N(0x099) /* HT signal field mod 11n */ 250#define B43_NPHY_C1_RXIQ_COMPA0 B43_PHY_N(0x09A) /* Core 1 RX I/Q comp A0 */ 251#define B43_NPHY_C1_RXIQ_COMPB0 B43_PHY_N(0x09B) /* Core 1 RX I/Q comp B0 */ 252#define B43_NPHY_C2_RXIQ_COMPA1 B43_PHY_N(0x09C) /* Core 2 RX I/Q comp A1 */ 253#define B43_NPHY_C2_RXIQ_COMPB1 B43_PHY_N(0x09D) /* Core 2 RX I/Q comp B1 */ 254#define B43_NPHY_RXCTL B43_PHY_N(0x0A0) /* RX control */ 255#define B43_NPHY_RXCTL_BSELU20 0x0010 /* Band select upper 20 */ 256#define B43_NPHY_RXCTL_RIFSEN 0x0080 /* RIFS enable */ 257#define B43_NPHY_RFSEQMODE B43_PHY_N(0x0A1) /* RF seq mode */ 258#define B43_NPHY_RFSEQMODE_CAOVER 0x0001 /* Core active override */ 259#define B43_NPHY_RFSEQMODE_TROVER 0x0002 /* Trigger override */ 260#define B43_NPHY_RFSEQCA B43_PHY_N(0x0A2) /* RF seq core active */ 261#define B43_NPHY_RFSEQCA_TXEN 0x000F /* TX enable */ 262#define B43_NPHY_RFSEQCA_TXEN_SHIFT 0 263#define B43_NPHY_RFSEQCA_RXEN 0x00F0 /* RX enable */ 264#define B43_NPHY_RFSEQCA_RXEN_SHIFT 4 265#define B43_NPHY_RFSEQCA_TXDIS 0x0F00 /* TX disable */ 266#define B43_NPHY_RFSEQCA_TXDIS_SHIFT 8 267#define B43_NPHY_RFSEQCA_RXDIS 0xF000 /* RX disable */ 268#define B43_NPHY_RFSEQCA_RXDIS_SHIFT 12 269#define B43_NPHY_RFSEQTR B43_PHY_N(0x0A3) /* RF seq trigger */ 270#define B43_NPHY_RFSEQTR_RX2TX 0x0001 /* RX2TX */ 271#define B43_NPHY_RFSEQTR_TX2RX 0x0002 /* TX2RX */ 272#define B43_NPHY_RFSEQTR_UPGH 0x0004 /* Update gain H */ 273#define B43_NPHY_RFSEQTR_UPGL 0x0008 /* Update gain L */ 274#define B43_NPHY_RFSEQTR_UPGU 0x0010 /* Update gain U */ 275#define B43_NPHY_RFSEQTR_RST2RX 0x0020 /* Reset to RX */ 276#define B43_NPHY_RFSEQST B43_PHY_N(0x0A4) /* RF seq status. Values same as trigger. */ 277#define B43_NPHY_AFECTL_OVER B43_PHY_N(0x0A5) /* AFE control override */ 278#define B43_NPHY_AFECTL_C1 B43_PHY_N(0x0A6) /* AFE control core 1 */ 279#define B43_NPHY_AFECTL_C2 B43_PHY_N(0x0A7) /* AFE control core 2 */ 280#define B43_NPHY_AFECTL_C3 B43_PHY_N(0x0A8) /* AFE control core 3 */ 281#define B43_NPHY_AFECTL_C4 B43_PHY_N(0x0A9) /* AFE control core 4 */ 282#define B43_NPHY_AFECTL_DACGAIN1 B43_PHY_N(0x0AA) /* AFE control DAC gain 1 */ 283#define B43_NPHY_AFECTL_DACGAIN2 B43_PHY_N(0x0AB) /* AFE control DAC gain 2 */ 284#define B43_NPHY_AFECTL_DACGAIN3 B43_PHY_N(0x0AC) /* AFE control DAC gain 3 */ 285#define B43_NPHY_AFECTL_DACGAIN4 B43_PHY_N(0x0AD) /* AFE control DAC gain 4 */ 286#define B43_NPHY_STR_ADDR1 B43_PHY_N(0x0AE) /* STR address 1 */ 287#define B43_NPHY_STR_ADDR2 B43_PHY_N(0x0AF) /* STR address 2 */ 288#define B43_NPHY_CLASSCTL B43_PHY_N(0x0B0) /* Classifier control */ 289#define B43_NPHY_CLASSCTL_CCKEN 0x0001 /* CCK enable */ 290#define B43_NPHY_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */ 291#define B43_NPHY_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */ 292#define B43_NPHY_IQFLIP B43_PHY_N(0x0B1) /* I/Q flip */ 293#define B43_NPHY_IQFLIP_ADC1 0x0001 /* ADC1 */ 294#define B43_NPHY_IQFLIP_ADC2 0x0010 /* ADC2 */ 295#define B43_NPHY_SISO_SNR_THRES B43_PHY_N(0x0B2) /* SISO SNR threshold */ 296#define B43_NPHY_SIGMA_N_MULT B43_PHY_N(0x0B3) /* Sigma N multiplier */ 297#define B43_NPHY_TXMACDELAY B43_PHY_N(0x0B4) /* TX MAC delay */ 298#define B43_NPHY_TXFRAMEDELAY B43_PHY_N(0x0B5) /* TX frame delay */ 299#define B43_NPHY_MLPARM B43_PHY_N(0x0B6) /* ML parameters */ 300#define B43_NPHY_MLCTL B43_PHY_N(0x0B7) /* ML control */ 301#define B43_NPHY_WWISE_20NCYCDAT B43_PHY_N(0x0B8) /* WWiSE 20 N cyc data */ 302#define B43_NPHY_WWISE_40NCYCDAT B43_PHY_N(0x0B9) /* WWiSE 40 N cyc data */ 303#define B43_NPHY_TGNSYNC_20NCYCDAT B43_PHY_N(0x0BA) /* TGNsync 20 N cyc data */ 304#define B43_NPHY_TGNSYNC_40NCYCDAT B43_PHY_N(0x0BB) /* TGNsync 40 N cyc data */ 305#define B43_NPHY_INITSWIZP B43_PHY_N(0x0BC) /* Initial swizzle pattern */ 306#define B43_NPHY_TXTAILCNT B43_PHY_N(0x0BD) /* TX tail count value */ 307#define B43_NPHY_BPHY_CTL1 B43_PHY_N(0x0BE) /* B PHY control 1 */ 308#define B43_NPHY_BPHY_CTL2 B43_PHY_N(0x0BF) /* B PHY control 2 */ 309#define B43_NPHY_BPHY_CTL2_LUT 0x001F /* LUT index */ 310#define B43_NPHY_BPHY_CTL2_LUT_SHIFT 0 311#define B43_NPHY_BPHY_CTL2_MACDEL 0x7FE0 /* MAC delay */ 312#define B43_NPHY_BPHY_CTL2_MACDEL_SHIFT 5 313#define B43_NPHY_IQLOCAL_CMD B43_PHY_N(0x0C0) /* I/Q LO cal command */ 314#define B43_NPHY_IQLOCAL_CMD_EN 0x8000 315#define B43_NPHY_IQLOCAL_CMDNNUM B43_PHY_N(0x0C1) /* I/Q LO cal command N num */ 316#define B43_NPHY_IQLOCAL_CMDGCTL B43_PHY_N(0x0C2) /* I/Q LO cal command G control */ 317#define B43_NPHY_SAMP_CMD B43_PHY_N(0x0C3) /* Sample command */ 318#define B43_NPHY_SAMP_CMD_STOP 0x0002 /* Stop */ 319#define B43_NPHY_SAMP_LOOPCNT B43_PHY_N(0x0C4) /* Sample loop count */ 320#define B43_NPHY_SAMP_WAITCNT B43_PHY_N(0x0C5) /* Sample wait count */ 321#define B43_NPHY_SAMP_DEPCNT B43_PHY_N(0x0C6) /* Sample depth count */ 322#define B43_NPHY_SAMP_STAT B43_PHY_N(0x0C7) /* Sample status */ 323#define B43_NPHY_GPIO_LOOEN B43_PHY_N(0x0C8) /* GPIO low out enable */ 324#define B43_NPHY_GPIO_HIOEN B43_PHY_N(0x0C9) /* GPIO high out enable */ 325#define B43_NPHY_GPIO_SEL B43_PHY_N(0x0CA) /* GPIO select */ 326#define B43_NPHY_GPIO_CLKCTL B43_PHY_N(0x0CB) /* GPIO clock control */ 327#define B43_NPHY_TXF_20CO_AS0 B43_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */ 328#define B43_NPHY_TXF_20CO_AS1 B43_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */ 329#define B43_NPHY_TXF_20CO_AS2 B43_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */ 330#define B43_NPHY_TXF_20CO_B32S0 B43_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */ 331#define B43_NPHY_TXF_20CO_B1S0 B43_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */ 332#define B43_NPHY_TXF_20CO_B32S1 B43_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */ 333#define B43_NPHY_TXF_20CO_B1S1 B43_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */ 334#define B43_NPHY_TXF_20CO_B32S2 B43_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */ 335#define B43_NPHY_TXF_20CO_B1S2 B43_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */ 336#define B43_NPHY_SIGFLDTOL B43_PHY_N(0x0D5) /* Signal fld tolerance */ 337#define B43_NPHY_TXSERFLD B43_PHY_N(0x0D6) /* TX service field */ 338#define B43_NPHY_AFESEQ_RX2TX_PUD B43_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */ 339#define B43_NPHY_AFESEQ_TX2RX_PUD B43_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */ 340#define B43_NPHY_TGNSYNC_SCRAMI0 B43_PHY_N(0x0D9) /* TGNsync scram init 0 */ 341#define B43_NPHY_TGNSYNC_SCRAMI1 B43_PHY_N(0x0DA) /* TGNsync scram init 1 */ 342#define B43_NPHY_INITSWIZPATTLEG B43_PHY_N(0x0DB) /* Initial swizzle pattern leg */ 343#define B43_NPHY_BPHY_CTL3 B43_PHY_N(0x0DC) /* B PHY control 3 */ 344#define B43_NPHY_BPHY_CTL3_SCALE 0x00FF /* Scale */ 345#define B43_NPHY_BPHY_CTL3_SCALE_SHIFT 0 346#define B43_NPHY_BPHY_CTL3_FSC 0xFF00 /* Frame start count value */ 347#define B43_NPHY_BPHY_CTL3_FSC_SHIFT 8 348#define B43_NPHY_BPHY_CTL4 B43_PHY_N(0x0DD) /* B PHY control 4 */ 349#define B43_NPHY_C1_TXBBMULT B43_PHY_N(0x0DE) /* Core 1 TX BB multiplier */ 350#define B43_NPHY_C2_TXBBMULT B43_PHY_N(0x0DF) /* Core 2 TX BB multiplier */ 351#define B43_NPHY_TXF_40CO_AS0 B43_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */ 352#define B43_NPHY_TXF_40CO_AS1 B43_PHY_N(0x0E2) /* TX filter 40 coeff A stage 1 */ 353#define B43_NPHY_TXF_40CO_AS2 B43_PHY_N(0x0E3) /* TX filter 40 coeff A stage 2 */ 354#define B43_NPHY_TXF_40CO_B32S0 B43_PHY_N(0x0E4) /* TX filter 40 coeff B32 stage 0 */ 355#define B43_NPHY_TXF_40CO_B1S0 B43_PHY_N(0x0E5) /* TX filter 40 coeff B1 stage 0 */ 356#define B43_NPHY_TXF_40CO_B32S1 B43_PHY_N(0x0E6) /* TX filter 40 coeff B32 stage 1 */ 357#define B43_NPHY_TXF_40CO_B1S1 B43_PHY_N(0x0E7) /* TX filter 40 coeff B1 stage 1 */ 358#define B43_NPHY_TXF_40CO_B32S2 B43_PHY_N(0x0E8) /* TX filter 40 coeff B32 stage 2 */ 359#define B43_NPHY_TXF_40CO_B1S2 B43_PHY_N(0x0E9) /* TX filter 40 coeff B1 stage 2 */ 360#define B43_NPHY_BIST_STAT2 B43_PHY_N(0x0EA) /* BIST status 2 */ 361#define B43_NPHY_BIST_STAT3 B43_PHY_N(0x0EB) /* BIST status 3 */ 362#define B43_NPHY_RFCTL_OVER B43_PHY_N(0x0EC) /* RF control override */ 363#define B43_NPHY_MIMOCFG B43_PHY_N(0x0ED) /* MIMO config */ 364#define B43_NPHY_MIMOCFG_GFMIX 0x0004 /* Greenfield or mixed mode */ 365#define B43_NPHY_MIMOCFG_AUTO 0x0100 /* Greenfield/mixed mode auto */ 366#define B43_NPHY_RADAR_BLNKCTL B43_PHY_N(0x0EE) /* Radar blank control */ 367#define B43_NPHY_A0RADAR_FIFOCTL B43_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */ 368#define B43_NPHY_A1RADAR_FIFOCTL B43_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */ 369#define B43_NPHY_A0RADAR_FIFODAT B43_PHY_N(0x0F1) /* Antenna 0 radar FIFO data */ 370#define B43_NPHY_A1RADAR_FIFODAT B43_PHY_N(0x0F2) /* Antenna 1 radar FIFO data */ 371#define B43_NPHY_RADAR_THRES0 B43_PHY_N(0x0F3) /* Radar threshold 0 */ 372#define B43_NPHY_RADAR_THRES1 B43_PHY_N(0x0F4) /* Radar threshold 1 */ 373#define B43_NPHY_RADAR_THRES0R B43_PHY_N(0x0F5) /* Radar threshold 0R */ 374#define B43_NPHY_RADAR_THRES1R B43_PHY_N(0x0F6) /* Radar threshold 1R */ 375#define B43_NPHY_CSEN_20IN40_DLEN B43_PHY_N(0x0F7) /* Carrier sense 20 in 40 dwell length */ 376#define B43_NPHY_RFCTL_LUT_TRSW_LO1 B43_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */ 377#define B43_NPHY_RFCTL_LUT_TRSW_UP1 B43_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */ 378#define B43_NPHY_RFCTL_LUT_TRSW_LO2 B43_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */ 379#define B43_NPHY_RFCTL_LUT_TRSW_UP2 B43_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */ 380#define B43_NPHY_RFCTL_LUT_TRSW_LO3 B43_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */ 381#define B43_NPHY_RFCTL_LUT_TRSW_UP3 B43_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */ 382#define B43_NPHY_RFCTL_LUT_TRSW_LO4 B43_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */ 383#define B43_NPHY_RFCTL_LUT_TRSW_UP4 B43_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */ 384#define B43_NPHY_RFCTL_LUT_LNAPA1 B43_PHY_N(0x100) /* RF control LUT LNA PA 1 */ 385#define B43_NPHY_RFCTL_LUT_LNAPA2 B43_PHY_N(0x101) /* RF control LUT LNA PA 2 */ 386#define B43_NPHY_RFCTL_LUT_LNAPA3 B43_PHY_N(0x102) /* RF control LUT LNA PA 3 */ 387#define B43_NPHY_RFCTL_LUT_LNAPA4 B43_PHY_N(0x103) /* RF control LUT LNA PA 4 */ 388#define B43_NPHY_TGNSYNC_CRCM0 B43_PHY_N(0x104) /* TGNsync CRC mask 0 */ 389#define B43_NPHY_TGNSYNC_CRCM1 B43_PHY_N(0x105) /* TGNsync CRC mask 1 */ 390#define B43_NPHY_TGNSYNC_CRCM2 B43_PHY_N(0x106) /* TGNsync CRC mask 2 */ 391#define B43_NPHY_TGNSYNC_CRCM3 B43_PHY_N(0x107) /* TGNsync CRC mask 3 */ 392#define B43_NPHY_TGNSYNC_CRCM4 B43_PHY_N(0x108) /* TGNsync CRC mask 4 */ 393#define B43_NPHY_CRCPOLY B43_PHY_N(0x109) /* CRC polynomial */ 394#define B43_NPHY_SIGCNT B43_PHY_N(0x10A) /* # sig count */ 395#define B43_NPHY_SIGSTARTBIT_CTL B43_PHY_N(0x10B) /* Sig start bit control */ 396#define B43_NPHY_CRCPOLY_ORDER B43_PHY_N(0x10C) /* CRC polynomial order */ 397#define B43_NPHY_RFCTL_CST0 B43_PHY_N(0x10D) /* RF control core swap table 0 */ 398#define B43_NPHY_RFCTL_CST1 B43_PHY_N(0x10E) /* RF control core swap table 1 */ 399#define B43_NPHY_RFCTL_CST2O B43_PHY_N(0x10F) /* RF control core swap table 2 + others */ 400#define B43_NPHY_BPHY_CTL5 B43_PHY_N(0x111) /* B PHY control 5 */ 401#define B43_NPHY_RFSEQ_LPFBW B43_PHY_N(0x112) /* RF seq LPF bandwidth */ 402#define B43_NPHY_TSSIBIAS1 B43_PHY_N(0x114) /* TSSI bias val 1 */ 403#define B43_NPHY_TSSIBIAS2 B43_PHY_N(0x115) /* TSSI bias val 2 */ 404#define B43_NPHY_TSSIBIAS_BIAS 0x00FF /* Bias */ 405#define B43_NPHY_TSSIBIAS_BIAS_SHIFT 0 406#define B43_NPHY_TSSIBIAS_VAL 0xFF00 /* Value */ 407#define B43_NPHY_TSSIBIAS_VAL_SHIFT 8 408#define B43_NPHY_ESTPWR1 B43_PHY_N(0x118) /* Estimated power 1 */ 409#define B43_NPHY_ESTPWR2 B43_PHY_N(0x119) /* Estimated power 2 */ 410#define B43_NPHY_ESTPWR_PWR 0x00FF /* Estimated power */ 411#define B43_NPHY_ESTPWR_PWR_SHIFT 0 412#define B43_NPHY_ESTPWR_VALID 0x0100 /* Estimated power valid */ 413#define B43_NPHY_TSSI_MAXTXFDT B43_PHY_N(0x11C) /* TSSI max TX frame delay time */ 414#define B43_NPHY_TSSI_MAXTXFDT_VAL 0x00FF /* max TX frame delay time */ 415#define B43_NPHY_TSSI_MAXTXFDT_VAL_SHIFT 0 416#define B43_NPHY_TSSI_MAXTDT B43_PHY_N(0x11D) /* TSSI max TSSI delay time */ 417#define B43_NPHY_TSSI_MAXTDT_VAL 0x00FF /* max TSSI delay time */ 418#define B43_NPHY_TSSI_MAXTDT_VAL_SHIFT 0 419#define B43_NPHY_ITSSI1 B43_PHY_N(0x11E) /* TSSI idle 1 */ 420#define B43_NPHY_ITSSI2 B43_PHY_N(0x11F) /* TSSI idle 2 */ 421#define B43_NPHY_ITSSI_VAL 0x00FF /* Idle TSSI */ 422#define B43_NPHY_ITSSI_VAL_SHIFT 0 423#define B43_NPHY_TSSIMODE B43_PHY_N(0x122) /* TSSI mode */ 424#define B43_NPHY_TSSIMODE_EN 0x0001 /* TSSI enable */ 425#define B43_NPHY_TSSIMODE_PDEN 0x0002 /* Power det enable */ 426#define B43_NPHY_RXMACIFM B43_PHY_N(0x123) /* RX Macif mode */ 427#define B43_NPHY_CRSIT_COCNT_LO B43_PHY_N(0x124) /* CRS idle time CRS-on count (low) */ 428#define B43_NPHY_CRSIT_COCNT_HI B43_PHY_N(0x125) /* CRS idle time CRS-on count (high) */ 429#define B43_NPHY_CRSIT_MTCNT_LO B43_PHY_N(0x126) /* CRS idle time measure time count (low) */ 430#define B43_NPHY_CRSIT_MTCNT_HI B43_PHY_N(0x127) /* CRS idle time measure time count (high) */ 431#define B43_NPHY_SAMTWC B43_PHY_N(0x128) /* Sample tail wait count */ 432#define B43_NPHY_IQEST_CMD B43_PHY_N(0x129) /* I/Q estimate command */ 433#define B43_NPHY_IQEST_CMD_START 0x0001 /* Start */ 434#define B43_NPHY_IQEST_CMD_MODE 0x0002 /* Mode */ 435#define B43_NPHY_IQEST_WT B43_PHY_N(0x12A) /* I/Q estimate wait time */ 436#define B43_NPHY_IQEST_WT_VAL 0x00FF /* Wait time */ 437#define B43_NPHY_IQEST_WT_VAL_SHIFT 0 438#define B43_NPHY_IQEST_SAMCNT B43_PHY_N(0x12B) /* I/Q estimate sample count */ 439#define B43_NPHY_IQEST_IQACC_LO0 B43_PHY_N(0x12C) /* I/Q estimate I/Q acc lo 0 */ 440#define B43_NPHY_IQEST_IQACC_HI0 B43_PHY_N(0x12D) /* I/Q estimate I/Q acc hi 0 */ 441#define B43_NPHY_IQEST_IPACC_LO0 B43_PHY_N(0x12E) /* I/Q estimate I power acc lo 0 */ 442#define B43_NPHY_IQEST_IPACC_HI0 B43_PHY_N(0x12F) /* I/Q estimate I power acc hi 0 */ 443#define B43_NPHY_IQEST_QPACC_LO0 B43_PHY_N(0x130) /* I/Q estimate Q power acc lo 0 */ 444#define B43_NPHY_IQEST_QPACC_HI0 B43_PHY_N(0x131) /* I/Q estimate Q power acc hi 0 */ 445#define B43_NPHY_IQEST_IQACC_LO1 B43_PHY_N(0x134) /* I/Q estimate I/Q acc lo 1 */ 446#define B43_NPHY_IQEST_IQACC_HI1 B43_PHY_N(0x135) /* I/Q estimate I/Q acc hi 1 */ 447#define B43_NPHY_IQEST_IPACC_LO1 B43_PHY_N(0x136) /* I/Q estimate I power acc lo 1 */ 448#define B43_NPHY_IQEST_IPACC_HI1 B43_PHY_N(0x137) /* I/Q estimate I power acc hi 1 */ 449#define B43_NPHY_IQEST_QPACC_LO1 B43_PHY_N(0x138) /* I/Q estimate Q power acc lo 1 */ 450#define B43_NPHY_IQEST_QPACC_HI1 B43_PHY_N(0x139) /* I/Q estimate Q power acc hi 1 */ 451#define B43_NPHY_MIMO_CRSTXEXT B43_PHY_N(0x13A) /* MIMO PHY CRS TX extension */ 452#define B43_NPHY_PWRDET1 B43_PHY_N(0x13B) /* Power det 1 */ 453#define B43_NPHY_PWRDET2 B43_PHY_N(0x13C) /* Power det 2 */ 454#define B43_NPHY_MAXRSSI_DTIME B43_PHY_N(0x13F) /* RSSI max RSSI delay time */ 455#define B43_NPHY_PIL_DW0 B43_PHY_N(0x141) /* Pilot data weight 0 */ 456#define B43_NPHY_PIL_DW1 B43_PHY_N(0x142) /* Pilot data weight 1 */ 457#define B43_NPHY_PIL_DW2 B43_PHY_N(0x143) /* Pilot data weight 2 */ 458#define B43_NPHY_PIL_DW_BPSK 0x000F /* BPSK */ 459#define B43_NPHY_PIL_DW_BPSK_SHIFT 0 460#define B43_NPHY_PIL_DW_QPSK 0x00F0 /* QPSK */ 461#define B43_NPHY_PIL_DW_QPSK_SHIFT 4 462#define B43_NPHY_PIL_DW_16QAM 0x0F00 /* 16-QAM */ 463#define B43_NPHY_PIL_DW_16QAM_SHIFT 8 464#define B43_NPHY_PIL_DW_64QAM 0xF000 /* 64-QAM */ 465#define B43_NPHY_PIL_DW_64QAM_SHIFT 12 466#define B43_NPHY_FMDEM_CFG B43_PHY_N(0x144) /* FM demodulation config */ 467#define B43_NPHY_PHASETR_A0 B43_PHY_N(0x145) /* Phase track alpha 0 */ 468#define B43_NPHY_PHASETR_A1 B43_PHY_N(0x146) /* Phase track alpha 1 */ 469#define B43_NPHY_PHASETR_A2 B43_PHY_N(0x147) /* Phase track alpha 2 */ 470#define B43_NPHY_PHASETR_B0 B43_PHY_N(0x148) /* Phase track beta 0 */ 471#define B43_NPHY_PHASETR_B1 B43_PHY_N(0x149) /* Phase track beta 1 */ 472#define B43_NPHY_PHASETR_B2 B43_PHY_N(0x14A) /* Phase track beta 2 */ 473#define B43_NPHY_PHASETR_CHG0 B43_PHY_N(0x14B) /* Phase track change 0 */ 474#define B43_NPHY_PHASETR_CHG1 B43_PHY_N(0x14C) /* Phase track change 1 */ 475#define B43_NPHY_PHASETW_OFF B43_PHY_N(0x14D) /* Phase track offset */ 476#define B43_NPHY_RFCTL_DBG B43_PHY_N(0x14E) /* RF control debug */ 477#define B43_NPHY_CCK_SHIFTB_REF B43_PHY_N(0x150) /* CCK shiftbits reference var */ 478#define B43_NPHY_OVER_DGAIN0 B43_PHY_N(0x152) /* Override digital gain 0 */ 479#define B43_NPHY_OVER_DGAIN1 B43_PHY_N(0x153) /* Override digital gain 1 */ 480#define B43_NPHY_OVER_DGAIN_FDGV 0x0007 /* Force digital gain value */ 481#define B43_NPHY_OVER_DGAIN_FDGV_SHIFT 0 482#define B43_NPHY_OVER_DGAIN_FDGEN 0x0008 /* Force digital gain enable */ 483#define B43_NPHY_OVER_DGAIN_CCKDGECV 0xFF00 /* CCK digital gain enable count value */ 484#define B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT 8 485#define B43_NPHY_BIST_STAT4 B43_PHY_N(0x156) /* BIST status 4 */ 486#define B43_NPHY_RADAR_MAL B43_PHY_N(0x157) /* Radar MA length */ 487#define B43_NPHY_RADAR_SRCCTL B43_PHY_N(0x158) /* Radar search control */ 488#define B43_NPHY_VLD_DTSIG B43_PHY_N(0x159) /* VLD data tones sig */ 489#define B43_NPHY_VLD_DTDAT B43_PHY_N(0x15A) /* VLD data tones data */ 490#define B43_NPHY_C1_BPHY_RXIQCA0 B43_PHY_N(0x15B) /* Core 1 B PHY RX I/Q comp A0 */ 491#define B43_NPHY_C1_BPHY_RXIQCB0 B43_PHY_N(0x15C) /* Core 1 B PHY RX I/Q comp B0 */ 492#define B43_NPHY_C2_BPHY_RXIQCA1 B43_PHY_N(0x15D) /* Core 2 B PHY RX I/Q comp A1 */ 493#define B43_NPHY_C2_BPHY_RXIQCB1 B43_PHY_N(0x15E) /* Core 2 B PHY RX I/Q comp B1 */ 494#define B43_NPHY_FREQGAIN0 B43_PHY_N(0x160) /* Frequency gain 0 */ 495#define B43_NPHY_FREQGAIN1 B43_PHY_N(0x161) /* Frequency gain 1 */ 496#define B43_NPHY_FREQGAIN2 B43_PHY_N(0x162) /* Frequency gain 2 */ 497#define B43_NPHY_FREQGAIN3 B43_PHY_N(0x163) /* Frequency gain 3 */ 498#define B43_NPHY_FREQGAIN4 B43_PHY_N(0x164) /* Frequency gain 4 */ 499#define B43_NPHY_FREQGAIN5 B43_PHY_N(0x165) /* Frequency gain 5 */ 500#define B43_NPHY_FREQGAIN6 B43_PHY_N(0x166) /* Frequency gain 6 */ 501#define B43_NPHY_FREQGAIN7 B43_PHY_N(0x167) /* Frequency gain 7 */ 502#define B43_NPHY_FREQGAIN_BYPASS B43_PHY_N(0x168) /* Frequency gain bypass */ 503#define B43_NPHY_TRLOSS B43_PHY_N(0x169) /* TR loss value */ 504#define B43_NPHY_C1_ADCCLIP B43_PHY_N(0x16A) /* Core 1 ADC clip */ 505#define B43_NPHY_C2_ADCCLIP B43_PHY_N(0x16B) /* Core 2 ADC clip */ 506#define B43_NPHY_LTRN_OFFGAIN B43_PHY_N(0x16F) /* LTRN offset gain */ 507#define B43_NPHY_LTRN_OFF B43_PHY_N(0x170) /* LTRN offset */ 508#define B43_NPHY_NRDATAT_WWISE20SIG B43_PHY_N(0x171) /* # data tones WWiSE 20 sig */ 509#define B43_NPHY_NRDATAT_WWISE40SIG B43_PHY_N(0x172) /* # data tones WWiSE 40 sig */ 510#define B43_NPHY_NRDATAT_TGNSYNC20SIG B43_PHY_N(0x173) /* # data tones TGNsync 20 sig */ 511#define B43_NPHY_NRDATAT_TGNSYNC40SIG B43_PHY_N(0x174) /* # data tones TGNsync 40 sig */ 512#define B43_NPHY_WWISE_CRCM0 B43_PHY_N(0x175) /* WWiSE CRC mask 0 */ 513#define B43_NPHY_WWISE_CRCM1 B43_PHY_N(0x176) /* WWiSE CRC mask 1 */ 514#define B43_NPHY_WWISE_CRCM2 B43_PHY_N(0x177) /* WWiSE CRC mask 2 */ 515#define B43_NPHY_WWISE_CRCM3 B43_PHY_N(0x178) /* WWiSE CRC mask 3 */ 516#define B43_NPHY_WWISE_CRCM4 B43_PHY_N(0x179) /* WWiSE CRC mask 4 */ 517#define B43_NPHY_CHANEST_CDDSH B43_PHY_N(0x17A) /* Channel estimate CDD shift */ 518#define B43_NPHY_HTAGC_WCNT B43_PHY_N(0x17B) /* HT ADC wait counters */ 519#define B43_NPHY_SQPARM B43_PHY_N(0x17C) /* SQ params */ 520#define B43_NPHY_MCSDUP6M B43_PHY_N(0x17D) /* MCS dup 6M */ 521#define B43_NPHY_NDATAT_DUP40 B43_PHY_N(0x17E) /* # data tones dup 40 */ 522#define B43_NPHY_DUP40_TGNSYNC_CYCD B43_PHY_N(0x17F) /* Dup40 TGNsync cycle data */ 523#define B43_NPHY_DUP40_GFBL B43_PHY_N(0x180) /* Dup40 GF format BL address */ 524#define B43_NPHY_DUP40_BL B43_PHY_N(0x181) /* Dup40 format BL address */ 525#define B43_NPHY_LEGDUP_FTA B43_PHY_N(0x182) /* Legacy dup frm table address */ 526#define B43_NPHY_PACPROC_DBG B43_PHY_N(0x183) /* Packet processing debug */ 527#define B43_NPHY_PIL_CYC1 B43_PHY_N(0x184) /* Pilot cycle counter 1 */ 528#define B43_NPHY_PIL_CYC2 B43_PHY_N(0x185) /* Pilot cycle counter 2 */ 529#define B43_NPHY_TXF_20CO_S0A1 B43_PHY_N(0x186) /* TX filter 20 coeff stage 0 A1 */ 530#define B43_NPHY_TXF_20CO_S0A2 B43_PHY_N(0x187) /* TX filter 20 coeff stage 0 A2 */ 531#define B43_NPHY_TXF_20CO_S1A1 B43_PHY_N(0x188) /* TX filter 20 coeff stage 1 A1 */ 532#define B43_NPHY_TXF_20CO_S1A2 B43_PHY_N(0x189) /* TX filter 20 coeff stage 1 A2 */ 533#define B43_NPHY_TXF_20CO_S2A1 B43_PHY_N(0x18A) /* TX filter 20 coeff stage 2 A1 */ 534#define B43_NPHY_TXF_20CO_S2A2 B43_PHY_N(0x18B) /* TX filter 20 coeff stage 2 A2 */ 535#define B43_NPHY_TXF_20CO_S0B1 B43_PHY_N(0x18C) /* TX filter 20 coeff stage 0 B1 */ 536#define B43_NPHY_TXF_20CO_S0B2 B43_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */ 537#define B43_NPHY_TXF_20CO_S0B3 B43_PHY_N(0x18E) /* TX filter 20 coeff stage 0 B3 */ 538#define B43_NPHY_TXF_20CO_S1B1 B43_PHY_N(0x18F) /* TX filter 20 coeff stage 1 B1 */ 539#define B43_NPHY_TXF_20CO_S1B2 B43_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */ 540#define B43_NPHY_TXF_20CO_S1B3 B43_PHY_N(0x191) /* TX filter 20 coeff stage 1 B3 */ 541#define B43_NPHY_TXF_20CO_S2B1 B43_PHY_N(0x192) /* TX filter 20 coeff stage 2 B1 */ 542#define B43_NPHY_TXF_20CO_S2B2 B43_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */ 543#define B43_NPHY_TXF_20CO_S2B3 B43_PHY_N(0x194) /* TX filter 20 coeff stage 2 B3 */ 544#define B43_NPHY_TXF_40CO_S0A1 B43_PHY_N(0x195) /* TX filter 40 coeff stage 0 A1 */ 545#define B43_NPHY_TXF_40CO_S0A2 B43_PHY_N(0x196) /* TX filter 40 coeff stage 0 A2 */ 546#define B43_NPHY_TXF_40CO_S1A1 B43_PHY_N(0x197) /* TX filter 40 coeff stage 1 A1 */ 547#define B43_NPHY_TXF_40CO_S1A2 B43_PHY_N(0x198) /* TX filter 40 coeff stage 1 A2 */ 548#define B43_NPHY_TXF_40CO_S2A1 B43_PHY_N(0x199) /* TX filter 40 coeff stage 2 A1 */ 549#define B43_NPHY_TXF_40CO_S2A2 B43_PHY_N(0x19A) /* TX filter 40 coeff stage 2 A2 */ 550#define B43_NPHY_TXF_40CO_S0B1 B43_PHY_N(0x19B) /* TX filter 40 coeff stage 0 B1 */ 551#define B43_NPHY_TXF_40CO_S0B2 B43_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */ 552#define B43_NPHY_TXF_40CO_S0B3 B43_PHY_N(0x19D) /* TX filter 40 coeff stage 0 B3 */ 553#define B43_NPHY_TXF_40CO_S1B1 B43_PHY_N(0x19E) /* TX filter 40 coeff stage 1 B1 */ 554#define B43_NPHY_TXF_40CO_S1B2 B43_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */ 555#define B43_NPHY_TXF_40CO_S1B3 B43_PHY_N(0x1A0) /* TX filter 40 coeff stage 1 B3 */ 556#define B43_NPHY_TXF_40CO_S2B1 B43_PHY_N(0x1A1) /* TX filter 40 coeff stage 2 B1 */ 557#define B43_NPHY_TXF_40CO_S2B2 B43_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */ 558#define B43_NPHY_TXF_40CO_S2B3 B43_PHY_N(0x1A3) /* TX filter 40 coeff stage 2 B3 */ 559#define B43_NPHY_RSSIMC_0I_RSSI_X B43_PHY_N(0x1A4) /* RSSI multiplication coefficient 0 I RSSI X */ 560#define B43_NPHY_RSSIMC_0I_RSSI_Y B43_PHY_N(0x1A5) /* RSSI multiplication coefficient 0 I RSSI Y */ 561#define B43_NPHY_RSSIMC_0I_RSSI_Z B43_PHY_N(0x1A6) /* RSSI multiplication coefficient 0 I RSSI Z */ 562#define B43_NPHY_RSSIMC_0I_TBD B43_PHY_N(0x1A7) /* RSSI multiplication coefficient 0 I TBD */ 563#define B43_NPHY_RSSIMC_0I_PWRDET B43_PHY_N(0x1A8) /* RSSI multiplication coefficient 0 I power det */ 564#define B43_NPHY_RSSIMC_0I_TSSI B43_PHY_N(0x1A9) /* RSSI multiplication coefficient 0 I TSSI */ 565#define B43_NPHY_RSSIMC_0Q_RSSI_X B43_PHY_N(0x1AA) /* RSSI multiplication coefficient 0 Q RSSI X */ 566#define B43_NPHY_RSSIMC_0Q_RSSI_Y B43_PHY_N(0x1AB) /* RSSI multiplication coefficient 0 Q RSSI Y */ 567#define B43_NPHY_RSSIMC_0Q_RSSI_Z B43_PHY_N(0x1AC) /* RSSI multiplication coefficient 0 Q RSSI Z */ 568#define B43_NPHY_RSSIMC_0Q_TBD B43_PHY_N(0x1AD) /* RSSI multiplication coefficient 0 Q TBD */ 569#define B43_NPHY_RSSIMC_0Q_PWRDET B43_PHY_N(0x1AE) /* RSSI multiplication coefficient 0 Q power det */ 570#define B43_NPHY_RSSIMC_0Q_TSSI B43_PHY_N(0x1AF) /* RSSI multiplication coefficient 0 Q TSSI */ 571#define B43_NPHY_RSSIMC_1I_RSSI_X B43_PHY_N(0x1B0) /* RSSI multiplication coefficient 1 I RSSI X */ 572#define B43_NPHY_RSSIMC_1I_RSSI_Y B43_PHY_N(0x1B1) /* RSSI multiplication coefficient 1 I RSSI Y */ 573#define B43_NPHY_RSSIMC_1I_RSSI_Z B43_PHY_N(0x1B2) /* RSSI multiplication coefficient 1 I RSSI Z */ 574#define B43_NPHY_RSSIMC_1I_TBD B43_PHY_N(0x1B3) /* RSSI multiplication coefficient 1 I TBD */ 575#define B43_NPHY_RSSIMC_1I_PWRDET B43_PHY_N(0x1B4) /* RSSI multiplication coefficient 1 I power det */ 576#define B43_NPHY_RSSIMC_1I_TSSI B43_PHY_N(0x1B5) /* RSSI multiplication coefficient 1 I TSSI */ 577#define B43_NPHY_RSSIMC_1Q_RSSI_X B43_PHY_N(0x1B6) /* RSSI multiplication coefficient 1 Q RSSI X */ 578#define B43_NPHY_RSSIMC_1Q_RSSI_Y B43_PHY_N(0x1B7) /* RSSI multiplication coefficient 1 Q RSSI Y */ 579#define B43_NPHY_RSSIMC_1Q_RSSI_Z B43_PHY_N(0x1B8) /* RSSI multiplication coefficient 1 Q RSSI Z */ 580#define B43_NPHY_RSSIMC_1Q_TBD B43_PHY_N(0x1B9) /* RSSI multiplication coefficient 1 Q TBD */ 581#define B43_NPHY_RSSIMC_1Q_PWRDET B43_PHY_N(0x1BA) /* RSSI multiplication coefficient 1 Q power det */ 582#define B43_NPHY_RSSIMC_1Q_TSSI B43_PHY_N(0x1BB) /* RSSI multiplication coefficient 1 Q TSSI */ 583#define B43_NPHY_SAMC_WCNT B43_PHY_N(0x1BC) /* Sample collect wait counter */ 584#define B43_NPHY_PTHROUGH_CNT B43_PHY_N(0x1BD) /* Pass-through counter */ 585#define B43_NPHY_LTRN_OFF_G20L B43_PHY_N(0x1C4) /* LTRN offset gain 20L */ 586#define B43_NPHY_LTRN_OFF_20L B43_PHY_N(0x1C5) /* LTRN offset 20L */ 587#define B43_NPHY_LTRN_OFF_G20U B43_PHY_N(0x1C6) /* LTRN offset gain 20U */ 588#define B43_NPHY_LTRN_OFF_20U B43_PHY_N(0x1C7) /* LTRN offset 20U */ 589#define B43_NPHY_DSSSCCK_GAINSL B43_PHY_N(0x1C8) /* DSSS/CCK gain settle length */ 590#define B43_NPHY_GPIO_LOOUT B43_PHY_N(0x1C9) /* GPIO low out */ 591#define B43_NPHY_GPIO_HIOUT B43_PHY_N(0x1CA) /* GPIO high out */ 592#define B43_NPHY_CRS_CHECK B43_PHY_N(0x1CB) /* CRS check */ 593#define B43_NPHY_ML_LOGSS_RAT B43_PHY_N(0x1CC) /* ML/logss ratio */ 594#define B43_NPHY_DUPSCALE B43_PHY_N(0x1CD) /* Dup scale */ 595#define B43_NPHY_BW1A B43_PHY_N(0x1CE) /* BW 1A */ 596#define B43_NPHY_BW2 B43_PHY_N(0x1CF) /* BW 2 */ 597#define B43_NPHY_BW3 B43_PHY_N(0x1D0) /* BW 3 */ 598#define B43_NPHY_BW4 B43_PHY_N(0x1D1) /* BW 4 */ 599#define B43_NPHY_BW5 B43_PHY_N(0x1D2) /* BW 5 */ 600#define B43_NPHY_BW6 B43_PHY_N(0x1D3) /* BW 6 */ 601#define B43_NPHY_COALEN0 B43_PHY_N(0x1D4) /* Coarse length 0 */ 602#define B43_NPHY_COALEN1 B43_PHY_N(0x1D5) /* Coarse length 1 */ 603#define B43_NPHY_CRSTHRES_1U B43_PHY_N(0x1D6) /* CRS threshold 1 U */ 604#define B43_NPHY_CRSTHRES_2U B43_PHY_N(0x1D7) /* CRS threshold 2 U */ 605#define B43_NPHY_CRSTHRES_3U B43_PHY_N(0x1D8) /* CRS threshold 3 U */ 606#define B43_NPHY_CRSCTL_U B43_PHY_N(0x1D9) /* CRS control U */ 607#define B43_NPHY_CRSTHRES_1L B43_PHY_N(0x1DA) /* CRS threshold 1 L */ 608#define B43_NPHY_CRSTHRES_2L B43_PHY_N(0x1DB) /* CRS threshold 2 L */ 609#define B43_NPHY_CRSTHRES_3L B43_PHY_N(0x1DC) /* CRS threshold 3 L */ 610#define B43_NPHY_CRSCTL_L B43_PHY_N(0x1DD) /* CRS control L */ 611#define B43_NPHY_STRA_1U B43_PHY_N(0x1DE) /* STR address 1 U */ 612#define B43_NPHY_STRA_2U B43_PHY_N(0x1DF) /* STR address 2 U */ 613#define B43_NPHY_STRA_1L B43_PHY_N(0x1E0) /* STR address 1 L */ 614#define B43_NPHY_STRA_2L B43_PHY_N(0x1E1) /* STR address 2 L */ 615#define B43_NPHY_CRSCHECK1 B43_PHY_N(0x1E2) /* CRS check 1 */ 616#define B43_NPHY_CRSCHECK2 B43_PHY_N(0x1E3) /* CRS check 2 */ 617#define B43_NPHY_CRSCHECK3 B43_PHY_N(0x1E4) /* CRS check 3 */ 618#define B43_NPHY_JMPSTP0 B43_PHY_N(0x1E5) /* Jump step 0 */ 619#define B43_NPHY_JMPSTP1 B43_PHY_N(0x1E6) /* Jump step 1 */ 620#define B43_NPHY_TXPCTL_CMD B43_PHY_N(0x1E7) /* TX power control command */ 621#define B43_NPHY_TXPCTL_CMD_INIT 0x007F /* Init */ 622#define B43_NPHY_TXPCTL_CMD_INIT_SHIFT 0 623#define B43_NPHY_TXPCTL_CMD_COEFF 0x2000 /* Power control coefficients */ 624#define B43_NPHY_TXPCTL_CMD_HWPCTLEN 0x4000 /* Hardware TX power control enable */ 625#define B43_NPHY_TXPCTL_CMD_PCTLEN 0x8000 /* TX power control enable */ 626#define B43_NPHY_TXPCTL_N B43_PHY_N(0x1E8) /* TX power control N num */ 627#define B43_NPHY_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */ 628#define B43_NPHY_TXPCTL_N_TSSID_SHIFT 0 629#define B43_NPHY_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */ 630#define B43_NPHY_TXPCTL_N_NPTIL2_SHIFT 8 631#define B43_NPHY_TXPCTL_ITSSI B43_PHY_N(0x1E9) /* TX power control idle TSSI */ 632#define B43_NPHY_TXPCTL_ITSSI_0 0x003F /* Idle TSSI 0 */ 633#define B43_NPHY_TXPCTL_ITSSI_0_SHIFT 0 634#define B43_NPHY_TXPCTL_ITSSI_1 0x3F00 /* Idle TSSI 1 */ 635#define B43_NPHY_TXPCTL_ITSSI_1_SHIFT 8 636#define B43_NPHY_TXPCTL_ITSSI_BINF 0x8000 /* Raw TSSI offset bin format */ 637#define B43_NPHY_TXPCTL_TPWR B43_PHY_N(0x1EA) /* TX power control target power */ 638#define B43_NPHY_TXPCTL_TPWR_0 0x00FF /* Power 0 */ 639#define B43_NPHY_TXPCTL_TPWR_0_SHIFT 0 640#define B43_NPHY_TXPCTL_TPWR_1 0xFF00 /* Power 1 */ 641#define B43_NPHY_TXPCTL_TPWR_1_SHIFT 8 642#define B43_NPHY_TXPCTL_BIDX B43_PHY_N(0x1EB) /* TX power control base index */ 643#define B43_NPHY_TXPCTL_BIDX_0 0x007F /* uC base index 0 */ 644#define B43_NPHY_TXPCTL_BIDX_0_SHIFT 0 645#define B43_NPHY_TXPCTL_BIDX_1 0x7F00 /* uC base index 1 */ 646#define B43_NPHY_TXPCTL_BIDX_1_SHIFT 8 647#define B43_NPHY_TXPCTL_BIDX_LOAD 0x8000 /* Load base index */ 648#define B43_NPHY_TXPCTL_PIDX B43_PHY_N(0x1EC) /* TX power control power index */ 649#define B43_NPHY_TXPCTL_PIDX_0 0x007F /* uC power index 0 */ 650#define B43_NPHY_TXPCTL_PIDX_0_SHIFT 0 651#define B43_NPHY_TXPCTL_PIDX_1 0x7F00 /* uC power index 1 */ 652#define B43_NPHY_TXPCTL_PIDX_1_SHIFT 8 653#define B43_NPHY_C1_TXPCTL_STAT B43_PHY_N(0x1ED) /* Core 1 TX power control status */ 654#define B43_NPHY_C2_TXPCTL_STAT B43_PHY_N(0x1EE) /* Core 2 TX power control status */ 655#define B43_NPHY_TXPCTL_STAT_EST 0x00FF /* Estimated power */ 656#define B43_NPHY_TXPCTL_STAT_EST_SHIFT 0 657#define B43_NPHY_TXPCTL_STAT_BIDX 0x7F00 /* Base index */ 658#define B43_NPHY_TXPCTL_STAT_BIDX_SHIFT 8 659#define B43_NPHY_TXPCTL_STAT_ESTVALID 0x8000 /* Estimated power valid */ 660#define B43_NPHY_SMALLSGS_LEN B43_PHY_N(0x1EF) /* Small sig gain settle length */ 661#define B43_NPHY_PHYSTAT_GAIN0 B43_PHY_N(0x1F0) /* PHY stats gain info 0 */ 662#define B43_NPHY_PHYSTAT_GAIN1 B43_PHY_N(0x1F1) /* PHY stats gain info 1 */ 663#define B43_NPHY_PHYSTAT_FREQEST B43_PHY_N(0x1F2) /* PHY stats frequency estimate */ 664#define B43_NPHY_PHYSTAT_ADVRET B43_PHY_N(0x1F3) /* PHY stats ADV retard */ 665#define B43_NPHY_PHYLB_MODE B43_PHY_N(0x1F4) /* PHY loopback mode */ 666#define B43_NPHY_TONE_MIDX20_1 B43_PHY_N(0x1F5) /* Tone map index 20/1 */ 667#define B43_NPHY_TONE_MIDX20_2 B43_PHY_N(0x1F6) /* Tone map index 20/2 */ 668#define B43_NPHY_TONE_MIDX20_3 B43_PHY_N(0x1F7) /* Tone map index 20/3 */ 669#define B43_NPHY_TONE_MIDX40_1 B43_PHY_N(0x1F8) /* Tone map index 40/1 */ 670#define B43_NPHY_TONE_MIDX40_2 B43_PHY_N(0x1F9) /* Tone map index 40/2 */ 671#define B43_NPHY_TONE_MIDX40_3 B43_PHY_N(0x1FA) /* Tone map index 40/3 */ 672#define B43_NPHY_TONE_MIDX40_4 B43_PHY_N(0x1FB) /* Tone map index 40/4 */ 673#define B43_NPHY_PILTONE_MIDX1 B43_PHY_N(0x1FC) /* Pilot tone map index 1 */ 674#define B43_NPHY_PILTONE_MIDX2 B43_PHY_N(0x1FD) /* Pilot tone map index 2 */ 675#define B43_NPHY_PILTONE_MIDX3 B43_PHY_N(0x1FE) /* Pilot tone map index 3 */ 676#define B43_NPHY_TXRIFS_FRDEL B43_PHY_N(0x1FF) /* TX RIFS frame delay */ 677#define B43_NPHY_AFESEQ_RX2TX_PUD_40M B43_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */ 678#define B43_NPHY_AFESEQ_TX2RX_PUD_40M B43_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */ 679#define B43_NPHY_AFESEQ_RX2TX_PUD_20M B43_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */ 680#define B43_NPHY_AFESEQ_TX2RX_PUD_20M B43_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */ 681#define B43_NPHY_RX_SIGCTL B43_PHY_N(0x204) /* RX signal control */ 682#define B43_NPHY_RXPIL_CYCNT0 B43_PHY_N(0x205) /* RX pilot cycle counter 0 */ 683#define B43_NPHY_RXPIL_CYCNT1 B43_PHY_N(0x206) /* RX pilot cycle counter 1 */ 684#define B43_NPHY_RXPIL_CYCNT2 B43_PHY_N(0x207) /* RX pilot cycle counter 2 */ 685#define B43_NPHY_AFESEQ_RX2TX_PUD_10M B43_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */ 686#define B43_NPHY_AFESEQ_TX2RX_PUD_10M B43_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */ 687#define B43_NPHY_DSSSCCK_CRSEXTL B43_PHY_N(0x20A) /* DSSS/CCK CRS extension length */ 688#define B43_NPHY_ML_LOGSS_RATSLOPE B43_PHY_N(0x20B) /* ML/logss ratio slope */ 689#define B43_NPHY_RIFS_SRCTL B43_PHY_N(0x20C) /* RIFS search timeout length */ 690#define B43_NPHY_TXREALFD B43_PHY_N(0x20D) /* TX real frame delay */ 691#define B43_NPHY_HPANT_SWTHRES B43_PHY_N(0x20E) /* High power antenna switch threshold */ 692#define B43_NPHY_EDCRS_ASSTHRES0 B43_PHY_N(0x210) /* ED CRS assert threshold 0 */ 693#define B43_NPHY_EDCRS_ASSTHRES1 B43_PHY_N(0x211) /* ED CRS assert threshold 1 */ 694#define B43_NPHY_EDCRS_DEASSTHRES0 B43_PHY_N(0x212) /* ED CRS deassert threshold 0 */ 695#define B43_NPHY_EDCRS_DEASSTHRES1 B43_PHY_N(0x213) /* ED CRS deassert threshold 1 */ 696#define B43_NPHY_STR_WTIME20U B43_PHY_N(0x214) /* STR wait time 20U */ 697#define B43_NPHY_STR_WTIME20L B43_PHY_N(0x215) /* STR wait time 20L */ 698#define B43_NPHY_TONE_MIDX657M B43_PHY_N(0x216) /* Tone map index 657M */ 699#define B43_NPHY_HTSIGTONES B43_PHY_N(0x217) /* HT signal tones */ 700#define B43_NPHY_RSSI1 B43_PHY_N(0x219) /* RSSI value 1 */ 701#define B43_NPHY_RSSI2 B43_PHY_N(0x21A) /* RSSI value 2 */ 702#define B43_NPHY_CHAN_ESTHANG B43_PHY_N(0x21D) /* Channel estimate hang */ 703#define B43_NPHY_FINERX2_CGC B43_PHY_N(0x221) /* Fine RX 2 clock gate control */ 704#define B43_NPHY_FINERX2_CGC_DECGC 0x0008 /* Decode gated clocks */ 705#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power controll init */ 706#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ 707#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 708 709 710 711/* Broadcom 2055 radio registers */ 712 713#define B2055_GEN_SPARE 0x00 /* GEN spare */ 714#define B2055_SP_PINPD 0x02 /* SP PIN PD */ 715#define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */ 716#define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */ 717#define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */ 718#define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */ 719#define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */ 720#define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */ 721#define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */ 722#define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */ 723#define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */ 724#define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */ 725#define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */ 726#define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */ 727#define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */ 728#define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */ 729#define B2055_MASTER1 0x11 /* Master control 1 */ 730#define B2055_MASTER2 0x12 /* Master control 2 */ 731#define B2055_PD_LGEN 0x13 /* PD LGEN */ 732#define B2055_PD_PLLTS 0x14 /* PD PLL TS */ 733#define B2055_C1_PD_LGBUF 0x15 /* PD Core 1 LGBUF */ 734#define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */ 735#define B2055_C1_PD_RXTX 0x17 /* PD Core 1 RXTX */ 736#define B2055_C1_PD_RSSIMISC 0x18 /* PD Core 1 RSSI MISC */ 737#define B2055_C2_PD_LGBUF 0x19 /* PD Core 2 LGBUF */ 738#define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */ 739#define B2055_C2_PD_RXTX 0x1B /* PD Core 2 RXTX */ 740#define B2055_C2_PD_RSSIMISC 0x1C /* PD Core 2 RSSI MISC */ 741#define B2055_PWRDET_LGEN 0x1D /* PWRDET LGEN */ 742#define B2055_C1_PWRDET_LGBUF 0x1E /* PWRDET LGBUF Core 1 */ 743#define B2055_C1_PWRDET_RXTX 0x1F /* PWRDET RXTX Core 1 */ 744#define B2055_C2_PWRDET_LGBUF 0x20 /* PWRDET LGBUF Core 2 */ 745#define B2055_C2_PWRDET_RXTX 0x21 /* PWRDET RXTX Core 2 */ 746#define B2055_RRCCAL_CS 0x22 /* RRCCAL Control spare */ 747#define B2055_RRCCAL_NOPTSEL 0x23 /* RRCCAL N OPT SEL */ 748#define B2055_CAL_MISC 0x24 /* CAL MISC */ 749#define B2055_CAL_COUT 0x25 /* CAL Counter out */ 750#define B2055_CAL_COUT2 0x26 /* CAL Counter out 2 */ 751#define B2055_CAL_CVARCTL 0x27 /* CAL CVAR Control */ 752#define B2055_CAL_RVARCTL 0x28 /* CAL RVAR Control */ 753#define B2055_CAL_LPOCTL 0x29 /* CAL LPO Control */ 754#define B2055_CAL_TS 0x2A /* CAL TS */ 755#define B2055_CAL_RCCALRTS 0x2B /* CAL RCCAL READ TS */ 756#define B2055_CAL_RCALRTS 0x2C /* CAL RCAL READ TS */ 757#define B2055_PADDRV 0x2D /* PAD driver */ 758#define B2055_XOCTL1 0x2E /* XO Control 1 */ 759#define B2055_XOCTL2 0x2F /* XO Control 2 */ 760#define B2055_XOREGUL 0x30 /* XO Regulator */ 761#define B2055_XOMISC 0x31 /* XO misc */ 762#define B2055_PLL_LFC1 0x32 /* PLL LF C1 */ 763#define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */ 764#define B2055_PLL_LFC2 0x34 /* PLL LF C2 */ 765#define B2055_PLL_REF 0x35 /* PLL reference */ 766#define B2055_PLL_LFR1 0x36 /* PLL LF R1 */ 767#define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */ 768#define B2055_PLL_IDAC_CPOPAMP 0x38 /* PLL IDAC CPOPAMP */ 769#define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */ 770#define B2055_PLL_RCAL 0x3A /* PLL RCAL */ 771#define B2055_RF_PLLMOD0 0x3B /* RF PLL MOD0 */ 772#define B2055_RF_PLLMOD1 0x3C /* RF PLL MOD1 */ 773#define B2055_RF_MMDIDAC1 0x3D /* RF MMD IDAC 1 */ 774#define B2055_RF_MMDIDAC0 0x3E /* RF MMD IDAC 0 */ 775#define B2055_RF_MMDSP 0x3F /* RF MMD spare */ 776#define B2055_VCO_CAL1 0x40 /* VCO cal 1 */ 777#define B2055_VCO_CAL2 0x41 /* VCO cal 2 */ 778#define B2055_VCO_CAL3 0x42 /* VCO cal 3 */ 779#define B2055_VCO_CAL4 0x43 /* VCO cal 4 */ 780#define B2055_VCO_CAL5 0x44 /* VCO cal 5 */ 781#define B2055_VCO_CAL6 0x45 /* VCO cal 6 */ 782#define B2055_VCO_CAL7 0x46 /* VCO cal 7 */ 783#define B2055_VCO_CAL8 0x47 /* VCO cal 8 */ 784#define B2055_VCO_CAL9 0x48 /* VCO cal 9 */ 785#define B2055_VCO_CAL10 0x49 /* VCO cal 10 */ 786#define B2055_VCO_CAL11 0x4A /* VCO cal 11 */ 787#define B2055_VCO_CAL12 0x4B /* VCO cal 12 */ 788#define B2055_VCO_CAL13 0x4C /* VCO cal 13 */ 789#define B2055_VCO_CAL14 0x4D /* VCO cal 14 */ 790#define B2055_VCO_CAL15 0x4E /* VCO cal 15 */ 791#define B2055_VCO_CAL16 0x4F /* VCO cal 16 */ 792#define B2055_VCO_KVCO 0x50 /* VCO KVCO */ 793#define B2055_VCO_CAPTAIL 0x51 /* VCO CAP TAIL */ 794#define B2055_VCO_IDACVCO 0x52 /* VCO IDAC VCO */ 795#define B2055_VCO_REG 0x53 /* VCO Regulator */ 796#define B2055_PLL_RFVTH 0x54 /* PLL RF VTH */ 797#define B2055_LGBUF_CENBUF 0x55 /* LGBUF CEN BUF */ 798#define B2055_LGEN_TUNE1 0x56 /* LGEN tune 1 */ 799#define B2055_LGEN_TUNE2 0x57 /* LGEN tune 2 */ 800#define B2055_LGEN_IDAC1 0x58 /* LGEN IDAC 1 */ 801#define B2055_LGEN_IDAC2 0x59 /* LGEN IDAC 2 */ 802#define B2055_LGEN_BIASC 0x5A /* LGEN BIAS counter */ 803#define B2055_LGEN_BIASIDAC 0x5B /* LGEN BIAS IDAC */ 804#define B2055_LGEN_RCAL 0x5C /* LGEN RCAL */ 805#define B2055_LGEN_DIV 0x5D /* LGEN div */ 806#define B2055_LGEN_SPARE2 0x5E /* LGEN spare 2 */ 807#define B2055_C1_LGBUF_ATUNE 0x5F /* Core 1 LGBUF A tune */ 808#define B2055_C1_LGBUF_GTUNE 0x60 /* Core 1 LGBUF G tune */ 809#define B2055_C1_LGBUF_DIV 0x61 /* Core 1 LGBUF div */ 810#define B2055_C1_LGBUF_AIDAC 0x62 /* Core 1 LGBUF A IDAC */ 811#define B2055_C1_LGBUF_GIDAC 0x63 /* Core 1 LGBUF G IDAC */ 812#define B2055_C1_LGBUF_IDACFO 0x64 /* Core 1 LGBUF IDAC filter override */ 813#define B2055_C1_LGBUF_SPARE 0x65 /* Core 1 LGBUF spare */ 814#define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */ 815#define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */ 816#define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */ 817#define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */ 818#define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */ 819#define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */ 820#define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */ 821#define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */ 822#define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */ 823#define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */ 824#define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */ 825#define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */ 826#define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */ 827#define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */ 828#define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */ 829#define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */ 830#define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */ 831#define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */ 832#define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */ 833#define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */ 834#define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */ 835#define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */ 836#define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */ 837#define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */ 838#define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */ 839#define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */ 840#define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */ 841#define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */ 842#define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */ 843#define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */ 844#define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */ 845#define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */ 846#define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */ 847#define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */ 848#define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */ 849#define B2055_C1_TXBB_RCCAL 0x89 /* Core 1 TXBB RC CAL Control */ 850#define B2055_C1_TXBB_LPF1 0x8A /* Core 1 TXBB LPF 1 */ 851#define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */ 852#define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */ 853#define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */ 854#define B2055_C2_LGBUF_ATUNE 0x8E /* Core 2 LGBUF A tune */ 855#define B2055_C2_LGBUF_GTUNE 0x8F /* Core 2 LGBUF G tune */ 856#define B2055_C2_LGBUF_DIV 0x90 /* Core 2 LGBUF div */ 857#define B2055_C2_LGBUF_AIDAC 0x91 /* Core 2 LGBUF A IDAC */ 858#define B2055_C2_LGBUF_GIDAC 0x92 /* Core 2 LGBUF G IDAC */ 859#define B2055_C2_LGBUF_IDACFO 0x93 /* Core 2 LGBUF IDAC filter override */ 860#define B2055_C2_LGBUF_SPARE 0x94 /* Core 2 LGBUF spare */ 861#define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */ 862#define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */ 863#define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */ 864#define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */ 865#define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */ 866#define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */ 867#define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */ 868#define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */ 869#define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */ 870#define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */ 871#define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */ 872#define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */ 873#define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */ 874#define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */ 875#define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */ 876#define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */ 877#define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */ 878#define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */ 879#define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */ 880#define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */ 881#define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */ 882#define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */ 883#define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */ 884#define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */ 885#define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */ 886#define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */ 887#define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */ 888#define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */ 889#define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */ 890#define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */ 891#define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */ 892#define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */ 893#define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */ 894#define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */ 895#define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */ 896#define B2055_C2_TXBB_RCCAL 0xB8 /* Core 2 TXBB RC CAL Control */ 897#define B2055_C2_TXBB_LPF1 0xB9 /* Core 2 TXBB LPF 1 */ 898#define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */ 899#define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */ 900#define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */ 901#define B2055_PRG_GCHP21 0xBD /* PRG GC HPVGA23 21 */ 902#define B2055_PRG_GCHP22 0xBE /* PRG GC HPVGA23 22 */ 903#define B2055_PRG_GCHP23 0xBF /* PRG GC HPVGA23 23 */ 904#define B2055_PRG_GCHP24 0xC0 /* PRG GC HPVGA23 24 */ 905#define B2055_PRG_GCHP25 0xC1 /* PRG GC HPVGA23 25 */ 906#define B2055_PRG_GCHP26 0xC2 /* PRG GC HPVGA23 26 */ 907#define B2055_PRG_GCHP27 0xC3 /* PRG GC HPVGA23 27 */ 908#define B2055_PRG_GCHP28 0xC4 /* PRG GC HPVGA23 28 */ 909#define B2055_PRG_GCHP29 0xC5 /* PRG GC HPVGA23 29 */ 910#define B2055_PRG_GCHP30 0xC6 /* PRG GC HPVGA23 30 */ 911#define B2055_C1_LNA_GAINBST 0xCD /* Core 1 LNA GAINBST */ 912#define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */ 913#define B2055_C1_GENSPARE2 0xD6 /* Core 1 GEN spare 2 */ 914#define B2055_C2_LNA_GAINBST 0xD9 /* Core 2 LNA GAINBST */ 915#define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */ 916#define B2055_C2_GENSPARE2 0xE2 /* Core 2 GEN spare 2 */ 917 918 919 920struct b43_wldev; 921 922struct b43_phy_n { 923 //TODO lots of missing stuff 924}; 925 926 927struct b43_phy_operations; 928extern const struct b43_phy_operations b43_phyops_n; 929 930#endif /* B43_NPHY_H_ */ 931