1#ifndef B43_XMIT_H_
2#define B43_XMIT_H_
3
4#include "main.h"
5
6#define _b43_declare_plcp_hdr(size) \
7 struct b43_plcp_hdr##size { \
8 union { \
9 __le32 data; \
10 __u8 raw[size]; \
11 } __attribute__((__packed__)); \
12 } __attribute__((__packed__))
13
14
15_b43_declare_plcp_hdr(4);
16
17_b43_declare_plcp_hdr(6);
18
19#undef _b43_declare_plcp_hdr
20
21
22struct b43_txhdr {
23 __le32 mac_ctl;
24 __le16 mac_frame_ctl;
25 __le16 tx_fes_time_norm;
26 __le16 phy_ctl;
27 __le16 phy_ctl1;
28 __le16 phy_ctl1_fb;
29 __le16 phy_ctl1_rts;
30 __le16 phy_ctl1_rts_fb;
31 __u8 phy_rate;
32 __u8 phy_rate_rts;
33 __u8 extra_ft;
34 __u8 chan_radio_code;
35 __u8 iv[16];
36 __u8 tx_receiver[6];
37 __le16 tx_fes_time_fb;
38 struct b43_plcp_hdr6 rts_plcp_fb;
39 __le16 rts_dur_fb;
40 struct b43_plcp_hdr6 plcp_fb;
41 __le16 dur_fb;
42 __le16 mimo_modelen;
43 __le16 mimo_ratelen_fb;
44 __le32 timeout;
45
46 union {
47
48 struct {
49 __le16 mimo_antenna;
50 __le16 preload_size;
51 PAD_BYTES(2);
52 __le16 cookie;
53 __le16 tx_status;
54 struct b43_plcp_hdr6 rts_plcp;
55 __u8 rts_frame[16];
56 PAD_BYTES(2);
57 struct b43_plcp_hdr6 plcp;
58 } new_format __attribute__ ((__packed__));
59
60
61 struct {
62 PAD_BYTES(2);
63 __le16 cookie;
64 __le16 tx_status;
65 struct b43_plcp_hdr6 rts_plcp;
66 __u8 rts_frame[16];
67 PAD_BYTES(2);
68 struct b43_plcp_hdr6 plcp;
69 } old_format __attribute__ ((__packed__));
70
71 } __attribute__ ((__packed__));
72} __attribute__ ((__packed__));
73
74
75#define B43_TXH_MAC_USEFBR 0x10000000
76#define B43_TXH_MAC_KEYIDX 0x0FF00000
77#define B43_TXH_MAC_KEYIDX_SHIFT 20
78#define B43_TXH_MAC_KEYALG 0x00070000
79#define B43_TXH_MAC_KEYALG_SHIFT 16
80#define B43_TXH_MAC_AMIC 0x00008000
81#define B43_TXH_MAC_RIFS 0x00004000
82#define B43_TXH_MAC_LIFETIME 0x00002000
83#define B43_TXH_MAC_FRAMEBURST 0x00001000
84#define B43_TXH_MAC_SENDCTS 0x00000800
85#define B43_TXH_MAC_AMPDU 0x00000600
86#define B43_TXH_MAC_AMPDU_MPDU 0x00000000
87#define B43_TXH_MAC_AMPDU_FIRST 0x00000200
88#define B43_TXH_MAC_AMPDU_INTER 0x00000400
89#define B43_TXH_MAC_AMPDU_LAST 0x00000600
90#define B43_TXH_MAC_40MHZ 0x00000100
91#define B43_TXH_MAC_5GHZ 0x00000080
92#define B43_TXH_MAC_DFCS 0x00000040
93#define B43_TXH_MAC_IGNPMQ 0x00000020
94#define B43_TXH_MAC_HWSEQ 0x00000010
95#define B43_TXH_MAC_STMSDU 0x00000008
96#define B43_TXH_MAC_SENDRTS 0x00000004
97#define B43_TXH_MAC_LONGFRAME 0x00000002
98#define B43_TXH_MAC_ACK 0x00000001
99
100
101#define B43_TXH_EFT_FB 0x03
102#define B43_TXH_EFT_FB_CCK 0x00
103#define B43_TXH_EFT_FB_OFDM 0x01
104#define B43_TXH_EFT_FB_EWC 0x02
105#define B43_TXH_EFT_FB_N 0x03
106#define B43_TXH_EFT_RTS 0x0C
107#define B43_TXH_EFT_RTS_CCK 0x00
108#define B43_TXH_EFT_RTS_OFDM 0x04
109#define B43_TXH_EFT_RTS_EWC 0x08
110#define B43_TXH_EFT_RTS_N 0x0C
111#define B43_TXH_EFT_RTSFB 0x30
112#define B43_TXH_EFT_RTSFB_CCK 0x00
113#define B43_TXH_EFT_RTSFB_OFDM 0x10
114#define B43_TXH_EFT_RTSFB_EWC 0x20
115#define B43_TXH_EFT_RTSFB_N 0x30
116
117
118#define B43_TXH_PHY_ENC 0x0003
119#define B43_TXH_PHY_ENC_CCK 0x0000
120#define B43_TXH_PHY_ENC_OFDM 0x0001
121#define B43_TXH_PHY_ENC_EWC 0x0002
122#define B43_TXH_PHY_ENC_N 0x0003
123#define B43_TXH_PHY_SHORTPRMBL 0x0010
124#define B43_TXH_PHY_ANT 0x03C0
125#define B43_TXH_PHY_ANT0 0x0000
126#define B43_TXH_PHY_ANT1 0x0040
127#define B43_TXH_PHY_ANT01AUTO 0x00C0
128#define B43_TXH_PHY_ANT2 0x0100
129#define B43_TXH_PHY_ANT3 0x0200
130#define B43_TXH_PHY_TXPWR 0xFC00
131#define B43_TXH_PHY_TXPWR_SHIFT 10
132
133
134#define B43_TXH_PHY1_BW 0x0007
135#define B43_TXH_PHY1_BW_10 0x0000
136#define B43_TXH_PHY1_BW_10U 0x0001
137#define B43_TXH_PHY1_BW_20 0x0002
138#define B43_TXH_PHY1_BW_20U 0x0003
139#define B43_TXH_PHY1_BW_40 0x0004
140#define B43_TXH_PHY1_BW_40DUP 0x0005
141#define B43_TXH_PHY1_MODE 0x0038
142#define B43_TXH_PHY1_MODE_SISO 0x0000
143#define B43_TXH_PHY1_MODE_CDD 0x0008
144#define B43_TXH_PHY1_MODE_STBC 0x0010
145#define B43_TXH_PHY1_MODE_SDM 0x0018
146#define B43_TXH_PHY1_CRATE 0x0700
147#define B43_TXH_PHY1_CRATE_1_2 0x0000
148#define B43_TXH_PHY1_CRATE_2_3 0x0100
149#define B43_TXH_PHY1_CRATE_3_4 0x0200
150#define B43_TXH_PHY1_CRATE_4_5 0x0300
151#define B43_TXH_PHY1_CRATE_5_6 0x0400
152#define B43_TXH_PHY1_CRATE_7_8 0x0600
153#define B43_TXH_PHY1_MODUL 0x3800
154#define B43_TXH_PHY1_MODUL_BPSK 0x0000
155#define B43_TXH_PHY1_MODUL_QPSK 0x0800
156#define B43_TXH_PHY1_MODUL_QAM16 0x1000
157#define B43_TXH_PHY1_MODUL_QAM64 0x1800
158#define B43_TXH_PHY1_MODUL_QAM256 0x2000
159
160
161
162static inline
163bool b43_is_old_txhdr_format(struct b43_wldev *dev)
164{
165 return (dev->fw.rev <= 351);
166}
167
168static inline
169size_t b43_txhdr_size(struct b43_wldev *dev)
170{
171 if (b43_is_old_txhdr_format(dev))
172 return 100 + sizeof(struct b43_plcp_hdr6);
173 return 104 + sizeof(struct b43_plcp_hdr6);
174}
175
176
177int b43_generate_txhdr(struct b43_wldev *dev,
178 u8 * txhdr,
179 struct sk_buff *skb_frag,
180 struct ieee80211_tx_info *txctl, u16 cookie);
181
182
183struct b43_txstatus {
184 u16 cookie;
185 u16 seq;
186 u8 phy_stat;
187 u8 frame_count;
188 u8 rts_count;
189 u8 supp_reason;
190
191 u8 pm_indicated;
192 u8 intermediate;
193 u8 for_ampdu;
194 u8 acked;
195};
196
197
198enum {
199 B43_TXST_SUPP_NONE,
200 B43_TXST_SUPP_PMQ,
201 B43_TXST_SUPP_FLUSH,
202 B43_TXST_SUPP_PREV,
203 B43_TXST_SUPP_CHAN,
204 B43_TXST_SUPP_LIFE,
205 B43_TXST_SUPP_UNDER,
206 B43_TXST_SUPP_ABNACK,
207};
208
209
210struct b43_rxhdr_fw4 {
211 __le16 frame_len;
212 PAD_BYTES(2);
213 __le16 phy_status0;
214 union {
215
216 struct {
217 __u8 jssi;
218 __u8 sig_qual;
219 } __attribute__ ((__packed__));
220
221
222 struct {
223 __s8 power0;
224 __s8 power1;
225 } __attribute__ ((__packed__));
226 } __attribute__ ((__packed__));
227 __le16 phy_status2;
228 __le16 phy_status3;
229 __le32 mac_status;
230 __le16 mac_time;
231 __le16 channel;
232} __attribute__ ((__packed__));
233
234
235#define B43_RX_PHYST0_GAINCTL 0x4000
236#define B43_RX_PHYST0_PLCPHCF 0x0200
237#define B43_RX_PHYST0_PLCPFV 0x0100
238#define B43_RX_PHYST0_SHORTPRMBL 0x0080
239#define B43_RX_PHYST0_LCRS 0x0040
240#define B43_RX_PHYST0_ANT 0x0020
241#define B43_RX_PHYST0_UNSRATE 0x0010
242#define B43_RX_PHYST0_CLIP 0x000C
243#define B43_RX_PHYST0_CLIP_SHIFT 2
244#define B43_RX_PHYST0_FTYPE 0x0003
245#define B43_RX_PHYST0_CCK 0x0000
246#define B43_RX_PHYST0_OFDM 0x0001
247#define B43_RX_PHYST0_PRE_N 0x0002
248#define B43_RX_PHYST0_STD_N 0x0003
249
250
251#define B43_RX_PHYST2_LNAG 0xC000
252#define B43_RX_PHYST2_LNAG_SHIFT 14
253#define B43_RX_PHYST2_PNAG 0x3C00
254#define B43_RX_PHYST2_PNAG_SHIFT 10
255#define B43_RX_PHYST2_FOFF 0x03FF
256
257
258#define B43_RX_PHYST3_DIGG 0x1800
259#define B43_RX_PHYST3_DIGG_SHIFT 11
260#define B43_RX_PHYST3_TRSTATE 0x0400
261
262
263#define B43_RX_MAC_RXST_VALID 0x01000000
264#define B43_RX_MAC_TKIP_MICERR 0x00100000
265#define B43_RX_MAC_TKIP_MICATT 0x00080000
266#define B43_RX_MAC_AGGTYPE 0x00060000
267#define B43_RX_MAC_AGGTYPE_SHIFT 17
268#define B43_RX_MAC_AMSDU 0x00010000
269#define B43_RX_MAC_BEACONSENT 0x00008000
270#define B43_RX_MAC_KEYIDX 0x000007E0
271#define B43_RX_MAC_KEYIDX_SHIFT 5
272#define B43_RX_MAC_DECERR 0x00000010
273#define B43_RX_MAC_DEC 0x00000008
274#define B43_RX_MAC_PADDING 0x00000004
275#define B43_RX_MAC_RESP 0x00000002
276#define B43_RX_MAC_FCSERR 0x00000001
277
278
279#define B43_RX_CHAN_40MHZ 0x1000
280#define B43_RX_CHAN_5GHZ 0x0800
281#define B43_RX_CHAN_ID 0x07F8
282#define B43_RX_CHAN_ID_SHIFT 3
283#define B43_RX_CHAN_PHYTYPE 0x0007
284
285
286u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
287u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
288
289void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
290 const u16 octets, const u8 bitrate);
291
292void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
293
294void b43_handle_txstatus(struct b43_wldev *dev,
295 const struct b43_txstatus *status);
296bool b43_fill_txstatus_report(struct b43_wldev *dev,
297 struct ieee80211_tx_info *report,
298 const struct b43_txstatus *status);
299
300void b43_tx_suspend(struct b43_wldev *dev);
301void b43_tx_resume(struct b43_wldev *dev);
302
303
304
305
306
307static inline int b43_new_kidx_api(struct b43_wldev *dev)
308{
309
310 return (dev->fw.rev >= 351);
311}
312static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
313{
314 u8 firmware_kidx;
315 if (b43_new_kidx_api(dev)) {
316 firmware_kidx = raw_kidx;
317 } else {
318 if (raw_kidx >= 4)
319 firmware_kidx = raw_kidx - 4;
320 else
321 firmware_kidx = raw_kidx;
322 }
323 return firmware_kidx;
324}
325static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
326{
327 u8 raw_kidx;
328 if (b43_new_kidx_api(dev))
329 raw_kidx = firmware_kidx;
330 else
331 raw_kidx = firmware_kidx + 4;
332 return raw_kidx;
333}
334
335#endif
336