LXR linux/drivers/net/wireless/b43legacy/dma.h

   1#ifndef B43legacy_DMA_H_
   2#define B43legacy_DMA_H_
   3
   4#include <linux/list.h>
   5#include <linux/spinlock.h>
   6#include <linux/workqueue.h>
   7#include <linux/linkage.h>
   8#include <asm/atomic.h>
   9
  10#include "b43legacy.h"
  11
  12
  13/* DMA-Interrupt reasons. */
  14#define B43legacy_DMAIRQ_FATALMASK      ((1 << 10) | (1 << 11) | (1 << 12) \
  15                                         | (1 << 14) | (1 << 15))
  16#define B43legacy_DMAIRQ_NONFATALMASK   (1 << 13)
  17#define B43legacy_DMAIRQ_RX_DONE                (1 << 16)
  18
  19
  20/*** 32-bit DMA Engine. ***/
  21
  22/* 32-bit DMA controller registers. */
  23#define B43legacy_DMA32_TXCTL                           0x00
  24#define         B43legacy_DMA32_TXENABLE                0x00000001
  25#define         B43legacy_DMA32_TXSUSPEND               0x00000002
  26#define         B43legacy_DMA32_TXLOOPBACK              0x00000004
  27#define         B43legacy_DMA32_TXFLUSH                 0x00000010
  28#define         B43legacy_DMA32_TXADDREXT_MASK          0x00030000
  29#define         B43legacy_DMA32_TXADDREXT_SHIFT         16
  30#define B43legacy_DMA32_TXRING                          0x04
  31#define B43legacy_DMA32_TXINDEX                         0x08
  32#define B43legacy_DMA32_TXSTATUS                        0x0C
  33#define         B43legacy_DMA32_TXDPTR                  0x00000FFF
  34#define         B43legacy_DMA32_TXSTATE                 0x0000F000
  35#define                 B43legacy_DMA32_TXSTAT_DISABLED 0x00000000
  36#define                 B43legacy_DMA32_TXSTAT_ACTIVE   0x00001000
  37#define                 B43legacy_DMA32_TXSTAT_IDLEWAIT 0x00002000
  38#define                 B43legacy_DMA32_TXSTAT_STOPPED  0x00003000
  39#define                 B43legacy_DMA32_TXSTAT_SUSP     0x00004000
  40#define         B43legacy_DMA32_TXERROR                 0x000F0000
  41#define                 B43legacy_DMA32_TXERR_NOERR     0x00000000
  42#define                 B43legacy_DMA32_TXERR_PROT      0x00010000
  43#define                 B43legacy_DMA32_TXERR_UNDERRUN  0x00020000
  44#define                 B43legacy_DMA32_TXERR_BUFREAD   0x00030000
  45#define                 B43legacy_DMA32_TXERR_DESCREAD  0x00040000
  46#define         B43legacy_DMA32_TXACTIVE                0xFFF00000
  47#define B43legacy_DMA32_RXCTL                           0x10
  48#define         B43legacy_DMA32_RXENABLE                0x00000001
  49#define         B43legacy_DMA32_RXFROFF_MASK            0x000000FE
  50#define         B43legacy_DMA32_RXFROFF_SHIFT           1
  51#define         B43legacy_DMA32_RXDIRECTFIFO            0x00000100
  52#define         B43legacy_DMA32_RXADDREXT_MASK          0x00030000
  53#define         B43legacy_DMA32_RXADDREXT_SHIFT         16
  54#define B43legacy_DMA32_RXRING                          0x14
  55#define B43legacy_DMA32_RXINDEX                         0x18
  56#define B43legacy_DMA32_RXSTATUS                        0x1C
  57#define         B43legacy_DMA32_RXDPTR                  0x00000FFF
  58#define         B43legacy_DMA32_RXSTATE                 0x0000F000
  59#define                 B43legacy_DMA32_RXSTAT_DISABLED 0x00000000
  60#define                 B43legacy_DMA32_RXSTAT_ACTIVE   0x00001000
  61#define                 B43legacy_DMA32_RXSTAT_IDLEWAIT 0x00002000
  62#define                 B43legacy_DMA32_RXSTAT_STOPPED  0x00003000
  63#define         B43legacy_DMA32_RXERROR                 0x000F0000
  64#define                 B43legacy_DMA32_RXERR_NOERR     0x00000000
  65#define                 B43legacy_DMA32_RXERR_PROT      0x00010000
  66#define                 B43legacy_DMA32_RXERR_OVERFLOW  0x00020000
  67#define                 B43legacy_DMA32_RXERR_BUFWRITE  0x00030000
  68#define                 B43legacy_DMA32_RXERR_DESCREAD  0x00040000
  69#define         B43legacy_DMA32_RXACTIVE                0xFFF00000
  70
  71/* 32-bit DMA descriptor. */
  72struct b43legacy_dmadesc32 {
  73        __le32 control;
  74        __le32 address;
  75} __attribute__((__packed__));
  76#define B43legacy_DMA32_DCTL_BYTECNT            0x00001FFF
  77#define B43legacy_DMA32_DCTL_ADDREXT_MASK       0x00030000
  78#define B43legacy_DMA32_DCTL_ADDREXT_SHIFT      16
  79#define B43legacy_DMA32_DCTL_DTABLEEND          0x10000000
  80#define B43legacy_DMA32_DCTL_IRQ                0x20000000
  81#define B43legacy_DMA32_DCTL_FRAMEEND           0x40000000
  82#define B43legacy_DMA32_DCTL_FRAMESTART         0x80000000
  83
  84
  85
  86/*** 64-bit DMA Engine. ***/
  87
  88/* 64-bit DMA controller registers. */
  89#define B43legacy_DMA64_TXCTL                           0x00
  90#define         B43legacy_DMA64_TXENABLE                0x00000001
  91#define         B43legacy_DMA64_TXSUSPEND               0x00000002
  92#define         B43legacy_DMA64_TXLOOPBACK              0x00000004
  93#define         B43legacy_DMA64_TXFLUSH                 0x00000010
  94#define         B43legacy_DMA64_TXADDREXT_MASK          0x00030000
  95#define         B43legacy_DMA64_TXADDREXT_SHIFT         16
  96#define B43legacy_DMA64_TXINDEX                         0x04
  97#define B43legacy_DMA64_TXRINGLO                        0x08
  98#define B43legacy_DMA64_TXRINGHI                        0x0C
  99#define B43legacy_DMA64_TXSTATUS                        0x10
 100#define         B43legacy_DMA64_TXSTATDPTR              0x00001FFF
 101#define         B43legacy_DMA64_TXSTAT                  0xF0000000
 102#define                 B43legacy_DMA64_TXSTAT_DISABLED 0x00000000
 103#define                 B43legacy_DMA64_TXSTAT_ACTIVE   0x10000000
 104#define                 B43legacy_DMA64_TXSTAT_IDLEWAIT 0x20000000
 105#define                 B43legacy_DMA64_TXSTAT_STOPPED  0x30000000
 106#define                 B43legacy_DMA64_TXSTAT_SUSP     0x40000000
 107#define B43legacy_DMA64_TXERROR                         0x14
 108#define         B43legacy_DMA64_TXERRDPTR               0x0001FFFF
 109#define         B43legacy_DMA64_TXERR                   0xF0000000
 110#define                 B43legacy_DMA64_TXERR_NOERR     0x00000000
 111#define                 B43legacy_DMA64_TXERR_PROT      0x10000000
 112#define                 B43legacy_DMA64_TXERR_UNDERRUN  0x20000000
 113#define                 B43legacy_DMA64_TXERR_TRANSFER  0x30000000
 114#define                 B43legacy_DMA64_TXERR_DESCREAD  0x40000000
 115#define                 B43legacy_DMA64_TXERR_CORE      0x50000000
 116#define B43legacy_DMA64_RXCTL                           0x20
 117#define         B43legacy_DMA64_RXENABLE                0x00000001
 118#define         B43legacy_DMA64_RXFROFF_MASK            0x000000FE
 119#define         B43legacy_DMA64_RXFROFF_SHIFT           1
 120#define         B43legacy_DMA64_RXDIRECTFIFO            0x00000100
 121#define         B43legacy_DMA64_RXADDREXT_MASK          0x00030000
 122#define         B43legacy_DMA64_RXADDREXT_SHIFT         16
 123#define B43legacy_DMA64_RXINDEX                         0x24
 124#define B43legacy_DMA64_RXRINGLO                        0x28
 125#define B43legacy_DMA64_RXRINGHI                        0x2C
 126#define B43legacy_DMA64_RXSTATUS                        0x30
 127#define         B43legacy_DMA64_RXSTATDPTR              0x00001FFF
 128#define         B43legacy_DMA64_RXSTAT                  0xF0000000
 129#define                 B43legacy_DMA64_RXSTAT_DISABLED 0x00000000
 130#define                 B43legacy_DMA64_RXSTAT_ACTIVE   0x10000000
 131#define                 B43legacy_DMA64_RXSTAT_IDLEWAIT 0x20000000
 132#define                 B43legacy_DMA64_RXSTAT_STOPPED  0x30000000
 133#define                 B43legacy_DMA64_RXSTAT_SUSP     0x40000000
 134#define B43legacy_DMA64_RXERROR                         0x34
 135#define         B43legacy_DMA64_RXERRDPTR               0x0001FFFF
 136#define         B43legacy_DMA64_RXERR                   0xF0000000
 137#define                 B43legacy_DMA64_RXERR_NOERR     0x00000000
 138#define                 B43legacy_DMA64_RXERR_PROT      0x10000000
 139#define                 B43legacy_DMA64_RXERR_UNDERRUN  0x20000000
 140#define                 B43legacy_DMA64_RXERR_TRANSFER  0x30000000
 141#define                 B43legacy_DMA64_RXERR_DESCREAD  0x40000000
 142#define                 B43legacy_DMA64_RXERR_CORE      0x50000000
 143
 144/* 64-bit DMA descriptor. */
 145struct b43legacy_dmadesc64 {
 146        __le32 control0;
 147        __le32 control1;
 148        __le32 address_low;
 149        __le32 address_high;
 150} __attribute__((__packed__));
 151#define B43legacy_DMA64_DCTL0_DTABLEEND         0x10000000
 152#define B43legacy_DMA64_DCTL0_IRQ               0x20000000
 153#define B43legacy_DMA64_DCTL0_FRAMEEND          0x40000000
 154#define B43legacy_DMA64_DCTL0_FRAMESTART        0x80000000
 155#define B43legacy_DMA64_DCTL1_BYTECNT           0x00001FFF
 156#define B43legacy_DMA64_DCTL1_ADDREXT_MASK      0x00030000
 157#define B43legacy_DMA64_DCTL1_ADDREXT_SHIFT     16
 158
 159
 160
 161struct b43legacy_dmadesc_generic {
 162        union {
 163                struct b43legacy_dmadesc32 dma32;
 164                struct b43legacy_dmadesc64 dma64;
 165        } __attribute__((__packed__));
 166} __attribute__((__packed__));
 167
 168
 169/* Misc DMA constants */
 170#define B43legacy_DMA_RINGMEMSIZE       PAGE_SIZE
 171#define B43legacy_DMA0_RX_FRAMEOFFSET   30
 172#define B43legacy_DMA3_RX_FRAMEOFFSET   0
 173
 174
 175/* DMA engine tuning knobs */
 176#define B43legacy_TXRING_SLOTS          128
 177#define B43legacy_RXRING_SLOTS          64
 178#define B43legacy_DMA0_RX_BUFFERSIZE    (2304 + 100)
 179#define B43legacy_DMA3_RX_BUFFERSIZE    16
 180
 181
 182
 183#ifdef CONFIG_B43LEGACY_DMA
 184
 185
 186struct sk_buff;
 187struct b43legacy_private;
 188struct b43legacy_txstatus;
 189
 190
 191struct b43legacy_dmadesc_meta {
 192        /* The kernel DMA-able buffer. */
 193        struct sk_buff *skb;
 194        /* DMA base bus-address of the descriptor buffer. */
 195        dma_addr_t dmaaddr;
 196        /* ieee80211 TX status. Only used once per 802.11 frag. */
 197        bool is_last_fragment;
 198};
 199
 200struct b43legacy_dmaring;
 201
 202/* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
 203struct b43legacy_dma_ops {
 204        struct b43legacy_dmadesc_generic * (*idx2desc)
 205                                           (struct b43legacy_dmaring *ring,
 206                                           int slot,
 207                                           struct b43legacy_dmadesc_meta
 208                                           **meta);
 209        void (*fill_descriptor)(struct b43legacy_dmaring *ring,
 210                                struct b43legacy_dmadesc_generic *desc,
 211                                dma_addr_t dmaaddr, u16 bufsize,
 212                                int start, int end, int irq);
 213        void (*poke_tx)(struct b43legacy_dmaring *ring, int slot);
 214        void (*tx_suspend)(struct b43legacy_dmaring *ring);
 215        void (*tx_resume)(struct b43legacy_dmaring *ring);
 216        int (*get_current_rxslot)(struct b43legacy_dmaring *ring);
 217        void (*set_current_rxslot)(struct b43legacy_dmaring *ring, int slot);
 218};
 219
 220enum b43legacy_dmatype {
 221        B43legacy_DMA_30BIT = 30,
 222        B43legacy_DMA_32BIT = 32,
 223        B43legacy_DMA_64BIT = 64,
 224};
 225
 226struct b43legacy_dmaring {
 227        /* Lowlevel DMA ops. */
 228        const struct b43legacy_dma_ops *ops;
 229        /* Kernel virtual base address of the ring memory. */
 230        void *descbase;
 231        /* Meta data about all descriptors. */
 232        struct b43legacy_dmadesc_meta *meta;
 233        /* Cache of TX headers for each slot.
 234         * This is to avoid an allocation on each TX.
 235         * This is NULL for an RX ring.
 236         */
 237        u8 *txhdr_cache;
 238        /* (Unadjusted) DMA base bus-address of the ring memory. */
 239        dma_addr_t dmabase;
 240        /* Number of descriptor slots in the ring. */
 241        int nr_slots;
 242        /* Number of used descriptor slots. */
 243        int used_slots;
 244        /* Currently used slot in the ring. */
 245        int current_slot;
 246        /* Total number of packets sent. Statistics only. */
 247        unsigned int nr_tx_packets;
 248        /* Frameoffset in octets. */
 249        u32 frameoffset;
 250        /* Descriptor buffer size. */
 251        u16 rx_buffersize;
 252        /* The MMIO base register of the DMA controller. */
 253        u16 mmio_base;
 254        /* DMA controller index number (0-5). */
 255        int index;
 256        /* Boolean. Is this a TX ring? */
 257        bool tx;
 258        /* The type of DMA engine used. */
 259        enum b43legacy_dmatype type;
 260        /* Boolean. Is this ring stopped at ieee80211 level? */
 261        bool stopped;
 262        /* Lock, only used for TX. */
 263        spinlock_t lock;
 264        struct b43legacy_wldev *dev;
 265#ifdef CONFIG_B43LEGACY_DEBUG
 266        /* Maximum number of used slots. */
 267        int max_used_slots;
 268        /* Last time we injected a ring overflow. */
 269        unsigned long last_injected_overflow;
 270#endif /* CONFIG_B43LEGACY_DEBUG*/
 271};
 272
 273
 274static inline
 275u32 b43legacy_dma_read(struct b43legacy_dmaring *ring,
 276                       u16 offset)
 277{
 278        return b43legacy_read32(ring->dev, ring->mmio_base + offset);
 279}
 280
 281static inline
 282void b43legacy_dma_write(struct b43legacy_dmaring *ring,
 283                         u16 offset, u32 value)
 284{
 285        b43legacy_write32(ring->dev, ring->mmio_base + offset, value);
 286}
 287
 288
 289int b43legacy_dma_init(struct b43legacy_wldev *dev);
 290void b43legacy_dma_free(struct b43legacy_wldev *dev);
 291
 292void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev);
 293void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev);
 294
 295void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
 296                                struct ieee80211_tx_queue_stats *stats);
 297
 298int b43legacy_dma_tx(struct b43legacy_wldev *dev,
 299                     struct sk_buff *skb);
 300void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
 301                                   const struct b43legacy_txstatus *status);
 302
 303void b43legacy_dma_rx(struct b43legacy_dmaring *ring);
 304
 305#else /* CONFIG_B43LEGACY_DMA */
 306
 307
 308static inline
 309int b43legacy_dma_init(struct b43legacy_wldev *dev)
 310{
 311        return 0;
 312}
 313static inline
 314void b43legacy_dma_free(struct b43legacy_wldev *dev)
 315{
 316}
 317static inline
 318void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
 319                                struct ieee80211_tx_queue_stats *stats)
 320{
 321}
 322static inline
 323int b43legacy_dma_tx(struct b43legacy_wldev *dev,
 324                     struct sk_buff *skb)
 325{
 326        return 0;
 327}
 328static inline
 329void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
 330                                   const struct b43legacy_txstatus *status)
 331{
 332}
 333static inline
 334void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
 335{
 336}
 337static inline
 338void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
 339{
 340}
 341static inline
 342void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
 343{
 344}
 345
 346#endif /* CONFIG_B43LEGACY_DMA */
 347#endif /* B43legacy_DMA_H_ */
 348