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30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/sched.h>
37#include <linux/skbuff.h>
38#include <linux/netdevice.h>
39#include <linux/wireless.h>
40#include <linux/firmware.h>
41#include <linux/etherdevice.h>
42#include <linux/if_arp.h>
43
44#include <net/ieee80211_radiotap.h>
45#include <net/lib80211.h>
46#include <net/mac80211.h>
47
48#include <asm/div64.h>
49
50#define DRV_NAME "iwl3945"
51
52#include "iwl-fh.h"
53#include "iwl-3945-fh.h"
54#include "iwl-commands.h"
55#include "iwl-sta.h"
56#include "iwl-3945.h"
57#include "iwl-helpers.h"
58#include "iwl-core.h"
59#include "iwl-dev.h"
60
61
62
63
64
65#define DRV_DESCRIPTION \
66"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
67
68#ifdef CONFIG_IWLWIFI_DEBUG
69#define VD "d"
70#else
71#define VD
72#endif
73
74#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
75#define VS "s"
76#else
77#define VS
78#endif
79
80#define IWL39_VERSION "1.2.26k" VD VS
81#define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
82#define DRV_AUTHOR "<ilw@linux.intel.com>"
83#define DRV_VERSION IWL39_VERSION
84
85
86MODULE_DESCRIPTION(DRV_DESCRIPTION);
87MODULE_VERSION(DRV_VERSION);
88MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
89MODULE_LICENSE("GPL");
90
91
92struct iwl_mod_params iwl3945_mod_params = {
93 .num_of_queues = IWL39_NUM_QUEUES,
94 .sw_crypto = 1,
95 .restart_fw = 1,
96
97};
98
99
100
101
102
103
104
105
106
107
108
109
110__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
111{
112 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
113
114 switch (iwl3945_mod_params.antenna) {
115 case IWL_ANTENNA_DIVERSITY:
116 return 0;
117
118 case IWL_ANTENNA_MAIN:
119 if (eeprom->antenna_switch_type)
120 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
121 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
122
123 case IWL_ANTENNA_AUX:
124 if (eeprom->antenna_switch_type)
125 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
126 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
127 }
128
129
130 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
131 iwl3945_mod_params.antenna);
132
133 return 0;
134}
135
136static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
137 struct ieee80211_key_conf *keyconf,
138 u8 sta_id)
139{
140 unsigned long flags;
141 __le16 key_flags = 0;
142 int ret;
143
144 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
145 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
146
147 if (sta_id == priv->hw_params.bcast_sta_id)
148 key_flags |= STA_KEY_MULTICAST_MSK;
149
150 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
151 keyconf->hw_key_idx = keyconf->keyidx;
152 key_flags &= ~STA_KEY_FLG_INVALID;
153
154 spin_lock_irqsave(&priv->sta_lock, flags);
155 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
156 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
157 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
158 keyconf->keylen);
159
160 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
161 keyconf->keylen);
162
163 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
164 == STA_KEY_FLG_NO_ENC)
165 priv->stations[sta_id].sta.key.key_offset =
166 iwl_get_free_ucode_key_index(priv);
167
168
169
170 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
171 "no space for a new key");
172
173 priv->stations[sta_id].sta.key.key_flags = key_flags;
174 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
175 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
176
177 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
178
179 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
180
181 spin_unlock_irqrestore(&priv->sta_lock, flags);
182
183 return ret;
184}
185
186static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
187 struct ieee80211_key_conf *keyconf,
188 u8 sta_id)
189{
190 return -EOPNOTSUPP;
191}
192
193static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
194 struct ieee80211_key_conf *keyconf,
195 u8 sta_id)
196{
197 return -EOPNOTSUPP;
198}
199
200static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
201{
202 unsigned long flags;
203
204 spin_lock_irqsave(&priv->sta_lock, flags);
205 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
206 memset(&priv->stations[sta_id].sta.key, 0,
207 sizeof(struct iwl4965_keyinfo));
208 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
209 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
210 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
211 spin_unlock_irqrestore(&priv->sta_lock, flags);
212
213 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
214 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
215 return 0;
216}
217
218static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
219 struct ieee80211_key_conf *keyconf, u8 sta_id)
220{
221 int ret = 0;
222
223 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
224
225 switch (keyconf->alg) {
226 case ALG_CCMP:
227 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
228 break;
229 case ALG_TKIP:
230 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
231 break;
232 case ALG_WEP:
233 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
234 break;
235 default:
236 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
237 ret = -EINVAL;
238 }
239
240 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
241 keyconf->alg, keyconf->keylen, keyconf->keyidx,
242 sta_id, ret);
243
244 return ret;
245}
246
247static int iwl3945_remove_static_key(struct iwl_priv *priv)
248{
249 int ret = -EOPNOTSUPP;
250
251 return ret;
252}
253
254static int iwl3945_set_static_key(struct iwl_priv *priv,
255 struct ieee80211_key_conf *key)
256{
257 if (key->alg == ALG_WEP)
258 return -EOPNOTSUPP;
259
260 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
261 return -EINVAL;
262}
263
264static void iwl3945_clear_free_frames(struct iwl_priv *priv)
265{
266 struct list_head *element;
267
268 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
269 priv->frames_count);
270
271 while (!list_empty(&priv->free_frames)) {
272 element = priv->free_frames.next;
273 list_del(element);
274 kfree(list_entry(element, struct iwl3945_frame, list));
275 priv->frames_count--;
276 }
277
278 if (priv->frames_count) {
279 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
280 priv->frames_count);
281 priv->frames_count = 0;
282 }
283}
284
285static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
286{
287 struct iwl3945_frame *frame;
288 struct list_head *element;
289 if (list_empty(&priv->free_frames)) {
290 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
291 if (!frame) {
292 IWL_ERR(priv, "Could not allocate frame!\n");
293 return NULL;
294 }
295
296 priv->frames_count++;
297 return frame;
298 }
299
300 element = priv->free_frames.next;
301 list_del(element);
302 return list_entry(element, struct iwl3945_frame, list);
303}
304
305static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
306{
307 memset(frame, 0, sizeof(*frame));
308 list_add(&frame->list, &priv->free_frames);
309}
310
311unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
312 struct ieee80211_hdr *hdr,
313 int left)
314{
315
316 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
317 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
318 (priv->iw_mode != NL80211_IFTYPE_AP)))
319 return 0;
320
321 if (priv->ibss_beacon->len > left)
322 return 0;
323
324 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
325
326 return priv->ibss_beacon->len;
327}
328
329static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
330{
331 struct iwl3945_frame *frame;
332 unsigned int frame_size;
333 int rc;
334 u8 rate;
335
336 frame = iwl3945_get_free_frame(priv);
337
338 if (!frame) {
339 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
340 "command.\n");
341 return -ENOMEM;
342 }
343
344 rate = iwl_rate_get_lowest_plcp(priv);
345
346 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
347
348 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
349 &frame->u.cmd[0]);
350
351 iwl3945_free_frame(priv, frame);
352
353 return rc;
354}
355
356static void iwl3945_unset_hw_params(struct iwl_priv *priv)
357{
358 if (priv->shared_virt)
359 pci_free_consistent(priv->pci_dev,
360 sizeof(struct iwl3945_shared),
361 priv->shared_virt,
362 priv->shared_phys);
363}
364
365static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
366 struct ieee80211_tx_info *info,
367 struct iwl_device_cmd *cmd,
368 struct sk_buff *skb_frag,
369 int sta_id)
370{
371 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
372 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
373
374 switch (keyinfo->alg) {
375 case ALG_CCMP:
376 tx->sec_ctl = TX_CMD_SEC_CCM;
377 memcpy(tx->key, keyinfo->key, keyinfo->keylen);
378 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
379 break;
380
381 case ALG_TKIP:
382 break;
383
384 case ALG_WEP:
385 tx->sec_ctl = TX_CMD_SEC_WEP |
386 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
387
388 if (keyinfo->keylen == 13)
389 tx->sec_ctl |= TX_CMD_SEC_KEY128;
390
391 memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
392
393 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
394 "with key %d\n", info->control.hw_key->hw_key_idx);
395 break;
396
397 default:
398 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
399 break;
400 }
401}
402
403
404
405
406static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
407 struct iwl_device_cmd *cmd,
408 struct ieee80211_tx_info *info,
409 struct ieee80211_hdr *hdr, u8 std_id)
410{
411 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
412 __le32 tx_flags = tx->tx_flags;
413 __le16 fc = hdr->frame_control;
414 u8 rc_flags = info->control.rates[0].flags;
415
416 tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
417 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
418 tx_flags |= TX_CMD_FLG_ACK_MSK;
419 if (ieee80211_is_mgmt(fc))
420 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
421 if (ieee80211_is_probe_resp(fc) &&
422 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
423 tx_flags |= TX_CMD_FLG_TSF_MSK;
424 } else {
425 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
426 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
427 }
428
429 tx->sta_id = std_id;
430 if (ieee80211_has_morefrags(fc))
431 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
432
433 if (ieee80211_is_data_qos(fc)) {
434 u8 *qc = ieee80211_get_qos_ctl(hdr);
435 tx->tid_tspec = qc[0] & 0xf;
436 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
437 } else {
438 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
439 }
440
441 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
442 tx_flags |= TX_CMD_FLG_RTS_MSK;
443 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
444 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
445 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
446 tx_flags |= TX_CMD_FLG_CTS_MSK;
447 }
448
449 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
450 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
451
452 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
453 if (ieee80211_is_mgmt(fc)) {
454 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
455 tx->timeout.pm_frame_timeout = cpu_to_le16(3);
456 else
457 tx->timeout.pm_frame_timeout = cpu_to_le16(2);
458 } else {
459 tx->timeout.pm_frame_timeout = 0;
460#ifdef CONFIG_IWLWIFI_LEDS
461 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
462#endif
463 }
464
465 tx->driver_txop = 0;
466 tx->tx_flags = tx_flags;
467 tx->next_frame_len = 0;
468}
469
470
471
472
473static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
474{
475 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
476 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
477 struct iwl3945_tx_cmd *tx;
478 struct iwl_tx_queue *txq = NULL;
479 struct iwl_queue *q = NULL;
480 struct iwl_device_cmd *out_cmd;
481 struct iwl_cmd_meta *out_meta;
482 dma_addr_t phys_addr;
483 dma_addr_t txcmd_phys;
484 int txq_id = skb_get_queue_mapping(skb);
485 u16 len, idx, len_org, hdr_len;
486 u8 id;
487 u8 unicast;
488 u8 sta_id;
489 u8 tid = 0;
490 u16 seq_number = 0;
491 __le16 fc;
492 u8 wait_write_ptr = 0;
493 u8 *qc = NULL;
494 unsigned long flags;
495 int rc;
496
497 spin_lock_irqsave(&priv->lock, flags);
498 if (iwl_is_rfkill(priv)) {
499 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
500 goto drop_unlock;
501 }
502
503 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
504 IWL_ERR(priv, "ERROR: No TX rate available.\n");
505 goto drop_unlock;
506 }
507
508 unicast = !is_multicast_ether_addr(hdr->addr1);
509 id = 0;
510
511 fc = hdr->frame_control;
512
513#ifdef CONFIG_IWLWIFI_DEBUG
514 if (ieee80211_is_auth(fc))
515 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
516 else if (ieee80211_is_assoc_req(fc))
517 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
518 else if (ieee80211_is_reassoc_req(fc))
519 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
520#endif
521
522
523 if (ieee80211_is_data(fc) &&
524 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
525 (!iwl_is_associated(priv) ||
526 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
527 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
528 goto drop_unlock;
529 }
530
531 spin_unlock_irqrestore(&priv->lock, flags);
532
533 hdr_len = ieee80211_hdrlen(fc);
534
535
536 if (info->flags & IEEE80211_TX_CTL_INJECTED)
537 sta_id = priv->hw_params.bcast_sta_id;
538 else
539 sta_id = iwl_get_sta_id(priv, hdr);
540 if (sta_id == IWL_INVALID_STATION) {
541 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
542 hdr->addr1);
543 goto drop;
544 }
545
546 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
547
548 if (ieee80211_is_data_qos(fc)) {
549 qc = ieee80211_get_qos_ctl(hdr);
550 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
551 if (unlikely(tid >= MAX_TID_COUNT))
552 goto drop;
553 seq_number = priv->stations[sta_id].tid[tid].seq_number &
554 IEEE80211_SCTL_SEQ;
555 hdr->seq_ctrl = cpu_to_le16(seq_number) |
556 (hdr->seq_ctrl &
557 cpu_to_le16(IEEE80211_SCTL_FRAG));
558 seq_number += 0x10;
559 }
560
561
562 txq = &priv->txq[txq_id];
563 q = &txq->q;
564
565 spin_lock_irqsave(&priv->lock, flags);
566
567 idx = get_cmd_index(q, q->write_ptr, 0);
568
569
570 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
571 txq->txb[q->write_ptr].skb[0] = skb;
572
573
574 out_cmd = txq->cmd[idx];
575 out_meta = &txq->meta[idx];
576 tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
577 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
578 memset(tx, 0, sizeof(*tx));
579
580
581
582
583
584
585
586 out_cmd->hdr.cmd = REPLY_TX;
587 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
588 INDEX_TO_SEQ(q->write_ptr)));
589
590
591 memcpy(tx->hdr, hdr, hdr_len);
592
593
594 if (info->control.hw_key)
595 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
596
597
598 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
599
600
601 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
602
603
604 len = (u16)skb->len;
605 tx->len = cpu_to_le16(len);
606
607 iwl_dbg_log_tx_data_frame(priv, len, hdr);
608 iwl_update_stats(priv, true, fc, len);
609 tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
610 tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
611
612 if (!ieee80211_has_morefrags(hdr->frame_control)) {
613 txq->need_update = 1;
614 if (qc)
615 priv->stations[sta_id].tid[tid].seq_number = seq_number;
616 } else {
617 wait_write_ptr = 1;
618 txq->need_update = 0;
619 }
620
621 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
622 le16_to_cpu(out_cmd->hdr.sequence));
623 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx->tx_flags));
624 iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
625 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
626 ieee80211_hdrlen(fc));
627
628
629
630
631
632
633
634
635
636
637 len = sizeof(struct iwl3945_tx_cmd) +
638 sizeof(struct iwl_cmd_header) + hdr_len;
639
640 len_org = len;
641 len = (len + 3) & ~3;
642
643 if (len_org != len)
644 len_org = 1;
645 else
646 len_org = 0;
647
648
649
650 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
651 len, PCI_DMA_TODEVICE);
652
653
654 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
655 pci_unmap_len_set(out_meta, len, len);
656
657
658
659 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
660 txcmd_phys, len, 1, 0);
661
662
663
664
665 len = skb->len - hdr_len;
666 if (len) {
667 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
668 len, PCI_DMA_TODEVICE);
669 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
670 phys_addr, len,
671 0, U32_PAD(len));
672 }
673
674
675
676 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
677 rc = iwl_txq_update_write_ptr(priv, txq);
678 spin_unlock_irqrestore(&priv->lock, flags);
679
680 if (rc)
681 return rc;
682
683 if ((iwl_queue_space(q) < q->high_mark)
684 && priv->mac80211_registered) {
685 if (wait_write_ptr) {
686 spin_lock_irqsave(&priv->lock, flags);
687 txq->need_update = 1;
688 iwl_txq_update_write_ptr(priv, txq);
689 spin_unlock_irqrestore(&priv->lock, flags);
690 }
691
692 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
693 }
694
695 return 0;
696
697drop_unlock:
698 spin_unlock_irqrestore(&priv->lock, flags);
699drop:
700 return -1;
701}
702
703#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
704
705#include "iwl-spectrum.h"
706
707#define BEACON_TIME_MASK_LOW 0x00FFFFFF
708#define BEACON_TIME_MASK_HIGH 0xFF000000
709#define TIME_UNIT 1024
710
711
712
713
714
715
716
717
718static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
719{
720 u32 quot;
721 u32 rem;
722 u32 interval = beacon_interval * 1024;
723
724 if (!interval || !usec)
725 return 0;
726
727 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
728 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
729
730 return (quot << 24) + rem;
731}
732
733
734
735
736
737static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
738{
739 u32 base_low = base & BEACON_TIME_MASK_LOW;
740 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
741 u32 interval = beacon_interval * TIME_UNIT;
742 u32 res = (base & BEACON_TIME_MASK_HIGH) +
743 (addon & BEACON_TIME_MASK_HIGH);
744
745 if (base_low > addon_low)
746 res += base_low - addon_low;
747 else if (base_low < addon_low) {
748 res += interval + base_low - addon_low;
749 res += (1 << 24);
750 } else
751 res += (1 << 24);
752
753 return cpu_to_le32(res);
754}
755
756static int iwl3945_get_measurement(struct iwl_priv *priv,
757 struct ieee80211_measurement_params *params,
758 u8 type)
759{
760 struct iwl_spectrum_cmd spectrum;
761 struct iwl_rx_packet *res;
762 struct iwl_host_cmd cmd = {
763 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
764 .data = (void *)&spectrum,
765 .flags = CMD_WANT_SKB,
766 };
767 u32 add_time = le64_to_cpu(params->start_time);
768 int rc;
769 int spectrum_resp_status;
770 int duration = le16_to_cpu(params->duration);
771
772 if (iwl_is_associated(priv))
773 add_time =
774 iwl3945_usecs_to_beacons(
775 le64_to_cpu(params->start_time) - priv->last_tsf,
776 le16_to_cpu(priv->rxon_timing.beacon_interval));
777
778 memset(&spectrum, 0, sizeof(spectrum));
779
780 spectrum.channel_count = cpu_to_le16(1);
781 spectrum.flags =
782 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
783 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
784 cmd.len = sizeof(spectrum);
785 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
786
787 if (iwl_is_associated(priv))
788 spectrum.start_time =
789 iwl3945_add_beacon_time(priv->last_beacon_time,
790 add_time,
791 le16_to_cpu(priv->rxon_timing.beacon_interval));
792 else
793 spectrum.start_time = 0;
794
795 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
796 spectrum.channels[0].channel = params->channel;
797 spectrum.channels[0].type = type;
798 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
799 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
800 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
801
802 rc = iwl_send_cmd_sync(priv, &cmd);
803 if (rc)
804 return rc;
805
806 res = (struct iwl_rx_packet *)cmd.reply_skb->data;
807 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
808 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
809 rc = -EIO;
810 }
811
812 spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
813 switch (spectrum_resp_status) {
814 case 0:
815 if (res->u.spectrum.id != 0xff) {
816 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
817 res->u.spectrum.id);
818 priv->measurement_status &= ~MEASUREMENT_READY;
819 }
820 priv->measurement_status |= MEASUREMENT_ACTIVE;
821 rc = 0;
822 break;
823
824 case 1:
825 rc = -EAGAIN;
826 break;
827 }
828
829 dev_kfree_skb_any(cmd.reply_skb);
830
831 return rc;
832}
833#endif
834
835static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
836 struct iwl_rx_mem_buffer *rxb)
837{
838 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
839 struct iwl_alive_resp *palive;
840 struct delayed_work *pwork;
841
842 palive = &pkt->u.alive_frame;
843
844 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
845 "0x%01X 0x%01X\n",
846 palive->is_valid, palive->ver_type,
847 palive->ver_subtype);
848
849 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
850 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
851 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
852 sizeof(struct iwl_alive_resp));
853 pwork = &priv->init_alive_start;
854 } else {
855 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
856 memcpy(&priv->card_alive, &pkt->u.alive_frame,
857 sizeof(struct iwl_alive_resp));
858 pwork = &priv->alive_start;
859 iwl3945_disable_events(priv);
860 }
861
862
863
864 if (palive->is_valid == UCODE_VALID_OK)
865 queue_delayed_work(priv->workqueue, pwork,
866 msecs_to_jiffies(5));
867 else
868 IWL_WARN(priv, "uCode did not respond OK.\n");
869}
870
871static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
872 struct iwl_rx_mem_buffer *rxb)
873{
874#ifdef CONFIG_IWLWIFI_DEBUG
875 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
876#endif
877
878 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
879 return;
880}
881
882static void iwl3945_bg_beacon_update(struct work_struct *work)
883{
884 struct iwl_priv *priv =
885 container_of(work, struct iwl_priv, beacon_update);
886 struct sk_buff *beacon;
887
888
889 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
890
891 if (!beacon) {
892 IWL_ERR(priv, "update beacon failed\n");
893 return;
894 }
895
896 mutex_lock(&priv->mutex);
897
898 if (priv->ibss_beacon)
899 dev_kfree_skb(priv->ibss_beacon);
900
901 priv->ibss_beacon = beacon;
902 mutex_unlock(&priv->mutex);
903
904 iwl3945_send_beacon_cmd(priv);
905}
906
907static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
908 struct iwl_rx_mem_buffer *rxb)
909{
910#ifdef CONFIG_IWLWIFI_DEBUG
911 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
912 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
913 u8 rate = beacon->beacon_notify_hdr.rate;
914
915 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
916 "tsf %d %d rate %d\n",
917 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
918 beacon->beacon_notify_hdr.failure_frame,
919 le32_to_cpu(beacon->ibss_mgr_status),
920 le32_to_cpu(beacon->high_tsf),
921 le32_to_cpu(beacon->low_tsf), rate);
922#endif
923
924 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
925 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
926 queue_work(priv->workqueue, &priv->beacon_update);
927}
928
929
930
931static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
932 struct iwl_rx_mem_buffer *rxb)
933{
934 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
935 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
936 unsigned long status = priv->status;
937
938 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
939 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
940 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
941
942 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
943 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
944
945 if (flags & HW_CARD_DISABLED)
946 set_bit(STATUS_RF_KILL_HW, &priv->status);
947 else
948 clear_bit(STATUS_RF_KILL_HW, &priv->status);
949
950
951 iwl_scan_cancel(priv);
952
953 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
954 test_bit(STATUS_RF_KILL_HW, &priv->status)))
955 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
956 test_bit(STATUS_RF_KILL_HW, &priv->status));
957 else
958 wake_up_interruptible(&priv->wait_command_queue);
959}
960
961
962
963
964
965
966
967
968
969
970static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
971{
972 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
973 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
974 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
975 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
976 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
977 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
978 iwl_rx_pm_debug_statistics_notif;
979 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
980
981
982
983
984
985
986 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
987 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
988
989 iwl_setup_spectrum_handlers(priv);
990 iwl_setup_rx_scan_handlers(priv);
991 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
992
993
994 iwl3945_hw_rx_handler_setup(priv);
995}
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
1065 dma_addr_t dma_addr)
1066{
1067 return cpu_to_le32((u32)dma_addr);
1068}
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
1082{
1083 struct iwl_rx_queue *rxq = &priv->rxq;
1084 struct list_head *element;
1085 struct iwl_rx_mem_buffer *rxb;
1086 unsigned long flags;
1087 int write, rc;
1088
1089 spin_lock_irqsave(&rxq->lock, flags);
1090 write = rxq->write & ~0x7;
1091 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
1092
1093 element = rxq->rx_free.next;
1094 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1095 list_del(element);
1096
1097
1098 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
1099 rxq->queue[rxq->write] = rxb;
1100 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1101 rxq->free_count--;
1102 }
1103 spin_unlock_irqrestore(&rxq->lock, flags);
1104
1105
1106 if (rxq->free_count <= RX_LOW_WATERMARK)
1107 queue_work(priv->workqueue, &priv->rx_replenish);
1108
1109
1110
1111
1112 if ((rxq->write_actual != (rxq->write & ~0x7))
1113 || (abs(rxq->write - rxq->read) > 7)) {
1114 spin_lock_irqsave(&rxq->lock, flags);
1115 rxq->need_update = 1;
1116 spin_unlock_irqrestore(&rxq->lock, flags);
1117 rc = iwl_rx_queue_update_write_ptr(priv, rxq);
1118 if (rc)
1119 return rc;
1120 }
1121
1122 return 0;
1123}
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
1134{
1135 struct iwl_rx_queue *rxq = &priv->rxq;
1136 struct list_head *element;
1137 struct iwl_rx_mem_buffer *rxb;
1138 struct sk_buff *skb;
1139 unsigned long flags;
1140
1141 while (1) {
1142 spin_lock_irqsave(&rxq->lock, flags);
1143
1144 if (list_empty(&rxq->rx_used)) {
1145 spin_unlock_irqrestore(&rxq->lock, flags);
1146 return;
1147 }
1148 spin_unlock_irqrestore(&rxq->lock, flags);
1149
1150 if (rxq->free_count > RX_LOW_WATERMARK)
1151 priority |= __GFP_NOWARN;
1152
1153 skb = alloc_skb(priv->hw_params.rx_buf_size, priority);
1154 if (!skb) {
1155 if (net_ratelimit())
1156 IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
1157 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
1158 net_ratelimit())
1159 IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
1160 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1161 rxq->free_count);
1162
1163
1164
1165 break;
1166 }
1167
1168 spin_lock_irqsave(&rxq->lock, flags);
1169 if (list_empty(&rxq->rx_used)) {
1170 spin_unlock_irqrestore(&rxq->lock, flags);
1171 dev_kfree_skb_any(skb);
1172 return;
1173 }
1174 element = rxq->rx_used.next;
1175 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1176 list_del(element);
1177 spin_unlock_irqrestore(&rxq->lock, flags);
1178
1179 rxb->skb = skb;
1180
1181
1182
1183
1184
1185
1186
1187 skb_reserve(rxb->skb, 4);
1188
1189
1190 rxb->real_dma_addr = pci_map_single(priv->pci_dev,
1191 rxb->skb->data,
1192 priv->hw_params.rx_buf_size,
1193 PCI_DMA_FROMDEVICE);
1194
1195 spin_lock_irqsave(&rxq->lock, flags);
1196 list_add_tail(&rxb->list, &rxq->rx_free);
1197 priv->alloc_rxb_skb++;
1198 rxq->free_count++;
1199 spin_unlock_irqrestore(&rxq->lock, flags);
1200 }
1201}
1202
1203void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1204{
1205 unsigned long flags;
1206 int i;
1207 spin_lock_irqsave(&rxq->lock, flags);
1208 INIT_LIST_HEAD(&rxq->rx_free);
1209 INIT_LIST_HEAD(&rxq->rx_used);
1210
1211 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1212
1213
1214 if (rxq->pool[i].skb != NULL) {
1215 pci_unmap_single(priv->pci_dev,
1216 rxq->pool[i].real_dma_addr,
1217 priv->hw_params.rx_buf_size,
1218 PCI_DMA_FROMDEVICE);
1219 priv->alloc_rxb_skb--;
1220 dev_kfree_skb(rxq->pool[i].skb);
1221 rxq->pool[i].skb = NULL;
1222 }
1223 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1224 }
1225
1226
1227
1228 rxq->read = rxq->write = 0;
1229 rxq->free_count = 0;
1230 rxq->write_actual = 0;
1231 spin_unlock_irqrestore(&rxq->lock, flags);
1232}
1233
1234void iwl3945_rx_replenish(void *data)
1235{
1236 struct iwl_priv *priv = data;
1237 unsigned long flags;
1238
1239 iwl3945_rx_allocate(priv, GFP_KERNEL);
1240
1241 spin_lock_irqsave(&priv->lock, flags);
1242 iwl3945_rx_queue_restock(priv);
1243 spin_unlock_irqrestore(&priv->lock, flags);
1244}
1245
1246static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1247{
1248 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1249
1250 iwl3945_rx_queue_restock(priv);
1251}
1252
1253
1254
1255
1256
1257
1258
1259static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1260{
1261 int i;
1262 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1263 if (rxq->pool[i].skb != NULL) {
1264 pci_unmap_single(priv->pci_dev,
1265 rxq->pool[i].real_dma_addr,
1266 priv->hw_params.rx_buf_size,
1267 PCI_DMA_FROMDEVICE);
1268 dev_kfree_skb(rxq->pool[i].skb);
1269 }
1270 }
1271
1272 pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1273 rxq->dma_addr);
1274 pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
1275 rxq->rb_stts, rxq->rb_stts_dma);
1276 rxq->bd = NULL;
1277 rxq->rb_stts = NULL;
1278}
1279
1280
1281
1282static u8 ratio2dB[100] = {
1283
1284 0, 0, 6, 10, 12, 14, 16, 17, 18, 19,
1285 20, 21, 22, 22, 23, 23, 24, 25, 26, 26,
1286 26, 26, 26, 27, 27, 28, 28, 28, 29, 29,
1287 29, 30, 30, 30, 31, 31, 31, 31, 32, 32,
1288 32, 32, 32, 33, 33, 33, 33, 33, 34, 34,
1289 34, 34, 34, 34, 35, 35, 35, 35, 35, 35,
1290 36, 36, 36, 36, 36, 36, 36, 37, 37, 37,
1291 37, 37, 37, 37, 37, 38, 38, 38, 38, 38,
1292 38, 38, 38, 38, 38, 39, 39, 39, 39, 39,
1293 39, 39, 39, 39, 39, 40, 40, 40, 40, 40
1294};
1295
1296
1297
1298
1299int iwl3945_calc_db_from_ratio(int sig_ratio)
1300{
1301
1302 if (sig_ratio >= 1000)
1303 return 60;
1304
1305
1306
1307 if (sig_ratio >= 100)
1308 return 20 + (int)ratio2dB[sig_ratio/10];
1309
1310
1311 if (sig_ratio < 1)
1312 return 0;
1313
1314
1315 return (int)ratio2dB[sig_ratio];
1316}
1317
1318#define PERFECT_RSSI (-20)
1319#define WORST_RSSI (-95)
1320#define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
1321
1322
1323
1324
1325int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
1326{
1327 int sig_qual;
1328 int degradation = PERFECT_RSSI - rssi_dbm;
1329
1330
1331
1332
1333
1334
1335 if (noise_dbm) {
1336 if (rssi_dbm - noise_dbm >= 40)
1337 return 100;
1338 else if (rssi_dbm < noise_dbm)
1339 return 0;
1340 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
1341
1342
1343
1344
1345
1346 } else
1347 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
1348 (15 * RSSI_RANGE + 62 * degradation)) /
1349 (RSSI_RANGE * RSSI_RANGE);
1350
1351 if (sig_qual > 100)
1352 sig_qual = 100;
1353 else if (sig_qual < 1)
1354 sig_qual = 0;
1355
1356 return sig_qual;
1357}
1358
1359
1360
1361
1362
1363
1364
1365
1366static void iwl3945_rx_handle(struct iwl_priv *priv)
1367{
1368 struct iwl_rx_mem_buffer *rxb;
1369 struct iwl_rx_packet *pkt;
1370 struct iwl_rx_queue *rxq = &priv->rxq;
1371 u32 r, i;
1372 int reclaim;
1373 unsigned long flags;
1374 u8 fill_rx = 0;
1375 u32 count = 8;
1376 int total_empty = 0;
1377
1378
1379
1380 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
1381 i = rxq->read;
1382
1383
1384 total_empty = r - priv->rxq.write_actual;
1385 if (total_empty < 0)
1386 total_empty += RX_QUEUE_SIZE;
1387
1388 if (total_empty > (RX_QUEUE_SIZE / 2))
1389 fill_rx = 1;
1390
1391 if (i == r)
1392 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
1393
1394 while (i != r) {
1395 rxb = rxq->queue[i];
1396
1397
1398
1399
1400 BUG_ON(rxb == NULL);
1401
1402 rxq->queue[i] = NULL;
1403
1404 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
1405 priv->hw_params.rx_buf_size,
1406 PCI_DMA_FROMDEVICE);
1407 pkt = (struct iwl_rx_packet *)rxb->skb->data;
1408
1409
1410
1411
1412
1413
1414
1415 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1416 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1417 (pkt->hdr.cmd != REPLY_TX);
1418
1419
1420
1421
1422 if (priv->rx_handlers[pkt->hdr.cmd]) {
1423 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
1424 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1425 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1426 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1427 } else {
1428
1429 IWL_DEBUG_RX(priv, "r %d i %d No handler needed for %s, 0x%02x\n",
1430 r, i, get_cmd_string(pkt->hdr.cmd),
1431 pkt->hdr.cmd);
1432 }
1433
1434 if (reclaim) {
1435
1436
1437
1438 if (rxb && rxb->skb)
1439 iwl_tx_cmd_complete(priv, rxb);
1440 else
1441 IWL_WARN(priv, "Claim null rxb?\n");
1442 }
1443
1444
1445
1446
1447 if (rxb->skb != NULL) {
1448 priv->alloc_rxb_skb--;
1449 dev_kfree_skb_any(rxb->skb);
1450 rxb->skb = NULL;
1451 }
1452
1453 spin_lock_irqsave(&rxq->lock, flags);
1454 list_add_tail(&rxb->list, &priv->rxq.rx_used);
1455 spin_unlock_irqrestore(&rxq->lock, flags);
1456 i = (i + 1) & RX_QUEUE_MASK;
1457
1458
1459 if (fill_rx) {
1460 count++;
1461 if (count >= 8) {
1462 priv->rxq.read = i;
1463 iwl3945_rx_replenish_now(priv);
1464 count = 0;
1465 }
1466 }
1467 }
1468
1469
1470 priv->rxq.read = i;
1471 if (fill_rx)
1472 iwl3945_rx_replenish_now(priv);
1473 else
1474 iwl3945_rx_queue_restock(priv);
1475}
1476
1477
1478static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1479{
1480
1481 synchronize_irq(priv->pci_dev->irq);
1482 tasklet_kill(&priv->irq_tasklet);
1483}
1484
1485#ifdef CONFIG_IWLWIFI_DEBUG
1486static const char *desc_lookup(int i)
1487{
1488 switch (i) {
1489 case 1:
1490 return "FAIL";
1491 case 2:
1492 return "BAD_PARAM";
1493 case 3:
1494 return "BAD_CHECKSUM";
1495 case 4:
1496 return "NMI_INTERRUPT";
1497 case 5:
1498 return "SYSASSERT";
1499 case 6:
1500 return "FATAL_ERROR";
1501 }
1502
1503 return "UNKNOWN";
1504}
1505
1506#define ERROR_START_OFFSET (1 * sizeof(u32))
1507#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1508
1509void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1510{
1511 u32 i;
1512 u32 desc, time, count, base, data1;
1513 u32 blink1, blink2, ilink1, ilink2;
1514
1515 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1516
1517 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
1518 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1519 return;
1520 }
1521
1522
1523 count = iwl_read_targ_mem(priv, base);
1524
1525 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1526 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1527 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1528 priv->status, count);
1529 }
1530
1531 IWL_ERR(priv, "Desc Time asrtPC blink2 "
1532 "ilink1 nmiPC Line\n");
1533 for (i = ERROR_START_OFFSET;
1534 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1535 i += ERROR_ELEM_SIZE) {
1536 desc = iwl_read_targ_mem(priv, base + i);
1537 time =
1538 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
1539 blink1 =
1540 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
1541 blink2 =
1542 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
1543 ilink1 =
1544 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
1545 ilink2 =
1546 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
1547 data1 =
1548 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
1549
1550 IWL_ERR(priv,
1551 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1552 desc_lookup(desc), desc, time, blink1, blink2,
1553 ilink1, ilink2, data1);
1554 }
1555
1556}
1557
1558#define EVENT_START_OFFSET (6 * sizeof(u32))
1559
1560
1561
1562
1563
1564static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1565 u32 num_events, u32 mode)
1566{
1567 u32 i;
1568 u32 base;
1569 u32 event_size;
1570 u32 ptr;
1571 u32 ev, time, data;
1572
1573 if (num_events == 0)
1574 return;
1575
1576 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1577
1578 if (mode == 0)
1579 event_size = 2 * sizeof(u32);
1580 else
1581 event_size = 3 * sizeof(u32);
1582
1583 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1584
1585
1586
1587 for (i = 0; i < num_events; i++) {
1588 ev = iwl_read_targ_mem(priv, ptr);
1589 ptr += sizeof(u32);
1590 time = iwl_read_targ_mem(priv, ptr);
1591 ptr += sizeof(u32);
1592 if (mode == 0) {
1593
1594 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1595 } else {
1596 data = iwl_read_targ_mem(priv, ptr);
1597 ptr += sizeof(u32);
1598 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
1599 }
1600 }
1601}
1602
1603void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
1604{
1605 u32 base;
1606 u32 capacity;
1607 u32 mode;
1608 u32 num_wraps;
1609 u32 next_entry;
1610 u32 size;
1611
1612 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1613 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
1614 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1615 return;
1616 }
1617
1618
1619 capacity = iwl_read_targ_mem(priv, base);
1620 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1621 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1622 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1623
1624 size = num_wraps ? capacity : next_entry;
1625
1626
1627 if (size == 0) {
1628 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1629 return;
1630 }
1631
1632 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1633 size, num_wraps);
1634
1635
1636
1637 if (num_wraps)
1638 iwl3945_print_event_log(priv, next_entry,
1639 capacity - next_entry, mode);
1640
1641
1642 iwl3945_print_event_log(priv, 0, next_entry, mode);
1643
1644}
1645#else
1646void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
1647{
1648}
1649
1650void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1651{
1652}
1653
1654#endif
1655
1656static void iwl3945_irq_tasklet(struct iwl_priv *priv)
1657{
1658 u32 inta, handled = 0;
1659 u32 inta_fh;
1660 unsigned long flags;
1661#ifdef CONFIG_IWLWIFI_DEBUG
1662 u32 inta_mask;
1663#endif
1664
1665 spin_lock_irqsave(&priv->lock, flags);
1666
1667
1668
1669
1670 inta = iwl_read32(priv, CSR_INT);
1671 iwl_write32(priv, CSR_INT, inta);
1672
1673
1674
1675
1676 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1677 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1678
1679#ifdef CONFIG_IWLWIFI_DEBUG
1680 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1681
1682 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1683 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1684 inta, inta_mask, inta_fh);
1685 }
1686#endif
1687
1688
1689
1690
1691
1692 if (inta_fh & CSR39_FH_INT_RX_MASK)
1693 inta |= CSR_INT_BIT_FH_RX;
1694 if (inta_fh & CSR39_FH_INT_TX_MASK)
1695 inta |= CSR_INT_BIT_FH_TX;
1696
1697
1698 if (inta & CSR_INT_BIT_HW_ERR) {
1699 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1700
1701
1702 iwl_disable_interrupts(priv);
1703
1704 priv->isr_stats.hw++;
1705 iwl_irq_handle_error(priv);
1706
1707 handled |= CSR_INT_BIT_HW_ERR;
1708
1709 spin_unlock_irqrestore(&priv->lock, flags);
1710
1711 return;
1712 }
1713
1714#ifdef CONFIG_IWLWIFI_DEBUG
1715 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1716
1717 if (inta & CSR_INT_BIT_SCD) {
1718 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1719 "the frame/frames.\n");
1720 priv->isr_stats.sch++;
1721 }
1722
1723
1724 if (inta & CSR_INT_BIT_ALIVE) {
1725 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1726 priv->isr_stats.alive++;
1727 }
1728 }
1729#endif
1730
1731 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1732
1733
1734 if (inta & CSR_INT_BIT_SW_ERR) {
1735 IWL_ERR(priv, "Microcode SW error detected. "
1736 "Restarting 0x%X.\n", inta);
1737 priv->isr_stats.sw++;
1738 priv->isr_stats.sw_err = inta;
1739 iwl_irq_handle_error(priv);
1740 handled |= CSR_INT_BIT_SW_ERR;
1741 }
1742
1743
1744 if (inta & CSR_INT_BIT_WAKEUP) {
1745 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1746 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1747 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1748 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1749 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1750 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1751 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1752 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1753
1754 priv->isr_stats.wakeup++;
1755 handled |= CSR_INT_BIT_WAKEUP;
1756 }
1757
1758
1759
1760
1761 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1762 iwl3945_rx_handle(priv);
1763 priv->isr_stats.rx++;
1764 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1765 }
1766
1767 if (inta & CSR_INT_BIT_FH_TX) {
1768 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1769 priv->isr_stats.tx++;
1770
1771 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
1772 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1773 (FH39_SRVC_CHNL), 0x0);
1774 handled |= CSR_INT_BIT_FH_TX;
1775 }
1776
1777 if (inta & ~handled) {
1778 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1779 priv->isr_stats.unhandled++;
1780 }
1781
1782 if (inta & ~priv->inta_mask) {
1783 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1784 inta & ~priv->inta_mask);
1785 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1786 }
1787
1788
1789
1790 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1791 iwl_enable_interrupts(priv);
1792
1793#ifdef CONFIG_IWLWIFI_DEBUG
1794 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1795 inta = iwl_read32(priv, CSR_INT);
1796 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1797 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1798 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1799 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1800 }
1801#endif
1802 spin_unlock_irqrestore(&priv->lock, flags);
1803}
1804
1805static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
1806 enum ieee80211_band band,
1807 u8 is_active, u8 n_probes,
1808 struct iwl3945_scan_channel *scan_ch)
1809{
1810 struct ieee80211_channel *chan;
1811 const struct ieee80211_supported_band *sband;
1812 const struct iwl_channel_info *ch_info;
1813 u16 passive_dwell = 0;
1814 u16 active_dwell = 0;
1815 int added, i;
1816
1817 sband = iwl_get_hw_mode(priv, band);
1818 if (!sband)
1819 return 0;
1820
1821 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1822 passive_dwell = iwl_get_passive_dwell_time(priv, band);
1823
1824 if (passive_dwell <= active_dwell)
1825 passive_dwell = active_dwell + 1;
1826
1827 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1828 chan = priv->scan_request->channels[i];
1829
1830 if (chan->band != band)
1831 continue;
1832
1833 scan_ch->channel = chan->hw_value;
1834
1835 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
1836 if (!is_channel_valid(ch_info)) {
1837 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1838 scan_ch->channel);
1839 continue;
1840 }
1841
1842 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1843 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1844
1845
1846
1847 if (!is_active || is_channel_passive(ch_info) ||
1848 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
1849 scan_ch->type = 0;
1850 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1851 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1852 } else {
1853 scan_ch->type = 1;
1854 }
1855
1856
1857
1858
1859
1860 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1861 if (n_probes)
1862 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
1863 } else {
1864
1865
1866 if ((scan_ch->type & 1) && n_probes)
1867 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
1868 }
1869
1870
1871 scan_ch->tpc.dsp_atten = 110;
1872
1873
1874
1875 if (band == IEEE80211_BAND_5GHZ)
1876 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1877 else {
1878 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1879
1880
1881
1882
1883 }
1884
1885 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
1886 scan_ch->channel,
1887 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1888 (scan_ch->type & 1) ?
1889 active_dwell : passive_dwell);
1890
1891 scan_ch++;
1892 added++;
1893 }
1894
1895 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
1896 return added;
1897}
1898
1899static void iwl3945_init_hw_rates(struct iwl_priv *priv,
1900 struct ieee80211_rate *rates)
1901{
1902 int i;
1903
1904 for (i = 0; i < IWL_RATE_COUNT; i++) {
1905 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1906 rates[i].hw_value = i;
1907 rates[i].hw_value_short = i;
1908 rates[i].flags = 0;
1909 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
1910
1911
1912
1913 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
1914 0 : IEEE80211_RATE_SHORT_PREAMBLE;
1915 }
1916 }
1917}
1918
1919
1920
1921
1922
1923
1924
1925static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
1926{
1927 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1928 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1929 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1930 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1931 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1932 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1933}
1934
1935
1936
1937
1938
1939static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
1940{
1941 u32 val;
1942 u32 save_len = len;
1943 int rc = 0;
1944 u32 errcnt;
1945
1946 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
1947
1948 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1949 IWL39_RTC_INST_LOWER_BOUND);
1950
1951 errcnt = 0;
1952 for (; len > 0; len -= sizeof(u32), image++) {
1953
1954
1955
1956 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1957 if (val != le32_to_cpu(*image)) {
1958 IWL_ERR(priv, "uCode INST section is invalid at "
1959 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1960 save_len - len, val, le32_to_cpu(*image));
1961 rc = -EIO;
1962 errcnt++;
1963 if (errcnt >= 20)
1964 break;
1965 }
1966 }
1967
1968
1969 if (!errcnt)
1970 IWL_DEBUG_INFO(priv,
1971 "ucode image in INSTRUCTION memory is good\n");
1972
1973 return rc;
1974}
1975
1976
1977
1978
1979
1980
1981
1982static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1983{
1984 u32 val;
1985 int rc = 0;
1986 u32 errcnt = 0;
1987 u32 i;
1988
1989 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
1990
1991 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1992
1993
1994
1995 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1996 i + IWL39_RTC_INST_LOWER_BOUND);
1997 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1998 if (val != le32_to_cpu(*image)) {
1999#if 0
2000 IWL_ERR(priv, "uCode INST section is invalid at "
2001 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2002 i, val, *image);
2003#endif
2004 rc = -EIO;
2005 errcnt++;
2006 if (errcnt >= 3)
2007 break;
2008 }
2009 }
2010
2011 return rc;
2012}
2013
2014
2015
2016
2017
2018
2019static int iwl3945_verify_ucode(struct iwl_priv *priv)
2020{
2021 __le32 *image;
2022 u32 len;
2023 int rc = 0;
2024
2025
2026 image = (__le32 *)priv->ucode_boot.v_addr;
2027 len = priv->ucode_boot.len;
2028 rc = iwl3945_verify_inst_sparse(priv, image, len);
2029 if (rc == 0) {
2030 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
2031 return 0;
2032 }
2033
2034
2035 image = (__le32 *)priv->ucode_init.v_addr;
2036 len = priv->ucode_init.len;
2037 rc = iwl3945_verify_inst_sparse(priv, image, len);
2038 if (rc == 0) {
2039 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
2040 return 0;
2041 }
2042
2043
2044 image = (__le32 *)priv->ucode_code.v_addr;
2045 len = priv->ucode_code.len;
2046 rc = iwl3945_verify_inst_sparse(priv, image, len);
2047 if (rc == 0) {
2048 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
2049 return 0;
2050 }
2051
2052 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
2053
2054
2055
2056
2057 image = (__le32 *)priv->ucode_boot.v_addr;
2058 len = priv->ucode_boot.len;
2059 rc = iwl3945_verify_inst_full(priv, image, len);
2060
2061 return rc;
2062}
2063
2064static void iwl3945_nic_start(struct iwl_priv *priv)
2065{
2066
2067 iwl_write32(priv, CSR_RESET, 0);
2068}
2069
2070
2071
2072
2073
2074
2075static int iwl3945_read_ucode(struct iwl_priv *priv)
2076{
2077 const struct iwl_ucode_header *ucode;
2078 int ret = -EINVAL, index;
2079 const struct firmware *ucode_raw;
2080
2081 const char *name_pre = priv->cfg->fw_name_pre;
2082 const unsigned int api_max = priv->cfg->ucode_api_max;
2083 const unsigned int api_min = priv->cfg->ucode_api_min;
2084 char buf[25];
2085 u8 *src;
2086 size_t len;
2087 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
2088
2089
2090
2091 for (index = api_max; index >= api_min; index--) {
2092 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2093 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2094 if (ret < 0) {
2095 IWL_ERR(priv, "%s firmware file req failed: %d\n",
2096 buf, ret);
2097 if (ret == -ENOENT)
2098 continue;
2099 else
2100 goto error;
2101 } else {
2102 if (index < api_max)
2103 IWL_ERR(priv, "Loaded firmware %s, "
2104 "which is deprecated. "
2105 " Please use API v%u instead.\n",
2106 buf, api_max);
2107 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2108 "(%zd bytes) from disk\n",
2109 buf, ucode_raw->size);
2110 break;
2111 }
2112 }
2113
2114 if (ret < 0)
2115 goto error;
2116
2117
2118 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
2119 IWL_ERR(priv, "File size way too small!\n");
2120 ret = -EINVAL;
2121 goto err_release;
2122 }
2123
2124
2125 ucode = (struct iwl_ucode_header *)ucode_raw->data;
2126
2127 priv->ucode_ver = le32_to_cpu(ucode->ver);
2128 api_ver = IWL_UCODE_API(priv->ucode_ver);
2129 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2130 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2131 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2132 init_data_size =
2133 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2134 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2135 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
2136
2137
2138
2139
2140
2141 if (api_ver < api_min || api_ver > api_max) {
2142 IWL_ERR(priv, "Driver unable to support your firmware API. "
2143 "Driver supports v%u, firmware is v%u.\n",
2144 api_max, api_ver);
2145 priv->ucode_ver = 0;
2146 ret = -EINVAL;
2147 goto err_release;
2148 }
2149 if (api_ver != api_max)
2150 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
2151 "got %u. New firmware can be obtained "
2152 "from http://www.intellinuxwireless.org.\n",
2153 api_max, api_ver);
2154
2155 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2156 IWL_UCODE_MAJOR(priv->ucode_ver),
2157 IWL_UCODE_MINOR(priv->ucode_ver),
2158 IWL_UCODE_API(priv->ucode_ver),
2159 IWL_UCODE_SERIAL(priv->ucode_ver));
2160
2161 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2162 priv->ucode_ver);
2163 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2164 inst_size);
2165 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2166 data_size);
2167 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2168 init_size);
2169 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2170 init_data_size);
2171 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2172 boot_size);
2173
2174
2175
2176 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
2177 inst_size + data_size + init_size +
2178 init_data_size + boot_size) {
2179
2180 IWL_DEBUG_INFO(priv,
2181 "uCode file size %zd does not match expected size\n",
2182 ucode_raw->size);
2183 ret = -EINVAL;
2184 goto err_release;
2185 }
2186
2187
2188 if (inst_size > IWL39_MAX_INST_SIZE) {
2189 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
2190 inst_size);
2191 ret = -EINVAL;
2192 goto err_release;
2193 }
2194
2195 if (data_size > IWL39_MAX_DATA_SIZE) {
2196 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
2197 data_size);
2198 ret = -EINVAL;
2199 goto err_release;
2200 }
2201 if (init_size > IWL39_MAX_INST_SIZE) {
2202 IWL_DEBUG_INFO(priv,
2203 "uCode init instr len %d too large to fit in\n",
2204 init_size);
2205 ret = -EINVAL;
2206 goto err_release;
2207 }
2208 if (init_data_size > IWL39_MAX_DATA_SIZE) {
2209 IWL_DEBUG_INFO(priv,
2210 "uCode init data len %d too large to fit in\n",
2211 init_data_size);
2212 ret = -EINVAL;
2213 goto err_release;
2214 }
2215 if (boot_size > IWL39_MAX_BSM_SIZE) {
2216 IWL_DEBUG_INFO(priv,
2217 "uCode boot instr len %d too large to fit in\n",
2218 boot_size);
2219 ret = -EINVAL;
2220 goto err_release;
2221 }
2222
2223
2224
2225
2226
2227
2228 priv->ucode_code.len = inst_size;
2229 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2230
2231 priv->ucode_data.len = data_size;
2232 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2233
2234 priv->ucode_data_backup.len = data_size;
2235 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2236
2237 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2238 !priv->ucode_data_backup.v_addr)
2239 goto err_pci_alloc;
2240
2241
2242 if (init_size && init_data_size) {
2243 priv->ucode_init.len = init_size;
2244 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2245
2246 priv->ucode_init_data.len = init_data_size;
2247 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2248
2249 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2250 goto err_pci_alloc;
2251 }
2252
2253
2254 if (boot_size) {
2255 priv->ucode_boot.len = boot_size;
2256 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2257
2258 if (!priv->ucode_boot.v_addr)
2259 goto err_pci_alloc;
2260 }
2261
2262
2263
2264
2265 len = inst_size;
2266 IWL_DEBUG_INFO(priv,
2267 "Copying (but not loading) uCode instr len %zd\n", len);
2268 memcpy(priv->ucode_code.v_addr, src, len);
2269 src += len;
2270
2271 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2272 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2273
2274
2275
2276 len = data_size;
2277 IWL_DEBUG_INFO(priv,
2278 "Copying (but not loading) uCode data len %zd\n", len);
2279 memcpy(priv->ucode_data.v_addr, src, len);
2280 memcpy(priv->ucode_data_backup.v_addr, src, len);
2281 src += len;
2282
2283
2284 if (init_size) {
2285 len = init_size;
2286 IWL_DEBUG_INFO(priv,
2287 "Copying (but not loading) init instr len %zd\n", len);
2288 memcpy(priv->ucode_init.v_addr, src, len);
2289 src += len;
2290 }
2291
2292
2293 if (init_data_size) {
2294 len = init_data_size;
2295 IWL_DEBUG_INFO(priv,
2296 "Copying (but not loading) init data len %zd\n", len);
2297 memcpy(priv->ucode_init_data.v_addr, src, len);
2298 src += len;
2299 }
2300
2301
2302 len = boot_size;
2303 IWL_DEBUG_INFO(priv,
2304 "Copying (but not loading) boot instr len %zd\n", len);
2305 memcpy(priv->ucode_boot.v_addr, src, len);
2306
2307
2308 release_firmware(ucode_raw);
2309 return 0;
2310
2311 err_pci_alloc:
2312 IWL_ERR(priv, "failed to allocate pci memory\n");
2313 ret = -ENOMEM;
2314 iwl3945_dealloc_ucode_pci(priv);
2315
2316 err_release:
2317 release_firmware(ucode_raw);
2318
2319 error:
2320 return ret;
2321}
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
2334{
2335 dma_addr_t pinst;
2336 dma_addr_t pdata;
2337
2338
2339 pinst = priv->ucode_code.p_addr;
2340 pdata = priv->ucode_data_backup.p_addr;
2341
2342
2343 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2344 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2345 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
2346 priv->ucode_data.len);
2347
2348
2349
2350 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
2351 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2352
2353 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
2354
2355 return 0;
2356}
2357
2358
2359
2360
2361
2362
2363
2364
2365static void iwl3945_init_alive_start(struct iwl_priv *priv)
2366{
2367
2368 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2369
2370
2371 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
2372 goto restart;
2373 }
2374
2375
2376
2377
2378 if (iwl3945_verify_ucode(priv)) {
2379
2380
2381 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
2382 goto restart;
2383 }
2384
2385
2386
2387
2388 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
2389 if (iwl3945_set_ucode_ptrs(priv)) {
2390
2391
2392 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
2393 goto restart;
2394 }
2395 return;
2396
2397 restart:
2398 queue_work(priv->workqueue, &priv->restart);
2399}
2400
2401
2402
2403
2404
2405
2406static void iwl3945_alive_start(struct iwl_priv *priv)
2407{
2408 int thermal_spin = 0;
2409 u32 rfkill;
2410
2411 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2412
2413 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2414
2415
2416 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2417 goto restart;
2418 }
2419
2420
2421
2422
2423 if (iwl3945_verify_ucode(priv)) {
2424
2425
2426 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2427 goto restart;
2428 }
2429
2430 iwl_clear_stations_table(priv);
2431
2432 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
2433 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
2434
2435 if (rfkill & 0x1) {
2436 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2437
2438
2439 while (iwl3945_hw_get_temperature(priv) == 0) {
2440 thermal_spin++;
2441 udelay(10);
2442 }
2443
2444 if (thermal_spin)
2445 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
2446 thermal_spin * 10);
2447 } else
2448 set_bit(STATUS_RF_KILL_HW, &priv->status);
2449
2450
2451 set_bit(STATUS_ALIVE, &priv->status);
2452
2453 if (iwl_is_rfkill(priv))
2454 return;
2455
2456 ieee80211_wake_queues(priv->hw);
2457
2458 priv->active_rate = priv->rates_mask;
2459 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2460
2461 iwl_power_update_mode(priv, false);
2462
2463 if (iwl_is_associated(priv)) {
2464 struct iwl3945_rxon_cmd *active_rxon =
2465 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
2466
2467 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2468 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2469 } else {
2470
2471 iwl_connection_init_rx_config(priv, priv->iw_mode);
2472 }
2473
2474
2475 iwl_send_bt_config(priv);
2476
2477
2478 iwlcore_commit_rxon(priv);
2479
2480 iwl3945_reg_txpower_periodic(priv);
2481
2482 iwl3945_led_register(priv);
2483
2484 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2485 set_bit(STATUS_READY, &priv->status);
2486 wake_up_interruptible(&priv->wait_command_queue);
2487
2488
2489 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2490 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2491 priv->vif);
2492 if (beacon)
2493 iwl_mac_beacon_update(priv->hw, beacon);
2494 }
2495
2496 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
2497 iwl_set_mode(priv, priv->iw_mode);
2498
2499 return;
2500
2501 restart:
2502 queue_work(priv->workqueue, &priv->restart);
2503}
2504
2505static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
2506
2507static void __iwl3945_down(struct iwl_priv *priv)
2508{
2509 unsigned long flags;
2510 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2511 struct ieee80211_conf *conf = NULL;
2512
2513 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2514
2515 conf = ieee80211_get_hw_conf(priv->hw);
2516
2517 if (!exit_pending)
2518 set_bit(STATUS_EXIT_PENDING, &priv->status);
2519
2520 iwl3945_led_unregister(priv);
2521 iwl_clear_stations_table(priv);
2522
2523
2524 wake_up_interruptible_all(&priv->wait_command_queue);
2525
2526
2527
2528 if (!exit_pending)
2529 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2530
2531
2532 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2533
2534
2535 spin_lock_irqsave(&priv->lock, flags);
2536 iwl_disable_interrupts(priv);
2537 spin_unlock_irqrestore(&priv->lock, flags);
2538 iwl_synchronize_irq(priv);
2539
2540 if (priv->mac80211_registered)
2541 ieee80211_stop_queues(priv->hw);
2542
2543
2544
2545 if (!iwl_is_init(priv)) {
2546 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2547 STATUS_RF_KILL_HW |
2548 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2549 STATUS_GEO_CONFIGURED |
2550 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2551 STATUS_EXIT_PENDING;
2552 goto exit;
2553 }
2554
2555
2556
2557 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2558 STATUS_RF_KILL_HW |
2559 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2560 STATUS_GEO_CONFIGURED |
2561 test_bit(STATUS_FW_ERROR, &priv->status) <<
2562 STATUS_FW_ERROR |
2563 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2564 STATUS_EXIT_PENDING;
2565
2566 priv->cfg->ops->lib->apm_ops.reset(priv);
2567 spin_lock_irqsave(&priv->lock, flags);
2568 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2569 spin_unlock_irqrestore(&priv->lock, flags);
2570
2571 iwl3945_hw_txq_ctx_stop(priv);
2572 iwl3945_hw_rxq_stop(priv);
2573
2574 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2575 APMG_CLK_VAL_DMA_CLK_RQT);
2576
2577 udelay(5);
2578
2579 if (exit_pending)
2580 priv->cfg->ops->lib->apm_ops.stop(priv);
2581 else
2582 priv->cfg->ops->lib->apm_ops.reset(priv);
2583
2584 exit:
2585 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2586
2587 if (priv->ibss_beacon)
2588 dev_kfree_skb(priv->ibss_beacon);
2589 priv->ibss_beacon = NULL;
2590
2591
2592 iwl3945_clear_free_frames(priv);
2593}
2594
2595static void iwl3945_down(struct iwl_priv *priv)
2596{
2597 mutex_lock(&priv->mutex);
2598 __iwl3945_down(priv);
2599 mutex_unlock(&priv->mutex);
2600
2601 iwl3945_cancel_deferred_work(priv);
2602}
2603
2604#define MAX_HW_RESTARTS 5
2605
2606static int __iwl3945_up(struct iwl_priv *priv)
2607{
2608 int rc, i;
2609
2610 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2611 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2612 return -EIO;
2613 }
2614
2615 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2616 IWL_ERR(priv, "ucode not available for device bring up\n");
2617 return -EIO;
2618 }
2619
2620
2621 if (iwl_read32(priv, CSR_GP_CNTRL) &
2622 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2623 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2624 else {
2625 set_bit(STATUS_RF_KILL_HW, &priv->status);
2626 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2627 return -ENODEV;
2628 }
2629
2630 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2631
2632 rc = iwl3945_hw_nic_init(priv);
2633 if (rc) {
2634 IWL_ERR(priv, "Unable to int nic\n");
2635 return rc;
2636 }
2637
2638
2639 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2640 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2641 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2642
2643
2644 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2645 iwl_enable_interrupts(priv);
2646
2647
2648 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2649 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2650
2651
2652
2653
2654 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2655 priv->ucode_data.len);
2656
2657
2658 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2659 return 0;
2660
2661 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2662
2663 iwl_clear_stations_table(priv);
2664
2665
2666
2667
2668 priv->cfg->ops->lib->load_ucode(priv);
2669
2670 if (rc) {
2671 IWL_ERR(priv,
2672 "Unable to set up bootstrap uCode: %d\n", rc);
2673 continue;
2674 }
2675
2676
2677 iwl3945_nic_start(priv);
2678
2679 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2680
2681 return 0;
2682 }
2683
2684 set_bit(STATUS_EXIT_PENDING, &priv->status);
2685 __iwl3945_down(priv);
2686 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2687
2688
2689
2690 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2691 return -EIO;
2692}
2693
2694
2695
2696
2697
2698
2699
2700
2701static void iwl3945_bg_init_alive_start(struct work_struct *data)
2702{
2703 struct iwl_priv *priv =
2704 container_of(data, struct iwl_priv, init_alive_start.work);
2705
2706 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2707 return;
2708
2709 mutex_lock(&priv->mutex);
2710 iwl3945_init_alive_start(priv);
2711 mutex_unlock(&priv->mutex);
2712}
2713
2714static void iwl3945_bg_alive_start(struct work_struct *data)
2715{
2716 struct iwl_priv *priv =
2717 container_of(data, struct iwl_priv, alive_start.work);
2718
2719 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2720 return;
2721
2722 mutex_lock(&priv->mutex);
2723 iwl3945_alive_start(priv);
2724 mutex_unlock(&priv->mutex);
2725}
2726
2727static void iwl3945_rfkill_poll(struct work_struct *data)
2728{
2729 struct iwl_priv *priv =
2730 container_of(data, struct iwl_priv, rfkill_poll.work);
2731
2732 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2733 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2734 else
2735 set_bit(STATUS_RF_KILL_HW, &priv->status);
2736
2737 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
2738 test_bit(STATUS_RF_KILL_HW, &priv->status));
2739
2740 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2741 round_jiffies_relative(2 * HZ));
2742
2743}
2744
2745#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
2746static void iwl3945_bg_request_scan(struct work_struct *data)
2747{
2748 struct iwl_priv *priv =
2749 container_of(data, struct iwl_priv, request_scan);
2750 struct iwl_host_cmd cmd = {
2751 .id = REPLY_SCAN_CMD,
2752 .len = sizeof(struct iwl3945_scan_cmd),
2753 .flags = CMD_SIZE_HUGE,
2754 };
2755 int rc = 0;
2756 struct iwl3945_scan_cmd *scan;
2757 struct ieee80211_conf *conf = NULL;
2758 u8 n_probes = 0;
2759 enum ieee80211_band band;
2760 bool is_active = false;
2761
2762 conf = ieee80211_get_hw_conf(priv->hw);
2763
2764 mutex_lock(&priv->mutex);
2765
2766 cancel_delayed_work(&priv->scan_check);
2767
2768 if (!iwl_is_ready(priv)) {
2769 IWL_WARN(priv, "request scan called when driver not ready.\n");
2770 goto done;
2771 }
2772
2773
2774
2775 if (!test_bit(STATUS_SCANNING, &priv->status))
2776 goto done;
2777
2778
2779
2780 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
2781 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2782 "Ignoring second request.\n");
2783 rc = -EIO;
2784 goto done;
2785 }
2786
2787 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2788 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
2789 goto done;
2790 }
2791
2792 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2793 IWL_DEBUG_HC(priv,
2794 "Scan request while abort pending. Queuing.\n");
2795 goto done;
2796 }
2797
2798 if (iwl_is_rfkill(priv)) {
2799 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
2800 goto done;
2801 }
2802
2803 if (!test_bit(STATUS_READY, &priv->status)) {
2804 IWL_DEBUG_HC(priv,
2805 "Scan request while uninitialized. Queuing.\n");
2806 goto done;
2807 }
2808
2809 if (!priv->scan_bands) {
2810 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
2811 goto done;
2812 }
2813
2814 if (!priv->scan) {
2815 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
2816 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
2817 if (!priv->scan) {
2818 rc = -ENOMEM;
2819 goto done;
2820 }
2821 }
2822 scan = priv->scan;
2823 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
2824
2825 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2826 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2827
2828 if (iwl_is_associated(priv)) {
2829 u16 interval = 0;
2830 u32 extra;
2831 u32 suspend_time = 100;
2832 u32 scan_suspend_time = 100;
2833 unsigned long flags;
2834
2835 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
2836
2837 spin_lock_irqsave(&priv->lock, flags);
2838 interval = priv->beacon_int;
2839 spin_unlock_irqrestore(&priv->lock, flags);
2840
2841 scan->suspend_time = 0;
2842 scan->max_out_time = cpu_to_le32(200 * 1024);
2843 if (!interval)
2844 interval = suspend_time;
2845
2846
2847
2848
2849
2850
2851
2852 extra = (suspend_time / interval) << 24;
2853 scan_suspend_time = 0xFF0FFFFF &
2854 (extra | ((suspend_time % interval) * 1024));
2855
2856 scan->suspend_time = cpu_to_le32(scan_suspend_time);
2857 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
2858 scan_suspend_time, interval);
2859 }
2860
2861 if (priv->scan_request->n_ssids) {
2862 int i, p = 0;
2863 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2864 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2865
2866 if (!priv->scan_request->ssids[i].ssid_len)
2867 continue;
2868 scan->direct_scan[p].id = WLAN_EID_SSID;
2869 scan->direct_scan[p].len =
2870 priv->scan_request->ssids[i].ssid_len;
2871 memcpy(scan->direct_scan[p].ssid,
2872 priv->scan_request->ssids[i].ssid,
2873 priv->scan_request->ssids[i].ssid_len);
2874 n_probes++;
2875 p++;
2876 }
2877 is_active = true;
2878 } else
2879 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
2880
2881
2882
2883 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
2884 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
2885 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2886
2887
2888
2889 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
2890 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2891 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2892 scan->good_CRC_th = 0;
2893 band = IEEE80211_BAND_2GHZ;
2894 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
2895 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
2896
2897
2898
2899
2900
2901 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
2902 band = IEEE80211_BAND_5GHZ;
2903 } else {
2904 IWL_WARN(priv, "Invalid scan band count\n");
2905 goto done;
2906 }
2907
2908 scan->tx_cmd.len = cpu_to_le16(
2909 iwl_fill_probe_req(priv,
2910 (struct ieee80211_mgmt *)scan->data,
2911 priv->scan_request->ie,
2912 priv->scan_request->ie_len,
2913 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
2914
2915
2916 scan->flags |= iwl3945_get_antenna_flags(priv);
2917
2918 if (iwl_is_monitor_mode(priv))
2919 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2920
2921 scan->channel_count =
2922 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
2923 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
2924
2925 if (scan->channel_count == 0) {
2926 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
2927 goto done;
2928 }
2929
2930 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
2931 scan->channel_count * sizeof(struct iwl3945_scan_channel);
2932 cmd.data = scan;
2933 scan->len = cpu_to_le16(cmd.len);
2934
2935 set_bit(STATUS_SCAN_HW, &priv->status);
2936 rc = iwl_send_cmd_sync(priv, &cmd);
2937 if (rc)
2938 goto done;
2939
2940 queue_delayed_work(priv->workqueue, &priv->scan_check,
2941 IWL_SCAN_CHECK_WATCHDOG);
2942
2943 mutex_unlock(&priv->mutex);
2944 return;
2945
2946 done:
2947
2948
2949
2950
2951
2952 clear_bit(STATUS_SCAN_HW, &priv->status);
2953 clear_bit(STATUS_SCANNING, &priv->status);
2954
2955
2956 queue_work(priv->workqueue, &priv->scan_completed);
2957 mutex_unlock(&priv->mutex);
2958}
2959
2960static void iwl3945_bg_up(struct work_struct *data)
2961{
2962 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
2963
2964 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2965 return;
2966
2967 mutex_lock(&priv->mutex);
2968 __iwl3945_up(priv);
2969 mutex_unlock(&priv->mutex);
2970}
2971
2972static void iwl3945_bg_restart(struct work_struct *data)
2973{
2974 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2975
2976 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2977 return;
2978
2979 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2980 mutex_lock(&priv->mutex);
2981 priv->vif = NULL;
2982 priv->is_open = 0;
2983 mutex_unlock(&priv->mutex);
2984 iwl3945_down(priv);
2985 ieee80211_restart_hw(priv->hw);
2986 } else {
2987 iwl3945_down(priv);
2988 queue_work(priv->workqueue, &priv->up);
2989 }
2990}
2991
2992static void iwl3945_bg_rx_replenish(struct work_struct *data)
2993{
2994 struct iwl_priv *priv =
2995 container_of(data, struct iwl_priv, rx_replenish);
2996
2997 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2998 return;
2999
3000 mutex_lock(&priv->mutex);
3001 iwl3945_rx_replenish(priv);
3002 mutex_unlock(&priv->mutex);
3003}
3004
3005#define IWL_DELAY_NEXT_SCAN (HZ*2)
3006
3007void iwl3945_post_associate(struct iwl_priv *priv)
3008{
3009 int rc = 0;
3010 struct ieee80211_conf *conf = NULL;
3011
3012 if (priv->iw_mode == NL80211_IFTYPE_AP) {
3013 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3014 return;
3015 }
3016
3017
3018 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3019 priv->assoc_id, priv->active_rxon.bssid_addr);
3020
3021 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3022 return;
3023
3024 if (!priv->vif || !priv->is_open)
3025 return;
3026
3027 iwl_scan_cancel_timeout(priv, 200);
3028
3029 conf = ieee80211_get_hw_conf(priv->hw);
3030
3031 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3032 iwlcore_commit_rxon(priv);
3033
3034 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
3035 iwl_setup_rxon_timing(priv);
3036 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3037 sizeof(priv->rxon_timing), &priv->rxon_timing);
3038 if (rc)
3039 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
3040 "Attempting to continue.\n");
3041
3042 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3043
3044 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
3045
3046 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3047 priv->assoc_id, priv->beacon_int);
3048
3049 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
3050 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3051 else
3052 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3053
3054 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
3055 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
3056 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
3057 else
3058 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3059
3060 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
3061 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3062
3063 }
3064
3065 iwlcore_commit_rxon(priv);
3066
3067 switch (priv->iw_mode) {
3068 case NL80211_IFTYPE_STATION:
3069 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
3070 break;
3071
3072 case NL80211_IFTYPE_ADHOC:
3073
3074 priv->assoc_id = 1;
3075 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
3076 iwl3945_sync_sta(priv, IWL_STA_ID,
3077 (priv->band == IEEE80211_BAND_5GHZ) ?
3078 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3079 CMD_ASYNC);
3080 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3081 iwl3945_send_beacon_cmd(priv);
3082
3083 break;
3084
3085 default:
3086 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3087 __func__, priv->iw_mode);
3088 break;
3089 }
3090
3091 iwl_activate_qos(priv, 0);
3092
3093
3094 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
3095}
3096
3097
3098
3099
3100
3101
3102
3103#define UCODE_READY_TIMEOUT (2 * HZ)
3104
3105static int iwl3945_mac_start(struct ieee80211_hw *hw)
3106{
3107 struct iwl_priv *priv = hw->priv;
3108 int ret;
3109
3110 IWL_DEBUG_MAC80211(priv, "enter\n");
3111
3112
3113 mutex_lock(&priv->mutex);
3114
3115
3116
3117
3118 if (!priv->ucode_code.len) {
3119 ret = iwl3945_read_ucode(priv);
3120 if (ret) {
3121 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
3122 mutex_unlock(&priv->mutex);
3123 goto out_release_irq;
3124 }
3125 }
3126
3127 ret = __iwl3945_up(priv);
3128
3129 mutex_unlock(&priv->mutex);
3130
3131 if (ret)
3132 goto out_release_irq;
3133
3134 IWL_DEBUG_INFO(priv, "Start UP work.\n");
3135
3136
3137
3138 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3139 test_bit(STATUS_READY, &priv->status),
3140 UCODE_READY_TIMEOUT);
3141 if (!ret) {
3142 if (!test_bit(STATUS_READY, &priv->status)) {
3143 IWL_ERR(priv,
3144 "Wait for START_ALIVE timeout after %dms.\n",
3145 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3146 ret = -ETIMEDOUT;
3147 goto out_release_irq;
3148 }
3149 }
3150
3151
3152
3153 cancel_delayed_work(&priv->rfkill_poll);
3154
3155 priv->is_open = 1;
3156 IWL_DEBUG_MAC80211(priv, "leave\n");
3157 return 0;
3158
3159out_release_irq:
3160 priv->is_open = 0;
3161 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
3162 return ret;
3163}
3164
3165static void iwl3945_mac_stop(struct ieee80211_hw *hw)
3166{
3167 struct iwl_priv *priv = hw->priv;
3168
3169 IWL_DEBUG_MAC80211(priv, "enter\n");
3170
3171 if (!priv->is_open) {
3172 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
3173 return;
3174 }
3175
3176 priv->is_open = 0;
3177
3178 if (iwl_is_ready_rf(priv)) {
3179
3180
3181
3182 mutex_lock(&priv->mutex);
3183 iwl_scan_cancel_timeout(priv, 100);
3184 mutex_unlock(&priv->mutex);
3185 }
3186
3187 iwl3945_down(priv);
3188
3189 flush_workqueue(priv->workqueue);
3190
3191
3192 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3193 round_jiffies_relative(2 * HZ));
3194
3195 IWL_DEBUG_MAC80211(priv, "leave\n");
3196}
3197
3198static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3199{
3200 struct iwl_priv *priv = hw->priv;
3201
3202 IWL_DEBUG_MAC80211(priv, "enter\n");
3203
3204 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3205 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3206
3207 if (iwl3945_tx_skb(priv, skb))
3208 dev_kfree_skb_any(skb);
3209
3210 IWL_DEBUG_MAC80211(priv, "leave\n");
3211 return NETDEV_TX_OK;
3212}
3213
3214void iwl3945_config_ap(struct iwl_priv *priv)
3215{
3216 int rc = 0;
3217
3218 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3219 return;
3220
3221
3222 if (!(iwl_is_associated(priv))) {
3223
3224
3225 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3226 iwlcore_commit_rxon(priv);
3227
3228
3229 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
3230 iwl_setup_rxon_timing(priv);
3231 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3232 sizeof(priv->rxon_timing),
3233 &priv->rxon_timing);
3234 if (rc)
3235 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
3236 "Attempting to continue.\n");
3237
3238
3239 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
3240 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
3241 priv->staging_rxon.flags |=
3242 RXON_FLG_SHORT_PREAMBLE_MSK;
3243 else
3244 priv->staging_rxon.flags &=
3245 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3246
3247 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
3248 if (priv->assoc_capability &
3249 WLAN_CAPABILITY_SHORT_SLOT_TIME)
3250 priv->staging_rxon.flags |=
3251 RXON_FLG_SHORT_SLOT_MSK;
3252 else
3253 priv->staging_rxon.flags &=
3254 ~RXON_FLG_SHORT_SLOT_MSK;
3255
3256 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
3257 priv->staging_rxon.flags &=
3258 ~RXON_FLG_SHORT_SLOT_MSK;
3259 }
3260
3261 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3262 iwlcore_commit_rxon(priv);
3263 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
3264 }
3265 iwl3945_send_beacon_cmd(priv);
3266
3267
3268
3269
3270}
3271
3272static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3273 struct ieee80211_vif *vif,
3274 struct ieee80211_sta *sta,
3275 struct ieee80211_key_conf *key)
3276{
3277 struct iwl_priv *priv = hw->priv;
3278 const u8 *addr;
3279 int ret = 0;
3280 u8 sta_id = IWL_INVALID_STATION;
3281 u8 static_key;
3282
3283 IWL_DEBUG_MAC80211(priv, "enter\n");
3284
3285 if (iwl3945_mod_params.sw_crypto) {
3286 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3287 return -EOPNOTSUPP;
3288 }
3289
3290 addr = sta ? sta->addr : iwl_bcast_addr;
3291 static_key = !iwl_is_associated(priv);
3292
3293 if (!static_key) {
3294 sta_id = iwl_find_station(priv, addr);
3295 if (sta_id == IWL_INVALID_STATION) {
3296 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
3297 addr);
3298 return -EINVAL;
3299 }
3300 }
3301
3302 mutex_lock(&priv->mutex);
3303 iwl_scan_cancel_timeout(priv, 100);
3304 mutex_unlock(&priv->mutex);
3305
3306 switch (cmd) {
3307 case SET_KEY:
3308 if (static_key)
3309 ret = iwl3945_set_static_key(priv, key);
3310 else
3311 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3312 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3313 break;
3314 case DISABLE_KEY:
3315 if (static_key)
3316 ret = iwl3945_remove_static_key(priv);
3317 else
3318 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3319 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3320 break;
3321 default:
3322 ret = -EINVAL;
3323 }
3324
3325 IWL_DEBUG_MAC80211(priv, "leave\n");
3326
3327 return ret;
3328}
3329
3330
3331
3332
3333
3334
3335
3336#ifdef CONFIG_IWLWIFI_DEBUG
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349static ssize_t show_debug_level(struct device *d,
3350 struct device_attribute *attr, char *buf)
3351{
3352 struct iwl_priv *priv = dev_get_drvdata(d);
3353 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
3354}
3355static ssize_t store_debug_level(struct device *d,
3356 struct device_attribute *attr,
3357 const char *buf, size_t count)
3358{
3359 struct iwl_priv *priv = dev_get_drvdata(d);
3360 unsigned long val;
3361 int ret;
3362
3363 ret = strict_strtoul(buf, 0, &val);
3364 if (ret)
3365 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
3366 else {
3367 priv->debug_level = val;
3368 if (iwl_alloc_traffic_mem(priv))
3369 IWL_ERR(priv,
3370 "Not enough memory to generate traffic log\n");
3371 }
3372 return strnlen(buf, count);
3373}
3374
3375static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3376 show_debug_level, store_debug_level);
3377
3378#endif
3379
3380static ssize_t show_temperature(struct device *d,
3381 struct device_attribute *attr, char *buf)
3382{
3383 struct iwl_priv *priv = dev_get_drvdata(d);
3384
3385 if (!iwl_is_alive(priv))
3386 return -EAGAIN;
3387
3388 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
3389}
3390
3391static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3392
3393static ssize_t show_tx_power(struct device *d,
3394 struct device_attribute *attr, char *buf)
3395{
3396 struct iwl_priv *priv = dev_get_drvdata(d);
3397 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
3398}
3399
3400static ssize_t store_tx_power(struct device *d,
3401 struct device_attribute *attr,
3402 const char *buf, size_t count)
3403{
3404 struct iwl_priv *priv = dev_get_drvdata(d);
3405 char *p = (char *)buf;
3406 u32 val;
3407
3408 val = simple_strtoul(p, &p, 10);
3409 if (p == buf)
3410 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
3411 else
3412 iwl3945_hw_reg_set_txpower(priv, val);
3413
3414 return count;
3415}
3416
3417static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3418
3419static ssize_t show_flags(struct device *d,
3420 struct device_attribute *attr, char *buf)
3421{
3422 struct iwl_priv *priv = dev_get_drvdata(d);
3423
3424 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
3425}
3426
3427static ssize_t store_flags(struct device *d,
3428 struct device_attribute *attr,
3429 const char *buf, size_t count)
3430{
3431 struct iwl_priv *priv = dev_get_drvdata(d);
3432 u32 flags = simple_strtoul(buf, NULL, 0);
3433
3434 mutex_lock(&priv->mutex);
3435 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
3436
3437 if (iwl_scan_cancel_timeout(priv, 100))
3438 IWL_WARN(priv, "Could not cancel scan.\n");
3439 else {
3440 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
3441 flags);
3442 priv->staging_rxon.flags = cpu_to_le32(flags);
3443 iwlcore_commit_rxon(priv);
3444 }
3445 }
3446 mutex_unlock(&priv->mutex);
3447
3448 return count;
3449}
3450
3451static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3452
3453static ssize_t show_filter_flags(struct device *d,
3454 struct device_attribute *attr, char *buf)
3455{
3456 struct iwl_priv *priv = dev_get_drvdata(d);
3457
3458 return sprintf(buf, "0x%04X\n",
3459 le32_to_cpu(priv->active_rxon.filter_flags));
3460}
3461
3462static ssize_t store_filter_flags(struct device *d,
3463 struct device_attribute *attr,
3464 const char *buf, size_t count)
3465{
3466 struct iwl_priv *priv = dev_get_drvdata(d);
3467 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3468
3469 mutex_lock(&priv->mutex);
3470 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
3471
3472 if (iwl_scan_cancel_timeout(priv, 100))
3473 IWL_WARN(priv, "Could not cancel scan.\n");
3474 else {
3475 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
3476 "0x%04X\n", filter_flags);
3477 priv->staging_rxon.filter_flags =
3478 cpu_to_le32(filter_flags);
3479 iwlcore_commit_rxon(priv);
3480 }
3481 }
3482 mutex_unlock(&priv->mutex);
3483
3484 return count;
3485}
3486
3487static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3488 store_filter_flags);
3489
3490#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
3491
3492static ssize_t show_measurement(struct device *d,
3493 struct device_attribute *attr, char *buf)
3494{
3495 struct iwl_priv *priv = dev_get_drvdata(d);
3496 struct iwl_spectrum_notification measure_report;
3497 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3498 u8 *data = (u8 *)&measure_report;
3499 unsigned long flags;
3500
3501 spin_lock_irqsave(&priv->lock, flags);
3502 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3503 spin_unlock_irqrestore(&priv->lock, flags);
3504 return 0;
3505 }
3506 memcpy(&measure_report, &priv->measure_report, size);
3507 priv->measurement_status = 0;
3508 spin_unlock_irqrestore(&priv->lock, flags);
3509
3510 while (size && (PAGE_SIZE - len)) {
3511 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3512 PAGE_SIZE - len, 1);
3513 len = strlen(buf);
3514 if (PAGE_SIZE - len)
3515 buf[len++] = '\n';
3516
3517 ofs += 16;
3518 size -= min(size, 16U);
3519 }
3520
3521 return len;
3522}
3523
3524static ssize_t store_measurement(struct device *d,
3525 struct device_attribute *attr,
3526 const char *buf, size_t count)
3527{
3528 struct iwl_priv *priv = dev_get_drvdata(d);
3529 struct ieee80211_measurement_params params = {
3530 .channel = le16_to_cpu(priv->active_rxon.channel),
3531 .start_time = cpu_to_le64(priv->last_tsf),
3532 .duration = cpu_to_le16(1),
3533 };
3534 u8 type = IWL_MEASURE_BASIC;
3535 u8 buffer[32];
3536 u8 channel;
3537
3538 if (count) {
3539 char *p = buffer;
3540 strncpy(buffer, buf, min(sizeof(buffer), count));
3541 channel = simple_strtoul(p, NULL, 0);
3542 if (channel)
3543 params.channel = channel;
3544
3545 p = buffer;
3546 while (*p && *p != ' ')
3547 p++;
3548 if (*p)
3549 type = simple_strtoul(p + 1, NULL, 0);
3550 }
3551
3552 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
3553 "channel %d (for '%s')\n", type, params.channel, buf);
3554 iwl3945_get_measurement(priv, ¶ms, type);
3555
3556 return count;
3557}
3558
3559static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3560 show_measurement, store_measurement);
3561#endif
3562
3563static ssize_t store_retry_rate(struct device *d,
3564 struct device_attribute *attr,
3565 const char *buf, size_t count)
3566{
3567 struct iwl_priv *priv = dev_get_drvdata(d);
3568
3569 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3570 if (priv->retry_rate <= 0)
3571 priv->retry_rate = 1;
3572
3573 return count;
3574}
3575
3576static ssize_t show_retry_rate(struct device *d,
3577 struct device_attribute *attr, char *buf)
3578{
3579 struct iwl_priv *priv = dev_get_drvdata(d);
3580 return sprintf(buf, "%d", priv->retry_rate);
3581}
3582
3583static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3584 store_retry_rate);
3585
3586
3587static ssize_t show_channels(struct device *d,
3588 struct device_attribute *attr, char *buf)
3589{
3590
3591 return 0;
3592}
3593
3594static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3595
3596static ssize_t show_statistics(struct device *d,
3597 struct device_attribute *attr, char *buf)
3598{
3599 struct iwl_priv *priv = dev_get_drvdata(d);
3600 u32 size = sizeof(struct iwl3945_notif_statistics);
3601 u32 len = 0, ofs = 0;
3602 u8 *data = (u8 *)&priv->statistics_39;
3603 int rc = 0;
3604
3605 if (!iwl_is_alive(priv))
3606 return -EAGAIN;
3607
3608 mutex_lock(&priv->mutex);
3609 rc = iwl_send_statistics_request(priv, 0);
3610 mutex_unlock(&priv->mutex);
3611
3612 if (rc) {
3613 len = sprintf(buf,
3614 "Error sending statistics request: 0x%08X\n", rc);
3615 return len;
3616 }
3617
3618 while (size && (PAGE_SIZE - len)) {
3619 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3620 PAGE_SIZE - len, 1);
3621 len = strlen(buf);
3622 if (PAGE_SIZE - len)
3623 buf[len++] = '\n';
3624
3625 ofs += 16;
3626 size -= min(size, 16U);
3627 }
3628
3629 return len;
3630}
3631
3632static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3633
3634static ssize_t show_antenna(struct device *d,
3635 struct device_attribute *attr, char *buf)
3636{
3637 struct iwl_priv *priv = dev_get_drvdata(d);
3638
3639 if (!iwl_is_alive(priv))
3640 return -EAGAIN;
3641
3642 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
3643}
3644
3645static ssize_t store_antenna(struct device *d,
3646 struct device_attribute *attr,
3647 const char *buf, size_t count)
3648{
3649 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
3650 int ant;
3651
3652 if (count == 0)
3653 return 0;
3654
3655 if (sscanf(buf, "%1i", &ant) != 1) {
3656 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
3657 return count;
3658 }
3659
3660 if ((ant >= 0) && (ant <= 2)) {
3661 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
3662 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
3663 } else
3664 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
3665
3666
3667 return count;
3668}
3669
3670static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3671
3672static ssize_t show_status(struct device *d,
3673 struct device_attribute *attr, char *buf)
3674{
3675 struct iwl_priv *priv = dev_get_drvdata(d);
3676 if (!iwl_is_alive(priv))
3677 return -EAGAIN;
3678 return sprintf(buf, "0x%08x\n", (int)priv->status);
3679}
3680
3681static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3682
3683static ssize_t dump_error_log(struct device *d,
3684 struct device_attribute *attr,
3685 const char *buf, size_t count)
3686{
3687 struct iwl_priv *priv = dev_get_drvdata(d);
3688 char *p = (char *)buf;
3689
3690 if (p[0] == '1')
3691 iwl3945_dump_nic_error_log(priv);
3692
3693 return strnlen(buf, count);
3694}
3695
3696static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3697
3698
3699
3700
3701
3702
3703
3704static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
3705{
3706 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3707
3708 init_waitqueue_head(&priv->wait_command_queue);
3709
3710 INIT_WORK(&priv->up, iwl3945_bg_up);
3711 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3712 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
3713 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
3714 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3715 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
3716 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
3717 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3718 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3719 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3720 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
3721
3722 iwl3945_hw_setup_deferred_work(priv);
3723
3724 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3725 iwl3945_irq_tasklet, (unsigned long)priv);
3726}
3727
3728static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
3729{
3730 iwl3945_hw_cancel_deferred_work(priv);
3731
3732 cancel_delayed_work_sync(&priv->init_alive_start);
3733 cancel_delayed_work(&priv->scan_check);
3734 cancel_delayed_work(&priv->alive_start);
3735 cancel_work_sync(&priv->beacon_update);
3736}
3737
3738static struct attribute *iwl3945_sysfs_entries[] = {
3739 &dev_attr_antenna.attr,
3740 &dev_attr_channels.attr,
3741 &dev_attr_dump_errors.attr,
3742 &dev_attr_flags.attr,
3743 &dev_attr_filter_flags.attr,
3744#ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
3745 &dev_attr_measurement.attr,
3746#endif
3747 &dev_attr_retry_rate.attr,
3748 &dev_attr_statistics.attr,
3749 &dev_attr_status.attr,
3750 &dev_attr_temperature.attr,
3751 &dev_attr_tx_power.attr,
3752#ifdef CONFIG_IWLWIFI_DEBUG
3753 &dev_attr_debug_level.attr,
3754#endif
3755 NULL
3756};
3757
3758static struct attribute_group iwl3945_attribute_group = {
3759 .name = NULL,
3760 .attrs = iwl3945_sysfs_entries,
3761};
3762
3763static struct ieee80211_ops iwl3945_hw_ops = {
3764 .tx = iwl3945_mac_tx,
3765 .start = iwl3945_mac_start,
3766 .stop = iwl3945_mac_stop,
3767 .add_interface = iwl_mac_add_interface,
3768 .remove_interface = iwl_mac_remove_interface,
3769 .config = iwl_mac_config,
3770 .configure_filter = iwl_configure_filter,
3771 .set_key = iwl3945_mac_set_key,
3772 .get_tx_stats = iwl_mac_get_tx_stats,
3773 .conf_tx = iwl_mac_conf_tx,
3774 .reset_tsf = iwl_mac_reset_tsf,
3775 .bss_info_changed = iwl_bss_info_changed,
3776 .hw_scan = iwl_mac_hw_scan
3777};
3778
3779static int iwl3945_init_drv(struct iwl_priv *priv)
3780{
3781 int ret;
3782 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
3783
3784 priv->retry_rate = 1;
3785 priv->ibss_beacon = NULL;
3786
3787 spin_lock_init(&priv->lock);
3788 spin_lock_init(&priv->sta_lock);
3789 spin_lock_init(&priv->hcmd_lock);
3790
3791 INIT_LIST_HEAD(&priv->free_frames);
3792
3793 mutex_init(&priv->mutex);
3794
3795
3796 iwl_clear_stations_table(priv);
3797
3798 priv->data_retry_limit = -1;
3799 priv->ieee_channels = NULL;
3800 priv->ieee_rates = NULL;
3801 priv->band = IEEE80211_BAND_2GHZ;
3802
3803 priv->iw_mode = NL80211_IFTYPE_STATION;
3804
3805 iwl_reset_qos(priv);
3806
3807 priv->qos_data.qos_active = 0;
3808 priv->qos_data.qos_cap.val = 0;
3809
3810 priv->rates_mask = IWL_RATES_MASK;
3811 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
3812
3813 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3814 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3815 eeprom->version);
3816 ret = -EINVAL;
3817 goto err;
3818 }
3819 ret = iwl_init_channel_map(priv);
3820 if (ret) {
3821 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3822 goto err;
3823 }
3824
3825
3826 if (iwl3945_txpower_set_from_eeprom(priv)) {
3827 ret = -EIO;
3828 goto err_free_channel_map;
3829 }
3830
3831 ret = iwlcore_init_geos(priv);
3832 if (ret) {
3833 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3834 goto err_free_channel_map;
3835 }
3836 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3837
3838 return 0;
3839
3840err_free_channel_map:
3841 iwl_free_channel_map(priv);
3842err:
3843 return ret;
3844}
3845
3846static int iwl3945_setup_mac(struct iwl_priv *priv)
3847{
3848 int ret;
3849 struct ieee80211_hw *hw = priv->hw;
3850
3851 hw->rate_control_algorithm = "iwl-3945-rs";
3852 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3853
3854
3855 hw->flags = IEEE80211_HW_SIGNAL_DBM |
3856 IEEE80211_HW_NOISE_DBM |
3857 IEEE80211_HW_SPECTRUM_MGMT |
3858 IEEE80211_HW_SUPPORTS_PS |
3859 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3860
3861 hw->wiphy->interface_modes =
3862 BIT(NL80211_IFTYPE_STATION) |
3863 BIT(NL80211_IFTYPE_ADHOC);
3864
3865 hw->wiphy->custom_regulatory = true;
3866
3867
3868 hw->wiphy->disable_beacon_hints = true;
3869
3870 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3871
3872 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
3873
3874
3875 hw->queues = 4;
3876
3877 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3878 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3879 &priv->bands[IEEE80211_BAND_2GHZ];
3880
3881 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3882 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3883 &priv->bands[IEEE80211_BAND_5GHZ];
3884
3885 ret = ieee80211_register_hw(priv->hw);
3886 if (ret) {
3887 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3888 return ret;
3889 }
3890 priv->mac80211_registered = 1;
3891
3892 return 0;
3893}
3894
3895static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3896{
3897 int err = 0;
3898 struct iwl_priv *priv;
3899 struct ieee80211_hw *hw;
3900 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3901 struct iwl3945_eeprom *eeprom;
3902 unsigned long flags;
3903
3904
3905
3906
3907
3908
3909
3910 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
3911 if (hw == NULL) {
3912 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
3913 err = -ENOMEM;
3914 goto out;
3915 }
3916 priv = hw->priv;
3917 SET_IEEE80211_DEV(hw, &pdev->dev);
3918
3919
3920
3921
3922
3923 if (iwl3945_mod_params.disable_hw_scan) {
3924 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
3925 iwl3945_hw_ops.hw_scan = NULL;
3926 }
3927
3928
3929 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3930 priv->cfg = cfg;
3931 priv->pci_dev = pdev;
3932 priv->inta_mask = CSR_INI_SET_MASK;
3933
3934#ifdef CONFIG_IWLWIFI_DEBUG
3935 atomic_set(&priv->restrict_refcnt, 0);
3936#endif
3937 if (iwl_alloc_traffic_mem(priv))
3938 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3939
3940
3941
3942
3943 if (pci_enable_device(pdev)) {
3944 err = -ENODEV;
3945 goto out_ieee80211_free_hw;
3946 }
3947
3948 pci_set_master(pdev);
3949
3950 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3951 if (!err)
3952 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3953 if (err) {
3954 IWL_WARN(priv, "No suitable DMA available.\n");
3955 goto out_pci_disable_device;
3956 }
3957
3958 pci_set_drvdata(pdev, priv);
3959 err = pci_request_regions(pdev, DRV_NAME);
3960 if (err)
3961 goto out_pci_disable_device;
3962
3963
3964
3965
3966 priv->hw_base = pci_iomap(pdev, 0, 0);
3967 if (!priv->hw_base) {
3968 err = -ENODEV;
3969 goto out_pci_release_regions;
3970 }
3971
3972 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3973 (unsigned long long) pci_resource_len(pdev, 0));
3974 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3975
3976
3977
3978 pci_write_config_byte(pdev, 0x41, 0x00);
3979
3980
3981
3982
3983 spin_lock_init(&priv->reg_lock);
3984
3985
3986 err = priv->cfg->ops->lib->apm_ops.init(priv);
3987 if (err < 0) {
3988 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
3989 goto out_iounmap;
3990 }
3991
3992
3993
3994
3995
3996
3997 err = iwl_eeprom_init(priv);
3998 if (err) {
3999 IWL_ERR(priv, "Unable to init EEPROM\n");
4000 goto out_iounmap;
4001 }
4002
4003 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4004 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
4005 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
4006 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
4007
4008
4009
4010
4011
4012 if (iwl3945_hw_set_hw_params(priv)) {
4013 IWL_ERR(priv, "failed to set hw settings\n");
4014 goto out_eeprom_free;
4015 }
4016
4017
4018
4019
4020
4021 err = iwl3945_init_drv(priv);
4022 if (err) {
4023 IWL_ERR(priv, "initializing driver failed\n");
4024 goto out_unset_hw_params;
4025 }
4026
4027 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4028 priv->cfg->name);
4029
4030
4031
4032
4033
4034 spin_lock_irqsave(&priv->lock, flags);
4035 iwl_disable_interrupts(priv);
4036 spin_unlock_irqrestore(&priv->lock, flags);
4037
4038 pci_enable_msi(priv->pci_dev);
4039
4040 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4041 IRQF_SHARED, DRV_NAME, priv);
4042 if (err) {
4043 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4044 goto out_disable_msi;
4045 }
4046
4047 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
4048 if (err) {
4049 IWL_ERR(priv, "failed to create sysfs device attributes\n");
4050 goto out_release_irq;
4051 }
4052
4053 iwl_set_rxon_channel(priv,
4054 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
4055 iwl3945_setup_deferred_work(priv);
4056 iwl3945_setup_rx_handlers(priv);
4057
4058
4059
4060
4061
4062 iwl_enable_interrupts(priv);
4063
4064 err = iwl3945_setup_mac(priv);
4065 if (err)
4066 goto out_remove_sysfs;
4067
4068 err = iwl_dbgfs_register(priv, DRV_NAME);
4069 if (err)
4070 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4071
4072
4073 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4074 2 * HZ);
4075
4076 return 0;
4077
4078 out_remove_sysfs:
4079 destroy_workqueue(priv->workqueue);
4080 priv->workqueue = NULL;
4081 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
4082 out_release_irq:
4083 free_irq(priv->pci_dev->irq, priv);
4084 out_disable_msi:
4085 pci_disable_msi(priv->pci_dev);
4086 iwlcore_free_geos(priv);
4087 iwl_free_channel_map(priv);
4088 out_unset_hw_params:
4089 iwl3945_unset_hw_params(priv);
4090 out_eeprom_free:
4091 iwl_eeprom_free(priv);
4092 out_iounmap:
4093 pci_iounmap(pdev, priv->hw_base);
4094 out_pci_release_regions:
4095 pci_release_regions(pdev);
4096 out_pci_disable_device:
4097 pci_set_drvdata(pdev, NULL);
4098 pci_disable_device(pdev);
4099 out_ieee80211_free_hw:
4100 iwl_free_traffic_mem(priv);
4101 ieee80211_free_hw(priv->hw);
4102 out:
4103 return err;
4104}
4105
4106static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
4107{
4108 struct iwl_priv *priv = pci_get_drvdata(pdev);
4109 unsigned long flags;
4110
4111 if (!priv)
4112 return;
4113
4114 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4115
4116 iwl_dbgfs_unregister(priv);
4117
4118 set_bit(STATUS_EXIT_PENDING, &priv->status);
4119
4120 if (priv->mac80211_registered) {
4121 ieee80211_unregister_hw(priv->hw);
4122 priv->mac80211_registered = 0;
4123 } else {
4124 iwl3945_down(priv);
4125 }
4126
4127
4128
4129
4130 spin_lock_irqsave(&priv->lock, flags);
4131 iwl_disable_interrupts(priv);
4132 spin_unlock_irqrestore(&priv->lock, flags);
4133
4134 iwl_synchronize_irq(priv);
4135
4136 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
4137
4138 cancel_delayed_work_sync(&priv->rfkill_poll);
4139
4140 iwl3945_dealloc_ucode_pci(priv);
4141
4142 if (priv->rxq.bd)
4143 iwl3945_rx_queue_free(priv, &priv->rxq);
4144 iwl3945_hw_txq_ctx_free(priv);
4145
4146 iwl3945_unset_hw_params(priv);
4147 iwl_clear_stations_table(priv);
4148
4149
4150 flush_workqueue(priv->workqueue);
4151
4152
4153
4154
4155 destroy_workqueue(priv->workqueue);
4156 priv->workqueue = NULL;
4157 iwl_free_traffic_mem(priv);
4158
4159 free_irq(pdev->irq, priv);
4160 pci_disable_msi(pdev);
4161
4162 pci_iounmap(pdev, priv->hw_base);
4163 pci_release_regions(pdev);
4164 pci_disable_device(pdev);
4165 pci_set_drvdata(pdev, NULL);
4166
4167 iwl_free_channel_map(priv);
4168 iwlcore_free_geos(priv);
4169 kfree(priv->scan);
4170 if (priv->ibss_beacon)
4171 dev_kfree_skb(priv->ibss_beacon);
4172
4173 ieee80211_free_hw(priv->hw);
4174}
4175
4176
4177
4178
4179
4180
4181
4182
4183static struct pci_driver iwl3945_driver = {
4184 .name = DRV_NAME,
4185 .id_table = iwl3945_hw_card_ids,
4186 .probe = iwl3945_pci_probe,
4187 .remove = __devexit_p(iwl3945_pci_remove),
4188#ifdef CONFIG_PM
4189 .suspend = iwl_pci_suspend,
4190 .resume = iwl_pci_resume,
4191#endif
4192};
4193
4194static int __init iwl3945_init(void)
4195{
4196
4197 int ret;
4198 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4199 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
4200
4201 ret = iwl3945_rate_control_register();
4202 if (ret) {
4203 printk(KERN_ERR DRV_NAME
4204 "Unable to register rate control algorithm: %d\n", ret);
4205 return ret;
4206 }
4207
4208 ret = pci_register_driver(&iwl3945_driver);
4209 if (ret) {
4210 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
4211 goto error_register;
4212 }
4213
4214 return ret;
4215
4216error_register:
4217 iwl3945_rate_control_unregister();
4218 return ret;
4219}
4220
4221static void __exit iwl3945_exit(void)
4222{
4223 pci_unregister_driver(&iwl3945_driver);
4224 iwl3945_rate_control_unregister();
4225}
4226
4227MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
4228
4229module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
4230MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4231module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
4232MODULE_PARM_DESC(swcrypto,
4233 "using software crypto (default 1 [software])\n");
4234#ifdef CONFIG_IWLWIFI_DEBUG
4235module_param_named(debug, iwl_debug_level, uint, 0644);
4236MODULE_PARM_DESC(debug, "debug output mask");
4237#endif
4238module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
4239MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4240module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, 0444);
4241MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4242
4243module_exit(iwl3945_exit);
4244module_init(iwl3945_init);
4245