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12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/completion.h>
20#include <linux/etherdevice.h>
21#include <net/mac80211.h>
22#include <linux/moduleparam.h>
23#include <linux/firmware.h>
24#include <linux/workqueue.h>
25
26#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
27#define MWL8K_NAME KBUILD_MODNAME
28#define MWL8K_VERSION "0.10"
29
30MODULE_DESCRIPTION(MWL8K_DESC);
31MODULE_VERSION(MWL8K_VERSION);
32MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
33MODULE_LICENSE("GPL");
34
35static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
36 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
37 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
38 { }
39};
40MODULE_DEVICE_TABLE(pci, mwl8k_table);
41
42
43#define MWL8K_HIU_GEN_PTR 0x00000c10
44#define MWL8K_MODE_STA 0x0000005a
45#define MWL8K_MODE_AP 0x000000a5
46#define MWL8K_HIU_INT_CODE 0x00000c14
47#define MWL8K_FWSTA_READY 0xf0f1f2f4
48#define MWL8K_FWAP_READY 0xf1f2f4a5
49#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
50#define MWL8K_HIU_SCRATCH 0x00000c40
51
52
53#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
54#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
55#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
56#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
57#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
58#define MWL8K_H2A_INT_DUMMY (1 << 20)
59#define MWL8K_H2A_INT_RESET (1 << 15)
60#define MWL8K_H2A_INT_DOORBELL (1 << 1)
61#define MWL8K_H2A_INT_PPA_READY (1 << 0)
62
63
64#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
65#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
66#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
67#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
68#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
69#define MWL8K_A2H_INT_DUMMY (1 << 20)
70#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
71#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
72#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
73#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
74#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
75#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
76#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
77#define MWL8K_A2H_INT_RX_READY (1 << 1)
78#define MWL8K_A2H_INT_TX_DONE (1 << 0)
79
80#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
81 MWL8K_A2H_INT_CHNL_SWITCHED | \
82 MWL8K_A2H_INT_QUEUE_EMPTY | \
83 MWL8K_A2H_INT_RADAR_DETECT | \
84 MWL8K_A2H_INT_RADIO_ON | \
85 MWL8K_A2H_INT_RADIO_OFF | \
86 MWL8K_A2H_INT_MAC_EVENT | \
87 MWL8K_A2H_INT_OPC_DONE | \
88 MWL8K_A2H_INT_RX_READY | \
89 MWL8K_A2H_INT_TX_DONE)
90
91
92#define WME_AC_BE 0
93#define WME_AC_BK 1
94#define WME_AC_VI 2
95#define WME_AC_VO 3
96
97#define MWL8K_RX_QUEUES 1
98#define MWL8K_TX_QUEUES 4
99
100struct mwl8k_rx_queue {
101 int rx_desc_count;
102
103
104 int rx_head;
105
106
107 int rx_tail;
108
109 struct mwl8k_rx_desc *rx_desc_area;
110 dma_addr_t rx_desc_dma;
111 struct sk_buff **rx_skb;
112};
113
114struct mwl8k_tx_queue {
115
116 int tx_head;
117
118
119 int tx_tail;
120
121 struct ieee80211_tx_queue_stats tx_stats;
122 struct mwl8k_tx_desc *tx_desc_area;
123 dma_addr_t tx_desc_dma;
124 struct sk_buff **tx_skb;
125};
126
127
128struct mwl8k_firmware {
129
130 struct firmware *ucode;
131
132
133 struct firmware *helper;
134};
135
136struct mwl8k_priv {
137 void __iomem *regs;
138 struct ieee80211_hw *hw;
139
140 struct pci_dev *pdev;
141 u8 name[16];
142
143
144 struct mwl8k_firmware fw;
145 u32 part_num;
146
147
148 struct mutex fw_mutex;
149 struct task_struct *fw_mutex_owner;
150 int fw_mutex_depth;
151 struct completion *tx_wait;
152 struct completion *hostcmd_wait;
153
154
155 spinlock_t tx_lock;
156
157 struct ieee80211_vif *vif;
158
159 struct ieee80211_channel *current_channel;
160
161
162 u32 *cookie;
163 dma_addr_t cookie_dma;
164
165 u16 num_mcaddrs;
166 u8 hw_rev;
167 u32 fw_rev;
168
169
170
171
172
173 int pending_tx_pkts;
174
175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
177
178
179 struct ieee80211_supported_band band;
180 struct ieee80211_channel channels[14];
181 struct ieee80211_rate rates[12];
182
183 bool radio_on;
184 bool radio_short_preamble;
185 bool wmm_enabled;
186
187
188 bool capture_beacon;
189 u8 capture_bssid[ETH_ALEN];
190 struct sk_buff *beacon_skb;
191
192
193
194
195
196
197
198 struct work_struct finalize_join_worker;
199
200
201 struct tasklet_struct tx_reclaim_task;
202
203
204 struct workqueue_struct *config_wq;
205};
206
207
208struct mwl8k_vif {
209
210 struct mwl8k_priv *priv;
211
212
213 struct ieee80211_bss_conf bss_info;
214
215
216 u8 bssid[ETH_ALEN];
217 u8 mac_addr[ETH_ALEN];
218
219
220
221
222
223 struct ieee80211_rate legacy_rates[12];
224
225
226 u8 legacy_nrates;
227
228
229 u8 peer_id;
230
231
232 u16 seqno;
233};
234
235#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
236
237static const struct ieee80211_channel mwl8k_channels[] = {
238 { .center_freq = 2412, .hw_value = 1, },
239 { .center_freq = 2417, .hw_value = 2, },
240 { .center_freq = 2422, .hw_value = 3, },
241 { .center_freq = 2427, .hw_value = 4, },
242 { .center_freq = 2432, .hw_value = 5, },
243 { .center_freq = 2437, .hw_value = 6, },
244 { .center_freq = 2442, .hw_value = 7, },
245 { .center_freq = 2447, .hw_value = 8, },
246 { .center_freq = 2452, .hw_value = 9, },
247 { .center_freq = 2457, .hw_value = 10, },
248 { .center_freq = 2462, .hw_value = 11, },
249};
250
251static const struct ieee80211_rate mwl8k_rates[] = {
252 { .bitrate = 10, .hw_value = 2, },
253 { .bitrate = 20, .hw_value = 4, },
254 { .bitrate = 55, .hw_value = 11, },
255 { .bitrate = 60, .hw_value = 12, },
256 { .bitrate = 90, .hw_value = 18, },
257 { .bitrate = 110, .hw_value = 22, },
258 { .bitrate = 120, .hw_value = 24, },
259 { .bitrate = 180, .hw_value = 36, },
260 { .bitrate = 240, .hw_value = 48, },
261 { .bitrate = 360, .hw_value = 72, },
262 { .bitrate = 480, .hw_value = 96, },
263 { .bitrate = 540, .hw_value = 108, },
264};
265
266
267#define MWL8K_CMD_SET 0x0001
268#define MWL8K_CMD_GET 0x0000
269
270
271#define MWL8K_CMD_CODE_DNLD 0x0001
272#define MWL8K_CMD_GET_HW_SPEC 0x0003
273#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
274#define MWL8K_CMD_GET_STAT 0x0014
275#define MWL8K_CMD_RADIO_CONTROL 0x001c
276#define MWL8K_CMD_RF_TX_POWER 0x001e
277#define MWL8K_CMD_SET_PRE_SCAN 0x0107
278#define MWL8K_CMD_SET_POST_SCAN 0x0108
279#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
280#define MWL8K_CMD_SET_AID 0x010d
281#define MWL8K_CMD_SET_RATE 0x0110
282#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
283#define MWL8K_CMD_RTS_THRESHOLD 0x0113
284#define MWL8K_CMD_SET_SLOT 0x0114
285#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
286#define MWL8K_CMD_SET_WMM_MODE 0x0123
287#define MWL8K_CMD_MIMO_CONFIG 0x0125
288#define MWL8K_CMD_USE_FIXED_RATE 0x0126
289#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
290#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
291#define MWL8K_CMD_UPDATE_STADB 0x1123
292
293static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
294{
295#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
296 snprintf(buf, bufsize, "%s", #x);\
297 return buf;\
298 } while (0)
299 switch (cmd & ~0x8000) {
300 MWL8K_CMDNAME(CODE_DNLD);
301 MWL8K_CMDNAME(GET_HW_SPEC);
302 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
303 MWL8K_CMDNAME(GET_STAT);
304 MWL8K_CMDNAME(RADIO_CONTROL);
305 MWL8K_CMDNAME(RF_TX_POWER);
306 MWL8K_CMDNAME(SET_PRE_SCAN);
307 MWL8K_CMDNAME(SET_POST_SCAN);
308 MWL8K_CMDNAME(SET_RF_CHANNEL);
309 MWL8K_CMDNAME(SET_AID);
310 MWL8K_CMDNAME(SET_RATE);
311 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
312 MWL8K_CMDNAME(RTS_THRESHOLD);
313 MWL8K_CMDNAME(SET_SLOT);
314 MWL8K_CMDNAME(SET_EDCA_PARAMS);
315 MWL8K_CMDNAME(SET_WMM_MODE);
316 MWL8K_CMDNAME(MIMO_CONFIG);
317 MWL8K_CMDNAME(USE_FIXED_RATE);
318 MWL8K_CMDNAME(ENABLE_SNIFFER);
319 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
320 MWL8K_CMDNAME(UPDATE_STADB);
321 default:
322 snprintf(buf, bufsize, "0x%x", cmd);
323 }
324#undef MWL8K_CMDNAME
325
326 return buf;
327}
328
329
330static void mwl8k_hw_reset(struct mwl8k_priv *priv)
331{
332 iowrite32(MWL8K_H2A_INT_RESET,
333 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
334 iowrite32(MWL8K_H2A_INT_RESET,
335 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
336 msleep(20);
337}
338
339
340static void mwl8k_release_fw(struct firmware **fw)
341{
342 if (*fw == NULL)
343 return;
344 release_firmware(*fw);
345 *fw = NULL;
346}
347
348static void mwl8k_release_firmware(struct mwl8k_priv *priv)
349{
350 mwl8k_release_fw(&priv->fw.ucode);
351 mwl8k_release_fw(&priv->fw.helper);
352}
353
354
355static int mwl8k_request_fw(struct mwl8k_priv *priv,
356 const char *fname, struct firmware **fw)
357{
358
359 if (*fw != NULL)
360 mwl8k_release_fw(fw);
361
362 return request_firmware((const struct firmware **)fw,
363 fname, &priv->pdev->dev);
364}
365
366static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
367{
368 u8 filename[64];
369 int rc;
370
371 priv->part_num = part_num;
372
373 snprintf(filename, sizeof(filename),
374 "mwl8k/helper_%u.fw", priv->part_num);
375
376 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
377 if (rc) {
378 printk(KERN_ERR
379 "%s Error requesting helper firmware file %s\n",
380 pci_name(priv->pdev), filename);
381 return rc;
382 }
383
384 snprintf(filename, sizeof(filename),
385 "mwl8k/fmimage_%u.fw", priv->part_num);
386
387 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
388 if (rc) {
389 printk(KERN_ERR "%s Error requesting firmware file %s\n",
390 pci_name(priv->pdev), filename);
391 mwl8k_release_fw(&priv->fw.helper);
392 return rc;
393 }
394
395 return 0;
396}
397
398struct mwl8k_cmd_pkt {
399 __le16 code;
400 __le16 length;
401 __le16 seq_num;
402 __le16 result;
403 char payload[0];
404} __attribute__((packed));
405
406
407
408
409static int
410mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
411{
412 void __iomem *regs = priv->regs;
413 dma_addr_t dma_addr;
414 int loops;
415
416 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
417 if (pci_dma_mapping_error(priv->pdev, dma_addr))
418 return -ENOMEM;
419
420 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
421 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
422 iowrite32(MWL8K_H2A_INT_DOORBELL,
423 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
424 iowrite32(MWL8K_H2A_INT_DUMMY,
425 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
426
427 loops = 1000;
428 do {
429 u32 int_code;
430
431 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
432 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
433 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
434 break;
435 }
436
437 udelay(1);
438 } while (--loops);
439
440 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
441
442 return loops ? 0 : -ETIMEDOUT;
443}
444
445static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
446 const u8 *data, size_t length)
447{
448 struct mwl8k_cmd_pkt *cmd;
449 int done;
450 int rc = 0;
451
452 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
453 if (cmd == NULL)
454 return -ENOMEM;
455
456 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
457 cmd->seq_num = 0;
458 cmd->result = 0;
459
460 done = 0;
461 while (length) {
462 int block_size = length > 256 ? 256 : length;
463
464 memcpy(cmd->payload, data + done, block_size);
465 cmd->length = cpu_to_le16(block_size);
466
467 rc = mwl8k_send_fw_load_cmd(priv, cmd,
468 sizeof(*cmd) + block_size);
469 if (rc)
470 break;
471
472 done += block_size;
473 length -= block_size;
474 }
475
476 if (!rc) {
477 cmd->length = 0;
478 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
479 }
480
481 kfree(cmd);
482
483 return rc;
484}
485
486static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
487 const u8 *data, size_t length)
488{
489 unsigned char *buffer;
490 int may_continue, rc = 0;
491 u32 done, prev_block_size;
492
493 buffer = kmalloc(1024, GFP_KERNEL);
494 if (buffer == NULL)
495 return -ENOMEM;
496
497 done = 0;
498 prev_block_size = 0;
499 may_continue = 1000;
500 while (may_continue > 0) {
501 u32 block_size;
502
503 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
504 if (block_size & 1) {
505 block_size &= ~1;
506 may_continue--;
507 } else {
508 done += prev_block_size;
509 length -= prev_block_size;
510 }
511
512 if (block_size > 1024 || block_size > length) {
513 rc = -EOVERFLOW;
514 break;
515 }
516
517 if (length == 0) {
518 rc = 0;
519 break;
520 }
521
522 if (block_size == 0) {
523 rc = -EPROTO;
524 may_continue--;
525 udelay(1);
526 continue;
527 }
528
529 prev_block_size = block_size;
530 memcpy(buffer, data + done, block_size);
531
532 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
533 if (rc)
534 break;
535 }
536
537 if (!rc && length != 0)
538 rc = -EREMOTEIO;
539
540 kfree(buffer);
541
542 return rc;
543}
544
545static int mwl8k_load_firmware(struct mwl8k_priv *priv)
546{
547 int loops, rc;
548
549 const u8 *ucode = priv->fw.ucode->data;
550 size_t ucode_len = priv->fw.ucode->size;
551 const u8 *helper = priv->fw.helper->data;
552 size_t helper_len = priv->fw.helper->size;
553
554 if (!memcmp(ucode, "\x01\x00\x00\x00", 4)) {
555 rc = mwl8k_load_fw_image(priv, helper, helper_len);
556 if (rc) {
557 printk(KERN_ERR "%s: unable to load firmware "
558 "helper image\n", pci_name(priv->pdev));
559 return rc;
560 }
561 msleep(1);
562
563 rc = mwl8k_feed_fw_image(priv, ucode, ucode_len);
564 } else {
565 rc = mwl8k_load_fw_image(priv, ucode, ucode_len);
566 }
567
568 if (rc) {
569 printk(KERN_ERR "%s: unable to load firmware data\n",
570 pci_name(priv->pdev));
571 return rc;
572 }
573
574 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
575 msleep(1);
576
577 loops = 200000;
578 do {
579 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
580 == MWL8K_FWSTA_READY)
581 break;
582 udelay(1);
583 } while (--loops);
584
585 return loops ? 0 : -ETIMEDOUT;
586}
587
588
589
590
591
592
593struct ewc_ht_info {
594 __le16 control1;
595 __le16 control2;
596 __le16 control3;
597} __attribute__((packed));
598
599
600#define MWL8K_STA_DB_ADD_ENTRY 0
601#define MWL8K_STA_DB_MODIFY_ENTRY 1
602#define MWL8K_STA_DB_DEL_ENTRY 2
603#define MWL8K_STA_DB_FLUSH 3
604
605
606#define MWL8K_PEER_TYPE_ACCESSPOINT 2
607
608#define MWL8K_IEEE_LEGACY_DATA_RATES 12
609#define MWL8K_MCS_BITMAP_SIZE 16
610
611struct peer_capability_info {
612
613 __u8 peer_type;
614
615
616 __le16 basic_caps;
617
618
619 __u8 ht_support;
620
621
622 __le16 ht_caps;
623 __u8 extended_ht_caps;
624 struct ewc_ht_info ewc_info;
625
626
627 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
628
629
630 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
631 __u8 pad[16];
632
633
634 __u8 interop;
635 __u8 pad2;
636 __u8 station_id;
637 __le16 amsdu_enabled;
638} __attribute__((packed));
639
640
641static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
642{
643 u16 val_mask = 1 << 4;
644
645
646 return qos | val_mask;
647}
648
649static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
650{
651 u16 val_mask = 0x3;
652 u8 shift = 5;
653 u16 qos_mask = ~(val_mask << shift);
654
655
656 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
657}
658
659static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
660{
661 u16 val_mask = 1 << 7;
662
663
664 return qos | val_mask;
665}
666
667static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
668{
669 u16 val_mask = 0xff;
670 u8 shift = 8;
671 u16 qos_mask = ~(val_mask << shift);
672
673
674 return (qos & qos_mask) | ((len & val_mask) << shift);
675}
676
677
678struct mwl8k_dma_data {
679 __le16 fwlen;
680 struct ieee80211_hdr wh;
681} __attribute__((packed));
682
683
684static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
685{
686 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
687 void *dst, *src = &tr->wh;
688 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
689 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
690
691 dst = (void *)tr + space;
692 if (dst != src) {
693 memmove(dst, src, hdrlen);
694 skb_pull(skb, space);
695 }
696}
697
698static inline void mwl8k_add_dma_header(struct sk_buff *skb)
699{
700 struct ieee80211_hdr *wh;
701 u32 hdrlen, pktlen;
702 struct mwl8k_dma_data *tr;
703
704 wh = (struct ieee80211_hdr *)skb->data;
705 hdrlen = ieee80211_hdrlen(wh->frame_control);
706 pktlen = skb->len;
707
708
709
710
711
712
713
714 if (hdrlen != sizeof(struct mwl8k_dma_data))
715 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
716
717 tr = (struct mwl8k_dma_data *)skb->data;
718 if (wh != &tr->wh)
719 memmove(&tr->wh, wh, hdrlen);
720
721
722 memset(tr->wh.addr4, 0, ETH_ALEN);
723
724
725
726
727
728
729 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
730}
731
732
733
734
735
736#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
737
738struct mwl8k_rx_desc {
739 __le16 pkt_len;
740 __u8 link_quality;
741 __u8 noise_level;
742 __le32 pkt_phys_addr;
743 __le32 next_rx_desc_phys_addr;
744 __le16 qos_control;
745 __le16 rate_info;
746 __le32 pad0[4];
747 __u8 rssi;
748 __u8 channel;
749 __le16 pad1;
750 __u8 rx_ctrl;
751 __u8 rx_status;
752 __u8 pad2[2];
753} __attribute__((packed));
754
755#define MWL8K_RX_DESCS 256
756#define MWL8K_RX_MAXSZ 3800
757
758static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
759{
760 struct mwl8k_priv *priv = hw->priv;
761 struct mwl8k_rx_queue *rxq = priv->rxq + index;
762 int size;
763 int i;
764
765 rxq->rx_desc_count = 0;
766 rxq->rx_head = 0;
767 rxq->rx_tail = 0;
768
769 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
770
771 rxq->rx_desc_area =
772 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
773 if (rxq->rx_desc_area == NULL) {
774 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
775 priv->name);
776 return -ENOMEM;
777 }
778 memset(rxq->rx_desc_area, 0, size);
779
780 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
781 sizeof(*rxq->rx_skb), GFP_KERNEL);
782 if (rxq->rx_skb == NULL) {
783 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
784 priv->name);
785 pci_free_consistent(priv->pdev, size,
786 rxq->rx_desc_area, rxq->rx_desc_dma);
787 return -ENOMEM;
788 }
789 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
790
791 for (i = 0; i < MWL8K_RX_DESCS; i++) {
792 struct mwl8k_rx_desc *rx_desc;
793 int nexti;
794
795 rx_desc = rxq->rx_desc_area + i;
796 nexti = (i + 1) % MWL8K_RX_DESCS;
797
798 rx_desc->next_rx_desc_phys_addr =
799 cpu_to_le32(rxq->rx_desc_dma
800 + nexti * sizeof(*rx_desc));
801 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
802 }
803
804 return 0;
805}
806
807static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
808{
809 struct mwl8k_priv *priv = hw->priv;
810 struct mwl8k_rx_queue *rxq = priv->rxq + index;
811 int refilled;
812
813 refilled = 0;
814 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
815 struct sk_buff *skb;
816 int rx;
817
818 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
819 if (skb == NULL)
820 break;
821
822 rxq->rx_desc_count++;
823
824 rx = rxq->rx_tail;
825 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
826
827 rxq->rx_desc_area[rx].pkt_phys_addr =
828 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
829 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
830
831 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
832 rxq->rx_skb[rx] = skb;
833 wmb();
834 rxq->rx_desc_area[rx].rx_ctrl = 0;
835
836 refilled++;
837 }
838
839 return refilled;
840}
841
842
843static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
844{
845 struct mwl8k_priv *priv = hw->priv;
846 struct mwl8k_rx_queue *rxq = priv->rxq + index;
847 int i;
848
849 for (i = 0; i < MWL8K_RX_DESCS; i++) {
850 if (rxq->rx_skb[i] != NULL) {
851 unsigned long addr;
852
853 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
854 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
855 PCI_DMA_FROMDEVICE);
856 kfree_skb(rxq->rx_skb[i]);
857 rxq->rx_skb[i] = NULL;
858 }
859 }
860
861 kfree(rxq->rx_skb);
862 rxq->rx_skb = NULL;
863
864 pci_free_consistent(priv->pdev,
865 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
866 rxq->rx_desc_area, rxq->rx_desc_dma);
867 rxq->rx_desc_area = NULL;
868}
869
870
871
872
873
874
875static inline int
876mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
877{
878 return priv->capture_beacon &&
879 ieee80211_is_beacon(wh->frame_control) &&
880 !compare_ether_addr(wh->addr3, priv->capture_bssid);
881}
882
883static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
884 struct sk_buff *skb)
885{
886 priv->capture_beacon = false;
887 memset(priv->capture_bssid, 0, ETH_ALEN);
888
889
890
891
892
893
894 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
895 if (priv->beacon_skb != NULL)
896 queue_work(priv->config_wq,
897 &priv->finalize_join_worker);
898}
899
900static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
901{
902 struct mwl8k_priv *priv = hw->priv;
903 struct mwl8k_rx_queue *rxq = priv->rxq + index;
904 int processed;
905
906 processed = 0;
907 while (rxq->rx_desc_count && limit--) {
908 struct mwl8k_rx_desc *rx_desc;
909 struct sk_buff *skb;
910 struct ieee80211_rx_status status;
911 unsigned long addr;
912 struct ieee80211_hdr *wh;
913
914 rx_desc = rxq->rx_desc_area + rxq->rx_head;
915 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
916 break;
917 rmb();
918
919 skb = rxq->rx_skb[rxq->rx_head];
920 if (skb == NULL)
921 break;
922 rxq->rx_skb[rxq->rx_head] = NULL;
923
924 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
925 rxq->rx_desc_count--;
926
927 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
928 pci_unmap_single(priv->pdev, addr,
929 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
930
931 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
932 mwl8k_remove_dma_header(skb);
933
934 wh = (struct ieee80211_hdr *)skb->data;
935
936
937
938
939
940
941 if (mwl8k_capture_bssid(priv, wh))
942 mwl8k_save_beacon(priv, skb);
943
944 memset(&status, 0, sizeof(status));
945 status.mactime = 0;
946 status.signal = -rx_desc->rssi;
947 status.noise = -rx_desc->noise_level;
948 status.qual = rx_desc->link_quality;
949 status.antenna = 1;
950 status.rate_idx = 1;
951 status.flag = 0;
952 status.band = IEEE80211_BAND_2GHZ;
953 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
954 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
955 ieee80211_rx_irqsafe(hw, skb);
956
957 processed++;
958 }
959
960 return processed;
961}
962
963
964
965
966
967
968
969enum {
970 MWL8K_WME_AC_BK = 0,
971 MWL8K_WME_AC_BE = 1,
972 MWL8K_WME_AC_VI = 2,
973 MWL8K_WME_AC_VO = 3,
974};
975
976
977#define MWL8K_TXD_ACK_POLICY_NORMAL 0
978#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
979
980#define GET_TXQ(_ac) (\
981 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
982 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
983 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
984 MWL8K_WME_AC_BE)
985
986#define MWL8K_TXD_STATUS_OK 0x00000001
987#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
988#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
989#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
990#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
991
992struct mwl8k_tx_desc {
993 __le32 status;
994 __u8 data_rate;
995 __u8 tx_priority;
996 __le16 qos_control;
997 __le32 pkt_phys_addr;
998 __le16 pkt_len;
999 __u8 dest_MAC_addr[ETH_ALEN];
1000 __le32 next_tx_desc_phys_addr;
1001 __le32 reserved;
1002 __le16 rate_info;
1003 __u8 peer_id;
1004 __u8 tx_frag_cnt;
1005} __attribute__((packed));
1006
1007#define MWL8K_TX_DESCS 128
1008
1009static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1010{
1011 struct mwl8k_priv *priv = hw->priv;
1012 struct mwl8k_tx_queue *txq = priv->txq + index;
1013 int size;
1014 int i;
1015
1016 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1017 txq->tx_stats.limit = MWL8K_TX_DESCS;
1018 txq->tx_head = 0;
1019 txq->tx_tail = 0;
1020
1021 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1022
1023 txq->tx_desc_area =
1024 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1025 if (txq->tx_desc_area == NULL) {
1026 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1027 priv->name);
1028 return -ENOMEM;
1029 }
1030 memset(txq->tx_desc_area, 0, size);
1031
1032 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1033 GFP_KERNEL);
1034 if (txq->tx_skb == NULL) {
1035 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1036 priv->name);
1037 pci_free_consistent(priv->pdev, size,
1038 txq->tx_desc_area, txq->tx_desc_dma);
1039 return -ENOMEM;
1040 }
1041 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1042
1043 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1044 struct mwl8k_tx_desc *tx_desc;
1045 int nexti;
1046
1047 tx_desc = txq->tx_desc_area + i;
1048 nexti = (i + 1) % MWL8K_TX_DESCS;
1049
1050 tx_desc->status = 0;
1051 tx_desc->next_tx_desc_phys_addr =
1052 cpu_to_le32(txq->tx_desc_dma +
1053 nexti * sizeof(*tx_desc));
1054 }
1055
1056 return 0;
1057}
1058
1059static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1060{
1061 iowrite32(MWL8K_H2A_INT_PPA_READY,
1062 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1063 iowrite32(MWL8K_H2A_INT_DUMMY,
1064 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1065 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1066}
1067
1068static inline int mwl8k_txq_busy(struct mwl8k_priv *priv)
1069{
1070 return priv->pending_tx_pkts;
1071}
1072
1073struct mwl8k_txq_info {
1074 u32 fw_owned;
1075 u32 drv_owned;
1076 u32 unused;
1077 u32 len;
1078 u32 head;
1079 u32 tail;
1080};
1081
1082static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1083 struct mwl8k_txq_info *txinfo)
1084{
1085 int count, desc, status;
1086 struct mwl8k_tx_queue *txq;
1087 struct mwl8k_tx_desc *tx_desc;
1088 int ndescs = 0;
1089
1090 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1091
1092 spin_lock_bh(&priv->tx_lock);
1093 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1094 txq = priv->txq + count;
1095 txinfo[count].len = txq->tx_stats.len;
1096 txinfo[count].head = txq->tx_head;
1097 txinfo[count].tail = txq->tx_tail;
1098 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1099 tx_desc = txq->tx_desc_area + desc;
1100 status = le32_to_cpu(tx_desc->status);
1101
1102 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1103 txinfo[count].fw_owned++;
1104 else
1105 txinfo[count].drv_owned++;
1106
1107 if (tx_desc->pkt_len == 0)
1108 txinfo[count].unused++;
1109 }
1110 }
1111 spin_unlock_bh(&priv->tx_lock);
1112
1113 return ndescs;
1114}
1115
1116
1117
1118
1119static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1120{
1121 struct mwl8k_priv *priv = hw->priv;
1122 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1123 u32 count;
1124 unsigned long timeout;
1125
1126 might_sleep();
1127
1128 spin_lock_bh(&priv->tx_lock);
1129 count = mwl8k_txq_busy(priv);
1130 if (count) {
1131 priv->tx_wait = &cmd_wait;
1132 if (priv->radio_on)
1133 mwl8k_tx_start(priv);
1134 }
1135 spin_unlock_bh(&priv->tx_lock);
1136
1137 if (count) {
1138 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1139 int index;
1140 int newcount;
1141
1142 timeout = wait_for_completion_timeout(&cmd_wait,
1143 msecs_to_jiffies(5000));
1144 if (timeout)
1145 return 0;
1146
1147 spin_lock_bh(&priv->tx_lock);
1148 priv->tx_wait = NULL;
1149 newcount = mwl8k_txq_busy(priv);
1150 spin_unlock_bh(&priv->tx_lock);
1151
1152 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1153 __func__, __LINE__, count, newcount);
1154
1155 mwl8k_scan_tx_ring(priv, txinfo);
1156 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1157 printk(KERN_ERR
1158 "TXQ:%u L:%u H:%u T:%u FW:%u DRV:%u U:%u\n",
1159 index,
1160 txinfo[index].len,
1161 txinfo[index].head,
1162 txinfo[index].tail,
1163 txinfo[index].fw_owned,
1164 txinfo[index].drv_owned,
1165 txinfo[index].unused);
1166
1167 return -ETIMEDOUT;
1168 }
1169
1170 return 0;
1171}
1172
1173#define MWL8K_TXD_SUCCESS(status) \
1174 ((status) & (MWL8K_TXD_STATUS_OK | \
1175 MWL8K_TXD_STATUS_OK_RETRY | \
1176 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1177
1178static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1179{
1180 struct mwl8k_priv *priv = hw->priv;
1181 struct mwl8k_tx_queue *txq = priv->txq + index;
1182 int wake = 0;
1183
1184 while (txq->tx_stats.len > 0) {
1185 int tx;
1186 struct mwl8k_tx_desc *tx_desc;
1187 unsigned long addr;
1188 int size;
1189 struct sk_buff *skb;
1190 struct ieee80211_tx_info *info;
1191 u32 status;
1192
1193 tx = txq->tx_head;
1194 tx_desc = txq->tx_desc_area + tx;
1195
1196 status = le32_to_cpu(tx_desc->status);
1197
1198 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1199 if (!force)
1200 break;
1201 tx_desc->status &=
1202 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1203 }
1204
1205 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1206 BUG_ON(txq->tx_stats.len == 0);
1207 txq->tx_stats.len--;
1208 priv->pending_tx_pkts--;
1209
1210 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1211 size = le16_to_cpu(tx_desc->pkt_len);
1212 skb = txq->tx_skb[tx];
1213 txq->tx_skb[tx] = NULL;
1214
1215 BUG_ON(skb == NULL);
1216 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1217
1218 mwl8k_remove_dma_header(skb);
1219
1220
1221 tx_desc->pkt_phys_addr = 0;
1222 tx_desc->pkt_len = 0;
1223
1224 info = IEEE80211_SKB_CB(skb);
1225 ieee80211_tx_info_clear_status(info);
1226 if (MWL8K_TXD_SUCCESS(status))
1227 info->flags |= IEEE80211_TX_STAT_ACK;
1228
1229 ieee80211_tx_status_irqsafe(hw, skb);
1230
1231 wake = 1;
1232 }
1233
1234 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1235 ieee80211_wake_queue(hw, index);
1236}
1237
1238
1239static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1240{
1241 struct mwl8k_priv *priv = hw->priv;
1242 struct mwl8k_tx_queue *txq = priv->txq + index;
1243
1244 mwl8k_txq_reclaim(hw, index, 1);
1245
1246 kfree(txq->tx_skb);
1247 txq->tx_skb = NULL;
1248
1249 pci_free_consistent(priv->pdev,
1250 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1251 txq->tx_desc_area, txq->tx_desc_dma);
1252 txq->tx_desc_area = NULL;
1253}
1254
1255static int
1256mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1257{
1258 struct mwl8k_priv *priv = hw->priv;
1259 struct ieee80211_tx_info *tx_info;
1260 struct mwl8k_vif *mwl8k_vif;
1261 struct ieee80211_hdr *wh;
1262 struct mwl8k_tx_queue *txq;
1263 struct mwl8k_tx_desc *tx;
1264 dma_addr_t dma;
1265 u32 txstatus;
1266 u8 txdatarate;
1267 u16 qos;
1268
1269 wh = (struct ieee80211_hdr *)skb->data;
1270 if (ieee80211_is_data_qos(wh->frame_control))
1271 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1272 else
1273 qos = 0;
1274
1275 mwl8k_add_dma_header(skb);
1276 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1277
1278 tx_info = IEEE80211_SKB_CB(skb);
1279 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1280
1281 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1282 u16 seqno = mwl8k_vif->seqno;
1283
1284 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1285 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1286 mwl8k_vif->seqno = seqno++ % 4096;
1287 }
1288
1289
1290 txstatus = 0;
1291 txdatarate = 0;
1292 if (ieee80211_is_mgmt(wh->frame_control) ||
1293 ieee80211_is_ctl(wh->frame_control)) {
1294 txdatarate = 0;
1295 qos = mwl8k_qos_setbit_eosp(qos);
1296
1297 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1298 } else if (ieee80211_is_data(wh->frame_control)) {
1299 txdatarate = 1;
1300 if (is_multicast_ether_addr(wh->addr1))
1301 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1302
1303
1304 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1305 qos = mwl8k_qos_setbit_ack(qos,
1306 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1307 else
1308 qos = mwl8k_qos_setbit_ack(qos,
1309 MWL8K_TXD_ACK_POLICY_NORMAL);
1310
1311 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1312 qos = mwl8k_qos_setbit_amsdu(qos);
1313 }
1314
1315 dma = pci_map_single(priv->pdev, skb->data,
1316 skb->len, PCI_DMA_TODEVICE);
1317
1318 if (pci_dma_mapping_error(priv->pdev, dma)) {
1319 printk(KERN_DEBUG "%s: failed to dma map skb, "
1320 "dropping TX frame.\n", priv->name);
1321 dev_kfree_skb(skb);
1322 return NETDEV_TX_OK;
1323 }
1324
1325 spin_lock_bh(&priv->tx_lock);
1326
1327 txq = priv->txq + index;
1328
1329 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1330 txq->tx_skb[txq->tx_tail] = skb;
1331
1332 tx = txq->tx_desc_area + txq->tx_tail;
1333 tx->data_rate = txdatarate;
1334 tx->tx_priority = index;
1335 tx->qos_control = cpu_to_le16(qos);
1336 tx->pkt_phys_addr = cpu_to_le32(dma);
1337 tx->pkt_len = cpu_to_le16(skb->len);
1338 tx->rate_info = 0;
1339 tx->peer_id = mwl8k_vif->peer_id;
1340 wmb();
1341 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1342
1343 txq->tx_stats.count++;
1344 txq->tx_stats.len++;
1345 priv->pending_tx_pkts++;
1346
1347 txq->tx_tail++;
1348 if (txq->tx_tail == MWL8K_TX_DESCS)
1349 txq->tx_tail = 0;
1350
1351 if (txq->tx_head == txq->tx_tail)
1352 ieee80211_stop_queue(hw, index);
1353
1354 mwl8k_tx_start(priv);
1355
1356 spin_unlock_bh(&priv->tx_lock);
1357
1358 return NETDEV_TX_OK;
1359}
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1379{
1380 struct mwl8k_priv *priv = hw->priv;
1381
1382 if (priv->fw_mutex_owner != current) {
1383 int rc;
1384
1385 mutex_lock(&priv->fw_mutex);
1386 ieee80211_stop_queues(hw);
1387
1388 rc = mwl8k_tx_wait_empty(hw);
1389 if (rc) {
1390 ieee80211_wake_queues(hw);
1391 mutex_unlock(&priv->fw_mutex);
1392
1393 return rc;
1394 }
1395
1396 priv->fw_mutex_owner = current;
1397 }
1398
1399 priv->fw_mutex_depth++;
1400
1401 return 0;
1402}
1403
1404static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1405{
1406 struct mwl8k_priv *priv = hw->priv;
1407
1408 if (!--priv->fw_mutex_depth) {
1409 ieee80211_wake_queues(hw);
1410 priv->fw_mutex_owner = NULL;
1411 mutex_unlock(&priv->fw_mutex);
1412 }
1413}
1414
1415
1416
1417
1418
1419
1420
1421#define MWL8K_CMD_TIMEOUT_MS 2000
1422
1423static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1424{
1425 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1426 struct mwl8k_priv *priv = hw->priv;
1427 void __iomem *regs = priv->regs;
1428 dma_addr_t dma_addr;
1429 unsigned int dma_size;
1430 int rc;
1431 unsigned long timeout = 0;
1432 u8 buf[32];
1433
1434 cmd->result = 0xFFFF;
1435 dma_size = le16_to_cpu(cmd->length);
1436 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1437 PCI_DMA_BIDIRECTIONAL);
1438 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1439 return -ENOMEM;
1440
1441 rc = mwl8k_fw_lock(hw);
1442 if (rc) {
1443 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1444 PCI_DMA_BIDIRECTIONAL);
1445 return rc;
1446 }
1447
1448 priv->hostcmd_wait = &cmd_wait;
1449 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1450 iowrite32(MWL8K_H2A_INT_DOORBELL,
1451 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1452 iowrite32(MWL8K_H2A_INT_DUMMY,
1453 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1454
1455 timeout = wait_for_completion_timeout(&cmd_wait,
1456 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1457
1458 priv->hostcmd_wait = NULL;
1459
1460 mwl8k_fw_unlock(hw);
1461
1462 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1463 PCI_DMA_BIDIRECTIONAL);
1464
1465 if (!timeout) {
1466 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1467 priv->name,
1468 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1469 MWL8K_CMD_TIMEOUT_MS);
1470 rc = -ETIMEDOUT;
1471 } else {
1472 rc = cmd->result ? -EINVAL : 0;
1473 if (rc)
1474 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1475 priv->name,
1476 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1477 le16_to_cpu(cmd->result));
1478 }
1479
1480 return rc;
1481}
1482
1483
1484
1485
1486struct mwl8k_cmd_get_hw_spec {
1487 struct mwl8k_cmd_pkt header;
1488 __u8 hw_rev;
1489 __u8 host_interface;
1490 __le16 num_mcaddrs;
1491 __u8 perm_addr[ETH_ALEN];
1492 __le16 region_code;
1493 __le32 fw_rev;
1494 __le32 ps_cookie;
1495 __le32 caps;
1496 __u8 mcs_bitmap[16];
1497 __le32 rx_queue_ptr;
1498 __le32 num_tx_queues;
1499 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1500 __le32 caps2;
1501 __le32 num_tx_desc_per_queue;
1502 __le32 total_rx_desc;
1503} __attribute__((packed));
1504
1505static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1506{
1507 struct mwl8k_priv *priv = hw->priv;
1508 struct mwl8k_cmd_get_hw_spec *cmd;
1509 int rc;
1510 int i;
1511
1512 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1513 if (cmd == NULL)
1514 return -ENOMEM;
1515
1516 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1517 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1518
1519 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1520 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1521 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
1522 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1523 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1524 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
1525 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1526 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
1527
1528 rc = mwl8k_post_cmd(hw, &cmd->header);
1529
1530 if (!rc) {
1531 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1532 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1533 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1534 priv->hw_rev = cmd->hw_rev;
1535 }
1536
1537 kfree(cmd);
1538 return rc;
1539}
1540
1541
1542
1543
1544struct mwl8k_cmd_mac_multicast_adr {
1545 struct mwl8k_cmd_pkt header;
1546 __le16 action;
1547 __le16 numaddr;
1548 __u8 addr[0][ETH_ALEN];
1549};
1550
1551#define MWL8K_ENABLE_RX_MULTICAST 0x000F
1552
1553static struct mwl8k_cmd_pkt *
1554__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1555 int mc_count, struct dev_addr_list *mclist)
1556{
1557 struct mwl8k_priv *priv = hw->priv;
1558 struct mwl8k_cmd_mac_multicast_adr *cmd;
1559 int size;
1560 int i;
1561
1562 if (mc_count > priv->num_mcaddrs)
1563 mc_count = priv->num_mcaddrs;
1564
1565 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1566
1567 cmd = kzalloc(size, GFP_ATOMIC);
1568 if (cmd == NULL)
1569 return NULL;
1570
1571 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1572 cmd->header.length = cpu_to_le16(size);
1573 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1574 cmd->numaddr = cpu_to_le16(mc_count);
1575
1576 for (i = 0; i < mc_count && mclist; i++) {
1577 if (mclist->da_addrlen != ETH_ALEN) {
1578 kfree(cmd);
1579 return NULL;
1580 }
1581 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1582 mclist = mclist->next;
1583 }
1584
1585 return &cmd->header;
1586}
1587
1588
1589
1590
1591struct mwl8k_cmd_802_11_get_stat {
1592 struct mwl8k_cmd_pkt header;
1593 __le16 action;
1594 __le32 stats[64];
1595} __attribute__((packed));
1596
1597#define MWL8K_STAT_ACK_FAILURE 9
1598#define MWL8K_STAT_RTS_FAILURE 12
1599#define MWL8K_STAT_FCS_ERROR 24
1600#define MWL8K_STAT_RTS_SUCCESS 11
1601
1602static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1603 struct ieee80211_low_level_stats *stats)
1604{
1605 struct mwl8k_cmd_802_11_get_stat *cmd;
1606 int rc;
1607
1608 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1609 if (cmd == NULL)
1610 return -ENOMEM;
1611
1612 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1613 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1614 cmd->action = cpu_to_le16(MWL8K_CMD_GET);
1615
1616 rc = mwl8k_post_cmd(hw, &cmd->header);
1617 if (!rc) {
1618 stats->dot11ACKFailureCount =
1619 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1620 stats->dot11RTSFailureCount =
1621 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1622 stats->dot11FCSErrorCount =
1623 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1624 stats->dot11RTSSuccessCount =
1625 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1626 }
1627 kfree(cmd);
1628
1629 return rc;
1630}
1631
1632
1633
1634
1635struct mwl8k_cmd_802_11_radio_control {
1636 struct mwl8k_cmd_pkt header;
1637 __le16 action;
1638 __le16 control;
1639 __le16 radio_on;
1640} __attribute__((packed));
1641
1642static int
1643mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1644{
1645 struct mwl8k_priv *priv = hw->priv;
1646 struct mwl8k_cmd_802_11_radio_control *cmd;
1647 int rc;
1648
1649 if (enable == priv->radio_on && !force)
1650 return 0;
1651
1652 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1653 if (cmd == NULL)
1654 return -ENOMEM;
1655
1656 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1657 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1658 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1659 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1660 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1661
1662 rc = mwl8k_post_cmd(hw, &cmd->header);
1663 kfree(cmd);
1664
1665 if (!rc)
1666 priv->radio_on = enable;
1667
1668 return rc;
1669}
1670
1671static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1672{
1673 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1674}
1675
1676static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1677{
1678 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1679}
1680
1681static int
1682mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1683{
1684 struct mwl8k_priv *priv;
1685
1686 if (hw == NULL || hw->priv == NULL)
1687 return -EINVAL;
1688 priv = hw->priv;
1689
1690 priv->radio_short_preamble = short_preamble;
1691
1692 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1693}
1694
1695
1696
1697
1698#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1699
1700struct mwl8k_cmd_802_11_rf_tx_power {
1701 struct mwl8k_cmd_pkt header;
1702 __le16 action;
1703 __le16 support_level;
1704 __le16 current_level;
1705 __le16 reserved;
1706 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1707} __attribute__((packed));
1708
1709static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1710{
1711 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1712 int rc;
1713
1714 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1715 if (cmd == NULL)
1716 return -ENOMEM;
1717
1718 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1719 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1720 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1721 cmd->support_level = cpu_to_le16(dBm);
1722
1723 rc = mwl8k_post_cmd(hw, &cmd->header);
1724 kfree(cmd);
1725
1726 return rc;
1727}
1728
1729
1730
1731
1732struct mwl8k_cmd_set_pre_scan {
1733 struct mwl8k_cmd_pkt header;
1734} __attribute__((packed));
1735
1736static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1737{
1738 struct mwl8k_cmd_set_pre_scan *cmd;
1739 int rc;
1740
1741 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1742 if (cmd == NULL)
1743 return -ENOMEM;
1744
1745 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1746 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1747
1748 rc = mwl8k_post_cmd(hw, &cmd->header);
1749 kfree(cmd);
1750
1751 return rc;
1752}
1753
1754
1755
1756
1757struct mwl8k_cmd_set_post_scan {
1758 struct mwl8k_cmd_pkt header;
1759 __le32 isibss;
1760 __u8 bssid[ETH_ALEN];
1761} __attribute__((packed));
1762
1763static int
1764mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1765{
1766 struct mwl8k_cmd_set_post_scan *cmd;
1767 int rc;
1768
1769 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1770 if (cmd == NULL)
1771 return -ENOMEM;
1772
1773 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1774 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1775 cmd->isibss = 0;
1776 memcpy(cmd->bssid, mac, ETH_ALEN);
1777
1778 rc = mwl8k_post_cmd(hw, &cmd->header);
1779 kfree(cmd);
1780
1781 return rc;
1782}
1783
1784
1785
1786
1787struct mwl8k_cmd_set_rf_channel {
1788 struct mwl8k_cmd_pkt header;
1789 __le16 action;
1790 __u8 current_channel;
1791 __le32 channel_flags;
1792} __attribute__((packed));
1793
1794static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1795 struct ieee80211_channel *channel)
1796{
1797 struct mwl8k_cmd_set_rf_channel *cmd;
1798 int rc;
1799
1800 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1801 if (cmd == NULL)
1802 return -ENOMEM;
1803
1804 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1805 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1806 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1807 cmd->current_channel = channel->hw_value;
1808 if (channel->band == IEEE80211_BAND_2GHZ)
1809 cmd->channel_flags = cpu_to_le32(0x00000081);
1810 else
1811 cmd->channel_flags = cpu_to_le32(0x00000000);
1812
1813 rc = mwl8k_post_cmd(hw, &cmd->header);
1814 kfree(cmd);
1815
1816 return rc;
1817}
1818
1819
1820
1821
1822struct mwl8k_cmd_set_slot {
1823 struct mwl8k_cmd_pkt header;
1824 __le16 action;
1825 __u8 short_slot;
1826} __attribute__((packed));
1827
1828static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1829{
1830 struct mwl8k_cmd_set_slot *cmd;
1831 int rc;
1832
1833 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1834 if (cmd == NULL)
1835 return -ENOMEM;
1836
1837 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1838 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1839 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1840 cmd->short_slot = short_slot_time;
1841
1842 rc = mwl8k_post_cmd(hw, &cmd->header);
1843 kfree(cmd);
1844
1845 return rc;
1846}
1847
1848
1849
1850
1851struct mwl8k_cmd_mimo_config {
1852 struct mwl8k_cmd_pkt header;
1853 __le32 action;
1854 __u8 rx_antenna_map;
1855 __u8 tx_antenna_map;
1856} __attribute__((packed));
1857
1858static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1859{
1860 struct mwl8k_cmd_mimo_config *cmd;
1861 int rc;
1862
1863 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1864 if (cmd == NULL)
1865 return -ENOMEM;
1866
1867 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1868 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1869 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1870 cmd->rx_antenna_map = rx;
1871 cmd->tx_antenna_map = tx;
1872
1873 rc = mwl8k_post_cmd(hw, &cmd->header);
1874 kfree(cmd);
1875
1876 return rc;
1877}
1878
1879
1880
1881
1882struct mwl8k_cmd_enable_sniffer {
1883 struct mwl8k_cmd_pkt header;
1884 __le32 action;
1885} __attribute__((packed));
1886
1887static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1888{
1889 struct mwl8k_cmd_enable_sniffer *cmd;
1890 int rc;
1891
1892 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1893 if (cmd == NULL)
1894 return -ENOMEM;
1895
1896 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1897 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1898 cmd->action = cpu_to_le32(!!enable);
1899
1900 rc = mwl8k_post_cmd(hw, &cmd->header);
1901 kfree(cmd);
1902
1903 return rc;
1904}
1905
1906
1907
1908
1909struct mwl8k_cmd_set_rate_adapt_mode {
1910 struct mwl8k_cmd_pkt header;
1911 __le16 action;
1912 __le16 mode;
1913} __attribute__((packed));
1914
1915static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1916{
1917 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1918 int rc;
1919
1920 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1921 if (cmd == NULL)
1922 return -ENOMEM;
1923
1924 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1925 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1926 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1927 cmd->mode = cpu_to_le16(mode);
1928
1929 rc = mwl8k_post_cmd(hw, &cmd->header);
1930 kfree(cmd);
1931
1932 return rc;
1933}
1934
1935
1936
1937
1938struct mwl8k_cmd_set_wmm {
1939 struct mwl8k_cmd_pkt header;
1940 __le16 action;
1941} __attribute__((packed));
1942
1943static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1944{
1945 struct mwl8k_priv *priv = hw->priv;
1946 struct mwl8k_cmd_set_wmm *cmd;
1947 int rc;
1948
1949 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1950 if (cmd == NULL)
1951 return -ENOMEM;
1952
1953 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1954 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1955 cmd->action = cpu_to_le16(!!enable);
1956
1957 rc = mwl8k_post_cmd(hw, &cmd->header);
1958 kfree(cmd);
1959
1960 if (!rc)
1961 priv->wmm_enabled = enable;
1962
1963 return rc;
1964}
1965
1966
1967
1968
1969struct mwl8k_cmd_rts_threshold {
1970 struct mwl8k_cmd_pkt header;
1971 __le16 action;
1972 __le16 threshold;
1973} __attribute__((packed));
1974
1975static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
1976 u16 action, u16 threshold)
1977{
1978 struct mwl8k_cmd_rts_threshold *cmd;
1979 int rc;
1980
1981 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1982 if (cmd == NULL)
1983 return -ENOMEM;
1984
1985 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
1986 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1987 cmd->action = cpu_to_le16(action);
1988 cmd->threshold = cpu_to_le16(threshold);
1989
1990 rc = mwl8k_post_cmd(hw, &cmd->header);
1991 kfree(cmd);
1992
1993 return rc;
1994}
1995
1996
1997
1998
1999struct mwl8k_cmd_set_edca_params {
2000 struct mwl8k_cmd_pkt header;
2001
2002
2003 __le16 action;
2004
2005
2006 __le16 txop;
2007
2008
2009 __u8 log_cw_max;
2010
2011
2012 __u8 log_cw_min;
2013
2014
2015 __u8 aifs;
2016
2017
2018 __u8 txq;
2019} __attribute__((packed));
2020
2021#define MWL8K_SET_EDCA_CW 0x01
2022#define MWL8K_SET_EDCA_TXOP 0x02
2023#define MWL8K_SET_EDCA_AIFS 0x04
2024
2025#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2026 MWL8K_SET_EDCA_TXOP | \
2027 MWL8K_SET_EDCA_AIFS)
2028
2029static int
2030mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2031 __u16 cw_min, __u16 cw_max,
2032 __u8 aifs, __u16 txop)
2033{
2034 struct mwl8k_cmd_set_edca_params *cmd;
2035 int rc;
2036
2037 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2038 if (cmd == NULL)
2039 return -ENOMEM;
2040
2041 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2042 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2043 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2044 cmd->txop = cpu_to_le16(txop);
2045 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2046 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2047 cmd->aifs = aifs;
2048 cmd->txq = qnum;
2049
2050 rc = mwl8k_post_cmd(hw, &cmd->header);
2051 kfree(cmd);
2052
2053 return rc;
2054}
2055
2056
2057
2058
2059
2060
2061#define MWL8K_FJ_BEACON_MAXLEN 128
2062
2063struct mwl8k_cmd_finalize_join {
2064 struct mwl8k_cmd_pkt header;
2065 __le32 sleep_interval;
2066 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2067} __attribute__((packed));
2068
2069static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2070 __u16 framelen, __u16 dtim)
2071{
2072 struct mwl8k_cmd_finalize_join *cmd;
2073 struct ieee80211_mgmt *payload = frame;
2074 u16 hdrlen;
2075 u32 payload_len;
2076 int rc;
2077
2078 if (frame == NULL)
2079 return -EINVAL;
2080
2081 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2082 if (cmd == NULL)
2083 return -ENOMEM;
2084
2085 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2086 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2087 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2088
2089 hdrlen = ieee80211_hdrlen(payload->frame_control);
2090
2091 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2092
2093
2094 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2095 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2096 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2097 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2098
2099 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2100 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2101
2102 if (payload && payload_len)
2103 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2104
2105 rc = mwl8k_post_cmd(hw, &cmd->header);
2106 kfree(cmd);
2107 return rc;
2108}
2109
2110
2111
2112
2113struct mwl8k_cmd_update_sta_db {
2114 struct mwl8k_cmd_pkt header;
2115
2116
2117 __le32 action;
2118
2119
2120 __u8 peer_addr[ETH_ALEN];
2121
2122 __le32 reserved;
2123
2124
2125 struct peer_capability_info peer_info;
2126} __attribute__((packed));
2127
2128static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2129 struct ieee80211_vif *vif, __u32 action)
2130{
2131 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2132 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2133 struct mwl8k_cmd_update_sta_db *cmd;
2134 struct peer_capability_info *peer_info;
2135 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2136 int rc;
2137 __u8 count, *rates;
2138
2139 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2140 if (cmd == NULL)
2141 return -ENOMEM;
2142
2143 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2144 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2145
2146 cmd->action = cpu_to_le32(action);
2147 peer_info = &cmd->peer_info;
2148 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2149
2150 switch (action) {
2151 case MWL8K_STA_DB_ADD_ENTRY:
2152 case MWL8K_STA_DB_MODIFY_ENTRY:
2153
2154 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2155 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2156 peer_info->interop = 1;
2157 peer_info->amsdu_enabled = 0;
2158
2159 rates = peer_info->legacy_rates;
2160 for (count = 0; count < mv_vif->legacy_nrates; count++)
2161 rates[count] = bitrates[count].hw_value;
2162
2163 rc = mwl8k_post_cmd(hw, &cmd->header);
2164 if (rc == 0)
2165 mv_vif->peer_id = peer_info->station_id;
2166
2167 break;
2168
2169 case MWL8K_STA_DB_DEL_ENTRY:
2170 case MWL8K_STA_DB_FLUSH:
2171 default:
2172 rc = mwl8k_post_cmd(hw, &cmd->header);
2173 if (rc == 0)
2174 mv_vif->peer_id = 0;
2175 break;
2176 }
2177 kfree(cmd);
2178
2179 return rc;
2180}
2181
2182
2183
2184
2185#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2186
2187#define MWL8K_FRAME_PROT_DISABLED 0x00
2188#define MWL8K_FRAME_PROT_11G 0x07
2189#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2190#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2191
2192struct mwl8k_cmd_update_set_aid {
2193 struct mwl8k_cmd_pkt header;
2194 __le16 aid;
2195
2196
2197 __u8 bssid[ETH_ALEN];
2198 __le16 protection_mode;
2199 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2200} __attribute__((packed));
2201
2202static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2203 struct ieee80211_vif *vif)
2204{
2205 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2206 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2207 struct mwl8k_cmd_update_set_aid *cmd;
2208 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2209 int count;
2210 u16 prot_mode;
2211 int rc;
2212
2213 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2214 if (cmd == NULL)
2215 return -ENOMEM;
2216
2217 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2218 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2219 cmd->aid = cpu_to_le16(info->aid);
2220
2221 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2222
2223 if (info->use_cts_prot) {
2224 prot_mode = MWL8K_FRAME_PROT_11G;
2225 } else {
2226 switch (info->ht_operation_mode &
2227 IEEE80211_HT_OP_MODE_PROTECTION) {
2228 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2229 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2230 break;
2231 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2232 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2233 break;
2234 default:
2235 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2236 break;
2237 }
2238 }
2239 cmd->protection_mode = cpu_to_le16(prot_mode);
2240
2241 for (count = 0; count < mv_vif->legacy_nrates; count++)
2242 cmd->supp_rates[count] = bitrates[count].hw_value;
2243
2244 rc = mwl8k_post_cmd(hw, &cmd->header);
2245 kfree(cmd);
2246
2247 return rc;
2248}
2249
2250
2251
2252
2253struct mwl8k_cmd_update_rateset {
2254 struct mwl8k_cmd_pkt header;
2255 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2256
2257
2258 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2259 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2260} __attribute__((packed));
2261
2262static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2263 struct ieee80211_vif *vif)
2264{
2265 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2266 struct mwl8k_cmd_update_rateset *cmd;
2267 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2268 int count;
2269 int rc;
2270
2271 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2272 if (cmd == NULL)
2273 return -ENOMEM;
2274
2275 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2276 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2277
2278 for (count = 0; count < mv_vif->legacy_nrates; count++)
2279 cmd->legacy_rates[count] = bitrates[count].hw_value;
2280
2281 rc = mwl8k_post_cmd(hw, &cmd->header);
2282 kfree(cmd);
2283
2284 return rc;
2285}
2286
2287
2288
2289
2290#define MWL8K_RATE_TABLE_SIZE 8
2291#define MWL8K_UCAST_RATE 0
2292#define MWL8K_USE_AUTO_RATE 0x0002
2293
2294struct mwl8k_rate_entry {
2295
2296 __le32 is_ht_rate;
2297
2298
2299 __le32 enable_retry;
2300
2301
2302 __le32 rate;
2303
2304
2305 __le32 retry_count;
2306} __attribute__((packed));
2307
2308struct mwl8k_rate_table {
2309
2310 __le32 allow_rate_drop;
2311 __le32 num_rates;
2312 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2313} __attribute__((packed));
2314
2315struct mwl8k_cmd_use_fixed_rate {
2316 struct mwl8k_cmd_pkt header;
2317 __le32 action;
2318 struct mwl8k_rate_table rate_table;
2319
2320
2321 __le32 rate_type;
2322 __le32 reserved1;
2323 __le32 reserved2;
2324} __attribute__((packed));
2325
2326static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2327 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2328{
2329 struct mwl8k_cmd_use_fixed_rate *cmd;
2330 int count;
2331 int rc;
2332
2333 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2334 if (cmd == NULL)
2335 return -ENOMEM;
2336
2337 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2338 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2339
2340 cmd->action = cpu_to_le32(action);
2341 cmd->rate_type = cpu_to_le32(rate_type);
2342
2343 if (rate_table != NULL) {
2344
2345
2346
2347 cmd->rate_table.allow_rate_drop =
2348 cpu_to_le32(rate_table->allow_rate_drop);
2349 cmd->rate_table.num_rates =
2350 cpu_to_le32(rate_table->num_rates);
2351
2352 for (count = 0; count < rate_table->num_rates; count++) {
2353 struct mwl8k_rate_entry *dst =
2354 &cmd->rate_table.rate_entry[count];
2355 struct mwl8k_rate_entry *src =
2356 &rate_table->rate_entry[count];
2357
2358 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2359 dst->enable_retry = cpu_to_le32(src->enable_retry);
2360 dst->rate = cpu_to_le32(src->rate);
2361 dst->retry_count = cpu_to_le32(src->retry_count);
2362 }
2363 }
2364
2365 rc = mwl8k_post_cmd(hw, &cmd->header);
2366 kfree(cmd);
2367
2368 return rc;
2369}
2370
2371
2372
2373
2374
2375static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2376{
2377 struct ieee80211_hw *hw = dev_id;
2378 struct mwl8k_priv *priv = hw->priv;
2379 u32 status;
2380
2381 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2382 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2383
2384 if (!status)
2385 return IRQ_NONE;
2386
2387 if (status & MWL8K_A2H_INT_TX_DONE)
2388 tasklet_schedule(&priv->tx_reclaim_task);
2389
2390 if (status & MWL8K_A2H_INT_RX_READY) {
2391 while (rxq_process(hw, 0, 1))
2392 rxq_refill(hw, 0, 1);
2393 }
2394
2395 if (status & MWL8K_A2H_INT_OPC_DONE) {
2396 if (priv->hostcmd_wait != NULL)
2397 complete(priv->hostcmd_wait);
2398 }
2399
2400 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2401 if (!mutex_is_locked(&priv->fw_mutex) &&
2402 priv->radio_on && mwl8k_txq_busy(priv))
2403 mwl8k_tx_start(priv);
2404 }
2405
2406 return IRQ_HANDLED;
2407}
2408
2409
2410
2411
2412
2413static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2414{
2415 struct mwl8k_priv *priv = hw->priv;
2416 int index = skb_get_queue_mapping(skb);
2417 int rc;
2418
2419 if (priv->current_channel == NULL) {
2420 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2421 "disabled\n", priv->name);
2422 dev_kfree_skb(skb);
2423 return NETDEV_TX_OK;
2424 }
2425
2426 rc = mwl8k_txq_xmit(hw, index, skb);
2427
2428 return rc;
2429}
2430
2431static int mwl8k_start(struct ieee80211_hw *hw)
2432{
2433 struct mwl8k_priv *priv = hw->priv;
2434 int rc;
2435
2436 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2437 IRQF_SHARED, MWL8K_NAME, hw);
2438 if (rc) {
2439 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2440 priv->name);
2441 return -EIO;
2442 }
2443
2444
2445 tasklet_enable(&priv->tx_reclaim_task);
2446
2447
2448 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2449
2450 rc = mwl8k_fw_lock(hw);
2451 if (!rc) {
2452 rc = mwl8k_cmd_802_11_radio_enable(hw);
2453
2454 if (!rc)
2455 rc = mwl8k_cmd_set_pre_scan(hw);
2456
2457 if (!rc)
2458 rc = mwl8k_cmd_set_post_scan(hw,
2459 "\x00\x00\x00\x00\x00\x00");
2460
2461 if (!rc)
2462 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2463
2464 if (!rc)
2465 rc = mwl8k_set_wmm(hw, 0);
2466
2467 if (!rc)
2468 rc = mwl8k_enable_sniffer(hw, 0);
2469
2470 mwl8k_fw_unlock(hw);
2471 }
2472
2473 if (rc) {
2474 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2475 free_irq(priv->pdev->irq, hw);
2476 tasklet_disable(&priv->tx_reclaim_task);
2477 }
2478
2479 return rc;
2480}
2481
2482static void mwl8k_stop(struct ieee80211_hw *hw)
2483{
2484 struct mwl8k_priv *priv = hw->priv;
2485 int i;
2486
2487 mwl8k_cmd_802_11_radio_disable(hw);
2488
2489 ieee80211_stop_queues(hw);
2490
2491
2492 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2493 free_irq(priv->pdev->irq, hw);
2494
2495
2496 cancel_work_sync(&priv->finalize_join_worker);
2497 if (priv->beacon_skb != NULL)
2498 dev_kfree_skb(priv->beacon_skb);
2499
2500
2501 tasklet_disable(&priv->tx_reclaim_task);
2502
2503
2504 flush_workqueue(priv->config_wq);
2505
2506
2507 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2508 mwl8k_txq_reclaim(hw, i, 1);
2509}
2510
2511static int mwl8k_add_interface(struct ieee80211_hw *hw,
2512 struct ieee80211_if_init_conf *conf)
2513{
2514 struct mwl8k_priv *priv = hw->priv;
2515 struct mwl8k_vif *mwl8k_vif;
2516
2517
2518
2519
2520 if (priv->vif != NULL)
2521 return -EBUSY;
2522
2523
2524
2525
2526 if (conf->type != NL80211_IFTYPE_STATION)
2527 return -EINVAL;
2528
2529
2530 mwl8k_vif = MWL8K_VIF(conf->vif);
2531 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2532
2533
2534 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2535
2536
2537 mwl8k_vif->priv = priv;
2538
2539
2540 memcpy(mwl8k_vif->legacy_rates,
2541 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2542 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2543
2544
2545 mwl8k_vif->seqno = 0;
2546
2547 priv->vif = conf->vif;
2548 priv->current_channel = NULL;
2549
2550 return 0;
2551}
2552
2553static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2554 struct ieee80211_if_init_conf *conf)
2555{
2556 struct mwl8k_priv *priv = hw->priv;
2557
2558 if (priv->vif == NULL)
2559 return;
2560
2561 priv->vif = NULL;
2562}
2563
2564static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2565{
2566 struct ieee80211_conf *conf = &hw->conf;
2567 struct mwl8k_priv *priv = hw->priv;
2568 int rc;
2569
2570 if (conf->flags & IEEE80211_CONF_IDLE) {
2571 mwl8k_cmd_802_11_radio_disable(hw);
2572 priv->current_channel = NULL;
2573 return 0;
2574 }
2575
2576 rc = mwl8k_fw_lock(hw);
2577 if (rc)
2578 return rc;
2579
2580 rc = mwl8k_cmd_802_11_radio_enable(hw);
2581 if (rc)
2582 goto out;
2583
2584 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2585 if (rc)
2586 goto out;
2587
2588 priv->current_channel = conf->channel;
2589
2590 if (conf->power_level > 18)
2591 conf->power_level = 18;
2592 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2593 if (rc)
2594 goto out;
2595
2596 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2597 rc = -EINVAL;
2598
2599out:
2600 mwl8k_fw_unlock(hw);
2601
2602 return rc;
2603}
2604
2605static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2606 struct ieee80211_vif *vif,
2607 struct ieee80211_bss_conf *info,
2608 u32 changed)
2609{
2610 struct mwl8k_priv *priv = hw->priv;
2611 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2612 int rc;
2613
2614 if (changed & BSS_CHANGED_BSSID)
2615 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2616
2617 if ((changed & BSS_CHANGED_ASSOC) == 0)
2618 return;
2619
2620 priv->capture_beacon = false;
2621
2622 rc = mwl8k_fw_lock(hw);
2623 if (rc)
2624 return;
2625
2626 if (info->assoc) {
2627 memcpy(&mwl8k_vif->bss_info, info,
2628 sizeof(struct ieee80211_bss_conf));
2629
2630
2631 rc = mwl8k_update_rateset(hw, vif);
2632 if (rc)
2633 goto out;
2634
2635
2636 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2637 MWL8K_UCAST_RATE, NULL);
2638 if (rc)
2639 goto out;
2640
2641
2642 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2643 if (rc)
2644 goto out;
2645
2646
2647 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2648 if (rc)
2649 goto out;
2650
2651
2652 rc = mwl8k_cmd_update_sta_db(hw, vif,
2653 MWL8K_STA_DB_MODIFY_ENTRY);
2654 if (rc)
2655 goto out;
2656
2657
2658 rc = mwl8k_cmd_set_aid(hw, vif);
2659 if (rc)
2660 goto out;
2661
2662
2663
2664
2665
2666 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2667 priv->capture_beacon = true;
2668 } else {
2669 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2670 memset(&mwl8k_vif->bss_info, 0,
2671 sizeof(struct ieee80211_bss_conf));
2672 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2673 }
2674
2675out:
2676 mwl8k_fw_unlock(hw);
2677}
2678
2679static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2680 int mc_count, struct dev_addr_list *mclist)
2681{
2682 struct mwl8k_cmd_pkt *cmd;
2683
2684 cmd = __mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist);
2685
2686 return (unsigned long)cmd;
2687}
2688
2689static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2690 unsigned int changed_flags,
2691 unsigned int *total_flags,
2692 u64 multicast)
2693{
2694 struct mwl8k_priv *priv = hw->priv;
2695 struct mwl8k_cmd_pkt *multicast_adr_cmd;
2696
2697
2698 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
2699
2700 if (mwl8k_fw_lock(hw))
2701 return;
2702
2703 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2704 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2705 mwl8k_cmd_set_pre_scan(hw);
2706 else {
2707 u8 *bssid;
2708
2709 bssid = "\x00\x00\x00\x00\x00\x00";
2710 if (priv->vif != NULL)
2711 bssid = MWL8K_VIF(priv->vif)->bssid;
2712
2713 mwl8k_cmd_set_post_scan(hw, bssid);
2714 }
2715 }
2716
2717 multicast_adr_cmd = (void *)(unsigned long)multicast;
2718 if (multicast_adr_cmd != NULL) {
2719 mwl8k_post_cmd(hw, multicast_adr_cmd);
2720 kfree(multicast_adr_cmd);
2721 }
2722
2723 mwl8k_fw_unlock(hw);
2724}
2725
2726static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2727{
2728 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2729}
2730
2731static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2732 const struct ieee80211_tx_queue_params *params)
2733{
2734 struct mwl8k_priv *priv = hw->priv;
2735 int rc;
2736
2737 rc = mwl8k_fw_lock(hw);
2738 if (!rc) {
2739 if (!priv->wmm_enabled)
2740 rc = mwl8k_set_wmm(hw, 1);
2741
2742 if (!rc)
2743 rc = mwl8k_set_edca_params(hw, queue,
2744 params->cw_min,
2745 params->cw_max,
2746 params->aifs,
2747 params->txop);
2748
2749 mwl8k_fw_unlock(hw);
2750 }
2751
2752 return rc;
2753}
2754
2755static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2756 struct ieee80211_tx_queue_stats *stats)
2757{
2758 struct mwl8k_priv *priv = hw->priv;
2759 struct mwl8k_tx_queue *txq;
2760 int index;
2761
2762 spin_lock_bh(&priv->tx_lock);
2763 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2764 txq = priv->txq + index;
2765 memcpy(&stats[index], &txq->tx_stats,
2766 sizeof(struct ieee80211_tx_queue_stats));
2767 }
2768 spin_unlock_bh(&priv->tx_lock);
2769
2770 return 0;
2771}
2772
2773static int mwl8k_get_stats(struct ieee80211_hw *hw,
2774 struct ieee80211_low_level_stats *stats)
2775{
2776 return mwl8k_cmd_802_11_get_stat(hw, stats);
2777}
2778
2779static const struct ieee80211_ops mwl8k_ops = {
2780 .tx = mwl8k_tx,
2781 .start = mwl8k_start,
2782 .stop = mwl8k_stop,
2783 .add_interface = mwl8k_add_interface,
2784 .remove_interface = mwl8k_remove_interface,
2785 .config = mwl8k_config,
2786 .bss_info_changed = mwl8k_bss_info_changed,
2787 .prepare_multicast = mwl8k_prepare_multicast,
2788 .configure_filter = mwl8k_configure_filter,
2789 .set_rts_threshold = mwl8k_set_rts_threshold,
2790 .conf_tx = mwl8k_conf_tx,
2791 .get_tx_stats = mwl8k_get_tx_stats,
2792 .get_stats = mwl8k_get_stats,
2793};
2794
2795static void mwl8k_tx_reclaim_handler(unsigned long data)
2796{
2797 int i;
2798 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2799 struct mwl8k_priv *priv = hw->priv;
2800
2801 spin_lock_bh(&priv->tx_lock);
2802 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2803 mwl8k_txq_reclaim(hw, i, 0);
2804
2805 if (priv->tx_wait != NULL && mwl8k_txq_busy(priv) == 0) {
2806 complete(priv->tx_wait);
2807 priv->tx_wait = NULL;
2808 }
2809 spin_unlock_bh(&priv->tx_lock);
2810}
2811
2812static void mwl8k_finalize_join_worker(struct work_struct *work)
2813{
2814 struct mwl8k_priv *priv =
2815 container_of(work, struct mwl8k_priv, finalize_join_worker);
2816 struct sk_buff *skb = priv->beacon_skb;
2817 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2818
2819 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2820 dev_kfree_skb(skb);
2821
2822 priv->beacon_skb = NULL;
2823}
2824
2825static int __devinit mwl8k_probe(struct pci_dev *pdev,
2826 const struct pci_device_id *id)
2827{
2828 static int printed_version = 0;
2829 struct ieee80211_hw *hw;
2830 struct mwl8k_priv *priv;
2831 int rc;
2832 int i;
2833
2834 if (!printed_version) {
2835 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2836 printed_version = 1;
2837 }
2838
2839 rc = pci_enable_device(pdev);
2840 if (rc) {
2841 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2842 MWL8K_NAME);
2843 return rc;
2844 }
2845
2846 rc = pci_request_regions(pdev, MWL8K_NAME);
2847 if (rc) {
2848 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2849 MWL8K_NAME);
2850 return rc;
2851 }
2852
2853 pci_set_master(pdev);
2854
2855 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2856 if (hw == NULL) {
2857 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2858 rc = -ENOMEM;
2859 goto err_free_reg;
2860 }
2861
2862 priv = hw->priv;
2863 priv->hw = hw;
2864 priv->pdev = pdev;
2865 priv->wmm_enabled = false;
2866 priv->pending_tx_pkts = 0;
2867 strncpy(priv->name, MWL8K_NAME, sizeof(priv->name));
2868
2869 SET_IEEE80211_DEV(hw, &pdev->dev);
2870 pci_set_drvdata(pdev, hw);
2871
2872 priv->regs = pci_iomap(pdev, 1, 0x10000);
2873 if (priv->regs == NULL) {
2874 printk(KERN_ERR "%s: Cannot map device memory\n", priv->name);
2875 goto err_iounmap;
2876 }
2877
2878 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
2879 priv->band.band = IEEE80211_BAND_2GHZ;
2880 priv->band.channels = priv->channels;
2881 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
2882 priv->band.bitrates = priv->rates;
2883 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
2884 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
2885
2886 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
2887 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
2888
2889
2890
2891
2892
2893 hw->extra_tx_headroom =
2894 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
2895
2896 hw->channel_change_time = 10;
2897
2898 hw->queues = MWL8K_TX_QUEUES;
2899
2900 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
2901
2902
2903 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
2904 hw->vif_data_size = sizeof(struct mwl8k_vif);
2905 priv->vif = NULL;
2906
2907
2908 priv->radio_on = 0;
2909 priv->radio_short_preamble = 0;
2910
2911
2912 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
2913
2914
2915 tasklet_init(&priv->tx_reclaim_task,
2916 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2917 tasklet_disable(&priv->tx_reclaim_task);
2918
2919
2920 priv->config_wq = create_singlethread_workqueue("mwl8k_config");
2921 if (priv->config_wq == NULL)
2922 goto err_iounmap;
2923
2924
2925 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2926 if (priv->cookie == NULL)
2927 goto err_iounmap;
2928
2929 rc = mwl8k_rxq_init(hw, 0);
2930 if (rc)
2931 goto err_iounmap;
2932 rxq_refill(hw, 0, INT_MAX);
2933
2934 mutex_init(&priv->fw_mutex);
2935 priv->fw_mutex_owner = NULL;
2936 priv->fw_mutex_depth = 0;
2937 priv->tx_wait = NULL;
2938 priv->hostcmd_wait = NULL;
2939
2940 spin_lock_init(&priv->tx_lock);
2941
2942 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
2943 rc = mwl8k_txq_init(hw, i);
2944 if (rc)
2945 goto err_free_queues;
2946 }
2947
2948 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2949 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2950 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
2951 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
2952
2953 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2954 IRQF_SHARED, MWL8K_NAME, hw);
2955 if (rc) {
2956 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2957 priv->name);
2958 goto err_free_queues;
2959 }
2960
2961
2962 mwl8k_hw_reset(priv);
2963
2964
2965 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
2966 if (rc) {
2967 printk(KERN_ERR "%s: Firmware files not found\n", priv->name);
2968 goto err_free_irq;
2969 }
2970
2971
2972 rc = mwl8k_load_firmware(priv);
2973 if (rc) {
2974 printk(KERN_ERR "%s: Cannot start firmware\n", priv->name);
2975 goto err_stop_firmware;
2976 }
2977
2978
2979 mwl8k_release_firmware(priv);
2980
2981
2982
2983
2984
2985
2986 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2987
2988
2989 rc = mwl8k_cmd_get_hw_spec(hw);
2990 if (rc) {
2991 printk(KERN_ERR "%s: Cannot initialise firmware\n", priv->name);
2992 goto err_stop_firmware;
2993 }
2994
2995
2996 rc = mwl8k_cmd_802_11_radio_disable(hw);
2997 if (rc) {
2998 printk(KERN_ERR "%s: Cannot disable\n", priv->name);
2999 goto err_stop_firmware;
3000 }
3001
3002
3003 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3004 free_irq(priv->pdev->irq, hw);
3005
3006 rc = ieee80211_register_hw(hw);
3007 if (rc) {
3008 printk(KERN_ERR "%s: Cannot register device\n", priv->name);
3009 goto err_stop_firmware;
3010 }
3011
3012 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3013 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3014 hw->wiphy->perm_addr,
3015 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3016 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3017
3018 return 0;
3019
3020err_stop_firmware:
3021 mwl8k_hw_reset(priv);
3022 mwl8k_release_firmware(priv);
3023
3024err_free_irq:
3025 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3026 free_irq(priv->pdev->irq, hw);
3027
3028err_free_queues:
3029 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3030 mwl8k_txq_deinit(hw, i);
3031 mwl8k_rxq_deinit(hw, 0);
3032
3033err_iounmap:
3034 if (priv->cookie != NULL)
3035 pci_free_consistent(priv->pdev, 4,
3036 priv->cookie, priv->cookie_dma);
3037
3038 if (priv->regs != NULL)
3039 pci_iounmap(pdev, priv->regs);
3040
3041 if (priv->config_wq != NULL)
3042 destroy_workqueue(priv->config_wq);
3043
3044 pci_set_drvdata(pdev, NULL);
3045 ieee80211_free_hw(hw);
3046
3047err_free_reg:
3048 pci_release_regions(pdev);
3049 pci_disable_device(pdev);
3050
3051 return rc;
3052}
3053
3054static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3055{
3056 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3057}
3058
3059static void __devexit mwl8k_remove(struct pci_dev *pdev)
3060{
3061 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3062 struct mwl8k_priv *priv;
3063 int i;
3064
3065 if (hw == NULL)
3066 return;
3067 priv = hw->priv;
3068
3069 ieee80211_stop_queues(hw);
3070
3071 ieee80211_unregister_hw(hw);
3072
3073
3074 tasklet_kill(&priv->tx_reclaim_task);
3075
3076
3077 destroy_workqueue(priv->config_wq);
3078
3079
3080 mwl8k_hw_reset(priv);
3081
3082
3083 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3084 mwl8k_txq_reclaim(hw, i, 1);
3085
3086 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3087 mwl8k_txq_deinit(hw, i);
3088
3089 mwl8k_rxq_deinit(hw, 0);
3090
3091 pci_free_consistent(priv->pdev, 4,
3092 priv->cookie, priv->cookie_dma);
3093
3094 pci_iounmap(pdev, priv->regs);
3095 pci_set_drvdata(pdev, NULL);
3096 ieee80211_free_hw(hw);
3097 pci_release_regions(pdev);
3098 pci_disable_device(pdev);
3099}
3100
3101static struct pci_driver mwl8k_driver = {
3102 .name = MWL8K_NAME,
3103 .id_table = mwl8k_table,
3104 .probe = mwl8k_probe,
3105 .remove = __devexit_p(mwl8k_remove),
3106 .shutdown = __devexit_p(mwl8k_shutdown),
3107};
3108
3109static int __init mwl8k_init(void)
3110{
3111 return pci_register_driver(&mwl8k_driver);
3112}
3113
3114static void __exit mwl8k_exit(void)
3115{
3116 pci_unregister_driver(&mwl8k_driver);
3117}
3118
3119module_init(mwl8k_init);
3120module_exit(mwl8k_exit);
3121
