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27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52#define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54#define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58 const unsigned int word, const u8 value)
59{
60 u32 reg;
61
62 mutex_lock(&rt2x00dev->csr_mutex);
63
64
65
66
67
68 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
69 reg = 0;
70 rt2x00_set_field32(®, BBPCSR_VALUE, value);
71 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
72 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
73 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
74
75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76 }
77
78 mutex_unlock(&rt2x00dev->csr_mutex);
79}
80
81static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82 const unsigned int word, u8 *value)
83{
84 u32 reg;
85
86 mutex_lock(&rt2x00dev->csr_mutex);
87
88
89
90
91
92
93
94
95
96 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
97 reg = 0;
98 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
101
102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104 WAIT_FOR_BBP(rt2x00dev, ®);
105 }
106
107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110}
111
112static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, const u32 value)
114{
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119
120
121
122
123 if (WAIT_FOR_RF(rt2x00dev, ®)) {
124 reg = 0;
125 rt2x00_set_field32(®, RFCSR_VALUE, value);
126 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
127 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
128 rt2x00_set_field32(®, RFCSR_BUSY, 1);
129
130 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
131 rt2x00_rf_write(rt2x00dev, word, value);
132 }
133
134 mutex_unlock(&rt2x00dev->csr_mutex);
135}
136
137static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
138{
139 struct rt2x00_dev *rt2x00dev = eeprom->data;
140 u32 reg;
141
142 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
143
144 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
145 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
146 eeprom->reg_data_clock =
147 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
148 eeprom->reg_chip_select =
149 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
150}
151
152static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
153{
154 struct rt2x00_dev *rt2x00dev = eeprom->data;
155 u32 reg = 0;
156
157 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
158 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
159 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
160 !!eeprom->reg_data_clock);
161 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
162 !!eeprom->reg_chip_select);
163
164 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
165}
166
167#ifdef CONFIG_RT2X00_LIB_DEBUGFS
168static const struct rt2x00debug rt2400pci_rt2x00debug = {
169 .owner = THIS_MODULE,
170 .csr = {
171 .read = rt2x00pci_register_read,
172 .write = rt2x00pci_register_write,
173 .flags = RT2X00DEBUGFS_OFFSET,
174 .word_base = CSR_REG_BASE,
175 .word_size = sizeof(u32),
176 .word_count = CSR_REG_SIZE / sizeof(u32),
177 },
178 .eeprom = {
179 .read = rt2x00_eeprom_read,
180 .write = rt2x00_eeprom_write,
181 .word_base = EEPROM_BASE,
182 .word_size = sizeof(u16),
183 .word_count = EEPROM_SIZE / sizeof(u16),
184 },
185 .bbp = {
186 .read = rt2400pci_bbp_read,
187 .write = rt2400pci_bbp_write,
188 .word_base = BBP_BASE,
189 .word_size = sizeof(u8),
190 .word_count = BBP_SIZE / sizeof(u8),
191 },
192 .rf = {
193 .read = rt2x00_rf_read,
194 .write = rt2400pci_rf_write,
195 .word_base = RF_BASE,
196 .word_size = sizeof(u32),
197 .word_count = RF_SIZE / sizeof(u32),
198 },
199};
200#endif
201
202static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
203{
204 u32 reg;
205
206 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
207 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
208}
209
210#ifdef CONFIG_RT2X00_LIB_LEDS
211static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
212 enum led_brightness brightness)
213{
214 struct rt2x00_led *led =
215 container_of(led_cdev, struct rt2x00_led, led_dev);
216 unsigned int enabled = brightness != LED_OFF;
217 u32 reg;
218
219 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
220
221 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
222 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
223 else if (led->type == LED_TYPE_ACTIVITY)
224 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
225
226 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
227}
228
229static int rt2400pci_blink_set(struct led_classdev *led_cdev,
230 unsigned long *delay_on,
231 unsigned long *delay_off)
232{
233 struct rt2x00_led *led =
234 container_of(led_cdev, struct rt2x00_led, led_dev);
235 u32 reg;
236
237 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
238 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
239 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
240 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
241
242 return 0;
243}
244
245static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
246 struct rt2x00_led *led,
247 enum led_type type)
248{
249 led->rt2x00dev = rt2x00dev;
250 led->type = type;
251 led->led_dev.brightness_set = rt2400pci_brightness_set;
252 led->led_dev.blink_set = rt2400pci_blink_set;
253 led->flags = LED_INITIALIZED;
254}
255#endif
256
257
258
259
260static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
261 const unsigned int filter_flags)
262{
263 u32 reg;
264
265
266
267
268
269
270 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
271 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
272 !(filter_flags & FIF_FCSFAIL));
273 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
274 !(filter_flags & FIF_PLCPFAIL));
275 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
276 !(filter_flags & FIF_CONTROL));
277 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
278 !(filter_flags & FIF_PROMISC_IN_BSS));
279 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
280 !(filter_flags & FIF_PROMISC_IN_BSS) &&
281 !rt2x00dev->intf_ap_count);
282 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
283 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
284}
285
286static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
287 struct rt2x00_intf *intf,
288 struct rt2x00intf_conf *conf,
289 const unsigned int flags)
290{
291 unsigned int bcn_preload;
292 u32 reg;
293
294 if (flags & CONFIG_UPDATE_TYPE) {
295
296
297
298 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
299 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
300 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
301 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
302
303
304
305
306 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
307 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
308 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
309 rt2x00_set_field32(®, CSR14_TBCN, 1);
310 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
311 }
312
313 if (flags & CONFIG_UPDATE_MAC)
314 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
315 conf->mac, sizeof(conf->mac));
316
317 if (flags & CONFIG_UPDATE_BSSID)
318 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
319 conf->bssid, sizeof(conf->bssid));
320}
321
322static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
323 struct rt2x00lib_erp *erp)
324{
325 int preamble_mask;
326 u32 reg;
327
328
329
330
331 preamble_mask = erp->short_preamble << 3;
332
333 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
334 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff);
335 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a);
336 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
337 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
338 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
339
340 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
341 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
342 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
343 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
344 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
345
346 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
347 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
348 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
349 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
350 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
351
352 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
353 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
354 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
355 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
356 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
357
358 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
359 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
360 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
361 rt2x00_set_field32(®, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
362 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
363
364 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
365
366 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
367 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
368 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
369
370 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
371 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
372 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
373 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
374
375 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
376 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
377 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
378 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
379
380 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
381 rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
382 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
383 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
384}
385
386static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
387 struct antenna_setup *ant)
388{
389 u8 r1;
390 u8 r4;
391
392
393
394
395
396 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
397 ant->tx == ANTENNA_SW_DIVERSITY);
398
399 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
400 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
401
402
403
404
405 switch (ant->tx) {
406 case ANTENNA_HW_DIVERSITY:
407 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
408 break;
409 case ANTENNA_A:
410 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
411 break;
412 case ANTENNA_B:
413 default:
414 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
415 break;
416 }
417
418
419
420
421 switch (ant->rx) {
422 case ANTENNA_HW_DIVERSITY:
423 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
424 break;
425 case ANTENNA_A:
426 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
427 break;
428 case ANTENNA_B:
429 default:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
431 break;
432 }
433
434 rt2400pci_bbp_write(rt2x00dev, 4, r4);
435 rt2400pci_bbp_write(rt2x00dev, 1, r1);
436}
437
438static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
439 struct rf_channel *rf)
440{
441
442
443
444 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
445 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
446
447 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
448 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
449 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
450
451
452
453
454 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
455 return;
456
457
458
459
460
461
462 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
463 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
464 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
465
466 msleep(1);
467
468 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
469 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
470 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
471
472 msleep(1);
473
474
475
476
477 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
478 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
479
480 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
481 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
482
483
484
485
486 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
487}
488
489static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
490{
491 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
492}
493
494static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
495 struct rt2x00lib_conf *libconf)
496{
497 u32 reg;
498
499 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
500 rt2x00_set_field32(®, CSR11_LONG_RETRY,
501 libconf->conf->long_frame_max_tx_count);
502 rt2x00_set_field32(®, CSR11_SHORT_RETRY,
503 libconf->conf->short_frame_max_tx_count);
504 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
505}
506
507static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
508 struct rt2x00lib_conf *libconf)
509{
510 enum dev_state state =
511 (libconf->conf->flags & IEEE80211_CONF_PS) ?
512 STATE_SLEEP : STATE_AWAKE;
513 u32 reg;
514
515 if (state == STATE_SLEEP) {
516 rt2x00pci_register_read(rt2x00dev, CSR20, ®);
517 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN,
518 (rt2x00dev->beacon_int - 20) * 16);
519 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP,
520 libconf->conf->listen_interval - 1);
521
522
523 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
524 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
525
526 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1);
527 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
528 }
529
530 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
531}
532
533static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
534 struct rt2x00lib_conf *libconf,
535 const unsigned int flags)
536{
537 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
538 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
539 if (flags & IEEE80211_CONF_CHANGE_POWER)
540 rt2400pci_config_txpower(rt2x00dev,
541 libconf->conf->power_level);
542 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
543 rt2400pci_config_retry_limit(rt2x00dev, libconf);
544 if (flags & IEEE80211_CONF_CHANGE_PS)
545 rt2400pci_config_ps(rt2x00dev, libconf);
546}
547
548static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
549 const int cw_min, const int cw_max)
550{
551 u32 reg;
552
553 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
554 rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
555 rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
556 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
557}
558
559
560
561
562static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
563 struct link_qual *qual)
564{
565 u32 reg;
566 u8 bbp;
567
568
569
570
571 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
572 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
573
574
575
576
577 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
578 qual->false_cca = bbp;
579}
580
581static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
582 struct link_qual *qual, u8 vgc_level)
583{
584 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
585 qual->vgc_level = vgc_level;
586 qual->vgc_level_reg = vgc_level;
587}
588
589static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
590 struct link_qual *qual)
591{
592 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
593}
594
595static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
596 struct link_qual *qual, const u32 count)
597{
598
599
600
601
602 if (count > 60 || !(count & 1))
603 return;
604
605
606
607
608 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
609 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
610 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
611 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
612}
613
614
615
616
617static bool rt2400pci_get_entry_state(struct queue_entry *entry)
618{
619 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
620 u32 word;
621
622 if (entry->queue->qid == QID_RX) {
623 rt2x00_desc_read(entry_priv->desc, 0, &word);
624
625 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
626 } else {
627 rt2x00_desc_read(entry_priv->desc, 0, &word);
628
629 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
630 rt2x00_get_field32(word, TXD_W0_VALID));
631 }
632}
633
634static void rt2400pci_clear_entry(struct queue_entry *entry)
635{
636 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
637 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
638 u32 word;
639
640 if (entry->queue->qid == QID_RX) {
641 rt2x00_desc_read(entry_priv->desc, 2, &word);
642 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
643 rt2x00_desc_write(entry_priv->desc, 2, word);
644
645 rt2x00_desc_read(entry_priv->desc, 1, &word);
646 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
647 rt2x00_desc_write(entry_priv->desc, 1, word);
648
649 rt2x00_desc_read(entry_priv->desc, 0, &word);
650 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
651 rt2x00_desc_write(entry_priv->desc, 0, word);
652 } else {
653 rt2x00_desc_read(entry_priv->desc, 0, &word);
654 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
655 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
656 rt2x00_desc_write(entry_priv->desc, 0, word);
657 }
658}
659
660static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
661{
662 struct queue_entry_priv_pci *entry_priv;
663 u32 reg;
664
665
666
667
668 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
669 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
670 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
671 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
672 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
673 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
674
675 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
676 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
677 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
678 entry_priv->desc_dma);
679 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
680
681 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
682 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
683 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
684 entry_priv->desc_dma);
685 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
686
687 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
688 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
689 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
690 entry_priv->desc_dma);
691 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
692
693 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
694 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
695 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
696 entry_priv->desc_dma);
697 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
698
699 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
700 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
701 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
702 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
703
704 entry_priv = rt2x00dev->rx->entries[0].priv_data;
705 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
706 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
707 entry_priv->desc_dma);
708 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
709
710 return 0;
711}
712
713static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
714{
715 u32 reg;
716
717 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
718 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
719 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
720 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
721
722 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
723 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
724 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
725 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
726 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
727
728 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
729 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
730 (rt2x00dev->rx->data_size / 128));
731 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
732
733 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
734 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
735 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
736 rt2x00_set_field32(®, CSR14_TBCN, 0);
737 rt2x00_set_field32(®, CSR14_TCFP, 0);
738 rt2x00_set_field32(®, CSR14_TATIMW, 0);
739 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
740 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
741 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
742 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
743
744 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
745
746 rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
747 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
748 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
749 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
750 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
751 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
752
753 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
754 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3);
755 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
756 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32);
757 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
758 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36);
759 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
760 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
761
762 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
763
764 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
765 return -EBUSY;
766
767 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
768 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
769
770 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
771 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
772 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
773
774 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
775 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
776 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
777 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
778 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
779 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
780
781 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
782 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
783 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
784 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
785 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
786
787 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
788 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
789 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
790 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
791
792
793
794
795
796
797 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
798 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
799
800 return 0;
801}
802
803static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
804{
805 unsigned int i;
806 u8 value;
807
808 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
809 rt2400pci_bbp_read(rt2x00dev, 0, &value);
810 if ((value != 0xff) && (value != 0x00))
811 return 0;
812 udelay(REGISTER_BUSY_DELAY);
813 }
814
815 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
816 return -EACCES;
817}
818
819static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
820{
821 unsigned int i;
822 u16 eeprom;
823 u8 reg_id;
824 u8 value;
825
826 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
827 return -EACCES;
828
829 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
830 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
831 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
832 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
833 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
834 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
835 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
836 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
837 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
838 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
839 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
840 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
841 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
842 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
843
844 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
845 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
846
847 if (eeprom != 0xffff && eeprom != 0x0000) {
848 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
849 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
850 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
851 }
852 }
853
854 return 0;
855}
856
857
858
859
860static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
861 enum dev_state state)
862{
863 u32 reg;
864
865 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
866 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
867 (state == STATE_RADIO_RX_OFF) ||
868 (state == STATE_RADIO_RX_OFF_LINK));
869 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
870}
871
872static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
873 enum dev_state state)
874{
875 int mask = (state == STATE_RADIO_IRQ_OFF);
876 u32 reg;
877
878
879
880
881
882 if (state == STATE_RADIO_IRQ_ON) {
883 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
884 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
885 }
886
887
888
889
890
891 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
892 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
893 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
894 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
895 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
896 rt2x00_set_field32(®, CSR8_RXDONE, mask);
897 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
898}
899
900static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
901{
902
903
904
905 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
906 rt2400pci_init_registers(rt2x00dev) ||
907 rt2400pci_init_bbp(rt2x00dev)))
908 return -EIO;
909
910 return 0;
911}
912
913static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
914{
915
916
917
918 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
919}
920
921static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
922 enum dev_state state)
923{
924 u32 reg;
925 unsigned int i;
926 char put_to_sleep;
927 char bbp_state;
928 char rf_state;
929
930 put_to_sleep = (state != STATE_AWAKE);
931
932 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
933 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
934 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
935 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
936 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
937 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
938
939
940
941
942
943
944 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
945 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
946 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
947 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
948 if (bbp_state == state && rf_state == state)
949 return 0;
950 msleep(10);
951 }
952
953 return -EBUSY;
954}
955
956static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
957 enum dev_state state)
958{
959 int retval = 0;
960
961 switch (state) {
962 case STATE_RADIO_ON:
963 retval = rt2400pci_enable_radio(rt2x00dev);
964 break;
965 case STATE_RADIO_OFF:
966 rt2400pci_disable_radio(rt2x00dev);
967 break;
968 case STATE_RADIO_RX_ON:
969 case STATE_RADIO_RX_ON_LINK:
970 case STATE_RADIO_RX_OFF:
971 case STATE_RADIO_RX_OFF_LINK:
972 rt2400pci_toggle_rx(rt2x00dev, state);
973 break;
974 case STATE_RADIO_IRQ_ON:
975 case STATE_RADIO_IRQ_OFF:
976 rt2400pci_toggle_irq(rt2x00dev, state);
977 break;
978 case STATE_DEEP_SLEEP:
979 case STATE_SLEEP:
980 case STATE_STANDBY:
981 case STATE_AWAKE:
982 retval = rt2400pci_set_state(rt2x00dev, state);
983 break;
984 default:
985 retval = -ENOTSUPP;
986 break;
987 }
988
989 if (unlikely(retval))
990 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
991 state, retval);
992
993 return retval;
994}
995
996
997
998
999static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1000 struct sk_buff *skb,
1001 struct txentry_desc *txdesc)
1002{
1003 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1004 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1005 __le32 *txd = skbdesc->desc;
1006 u32 word;
1007
1008
1009
1010
1011 rt2x00_desc_read(entry_priv->desc, 1, &word);
1012 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1013 rt2x00_desc_write(entry_priv->desc, 1, word);
1014
1015 rt2x00_desc_read(txd, 2, &word);
1016 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1017 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1018 rt2x00_desc_write(txd, 2, word);
1019
1020 rt2x00_desc_read(txd, 3, &word);
1021 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1022 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1023 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1024 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1025 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1026 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1027 rt2x00_desc_write(txd, 3, word);
1028
1029 rt2x00_desc_read(txd, 4, &word);
1030 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1031 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1032 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1033 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1034 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1035 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1036 rt2x00_desc_write(txd, 4, word);
1037
1038 rt2x00_desc_read(txd, 0, &word);
1039 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1040 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1041 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1042 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1043 rt2x00_set_field32(&word, TXD_W0_ACK,
1044 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1045 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1046 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1047 rt2x00_set_field32(&word, TXD_W0_RTS,
1048 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1049 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1050 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1051 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1052 rt2x00_desc_write(txd, 0, word);
1053}
1054
1055
1056
1057
1058static void rt2400pci_write_beacon(struct queue_entry *entry)
1059{
1060 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1061 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1062 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1063 u32 word;
1064 u32 reg;
1065
1066
1067
1068
1069
1070 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1071 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1072 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1073
1074
1075
1076
1077
1078
1079
1080 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1081 skbdesc->desc = entry_priv->desc;
1082
1083 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1084
1085 rt2x00_desc_read(entry_priv->desc, 1, &word);
1086 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1087 rt2x00_desc_write(entry_priv->desc, 1, word);
1088}
1089
1090static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1091 const enum data_queue_qid queue)
1092{
1093 u32 reg;
1094
1095 if (queue == QID_BEACON) {
1096 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1097 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1098 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
1099 rt2x00_set_field32(®, CSR14_TBCN, 1);
1100 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1101 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1102 }
1103 return;
1104 }
1105
1106 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1107 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1108 rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1109 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1110 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1111}
1112
1113static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1114 const enum data_queue_qid qid)
1115{
1116 u32 reg;
1117
1118 if (qid == QID_BEACON) {
1119 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1120 } else {
1121 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1122 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
1123 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1124 }
1125}
1126
1127
1128
1129
1130static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1131 struct rxdone_entry_desc *rxdesc)
1132{
1133 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1134 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1135 u32 word0;
1136 u32 word2;
1137 u32 word3;
1138 u32 word4;
1139 u64 tsf;
1140 u32 rx_low;
1141 u32 rx_high;
1142
1143 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1144 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1145 rt2x00_desc_read(entry_priv->desc, 3, &word3);
1146 rt2x00_desc_read(entry_priv->desc, 4, &word4);
1147
1148 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1149 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1150 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1151 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1163 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1164 rx_high = upper_32_bits(tsf);
1165
1166 if ((u32)tsf <= rx_low)
1167 rx_high--;
1168
1169
1170
1171
1172
1173
1174 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1175 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1176 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1177 entry->queue->rt2x00dev->rssi_offset;
1178 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1179
1180 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1181 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1182 rxdesc->dev_flags |= RXDONE_MY_BSS;
1183}
1184
1185
1186
1187
1188static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1189 const enum data_queue_qid queue_idx)
1190{
1191 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1192 struct queue_entry_priv_pci *entry_priv;
1193 struct queue_entry *entry;
1194 struct txdone_entry_desc txdesc;
1195 u32 word;
1196
1197 while (!rt2x00queue_empty(queue)) {
1198 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1199 entry_priv = entry->priv_data;
1200 rt2x00_desc_read(entry_priv->desc, 0, &word);
1201
1202 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1203 !rt2x00_get_field32(word, TXD_W0_VALID))
1204 break;
1205
1206
1207
1208
1209 txdesc.flags = 0;
1210 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1211 case 0:
1212 case 1:
1213 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1214 break;
1215 case 2:
1216 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1217
1218 default:
1219 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1220 }
1221 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1222
1223 rt2x00lib_txdone(entry, &txdesc);
1224 }
1225}
1226
1227static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1228{
1229 struct rt2x00_dev *rt2x00dev = dev_instance;
1230 u32 reg;
1231
1232
1233
1234
1235
1236 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1237 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1238
1239 if (!reg)
1240 return IRQ_NONE;
1241
1242 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1243 return IRQ_HANDLED;
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1255 rt2x00lib_beacondone(rt2x00dev);
1256
1257
1258
1259
1260 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1261 rt2x00pci_rxdone(rt2x00dev);
1262
1263
1264
1265
1266 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1267 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1268
1269
1270
1271
1272 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1273 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1274
1275
1276
1277
1278 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1279 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1280
1281 return IRQ_HANDLED;
1282}
1283
1284
1285
1286
1287static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1288{
1289 struct eeprom_93cx6 eeprom;
1290 u32 reg;
1291 u16 word;
1292 u8 *mac;
1293
1294 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1295
1296 eeprom.data = rt2x00dev;
1297 eeprom.register_read = rt2400pci_eepromregister_read;
1298 eeprom.register_write = rt2400pci_eepromregister_write;
1299 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1300 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1301 eeprom.reg_data_in = 0;
1302 eeprom.reg_data_out = 0;
1303 eeprom.reg_data_clock = 0;
1304 eeprom.reg_chip_select = 0;
1305
1306 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1307 EEPROM_SIZE / sizeof(u16));
1308
1309
1310
1311
1312 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1313 if (!is_valid_ether_addr(mac)) {
1314 random_ether_addr(mac);
1315 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1316 }
1317
1318 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1319 if (word == 0xffff) {
1320 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1321 return -EINVAL;
1322 }
1323
1324 return 0;
1325}
1326
1327static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1328{
1329 u32 reg;
1330 u16 value;
1331 u16 eeprom;
1332
1333
1334
1335
1336 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1337
1338
1339
1340
1341 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1342 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1343 rt2x00_set_chip_rf(rt2x00dev, value, reg);
1344
1345 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1346 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1347 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1348 return -ENODEV;
1349 }
1350
1351
1352
1353
1354 rt2x00dev->default_ant.tx =
1355 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1356 rt2x00dev->default_ant.rx =
1357 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1358
1359
1360
1361
1362
1363
1364
1365 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1366 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1367 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1368 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1369
1370
1371
1372
1373#ifdef CONFIG_RT2X00_LIB_LEDS
1374 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1375
1376 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1377 if (value == LED_MODE_TXRX_ACTIVITY ||
1378 value == LED_MODE_DEFAULT ||
1379 value == LED_MODE_ASUS)
1380 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1381 LED_TYPE_ACTIVITY);
1382#endif
1383
1384
1385
1386
1387 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1388 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1389
1390
1391
1392
1393 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1394 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1395
1396 return 0;
1397}
1398
1399
1400
1401
1402
1403static const struct rf_channel rf_vals_b[] = {
1404 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1405 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1406 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1407 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1408 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1409 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1410 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1411 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1412 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1413 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1414 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1415 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1416 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1417 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1418};
1419
1420static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1421{
1422 struct hw_mode_spec *spec = &rt2x00dev->spec;
1423 struct channel_info *info;
1424 char *tx_power;
1425 unsigned int i;
1426
1427
1428
1429
1430 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1431 IEEE80211_HW_SIGNAL_DBM |
1432 IEEE80211_HW_SUPPORTS_PS |
1433 IEEE80211_HW_PS_NULLFUNC_STACK;
1434 rt2x00dev->hw->extra_tx_headroom = 0;
1435
1436 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1437 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1438 rt2x00_eeprom_addr(rt2x00dev,
1439 EEPROM_MAC_ADDR_0));
1440
1441
1442
1443
1444 spec->supported_bands = SUPPORT_BAND_2GHZ;
1445 spec->supported_rates = SUPPORT_RATE_CCK;
1446
1447 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1448 spec->channels = rf_vals_b;
1449
1450
1451
1452
1453 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1454 if (!info)
1455 return -ENOMEM;
1456
1457 spec->channels_info = info;
1458
1459 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1460 for (i = 0; i < 14; i++)
1461 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1462
1463 return 0;
1464}
1465
1466static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1467{
1468 int retval;
1469
1470
1471
1472
1473 retval = rt2400pci_validate_eeprom(rt2x00dev);
1474 if (retval)
1475 return retval;
1476
1477 retval = rt2400pci_init_eeprom(rt2x00dev);
1478 if (retval)
1479 return retval;
1480
1481
1482
1483
1484 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1485 if (retval)
1486 return retval;
1487
1488
1489
1490
1491 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1492 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1493
1494
1495
1496
1497 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1498
1499 return 0;
1500}
1501
1502
1503
1504
1505static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1506 const struct ieee80211_tx_queue_params *params)
1507{
1508 struct rt2x00_dev *rt2x00dev = hw->priv;
1509
1510
1511
1512
1513
1514
1515 if (queue != 0)
1516 return -EINVAL;
1517
1518 if (rt2x00mac_conf_tx(hw, queue, params))
1519 return -EINVAL;
1520
1521
1522
1523
1524 rt2400pci_config_cw(rt2x00dev,
1525 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1526
1527 return 0;
1528}
1529
1530static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1531{
1532 struct rt2x00_dev *rt2x00dev = hw->priv;
1533 u64 tsf;
1534 u32 reg;
1535
1536 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1537 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1538 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1539 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1540
1541 return tsf;
1542}
1543
1544static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1545{
1546 struct rt2x00_dev *rt2x00dev = hw->priv;
1547 u32 reg;
1548
1549 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1550 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1551}
1552
1553static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1554 .tx = rt2x00mac_tx,
1555 .start = rt2x00mac_start,
1556 .stop = rt2x00mac_stop,
1557 .add_interface = rt2x00mac_add_interface,
1558 .remove_interface = rt2x00mac_remove_interface,
1559 .config = rt2x00mac_config,
1560 .configure_filter = rt2x00mac_configure_filter,
1561 .set_tim = rt2x00mac_set_tim,
1562 .get_stats = rt2x00mac_get_stats,
1563 .bss_info_changed = rt2x00mac_bss_info_changed,
1564 .conf_tx = rt2400pci_conf_tx,
1565 .get_tx_stats = rt2x00mac_get_tx_stats,
1566 .get_tsf = rt2400pci_get_tsf,
1567 .tx_last_beacon = rt2400pci_tx_last_beacon,
1568 .rfkill_poll = rt2x00mac_rfkill_poll,
1569};
1570
1571static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1572 .irq_handler = rt2400pci_interrupt,
1573 .probe_hw = rt2400pci_probe_hw,
1574 .initialize = rt2x00pci_initialize,
1575 .uninitialize = rt2x00pci_uninitialize,
1576 .get_entry_state = rt2400pci_get_entry_state,
1577 .clear_entry = rt2400pci_clear_entry,
1578 .set_device_state = rt2400pci_set_device_state,
1579 .rfkill_poll = rt2400pci_rfkill_poll,
1580 .link_stats = rt2400pci_link_stats,
1581 .reset_tuner = rt2400pci_reset_tuner,
1582 .link_tuner = rt2400pci_link_tuner,
1583 .write_tx_desc = rt2400pci_write_tx_desc,
1584 .write_tx_data = rt2x00pci_write_tx_data,
1585 .write_beacon = rt2400pci_write_beacon,
1586 .kick_tx_queue = rt2400pci_kick_tx_queue,
1587 .kill_tx_queue = rt2400pci_kill_tx_queue,
1588 .fill_rxdone = rt2400pci_fill_rxdone,
1589 .config_filter = rt2400pci_config_filter,
1590 .config_intf = rt2400pci_config_intf,
1591 .config_erp = rt2400pci_config_erp,
1592 .config_ant = rt2400pci_config_ant,
1593 .config = rt2400pci_config,
1594};
1595
1596static const struct data_queue_desc rt2400pci_queue_rx = {
1597 .entry_num = RX_ENTRIES,
1598 .data_size = DATA_FRAME_SIZE,
1599 .desc_size = RXD_DESC_SIZE,
1600 .priv_size = sizeof(struct queue_entry_priv_pci),
1601};
1602
1603static const struct data_queue_desc rt2400pci_queue_tx = {
1604 .entry_num = TX_ENTRIES,
1605 .data_size = DATA_FRAME_SIZE,
1606 .desc_size = TXD_DESC_SIZE,
1607 .priv_size = sizeof(struct queue_entry_priv_pci),
1608};
1609
1610static const struct data_queue_desc rt2400pci_queue_bcn = {
1611 .entry_num = BEACON_ENTRIES,
1612 .data_size = MGMT_FRAME_SIZE,
1613 .desc_size = TXD_DESC_SIZE,
1614 .priv_size = sizeof(struct queue_entry_priv_pci),
1615};
1616
1617static const struct data_queue_desc rt2400pci_queue_atim = {
1618 .entry_num = ATIM_ENTRIES,
1619 .data_size = DATA_FRAME_SIZE,
1620 .desc_size = TXD_DESC_SIZE,
1621 .priv_size = sizeof(struct queue_entry_priv_pci),
1622};
1623
1624static const struct rt2x00_ops rt2400pci_ops = {
1625 .name = KBUILD_MODNAME,
1626 .max_sta_intf = 1,
1627 .max_ap_intf = 1,
1628 .eeprom_size = EEPROM_SIZE,
1629 .rf_size = RF_SIZE,
1630 .tx_queues = NUM_TX_QUEUES,
1631 .rx = &rt2400pci_queue_rx,
1632 .tx = &rt2400pci_queue_tx,
1633 .bcn = &rt2400pci_queue_bcn,
1634 .atim = &rt2400pci_queue_atim,
1635 .lib = &rt2400pci_rt2x00_ops,
1636 .hw = &rt2400pci_mac80211_ops,
1637#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1638 .debugfs = &rt2400pci_rt2x00debug,
1639#endif
1640};
1641
1642
1643
1644
1645static struct pci_device_id rt2400pci_device_table[] = {
1646 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1647 { 0, }
1648};
1649
1650MODULE_AUTHOR(DRV_PROJECT);
1651MODULE_VERSION(DRV_VERSION);
1652MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1653MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1654MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1655MODULE_LICENSE("GPL");
1656
1657static struct pci_driver rt2400pci_driver = {
1658 .name = KBUILD_MODNAME,
1659 .id_table = rt2400pci_device_table,
1660 .probe = rt2x00pci_probe,
1661 .remove = __devexit_p(rt2x00pci_remove),
1662 .suspend = rt2x00pci_suspend,
1663 .resume = rt2x00pci_resume,
1664};
1665
1666static int __init rt2400pci_init(void)
1667{
1668 return pci_register_driver(&rt2400pci_driver);
1669}
1670
1671static void __exit rt2400pci_exit(void)
1672{
1673 pci_unregister_driver(&rt2400pci_driver);
1674}
1675
1676module_init(rt2400pci_init);
1677module_exit(rt2400pci_exit);
1678