1/* 2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the 17 Free Software Foundation, Inc., 18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21/* 22 Module: rt2x00 23 Abstract: rt2x00 queue datastructures and routines 24 */ 25 26#ifndef RT2X00QUEUE_H 27#define RT2X00QUEUE_H 28 29#include <linux/prefetch.h> 30 31/** 32 * DOC: Entry frame size 33 * 34 * Ralink PCI devices demand the Frame size to be a multiple of 128 bytes, 35 * for USB devices this restriction does not apply, but the value of 36 * 2432 makes sense since it is big enough to contain the maximum fragment 37 * size according to the ieee802.11 specs. 38 * The aggregation size depends on support from the driver, but should 39 * be something around 3840 bytes. 40 */ 41#define DATA_FRAME_SIZE 2432 42#define MGMT_FRAME_SIZE 256 43#define AGGREGATION_SIZE 3840 44 45/** 46 * DOC: Number of entries per queue 47 * 48 * Under normal load without fragmentation, 12 entries are sufficient 49 * without the queue being filled up to the maximum. When using fragmentation 50 * and the queue threshold code, we need to add some additional margins to 51 * make sure the queue will never (or only under extreme load) fill up 52 * completely. 53 * Since we don't use preallocated DMA, having a large number of queue entries 54 * will have minimal impact on the memory requirements for the queue. 55 */ 56#define RX_ENTRIES 24 57#define TX_ENTRIES 24 58#define BEACON_ENTRIES 1 59#define ATIM_ENTRIES 8 60 61/** 62 * enum data_queue_qid: Queue identification 63 * 64 * @QID_AC_BE: AC BE queue 65 * @QID_AC_BK: AC BK queue 66 * @QID_AC_VI: AC VI queue 67 * @QID_AC_VO: AC VO queue 68 * @QID_HCCA: HCCA queue 69 * @QID_MGMT: MGMT queue (prio queue) 70 * @QID_RX: RX queue 71 * @QID_OTHER: None of the above (don't use, only present for completeness) 72 * @QID_BEACON: Beacon queue (value unspecified, don't send it to device) 73 * @QID_ATIM: Atim queue (value unspeficied, don't send it to device) 74 */ 75enum data_queue_qid { 76 QID_AC_BE = 0, 77 QID_AC_BK = 1, 78 QID_AC_VI = 2, 79 QID_AC_VO = 3, 80 QID_HCCA = 4, 81 QID_MGMT = 13, 82 QID_RX = 14, 83 QID_OTHER = 15, 84 QID_BEACON, 85 QID_ATIM, 86}; 87 88/** 89 * enum skb_frame_desc_flags: Flags for &struct skb_frame_desc 90 * 91 * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX 92 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX 93 * @SKBDESC_IV_STRIPPED: Frame contained a IV/EIV provided by 94 * mac80211 but was stripped for processing by the driver. 95 * @SKBDESC_L2_PADDED: Payload has been padded for 4-byte alignment, 96 * the padded bytes are located between header and payload. 97 */ 98enum skb_frame_desc_flags { 99 SKBDESC_DMA_MAPPED_RX = 1 << 0, 100 SKBDESC_DMA_MAPPED_TX = 1 << 1, 101 SKBDESC_IV_STRIPPED = 1 << 2, 102 SKBDESC_L2_PADDED = 1 << 3 103}; 104 105/** 106 * struct skb_frame_desc: Descriptor information for the skb buffer 107 * 108 * This structure is placed over the driver_data array, this means that 109 * this structure should not exceed the size of that array (40 bytes). 110 * 111 * @flags: Frame flags, see &enum skb_frame_desc_flags. 112 * @desc_len: Length of the frame descriptor. 113 * @tx_rate_idx: the index of the TX rate, used for TX status reporting 114 * @tx_rate_flags: the TX rate flags, used for TX status reporting 115 * @desc: Pointer to descriptor part of the frame. 116 * Note that this pointer could point to something outside 117 * of the scope of the skb->data pointer. 118 * @iv: IV/EIV data used during encryption/decryption. 119 * @skb_dma: (PCI-only) the DMA address associated with the sk buffer. 120 * @entry: The entry to which this sk buffer belongs. 121 */ 122struct skb_frame_desc { 123 u8 flags; 124 125 u8 desc_len; 126 u8 tx_rate_idx; 127 u8 tx_rate_flags; 128 129 void *desc; 130 131 __le32 iv[2]; 132 133 dma_addr_t skb_dma; 134 135 struct queue_entry *entry; 136}; 137 138/** 139 * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff. 140 * @skb: &struct sk_buff from where we obtain the &struct skb_frame_desc 141 */ 142static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb) 143{ 144 BUILD_BUG_ON(sizeof(struct skb_frame_desc) > 145 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 146 return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data; 147} 148 149/** 150 * enum rxdone_entry_desc_flags: Flags for &struct rxdone_entry_desc 151 * 152 * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value. 153 * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value. 154 * @RXDONE_SIGNAL_MCS: Signal field contains the mcs value. 155 * @RXDONE_MY_BSS: Does this frame originate from device's BSS. 156 * @RXDONE_CRYPTO_IV: Driver provided IV/EIV data. 157 * @RXDONE_CRYPTO_ICV: Driver provided ICV data. 158 * @RXDONE_L2PAD: 802.11 payload has been padded to 4-byte boundary. 159 */ 160enum rxdone_entry_desc_flags { 161 RXDONE_SIGNAL_PLCP = BIT(0), 162 RXDONE_SIGNAL_BITRATE = BIT(1), 163 RXDONE_SIGNAL_MCS = BIT(2), 164 RXDONE_MY_BSS = BIT(3), 165 RXDONE_CRYPTO_IV = BIT(4), 166 RXDONE_CRYPTO_ICV = BIT(5), 167 RXDONE_L2PAD = BIT(6), 168}; 169 170/** 171 * RXDONE_SIGNAL_MASK - Define to mask off all &rxdone_entry_desc_flags flags 172 * except for the RXDONE_SIGNAL_* flags. This is useful to convert the dev_flags 173 * from &rxdone_entry_desc to a signal value type. 174 */ 175#define RXDONE_SIGNAL_MASK \ 176 ( RXDONE_SIGNAL_PLCP | RXDONE_SIGNAL_BITRATE | RXDONE_SIGNAL_MCS ) 177 178/** 179 * struct rxdone_entry_desc: RX Entry descriptor 180 * 181 * Summary of information that has been read from the RX frame descriptor. 182 * 183 * @timestamp: RX Timestamp 184 * @signal: Signal of the received frame. 185 * @rssi: RSSI of the received frame. 186 * @noise: Measured noise during frame reception. 187 * @size: Data size of the received frame. 188 * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags). 189 * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags). 190 * @rate_mode: Rate mode (See @enum rate_modulation). 191 * @cipher: Cipher type used during decryption. 192 * @cipher_status: Decryption status. 193 * @iv: IV/EIV data used during decryption. 194 * @icv: ICV data used during decryption. 195 */ 196struct rxdone_entry_desc { 197 u64 timestamp; 198 int signal; 199 int rssi; 200 int noise; 201 int size; 202 int flags; 203 int dev_flags; 204 u16 rate_mode; 205 u8 cipher; 206 u8 cipher_status; 207 208 __le32 iv[2]; 209 __le32 icv; 210}; 211 212/** 213 * enum txdone_entry_desc_flags: Flags for &struct txdone_entry_desc 214 * 215 * @TXDONE_UNKNOWN: Hardware could not determine success of transmission. 216 * @TXDONE_SUCCESS: Frame was successfully send 217 * @TXDONE_FALLBACK: Frame was successfully send using a fallback rate. 218 * @TXDONE_FAILURE: Frame was not successfully send 219 * @TXDONE_EXCESSIVE_RETRY: In addition to &TXDONE_FAILURE, the 220 * frame transmission failed due to excessive retries. 221 */ 222enum txdone_entry_desc_flags { 223 TXDONE_UNKNOWN, 224 TXDONE_SUCCESS, 225 TXDONE_FALLBACK, 226 TXDONE_FAILURE, 227 TXDONE_EXCESSIVE_RETRY, 228}; 229 230/** 231 * struct txdone_entry_desc: TX done entry descriptor 232 * 233 * Summary of information that has been read from the TX frame descriptor 234 * after the device is done with transmission. 235 * 236 * @flags: TX done flags (See &enum txdone_entry_desc_flags). 237 * @retry: Retry count. 238 */ 239struct txdone_entry_desc { 240 unsigned long flags; 241 int retry; 242}; 243 244/** 245 * enum txentry_desc_flags: Status flags for TX entry descriptor 246 * 247 * @ENTRY_TXD_RTS_FRAME: This frame is a RTS frame. 248 * @ENTRY_TXD_CTS_FRAME: This frame is a CTS-to-self frame. 249 * @ENTRY_TXD_GENERATE_SEQ: This frame requires sequence counter. 250 * @ENTRY_TXD_FIRST_FRAGMENT: This is the first frame. 251 * @ENTRY_TXD_MORE_FRAG: This frame is followed by another fragment. 252 * @ENTRY_TXD_REQ_TIMESTAMP: Require timestamp to be inserted. 253 * @ENTRY_TXD_BURST: This frame belongs to the same burst event. 254 * @ENTRY_TXD_ACK: An ACK is required for this frame. 255 * @ENTRY_TXD_RETRY_MODE: When set, the long retry count is used. 256 * @ENTRY_TXD_ENCRYPT: This frame should be encrypted. 257 * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared). 258 * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware. 259 * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware. 260 * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU. 261 * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth. 262 * @ENTRY_TXD_HT_SHORT_GI: Use short GI. 263 */ 264enum txentry_desc_flags { 265 ENTRY_TXD_RTS_FRAME, 266 ENTRY_TXD_CTS_FRAME, 267 ENTRY_TXD_GENERATE_SEQ, 268 ENTRY_TXD_FIRST_FRAGMENT, 269 ENTRY_TXD_MORE_FRAG, 270 ENTRY_TXD_REQ_TIMESTAMP, 271 ENTRY_TXD_BURST, 272 ENTRY_TXD_ACK, 273 ENTRY_TXD_RETRY_MODE, 274 ENTRY_TXD_ENCRYPT, 275 ENTRY_TXD_ENCRYPT_PAIRWISE, 276 ENTRY_TXD_ENCRYPT_IV, 277 ENTRY_TXD_ENCRYPT_MMIC, 278 ENTRY_TXD_HT_AMPDU, 279 ENTRY_TXD_HT_BW_40, 280 ENTRY_TXD_HT_SHORT_GI, 281}; 282 283/** 284 * struct txentry_desc: TX Entry descriptor 285 * 286 * Summary of information for the frame descriptor before sending a TX frame. 287 * 288 * @flags: Descriptor flags (See &enum queue_entry_flags). 289 * @queue: Queue identification (See &enum data_queue_qid). 290 * @header_length: Length of 802.11 header. 291 * @l2pad: Amount of padding to align 802.11 payload to 4-byte boundrary. 292 * @length_high: PLCP length high word. 293 * @length_low: PLCP length low word. 294 * @signal: PLCP signal. 295 * @service: PLCP service. 296 * @msc: MCS. 297 * @stbc: STBC. 298 * @ba_size: BA size. 299 * @rate_mode: Rate mode (See @enum rate_modulation). 300 * @mpdu_density: MDPU density. 301 * @retry_limit: Max number of retries. 302 * @aifs: AIFS value. 303 * @ifs: IFS value. 304 * @cw_min: cwmin value. 305 * @cw_max: cwmax value. 306 * @cipher: Cipher type used for encryption. 307 * @key_idx: Key index used for encryption. 308 * @iv_offset: Position where IV should be inserted by hardware. 309 * @iv_len: Length of IV data. 310 */ 311struct txentry_desc { 312 unsigned long flags; 313 314 enum data_queue_qid queue; 315 316 u16 header_length; 317 u16 l2pad; 318 319 u16 length_high; 320 u16 length_low; 321 u16 signal; 322 u16 service; 323 324 u16 mcs; 325 u16 stbc; 326 u16 ba_size; 327 u16 rate_mode; 328 u16 mpdu_density; 329 330 short retry_limit; 331 short aifs; 332 short ifs; 333 short cw_min; 334 short cw_max; 335 336 enum cipher cipher; 337 u16 key_idx; 338 u16 iv_offset; 339 u16 iv_len; 340}; 341 342/** 343 * enum queue_entry_flags: Status flags for queue entry 344 * 345 * @ENTRY_BCN_ASSIGNED: This entry has been assigned to an interface. 346 * As long as this bit is set, this entry may only be touched 347 * through the interface structure. 348 * @ENTRY_OWNER_DEVICE_DATA: This entry is owned by the device for data 349 * transfer (either TX or RX depending on the queue). The entry should 350 * only be touched after the device has signaled it is done with it. 351 * @ENTRY_OWNER_DEVICE_CRYPTO: This entry is owned by the device for data 352 * encryption or decryption. The entry should only be touched after 353 * the device has signaled it is done with it. 354 * @ENTRY_DATA_PENDING: This entry contains a valid frame and is waiting 355 * for the signal to start sending. 356 */ 357enum queue_entry_flags { 358 ENTRY_BCN_ASSIGNED, 359 ENTRY_OWNER_DEVICE_DATA, 360 ENTRY_OWNER_DEVICE_CRYPTO, 361 ENTRY_DATA_PENDING, 362}; 363 364/** 365 * struct queue_entry: Entry inside the &struct data_queue 366 * 367 * @flags: Entry flags, see &enum queue_entry_flags. 368 * @queue: The data queue (&struct data_queue) to which this entry belongs. 369 * @skb: The buffer which is currently being transmitted (for TX queue), 370 * or used to directly recieve data in (for RX queue). 371 * @entry_idx: The entry index number. 372 * @priv_data: Private data belonging to this queue entry. The pointer 373 * points to data specific to a particular driver and queue type. 374 */ 375struct queue_entry { 376 unsigned long flags; 377 378 struct data_queue *queue; 379 380 struct sk_buff *skb; 381 382 unsigned int entry_idx; 383 384 void *priv_data; 385}; 386 387/** 388 * enum queue_index: Queue index type 389 * 390 * @Q_INDEX: Index pointer to the current entry in the queue, if this entry is 391 * owned by the hardware then the queue is considered to be full. 392 * @Q_INDEX_DONE: Index pointer to the next entry which will be completed by 393 * the hardware and for which we need to run the txdone handler. If this 394 * entry is not owned by the hardware the queue is considered to be empty. 395 * @Q_INDEX_CRYPTO: Index pointer to the next entry which encryption/decription 396 * will be completed by the hardware next. 397 * @Q_INDEX_MAX: Keep last, used in &struct data_queue to determine the size 398 * of the index array. 399 */ 400enum queue_index { 401 Q_INDEX, 402 Q_INDEX_DONE, 403 Q_INDEX_CRYPTO, 404 Q_INDEX_MAX, 405}; 406 407/** 408 * struct data_queue: Data queue 409 * 410 * @rt2x00dev: Pointer to main &struct rt2x00dev where this queue belongs to. 411 * @entries: Base address of the &struct queue_entry which are 412 * part of this queue. 413 * @qid: The queue identification, see &enum data_queue_qid. 414 * @lock: Spinlock to protect index handling. Whenever @index, @index_done or 415 * @index_crypt needs to be changed this lock should be grabbed to prevent 416 * index corruption due to concurrency. 417 * @count: Number of frames handled in the queue. 418 * @limit: Maximum number of entries in the queue. 419 * @threshold: Minimum number of free entries before queue is kicked by force. 420 * @length: Number of frames in queue. 421 * @index: Index pointers to entry positions in the queue, 422 * use &enum queue_index to get a specific index field. 423 * @txop: maximum burst time. 424 * @aifs: The aifs value for outgoing frames (field ignored in RX queue). 425 * @cw_min: The cw min value for outgoing frames (field ignored in RX queue). 426 * @cw_max: The cw max value for outgoing frames (field ignored in RX queue). 427 * @data_size: Maximum data size for the frames in this queue. 428 * @desc_size: Hardware descriptor size for the data in this queue. 429 * @usb_endpoint: Device endpoint used for communication (USB only) 430 * @usb_maxpacket: Max packet size for given endpoint (USB only) 431 */ 432struct data_queue { 433 struct rt2x00_dev *rt2x00dev; 434 struct queue_entry *entries; 435 436 enum data_queue_qid qid; 437 438 spinlock_t lock; 439 unsigned int count; 440 unsigned short limit; 441 unsigned short threshold; 442 unsigned short length; 443 unsigned short index[Q_INDEX_MAX]; 444 445 unsigned short txop; 446 unsigned short aifs; 447 unsigned short cw_min; 448 unsigned short cw_max; 449 450 unsigned short data_size; 451 unsigned short desc_size; 452 453 unsigned short usb_endpoint; 454 unsigned short usb_maxpacket; 455}; 456 457/** 458 * struct data_queue_desc: Data queue description 459 * 460 * The information in this structure is used by drivers 461 * to inform rt2x00lib about the creation of the data queue. 462 * 463 * @entry_num: Maximum number of entries for a queue. 464 * @data_size: Maximum data size for the frames in this queue. 465 * @desc_size: Hardware descriptor size for the data in this queue. 466 * @priv_size: Size of per-queue_entry private data. 467 */ 468struct data_queue_desc { 469 unsigned short entry_num; 470 unsigned short data_size; 471 unsigned short desc_size; 472 unsigned short priv_size; 473}; 474 475/** 476 * queue_end - Return pointer to the last queue (HELPER MACRO). 477 * @__dev: Pointer to &struct rt2x00_dev 478 * 479 * Using the base rx pointer and the maximum number of available queues, 480 * this macro will return the address of 1 position beyond the end of the 481 * queues array. 482 */ 483#define queue_end(__dev) \ 484 &(__dev)->rx[(__dev)->data_queues] 485 486/** 487 * tx_queue_end - Return pointer to the last TX queue (HELPER MACRO). 488 * @__dev: Pointer to &struct rt2x00_dev 489 * 490 * Using the base tx pointer and the maximum number of available TX 491 * queues, this macro will return the address of 1 position beyond 492 * the end of the TX queue array. 493 */ 494#define tx_queue_end(__dev) \ 495 &(__dev)->tx[(__dev)->ops->tx_queues] 496 497/** 498 * queue_next - Return pointer to next queue in list (HELPER MACRO). 499 * @__queue: Current queue for which we need the next queue 500 * 501 * Using the current queue address we take the address directly 502 * after the queue to take the next queue. Note that this macro 503 * should be used carefully since it does not protect against 504 * moving past the end of the list. (See macros &queue_end and 505 * &tx_queue_end for determining the end of the queue). 506 */ 507#define queue_next(__queue) \ 508 &(__queue)[1] 509 510/** 511 * queue_loop - Loop through the queues within a specific range (HELPER MACRO). 512 * @__entry: Pointer where the current queue entry will be stored in. 513 * @__start: Start queue pointer. 514 * @__end: End queue pointer. 515 * 516 * This macro will loop through all queues between &__start and &__end. 517 */ 518#define queue_loop(__entry, __start, __end) \ 519 for ((__entry) = (__start); \ 520 prefetch(queue_next(__entry)), (__entry) != (__end);\ 521 (__entry) = queue_next(__entry)) 522 523/** 524 * queue_for_each - Loop through all queues 525 * @__dev: Pointer to &struct rt2x00_dev 526 * @__entry: Pointer where the current queue entry will be stored in. 527 * 528 * This macro will loop through all available queues. 529 */ 530#define queue_for_each(__dev, __entry) \ 531 queue_loop(__entry, (__dev)->rx, queue_end(__dev)) 532 533/** 534 * tx_queue_for_each - Loop through the TX queues 535 * @__dev: Pointer to &struct rt2x00_dev 536 * @__entry: Pointer where the current queue entry will be stored in. 537 * 538 * This macro will loop through all TX related queues excluding 539 * the Beacon and Atim queues. 540 */ 541#define tx_queue_for_each(__dev, __entry) \ 542 queue_loop(__entry, (__dev)->tx, tx_queue_end(__dev)) 543 544/** 545 * txall_queue_for_each - Loop through all TX related queues 546 * @__dev: Pointer to &struct rt2x00_dev 547 * @__entry: Pointer where the current queue entry will be stored in. 548 * 549 * This macro will loop through all TX related queues including 550 * the Beacon and Atim queues. 551 */ 552#define txall_queue_for_each(__dev, __entry) \ 553 queue_loop(__entry, (__dev)->tx, queue_end(__dev)) 554 555/** 556 * rt2x00queue_empty - Check if the queue is empty. 557 * @queue: Queue to check if empty. 558 */ 559static inline int rt2x00queue_empty(struct data_queue *queue) 560{ 561 return queue->length == 0; 562} 563 564/** 565 * rt2x00queue_full - Check if the queue is full. 566 * @queue: Queue to check if full. 567 */ 568static inline int rt2x00queue_full(struct data_queue *queue) 569{ 570 return queue->length == queue->limit; 571} 572 573/** 574 * rt2x00queue_free - Check the number of available entries in queue. 575 * @queue: Queue to check. 576 */ 577static inline int rt2x00queue_available(struct data_queue *queue) 578{ 579 return queue->limit - queue->length; 580} 581 582/** 583 * rt2x00queue_threshold - Check if the queue is below threshold 584 * @queue: Queue to check. 585 */ 586static inline int rt2x00queue_threshold(struct data_queue *queue) 587{ 588 return rt2x00queue_available(queue) < queue->threshold; 589} 590 591/** 592 * _rt2x00_desc_read - Read a word from the hardware descriptor. 593 * @desc: Base descriptor address 594 * @word: Word index from where the descriptor should be read. 595 * @value: Address where the descriptor value should be written into. 596 */ 597static inline void _rt2x00_desc_read(__le32 *desc, const u8 word, __le32 *value) 598{ 599 *value = desc[word]; 600} 601 602/** 603 * rt2x00_desc_read - Read a word from the hardware descriptor, this 604 * function will take care of the byte ordering. 605 * @desc: Base descriptor address 606 * @word: Word index from where the descriptor should be read. 607 * @value: Address where the descriptor value should be written into. 608 */ 609static inline void rt2x00_desc_read(__le32 *desc, const u8 word, u32 *value) 610{ 611 __le32 tmp; 612 _rt2x00_desc_read(desc, word, &tmp); 613 *value = le32_to_cpu(tmp); 614} 615 616/** 617 * rt2x00_desc_write - write a word to the hardware descriptor, this 618 * function will take care of the byte ordering. 619 * @desc: Base descriptor address 620 * @word: Word index from where the descriptor should be written. 621 * @value: Value that should be written into the descriptor. 622 */ 623static inline void _rt2x00_desc_write(__le32 *desc, const u8 word, __le32 value) 624{ 625 desc[word] = value; 626} 627 628/** 629 * rt2x00_desc_write - write a word to the hardware descriptor. 630 * @desc: Base descriptor address 631 * @word: Word index from where the descriptor should be written. 632 * @value: Value that should be written into the descriptor. 633 */ 634static inline void rt2x00_desc_write(__le32 *desc, const u8 word, u32 value) 635{ 636 _rt2x00_desc_write(desc, word, cpu_to_le32(value)); 637} 638 639#endif /* RT2X00QUEUE_H */ 640