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25#ifndef __WL1251_ACX_H__
26#define __WL1251_ACX_H__
27
28#include "wl1251.h"
29#include "wl1251_cmd.h"
30
31
32struct acx_header {
33 struct wl1251_cmd_header cmd;
34
35
36 u16 id;
37
38
39 u16 len;
40};
41
42struct acx_error_counter {
43 struct acx_header header;
44
45
46
47
48 u32 PLCP_error;
49
50
51
52
53 u32 FCS_error;
54
55
56
57
58 u32 valid_frame;
59
60
61
62 u32 seq_num_miss;
63} __attribute__ ((packed));
64
65struct acx_revision {
66 struct acx_header header;
67
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80
81
82 char fw_version[20];
83
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89
90
91 u32 hw_version;
92} __attribute__ ((packed));
93
94enum wl1251_psm_mode {
95
96 WL1251_PSM_CAM = 0,
97
98
99 WL1251_PSM_PS = 1,
100
101
102 WL1251_PSM_ELP = 2,
103};
104
105struct acx_sleep_auth {
106 struct acx_header header;
107
108
109
110
111
112 u8 sleep_auth;
113 u8 padding[3];
114} __attribute__ ((packed));
115
116enum {
117 HOSTIF_PCI_MASTER_HOST_INDIRECT,
118 HOSTIF_PCI_MASTER_HOST_DIRECT,
119 HOSTIF_SLAVE,
120 HOSTIF_PKT_RING,
121 HOSTIF_DONTCARE = 0xFF
122};
123
124#define DEFAULT_UCAST_PRIORITY 0
125#define DEFAULT_RX_Q_PRIORITY 0
126#define DEFAULT_NUM_STATIONS 1
127#define DEFAULT_RXQ_PRIORITY 0
128#define DEFAULT_RXQ_TYPE 0x07
129#define TRACE_BUFFER_MAX_SIZE 256
130
131#define DP_RX_PACKET_RING_CHUNK_SIZE 1600
132#define DP_TX_PACKET_RING_CHUNK_SIZE 1600
133#define DP_RX_PACKET_RING_CHUNK_NUM 2
134#define DP_TX_PACKET_RING_CHUNK_NUM 2
135#define DP_TX_COMPLETE_TIME_OUT 20
136#define FW_TX_CMPLT_BLOCK_SIZE 16
137
138struct acx_data_path_params {
139 struct acx_header header;
140
141 u16 rx_packet_ring_chunk_size;
142 u16 tx_packet_ring_chunk_size;
143
144 u8 rx_packet_ring_chunk_num;
145 u8 tx_packet_ring_chunk_num;
146
147
148
149
150
151
152 u8 tx_complete_threshold;
153
154
155 u8 tx_complete_ring_depth;
156
157
158
159
160
161 u32 tx_complete_timeout;
162} __attribute__ ((packed));
163
164
165struct acx_data_path_params_resp {
166 struct acx_header header;
167
168 u16 rx_packet_ring_chunk_size;
169 u16 tx_packet_ring_chunk_size;
170
171 u8 rx_packet_ring_chunk_num;
172 u8 tx_packet_ring_chunk_num;
173
174 u8 pad[2];
175
176 u32 rx_packet_ring_addr;
177 u32 tx_packet_ring_addr;
178
179 u32 rx_control_addr;
180 u32 tx_control_addr;
181
182 u32 tx_complete_addr;
183} __attribute__ ((packed));
184
185#define TX_MSDU_LIFETIME_MIN 0
186#define TX_MSDU_LIFETIME_MAX 3000
187#define TX_MSDU_LIFETIME_DEF 512
188#define RX_MSDU_LIFETIME_MIN 0
189#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
190#define RX_MSDU_LIFETIME_DEF 512000
191
192struct acx_rx_msdu_lifetime {
193 struct acx_header header;
194
195
196
197
198
199 u32 lifetime;
200} __attribute__ ((packed));
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282
283struct acx_rx_config {
284 struct acx_header header;
285
286 u32 config_options;
287 u32 filter_options;
288} __attribute__ ((packed));
289
290enum {
291 QOS_AC_BE = 0,
292 QOS_AC_BK,
293 QOS_AC_VI,
294 QOS_AC_VO,
295 QOS_HIGHEST_AC_INDEX = QOS_AC_VO,
296};
297
298#define MAX_NUM_OF_AC (QOS_HIGHEST_AC_INDEX+1)
299#define FIRST_AC_INDEX QOS_AC_BE
300#define MAX_NUM_OF_802_1d_TAGS 8
301#define AC_PARAMS_MAX_TSID 15
302#define MAX_APSD_CONF 0xffff
303
304#define QOS_TX_HIGH_MIN (0)
305#define QOS_TX_HIGH_MAX (100)
306
307#define QOS_TX_HIGH_BK_DEF (25)
308#define QOS_TX_HIGH_BE_DEF (35)
309#define QOS_TX_HIGH_VI_DEF (35)
310#define QOS_TX_HIGH_VO_DEF (35)
311
312#define QOS_TX_LOW_BK_DEF (15)
313#define QOS_TX_LOW_BE_DEF (25)
314#define QOS_TX_LOW_VI_DEF (25)
315#define QOS_TX_LOW_VO_DEF (25)
316
317struct acx_tx_queue_qos_config {
318 struct acx_header header;
319
320 u8 qid;
321 u8 pad[3];
322
323
324 u16 high_threshold;
325
326
327 u16 low_threshold;
328} __attribute__ ((packed));
329
330struct acx_packet_detection {
331 struct acx_header header;
332
333 u32 threshold;
334} __attribute__ ((packed));
335
336
337enum acx_slot_type {
338 SLOT_TIME_LONG = 0,
339 SLOT_TIME_SHORT = 1,
340 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
341 MAX_SLOT_TIMES = 0xFF
342};
343
344#define STATION_WONE_INDEX 0
345
346struct acx_slot {
347 struct acx_header header;
348
349 u8 wone_index;
350 u8 slot_time;
351 u8 reserved[6];
352} __attribute__ ((packed));
353
354
355#define ADDRESS_GROUP_MAX (8)
356#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ADDRESS_GROUP_MAX)
357
358struct acx_dot11_grp_addr_tbl {
359 struct acx_header header;
360
361 u8 enabled;
362 u8 num_groups;
363 u8 pad[2];
364 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
365} __attribute__ ((packed));
366
367
368#define RX_TIMEOUT_PS_POLL_MIN 0
369#define RX_TIMEOUT_PS_POLL_MAX (200000)
370#define RX_TIMEOUT_PS_POLL_DEF (15)
371#define RX_TIMEOUT_UPSD_MIN 0
372#define RX_TIMEOUT_UPSD_MAX (200000)
373#define RX_TIMEOUT_UPSD_DEF (15)
374
375struct acx_rx_timeout {
376 struct acx_header header;
377
378
379
380
381
382
383 u16 ps_poll_timeout;
384
385
386
387
388
389
390 u16 upsd_timeout;
391} __attribute__ ((packed));
392
393#define RTS_THRESHOLD_MIN 0
394#define RTS_THRESHOLD_MAX 4096
395#define RTS_THRESHOLD_DEF 2347
396
397struct acx_rts_threshold {
398 struct acx_header header;
399
400 u16 threshold;
401 u8 pad[2];
402} __attribute__ ((packed));
403
404struct acx_beacon_filter_option {
405 struct acx_header header;
406
407 u8 enable;
408
409
410
411
412
413
414
415
416 u8 max_num_beacons;
417 u8 pad[2];
418} __attribute__ ((packed));
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443
444#define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
445#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
446#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
447#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
448#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
449 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
450 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
451 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
452
453struct acx_beacon_filter_ie_table {
454 struct acx_header header;
455
456 u8 num_ie;
457 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
458 u8 pad[3];
459} __attribute__ ((packed));
460
461enum {
462 SG_ENABLE = 0,
463 SG_DISABLE,
464 SG_SENSE_NO_ACTIVITY,
465 SG_SENSE_ACTIVE
466};
467
468struct acx_bt_wlan_coex {
469 struct acx_header header;
470
471
472
473
474
475
476
477
478
479
480 u8 enable;
481 u8 pad[3];
482} __attribute__ ((packed));
483
484#define PTA_ANTENNA_TYPE_DEF (0)
485#define PTA_BT_HP_MAXTIME_DEF (2000)
486#define PTA_WLAN_HP_MAX_TIME_DEF (5000)
487#define PTA_SENSE_DISABLE_TIMER_DEF (1350)
488#define PTA_PROTECTIVE_RX_TIME_DEF (1500)
489#define PTA_PROTECTIVE_TX_TIME_DEF (1500)
490#define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000)
491#define PTA_SIGNALING_TYPE_DEF (1)
492#define PTA_AFH_LEVERAGE_ON_DEF (0)
493#define PTA_NUMBER_QUIET_CYCLE_DEF (0)
494#define PTA_MAX_NUM_CTS_DEF (3)
495#define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2)
496#define PTA_NUMBER_OF_BT_PACKETS_DEF (2)
497#define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500)
498#define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000)
499#define PTA_CYCLE_TIME_FAST_DEF (8700)
500#define PTA_RX_FOR_AVALANCHE_DEF (5)
501#define PTA_ELP_HP_DEF (0)
502#define PTA_ANTI_STARVE_PERIOD_DEF (500)
503#define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4)
504#define PTA_ALLOW_PA_SD_DEF (1)
505#define PTA_TIME_BEFORE_BEACON_DEF (6300)
506#define PTA_HPDM_MAX_TIME_DEF (1600)
507#define PTA_TIME_OUT_NEXT_WLAN_DEF (2550)
508#define PTA_AUTO_MODE_NO_CTS_DEF (0)
509#define PTA_BT_HP_RESPECTED_DEF (3)
510#define PTA_WLAN_RX_MIN_RATE_DEF (24)
511#define PTA_ACK_MODE_DEF (1)
512
513struct acx_bt_wlan_coex_param {
514 struct acx_header header;
515
516
517
518
519
520
521 u32 min_rate;
522
523
524 u16 bt_hp_max_time;
525
526
527 u16 wlan_hp_max_time;
528
529
530
531
532
533
534 u16 sense_disable_timer;
535
536
537 u16 rx_time_bt_hp;
538 u16 tx_time_bt_hp;
539
540
541 u16 rx_time_bt_hp_fast;
542 u16 tx_time_bt_hp_fast;
543
544
545 u16 wlan_cycle_fast;
546
547
548 u16 bt_anti_starvation_period;
549
550
551 u16 next_bt_lp_packet;
552
553
554 u16 wake_up_beacon;
555
556
557 u16 hp_dm_max_guard_time;
558
559
560
561
562
563
564 u16 next_wlan_packet;
565
566
567 u8 antenna_type;
568
569
570
571
572
573 u8 signal_type;
574
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579
580
581 u8 afh_leverage_on;
582
583
584
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586
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588 u8 quiet_cycle_num;
589
590
591
592
593
594
595 u8 max_cts;
596
597
598
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600
601
602 u8 wlan_packets_num;
603
604
605
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607
608
609 u8 bt_packets_num;
610
611
612 u8 missed_rx_avalanche;
613
614
615 u8 wlan_elp_hp;
616
617
618 u8 bt_anti_starvation_cycles;
619
620 u8 ack_mode_dual_ant;
621
622
623
624
625
626 u8 pa_sd_enable;
627
628
629
630
631
632 u8 pta_auto_mode_enable;
633
634
635 u8 bt_hp_respected_num;
636} __attribute__ ((packed));
637
638#define CCA_THRSH_ENABLE_ENERGY_D 0x140A
639#define CCA_THRSH_DISABLE_ENERGY_D 0xFFEF
640
641struct acx_energy_detection {
642 struct acx_header header;
643
644
645 u16 rx_cca_threshold;
646 u8 tx_energy_detection;
647 u8 pad;
648} __attribute__ ((packed));
649
650#define BCN_RX_TIMEOUT_DEF_VALUE 10000
651#define BROADCAST_RX_TIMEOUT_DEF_VALUE 20000
652#define RX_BROADCAST_IN_PS_DEF_VALUE 1
653#define CONSECUTIVE_PS_POLL_FAILURE_DEF 4
654
655struct acx_beacon_broadcast {
656 struct acx_header header;
657
658 u16 beacon_rx_timeout;
659 u16 broadcast_timeout;
660
661
662 u8 rx_broadcast_in_ps;
663
664
665 u8 ps_poll_threshold;
666 u8 pad[2];
667} __attribute__ ((packed));
668
669struct acx_event_mask {
670 struct acx_header header;
671
672 u32 event_mask;
673 u32 high_event_mask;
674} __attribute__ ((packed));
675
676#define CFG_RX_FCS BIT(2)
677#define CFG_RX_ALL_GOOD BIT(3)
678#define CFG_UNI_FILTER_EN BIT(4)
679#define CFG_BSSID_FILTER_EN BIT(5)
680#define CFG_MC_FILTER_EN BIT(6)
681#define CFG_MC_ADDR0_EN BIT(7)
682#define CFG_MC_ADDR1_EN BIT(8)
683#define CFG_BC_REJECT_EN BIT(9)
684#define CFG_SSID_FILTER_EN BIT(10)
685#define CFG_RX_INT_FCS_ERROR BIT(11)
686#define CFG_RX_INT_ENCRYPTED BIT(12)
687#define CFG_RX_WR_RX_STATUS BIT(13)
688#define CFG_RX_FILTER_NULTI BIT(14)
689#define CFG_RX_RESERVE BIT(15)
690#define CFG_RX_TIMESTAMP_TSF BIT(16)
691
692#define CFG_RX_RSV_EN BIT(0)
693#define CFG_RX_RCTS_ACK BIT(1)
694#define CFG_RX_PRSP_EN BIT(2)
695#define CFG_RX_PREQ_EN BIT(3)
696#define CFG_RX_MGMT_EN BIT(4)
697#define CFG_RX_FCS_ERROR BIT(5)
698#define CFG_RX_DATA_EN BIT(6)
699#define CFG_RX_CTL_EN BIT(7)
700#define CFG_RX_CF_EN BIT(8)
701#define CFG_RX_BCN_EN BIT(9)
702#define CFG_RX_AUTH_EN BIT(10)
703#define CFG_RX_ASSOC_EN BIT(11)
704
705#define SCAN_PASSIVE BIT(0)
706#define SCAN_5GHZ_BAND BIT(1)
707#define SCAN_TRIGGERED BIT(2)
708#define SCAN_PRIORITY_HIGH BIT(3)
709
710struct acx_fw_gen_frame_rates {
711 struct acx_header header;
712
713 u8 tx_ctrl_frame_rate;
714 u8 tx_ctrl_frame_mod;
715 u8 tx_mgt_frame_rate;
716 u8 tx_mgt_frame_mod;
717} __attribute__ ((packed));
718
719
720struct acx_dot11_station_id {
721 struct acx_header header;
722
723 u8 mac[ETH_ALEN];
724 u8 pad[2];
725} __attribute__ ((packed));
726
727struct acx_feature_config {
728 struct acx_header header;
729
730 u32 options;
731 u32 data_flow_options;
732} __attribute__ ((packed));
733
734struct acx_current_tx_power {
735 struct acx_header header;
736
737 u8 current_tx_power;
738 u8 padding[3];
739} __attribute__ ((packed));
740
741struct acx_dot11_default_key {
742 struct acx_header header;
743
744 u8 id;
745 u8 pad[3];
746} __attribute__ ((packed));
747
748struct acx_tsf_info {
749 struct acx_header header;
750
751 u32 current_tsf_msb;
752 u32 current_tsf_lsb;
753 u32 last_TBTT_msb;
754 u32 last_TBTT_lsb;
755 u8 last_dtim_count;
756 u8 pad[3];
757} __attribute__ ((packed));
758
759enum acx_wake_up_event {
760 WAKE_UP_EVENT_BEACON_BITMAP = 0x01,
761 WAKE_UP_EVENT_DTIM_BITMAP = 0x02,
762 WAKE_UP_EVENT_N_DTIM_BITMAP = 0x04,
763 WAKE_UP_EVENT_N_BEACONS_BITMAP = 0x08,
764 WAKE_UP_EVENT_BITS_MASK = 0x0F
765};
766
767struct acx_wake_up_condition {
768 struct acx_header header;
769
770 u8 wake_up_event;
771 u8 listen_interval;
772 u8 pad[2];
773} __attribute__ ((packed));
774
775struct acx_aid {
776 struct acx_header header;
777
778
779
780
781 u16 aid;
782 u8 pad[2];
783} __attribute__ ((packed));
784
785enum acx_preamble_type {
786 ACX_PREAMBLE_LONG = 0,
787 ACX_PREAMBLE_SHORT = 1
788};
789
790struct acx_preamble {
791 struct acx_header header;
792
793
794
795
796
797 u8 preamble;
798 u8 padding[3];
799} __attribute__ ((packed));
800
801enum acx_ctsprotect_type {
802 CTSPROTECT_DISABLE = 0,
803 CTSPROTECT_ENABLE = 1
804};
805
806struct acx_ctsprotect {
807 struct acx_header header;
808 u8 ctsprotect;
809 u8 padding[3];
810} __attribute__ ((packed));
811
812struct acx_tx_statistics {
813 u32 internal_desc_overflow;
814} __attribute__ ((packed));
815
816struct acx_rx_statistics {
817 u32 out_of_mem;
818 u32 hdr_overflow;
819 u32 hw_stuck;
820 u32 dropped;
821 u32 fcs_err;
822 u32 xfr_hint_trig;
823 u32 path_reset;
824 u32 reset_counter;
825} __attribute__ ((packed));
826
827struct acx_dma_statistics {
828 u32 rx_requested;
829 u32 rx_errors;
830 u32 tx_requested;
831 u32 tx_errors;
832} __attribute__ ((packed));
833
834struct acx_isr_statistics {
835
836 u32 cmd_cmplt;
837
838
839 u32 fiqs;
840
841
842 u32 rx_headers;
843
844
845 u32 rx_completes;
846
847
848 u32 rx_mem_overflow;
849
850
851 u32 rx_rdys;
852
853
854 u32 irqs;
855
856
857 u32 tx_procs;
858
859
860 u32 decrypt_done;
861
862
863 u32 dma0_done;
864
865
866 u32 dma1_done;
867
868
869 u32 tx_exch_complete;
870
871
872 u32 commands;
873
874
875 u32 rx_procs;
876
877
878 u32 hw_pm_mode_changes;
879
880
881 u32 host_acknowledges;
882
883
884 u32 pci_pm;
885
886
887 u32 wakeups;
888
889
890 u32 low_rssi;
891} __attribute__ ((packed));
892
893struct acx_wep_statistics {
894
895 u32 addr_key_count;
896
897
898 u32 default_key_count;
899
900 u32 reserved;
901
902
903 u32 key_not_found;
904
905
906 u32 decrypt_fail;
907
908
909 u32 packets;
910
911
912 u32 interrupt;
913} __attribute__ ((packed));
914
915#define ACX_MISSED_BEACONS_SPREAD 10
916
917struct acx_pwr_statistics {
918
919 u32 ps_enter;
920
921
922 u32 elp_enter;
923
924
925 u32 missing_bcns;
926
927
928 u32 wake_on_host;
929
930
931 u32 wake_on_timer_exp;
932
933
934 u32 tx_with_ps;
935
936
937 u32 tx_without_ps;
938
939
940 u32 rcvd_beacons;
941
942
943 u32 power_save_off;
944
945
946 u16 enable_ps;
947
948
949
950
951
952 u16 disable_ps;
953
954
955
956
957
958 u32 fix_tsf_ps;
959
960
961
962
963
964
965
966
967
968
969 u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
970
971
972 u32 rcvd_awake_beacons;
973} __attribute__ ((packed));
974
975struct acx_mic_statistics {
976 u32 rx_pkts;
977 u32 calc_failure;
978} __attribute__ ((packed));
979
980struct acx_aes_statistics {
981 u32 encrypt_fail;
982 u32 decrypt_fail;
983 u32 encrypt_packets;
984 u32 decrypt_packets;
985 u32 encrypt_interrupt;
986 u32 decrypt_interrupt;
987} __attribute__ ((packed));
988
989struct acx_event_statistics {
990 u32 heart_beat;
991 u32 calibration;
992 u32 rx_mismatch;
993 u32 rx_mem_empty;
994 u32 rx_pool;
995 u32 oom_late;
996 u32 phy_transmit_error;
997 u32 tx_stuck;
998} __attribute__ ((packed));
999
1000struct acx_ps_statistics {
1001 u32 pspoll_timeouts;
1002 u32 upsd_timeouts;
1003 u32 upsd_max_sptime;
1004 u32 upsd_max_apturn;
1005 u32 pspoll_max_apturn;
1006 u32 pspoll_utilization;
1007 u32 upsd_utilization;
1008} __attribute__ ((packed));
1009
1010struct acx_rxpipe_statistics {
1011 u32 rx_prep_beacon_drop;
1012 u32 descr_host_int_trig_rx_data;
1013 u32 beacon_buffer_thres_host_int_trig_rx_data;
1014 u32 missed_beacon_host_int_trig_rx_data;
1015 u32 tx_xfr_host_int_trig_rx_data;
1016} __attribute__ ((packed));
1017
1018struct acx_statistics {
1019 struct acx_header header;
1020
1021 struct acx_tx_statistics tx;
1022 struct acx_rx_statistics rx;
1023 struct acx_dma_statistics dma;
1024 struct acx_isr_statistics isr;
1025 struct acx_wep_statistics wep;
1026 struct acx_pwr_statistics pwr;
1027 struct acx_aes_statistics aes;
1028 struct acx_mic_statistics mic;
1029 struct acx_event_statistics event;
1030 struct acx_ps_statistics ps;
1031 struct acx_rxpipe_statistics rxpipe;
1032} __attribute__ ((packed));
1033
1034#define ACX_MAX_RATE_CLASSES 8
1035#define ACX_RATE_MASK_UNSPECIFIED 0
1036#define ACX_RATE_RETRY_LIMIT 10
1037
1038struct acx_rate_class {
1039 u32 enabled_rates;
1040 u8 short_retry_limit;
1041 u8 long_retry_limit;
1042 u8 aflags;
1043 u8 reserved;
1044};
1045
1046struct acx_rate_policy {
1047 struct acx_header header;
1048
1049 u32 rate_class_cnt;
1050 struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES];
1051} __attribute__ ((packed));
1052
1053struct wl1251_acx_memory {
1054 __le16 num_stations;
1055 u16 reserved_1;
1056
1057
1058
1059
1060
1061
1062
1063 u8 rx_mem_block_num;
1064 u8 reserved_2;
1065 u8 num_tx_queues;
1066 u8 host_if_options;
1067 u8 tx_min_mem_block_num;
1068 u8 num_ssid_profiles;
1069 __le16 debug_buffer_size;
1070} __attribute__ ((packed));
1071
1072
1073#define ACX_RX_DESC_MIN 1
1074#define ACX_RX_DESC_MAX 127
1075#define ACX_RX_DESC_DEF 32
1076struct wl1251_acx_rx_queue_config {
1077 u8 num_descs;
1078 u8 pad;
1079 u8 type;
1080 u8 priority;
1081 __le32 dma_address;
1082} __attribute__ ((packed));
1083
1084#define ACX_TX_DESC_MIN 1
1085#define ACX_TX_DESC_MAX 127
1086#define ACX_TX_DESC_DEF 16
1087struct wl1251_acx_tx_queue_config {
1088 u8 num_descs;
1089 u8 pad[2];
1090 u8 attributes;
1091} __attribute__ ((packed));
1092
1093#define MAX_TX_QUEUE_CONFIGS 5
1094#define MAX_TX_QUEUES 4
1095struct wl1251_acx_config_memory {
1096 struct acx_header header;
1097
1098 struct wl1251_acx_memory mem_config;
1099 struct wl1251_acx_rx_queue_config rx_queue_config;
1100 struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS];
1101} __attribute__ ((packed));
1102
1103struct wl1251_acx_mem_map {
1104 struct acx_header header;
1105
1106 void *code_start;
1107 void *code_end;
1108
1109 void *wep_defkey_start;
1110 void *wep_defkey_end;
1111
1112 void *sta_table_start;
1113 void *sta_table_end;
1114
1115 void *packet_template_start;
1116 void *packet_template_end;
1117
1118 void *queue_memory_start;
1119 void *queue_memory_end;
1120
1121 void *packet_memory_pool_start;
1122 void *packet_memory_pool_end;
1123
1124 void *debug_buffer1_start;
1125 void *debug_buffer1_end;
1126
1127 void *debug_buffer2_start;
1128 void *debug_buffer2_end;
1129
1130
1131 u32 num_tx_mem_blocks;
1132
1133
1134 u32 num_rx_mem_blocks;
1135} __attribute__ ((packed));
1136
1137
1138
1139
1140
1141
1142
1143
1144#define WL1251_ACX_INTR_RX0_DATA BIT(0)
1145
1146
1147#define WL1251_ACX_INTR_TX_RESULT BIT(1)
1148
1149
1150#define WL1251_ACX_INTR_TX_XFR BIT(2)
1151
1152
1153#define WL1251_ACX_INTR_RX1_DATA BIT(3)
1154
1155
1156#define WL1251_ACX_INTR_EVENT_A BIT(4)
1157
1158
1159#define WL1251_ACX_INTR_EVENT_B BIT(5)
1160
1161
1162#define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6)
1163
1164
1165#define WL1251_ACX_INTR_TRACE_A BIT(7)
1166
1167
1168#define WL1251_ACX_INTR_TRACE_B BIT(8)
1169
1170
1171#define WL1251_ACX_INTR_CMD_COMPLETE BIT(9)
1172
1173
1174#define WL1251_ACX_INTR_INIT_COMPLETE BIT(14)
1175
1176#define WL1251_ACX_INTR_ALL 0xFFFFFFFF
1177
1178enum {
1179 ACX_WAKE_UP_CONDITIONS = 0x0002,
1180 ACX_MEM_CFG = 0x0003,
1181 ACX_SLOT = 0x0004,
1182 ACX_QUEUE_HEAD = 0x0005,
1183 ACX_AC_CFG = 0x0007,
1184 ACX_MEM_MAP = 0x0008,
1185 ACX_AID = 0x000A,
1186 ACX_RADIO_PARAM = 0x000B,
1187 ACX_CFG = 0x000C,
1188 ACX_FW_REV = 0x000D,
1189 ACX_MEDIUM_USAGE = 0x000F,
1190 ACX_RX_CFG = 0x0010,
1191 ACX_TX_QUEUE_CFG = 0x0011,
1192 ACX_BSS_IN_PS = 0x0012,
1193 ACX_STATISTICS = 0x0013,
1194 ACX_FEATURE_CFG = 0x0015,
1195 ACX_MISC_CFG = 0x0017,
1196 ACX_TID_CFG = 0x001A,
1197 ACX_BEACON_FILTER_OPT = 0x001F,
1198 ACX_LOW_RSSI = 0x0020,
1199 ACX_NOISE_HIST = 0x0021,
1200 ACX_HDK_VERSION = 0x0022,
1201 ACX_PD_THRESHOLD = 0x0023,
1202 ACX_DATA_PATH_PARAMS = 0x0024,
1203 ACX_DATA_PATH_RESP_PARAMS = 0x0024,
1204 ACX_CCA_THRESHOLD = 0x0025,
1205 ACX_EVENT_MBOX_MASK = 0x0026,
1206#ifdef FW_RUNNING_AS_AP
1207 ACX_DTIM_PERIOD = 0x0027,
1208#else
1209 ACX_WR_TBTT_AND_DTIM = 0x0027,
1210#endif
1211 ACX_ACI_OPTION_CFG = 0x0029,
1212 ACX_GPIO_CFG = 0x002A,
1213 ACX_GPIO_SET = 0x002B,
1214 ACX_PM_CFG = 0x002C,
1215 ACX_CONN_MONIT_PARAMS = 0x002D,
1216 ACX_AVERAGE_RSSI = 0x002E,
1217 ACX_CONS_TX_FAILURE = 0x002F,
1218 ACX_BCN_DTIM_OPTIONS = 0x0031,
1219 ACX_SG_ENABLE = 0x0032,
1220 ACX_SG_CFG = 0x0033,
1221 ACX_ANTENNA_DIVERSITY_CFG = 0x0035,
1222 ACX_LOW_SNR = 0x0037,
1223 ACX_BEACON_FILTER_TABLE = 0x0038,
1224 ACX_ARP_IP_FILTER = 0x0039,
1225 ACX_ROAMING_STATISTICS_TBL = 0x003B,
1226 ACX_RATE_POLICY = 0x003D,
1227 ACX_CTS_PROTECTION = 0x003E,
1228 ACX_SLEEP_AUTH = 0x003F,
1229 ACX_PREAMBLE_TYPE = 0x0040,
1230 ACX_ERROR_CNT = 0x0041,
1231 ACX_FW_GEN_FRAME_RATES = 0x0042,
1232 ACX_IBSS_FILTER = 0x0044,
1233 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045,
1234 ACX_TSF_INFO = 0x0046,
1235 ACX_CONFIG_PS_WMM = 0x0049,
1236 ACX_ENABLE_RX_DATA_FILTER = 0x004A,
1237 ACX_SET_RX_DATA_FILTER = 0x004B,
1238 ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1239 ACX_POWER_LEVEL_TABLE = 0x004D,
1240 ACX_BET_ENABLE = 0x0050,
1241 DOT11_STATION_ID = 0x1001,
1242 DOT11_RX_MSDU_LIFE_TIME = 0x1004,
1243 DOT11_CUR_TX_PWR = 0x100D,
1244 DOT11_DEFAULT_KEY = 0x1010,
1245 DOT11_RX_DOT11_MODE = 0x1012,
1246 DOT11_RTS_THRESHOLD = 0x1013,
1247 DOT11_GROUP_ADDRESS_TBL = 0x1014,
1248
1249 MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
1250
1251 MAX_IE = 0xFFFF
1252};
1253
1254
1255int wl1251_acx_frame_rates(struct wl1251 *wl, u8 ctrl_rate, u8 ctrl_mod,
1256 u8 mgt_rate, u8 mgt_mod);
1257int wl1251_acx_station_id(struct wl1251 *wl);
1258int wl1251_acx_default_key(struct wl1251 *wl, u8 key_id);
1259int wl1251_acx_wake_up_conditions(struct wl1251 *wl, u8 wake_up_event,
1260 u8 listen_interval);
1261int wl1251_acx_sleep_auth(struct wl1251 *wl, u8 sleep_auth);
1262int wl1251_acx_fw_version(struct wl1251 *wl, char *buf, size_t len);
1263int wl1251_acx_tx_power(struct wl1251 *wl, int power);
1264int wl1251_acx_feature_cfg(struct wl1251 *wl);
1265int wl1251_acx_mem_map(struct wl1251 *wl,
1266 struct acx_header *mem_map, size_t len);
1267int wl1251_acx_data_path_params(struct wl1251 *wl,
1268 struct acx_data_path_params_resp *data_path);
1269int wl1251_acx_rx_msdu_life_time(struct wl1251 *wl, u32 life_time);
1270int wl1251_acx_rx_config(struct wl1251 *wl, u32 config, u32 filter);
1271int wl1251_acx_pd_threshold(struct wl1251 *wl);
1272int wl1251_acx_slot(struct wl1251 *wl, enum acx_slot_type slot_time);
1273int wl1251_acx_group_address_tbl(struct wl1251 *wl);
1274int wl1251_acx_service_period_timeout(struct wl1251 *wl);
1275int wl1251_acx_rts_threshold(struct wl1251 *wl, u16 rts_threshold);
1276int wl1251_acx_beacon_filter_opt(struct wl1251 *wl);
1277int wl1251_acx_beacon_filter_table(struct wl1251 *wl);
1278int wl1251_acx_sg_enable(struct wl1251 *wl);
1279int wl1251_acx_sg_cfg(struct wl1251 *wl);
1280int wl1251_acx_cca_threshold(struct wl1251 *wl);
1281int wl1251_acx_bcn_dtim_options(struct wl1251 *wl);
1282int wl1251_acx_aid(struct wl1251 *wl, u16 aid);
1283int wl1251_acx_event_mbox_mask(struct wl1251 *wl, u32 event_mask);
1284int wl1251_acx_set_preamble(struct wl1251 *wl, enum acx_preamble_type preamble);
1285int wl1251_acx_cts_protect(struct wl1251 *wl,
1286 enum acx_ctsprotect_type ctsprotect);
1287int wl1251_acx_statistics(struct wl1251 *wl, struct acx_statistics *stats);
1288int wl1251_acx_tsf_info(struct wl1251 *wl, u64 *mactime);
1289int wl1251_acx_rate_policies(struct wl1251 *wl);
1290int wl1251_acx_mem_cfg(struct wl1251 *wl);
1291
1292#endif
1293