1/* 2 * This file is part of wl12xx 3 * 4 * Copyright (c) 1998-2007 Texas Instruments Incorporated 5 * Copyright (C) 2008 Nokia Corporation 6 * 7 * Contact: Kalle Valo <kalle.valo@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 */ 24 25#ifndef __REG_H__ 26#define __REG_H__ 27 28#include <linux/bitops.h> 29 30#define REGISTERS_BASE 0x00300000 31#define DRPW_BASE 0x00310000 32 33#define REGISTERS_DOWN_SIZE 0x00008800 34#define REGISTERS_WORK_SIZE 0x0000b000 35 36#define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC 37 38/* ELP register commands */ 39#define ELPCTRL_WAKE_UP 0x1 40#define ELPCTRL_WAKE_UP_WLAN_READY 0x5 41#define ELPCTRL_SLEEP 0x0 42/* ELP WLAN_READY bit */ 43#define ELPCTRL_WLAN_READY 0x2 44 45/* Device Configuration registers*/ 46#define SOR_CFG (REGISTERS_BASE + 0x0800) 47#define ECPU_CTRL (REGISTERS_BASE + 0x0804) 48#define HI_CFG (REGISTERS_BASE + 0x0808) 49#define EE_START (REGISTERS_BASE + 0x080C) 50 51#define CHIP_ID_B (REGISTERS_BASE + 0x5674) 52 53#define CHIP_ID_1251_PG10 (0x7010101) 54#define CHIP_ID_1251_PG11 (0x7020101) 55#define CHIP_ID_1251_PG12 (0x7030101) 56 57#define ENABLE (REGISTERS_BASE + 0x5450) 58 59/* Power Management registers */ 60#define ELP_CFG_MODE (REGISTERS_BASE + 0x5804) 61#define ELP_CMD (REGISTERS_BASE + 0x5808) 62#define PLL_CAL_TIME (REGISTERS_BASE + 0x5810) 63#define CLK_REQ_TIME (REGISTERS_BASE + 0x5814) 64#define CLK_BUF_TIME (REGISTERS_BASE + 0x5818) 65 66#define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820) 67 68/* Scratch Pad registers*/ 69#define SCR_PAD0 (REGISTERS_BASE + 0x5608) 70#define SCR_PAD1 (REGISTERS_BASE + 0x560C) 71#define SCR_PAD2 (REGISTERS_BASE + 0x5610) 72#define SCR_PAD3 (REGISTERS_BASE + 0x5614) 73#define SCR_PAD4 (REGISTERS_BASE + 0x5618) 74#define SCR_PAD4_SET (REGISTERS_BASE + 0x561C) 75#define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620) 76#define SCR_PAD5 (REGISTERS_BASE + 0x5624) 77#define SCR_PAD5_SET (REGISTERS_BASE + 0x5628) 78#define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C) 79#define SCR_PAD6 (REGISTERS_BASE + 0x5630) 80#define SCR_PAD7 (REGISTERS_BASE + 0x5634) 81#define SCR_PAD8 (REGISTERS_BASE + 0x5638) 82#define SCR_PAD9 (REGISTERS_BASE + 0x563C) 83 84/* Spare registers*/ 85#define SPARE_A1 (REGISTERS_BASE + 0x0994) 86#define SPARE_A2 (REGISTERS_BASE + 0x0998) 87#define SPARE_A3 (REGISTERS_BASE + 0x099C) 88#define SPARE_A4 (REGISTERS_BASE + 0x09A0) 89#define SPARE_A5 (REGISTERS_BASE + 0x09A4) 90#define SPARE_A6 (REGISTERS_BASE + 0x09A8) 91#define SPARE_A7 (REGISTERS_BASE + 0x09AC) 92#define SPARE_A8 (REGISTERS_BASE + 0x09B0) 93#define SPARE_B1 (REGISTERS_BASE + 0x5420) 94#define SPARE_B2 (REGISTERS_BASE + 0x5424) 95#define SPARE_B3 (REGISTERS_BASE + 0x5428) 96#define SPARE_B4 (REGISTERS_BASE + 0x542C) 97#define SPARE_B5 (REGISTERS_BASE + 0x5430) 98#define SPARE_B6 (REGISTERS_BASE + 0x5434) 99#define SPARE_B7 (REGISTERS_BASE + 0x5438) 100#define SPARE_B8 (REGISTERS_BASE + 0x543C) 101 102enum wl12xx_acx_int_reg { 103 ACX_REG_INTERRUPT_TRIG, 104 ACX_REG_INTERRUPT_TRIG_H, 105 106/*============================================= 107 Host Interrupt Mask Register - 32bit (RW) 108 ------------------------------------------ 109 Setting a bit in this register masks the 110 corresponding interrupt to the host. 111 0 - RX0 - Rx first dubble buffer Data Interrupt 112 1 - TXD - Tx Data Interrupt 113 2 - TXXFR - Tx Transfer Interrupt 114 3 - RX1 - Rx second dubble buffer Data Interrupt 115 4 - RXXFR - Rx Transfer Interrupt 116 5 - EVENT_A - Event Mailbox interrupt 117 6 - EVENT_B - Event Mailbox interrupt 118 7 - WNONHST - Wake On Host Interrupt 119 8 - TRACE_A - Debug Trace interrupt 120 9 - TRACE_B - Debug Trace interrupt 121 10 - CDCMP - Command Complete Interrupt 122 11 - 123 12 - 124 13 - 125 14 - ICOMP - Initialization Complete Interrupt 126 16 - SG SE - Soft Gemini - Sense enable interrupt 127 17 - SG SD - Soft Gemini - Sense disable interrupt 128 18 - - 129 19 - - 130 20 - - 131 21- - 132 Default: 0x0001 133*==============================================*/ 134 ACX_REG_INTERRUPT_MASK, 135 136/*============================================= 137 Host Interrupt Mask Set 16bit, (Write only) 138 ------------------------------------------ 139 Setting a bit in this register sets 140 the corresponding bin in ACX_HINT_MASK register 141 without effecting the mask 142 state of other bits (0 = no effect). 143==============================================*/ 144 ACX_REG_HINT_MASK_SET, 145 146/*============================================= 147 Host Interrupt Mask Clear 16bit,(Write only) 148 ------------------------------------------ 149 Setting a bit in this register clears 150 the corresponding bin in ACX_HINT_MASK register 151 without effecting the mask 152 state of other bits (0 = no effect). 153=============================================*/ 154 ACX_REG_HINT_MASK_CLR, 155 156/*============================================= 157 Host Interrupt Status Nondestructive Read 158 16bit,(Read only) 159 ------------------------------------------ 160 The host can read this register to determine 161 which interrupts are active. 162 Reading this register doesn't 163 effect its content. 164=============================================*/ 165 ACX_REG_INTERRUPT_NO_CLEAR, 166 167/*============================================= 168 Host Interrupt Status Clear on Read Register 169 16bit,(Read only) 170 ------------------------------------------ 171 The host can read this register to determine 172 which interrupts are active. 173 Reading this register clears it, 174 thus making all interrupts inactive. 175==============================================*/ 176 ACX_REG_INTERRUPT_CLEAR, 177 178/*============================================= 179 Host Interrupt Acknowledge Register 180 16bit,(Write only) 181 ------------------------------------------ 182 The host can set individual bits in this 183 register to clear (acknowledge) the corresp. 184 interrupt status bits in the HINT_STS_CLR and 185 HINT_STS_ND registers, thus making the 186 assotiated interrupt inactive. (0-no effect) 187==============================================*/ 188 ACX_REG_INTERRUPT_ACK, 189 190/*=============================================== 191 Host Software Reset - 32bit RW 192 ------------------------------------------ 193 [31:1] Reserved 194 0 SOFT_RESET Soft Reset - When this bit is set, 195 it holds the Wlan hardware in a soft reset state. 196 This reset disables all MAC and baseband processor 197 clocks except the CardBus/PCI interface clock. 198 It also initializes all MAC state machines except 199 the host interface. It does not reload the 200 contents of the EEPROM. When this bit is cleared 201 (not self-clearing), the Wlan hardware 202 exits the software reset state. 203===============================================*/ 204 ACX_REG_SLV_SOFT_RESET, 205 206/*=============================================== 207 EEPROM Burst Read Start - 32bit RW 208 ------------------------------------------ 209 [31:1] Reserved 210 0 ACX_EE_START - EEPROM Burst Read Start 0 211 Setting this bit starts a burst read from 212 the external EEPROM. 213 If this bit is set (after reset) before an EEPROM read/write, 214 the burst read starts at EEPROM address 0. 215 Otherwise, it starts at the address 216 following the address of the previous access. 217 TheWlan hardware hardware clears this bit automatically. 218 219 Default: 0x00000000 220*================================================*/ 221 ACX_REG_EE_START, 222 223/* Embedded ARM CPU Control */ 224 225/*=============================================== 226 Halt eCPU - 32bit RW 227 ------------------------------------------ 228 0 HALT_ECPU Halt Embedded CPU - This bit is the 229 compliment of bit 1 (MDATA2) in the SOR_CFG register. 230 During a hardware reset, this bit holds 231 the inverse of MDATA2. 232 When downloading firmware from the host, 233 set this bit (pull down MDATA2). 234 The host clears this bit after downloading the firmware into 235 zero-wait-state SSRAM. 236 When loading firmware from Flash, clear this bit (pull up MDATA2) 237 so that the eCPU can run the bootloader code in Flash 238 HALT_ECPU eCPU State 239 -------------------- 240 1 halt eCPU 241 0 enable eCPU 242 ===============================================*/ 243 ACX_REG_ECPU_CONTROL, 244 245 ACX_REG_TABLE_LEN 246}; 247 248#define ACX_SLV_SOFT_RESET_BIT BIT(0) 249#define ACX_REG_EEPROM_START_BIT BIT(0) 250 251/* Command/Information Mailbox Pointers */ 252 253/*=============================================== 254 Command Mailbox Pointer - 32bit RW 255 ------------------------------------------ 256 This register holds the start address of 257 the command mailbox located in the Wlan hardware memory. 258 The host must read this pointer after a reset to 259 find the location of the command mailbox. 260 The Wlan hardware initializes the command mailbox 261 pointer with the default address of the command mailbox. 262 The command mailbox pointer is not valid until after 263 the host receives the Init Complete interrupt from 264 the Wlan hardware. 265 ===============================================*/ 266#define REG_COMMAND_MAILBOX_PTR (SCR_PAD0) 267 268/*=============================================== 269 Information Mailbox Pointer - 32bit RW 270 ------------------------------------------ 271 This register holds the start address of 272 the information mailbox located in the Wlan hardware memory. 273 The host must read this pointer after a reset to find 274 the location of the information mailbox. 275 The Wlan hardware initializes the information mailbox pointer 276 with the default address of the information mailbox. 277 The information mailbox pointer is not valid 278 until after the host receives the Init Complete interrupt from 279 the Wlan hardware. 280 ===============================================*/ 281#define REG_EVENT_MAILBOX_PTR (SCR_PAD1) 282 283 284/* Misc */ 285 286#define REG_ENABLE_TX_RX (ENABLE) 287/* 288 * Rx configuration (filter) information element 289 * --------------------------------------------- 290 */ 291#define REG_RX_CONFIG (RX_CFG) 292#define REG_RX_FILTER (RX_FILTER_CFG) 293 294 295#define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002 296 297/* promiscuous - receives all valid frames */ 298#define RX_CFG_PROMISCUOUS 0x0008 299 300/* receives frames from any BSSID */ 301#define RX_CFG_BSSID 0x0020 302 303/* receives frames destined to any MAC address */ 304#define RX_CFG_MAC 0x0010 305 306#define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010 307#define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000 308#define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020 309#define RX_CFG_ENABLE_ANY_BSSID 0x0000 310 311/* discards all broadcast frames */ 312#define RX_CFG_DISABLE_BCAST 0x0200 313 314#define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400 315#define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800 316#define RX_CFG_COPY_RX_STATUS 0x2000 317#define RX_CFG_TSF 0x10000 318 319#define RX_CONFIG_OPTION_ANY_DST_MY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \ 320 RX_CFG_ENABLE_ONLY_MY_BSSID) 321 322#define RX_CONFIG_OPTION_MY_DST_ANY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\ 323 | RX_CFG_ENABLE_ANY_BSSID) 324 325#define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \ 326 RX_CFG_ENABLE_ANY_BSSID) 327 328#define RX_CONFIG_OPTION_MY_DST_MY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\ 329 | RX_CFG_ENABLE_ONLY_MY_BSSID) 330 331#define RX_CONFIG_OPTION_FOR_SCAN (RX_CFG_ENABLE_PHY_HEADER_PLCP \ 332 | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \ 333 | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF) 334 335#define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC) 336 337#define RX_CONFIG_OPTION_FOR_JOIN (RX_CFG_ENABLE_ONLY_MY_BSSID | \ 338 RX_CFG_ENABLE_ONLY_MY_DEST_MAC) 339 340#define RX_CONFIG_OPTION_FOR_IBSS_JOIN (RX_CFG_ENABLE_ONLY_MY_SSID | \ 341 RX_CFG_ENABLE_ONLY_MY_DEST_MAC) 342 343#define RX_FILTER_OPTION_DEF (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\ 344 | CFG_RX_CTL_EN | CFG_RX_BCN_EN\ 345 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN) 346 347#define RX_FILTER_OPTION_FILTER_ALL 0 348 349#define RX_FILTER_OPTION_DEF_PRSP_BCN (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\ 350 | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN) 351 352#define RX_FILTER_OPTION_JOIN (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\ 353 | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\ 354 | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\ 355 | CFG_RX_PRSP_EN) 356 357 358/*=============================================== 359 EEPROM Read/Write Request 32bit RW 360 ------------------------------------------ 361 1 EE_READ - EEPROM Read Request 1 - Setting this bit 362 loads a single byte of data into the EE_DATA 363 register from the EEPROM location specified in 364 the EE_ADDR register. 365 The Wlan hardware hardware clears this bit automatically. 366 EE_DATA is valid when this bit is cleared. 367 368 0 EE_WRITE - EEPROM Write Request - Setting this bit 369 writes a single byte of data from the EE_DATA register into the 370 EEPROM location specified in the EE_ADDR register. 371 The Wlan hardware hardware clears this bit automatically. 372*===============================================*/ 373#define ACX_EE_CTL_REG EE_CTL 374#define EE_WRITE 0x00000001ul 375#define EE_READ 0x00000002ul 376 377/*=============================================== 378 EEPROM Address - 32bit RW 379 ------------------------------------------ 380 This register specifies the address 381 within the EEPROM from/to which to read/write data. 382 ===============================================*/ 383#define ACX_EE_ADDR_REG EE_ADDR 384 385/*=============================================== 386 EEPROM Data - 32bit RW 387 ------------------------------------------ 388 This register either holds the read 8 bits of 389 data from the EEPROM or the write data 390 to be written to the EEPROM. 391 ===============================================*/ 392#define ACX_EE_DATA_REG EE_DATA 393 394/*=============================================== 395 EEPROM Base Address - 32bit RW 396 ------------------------------------------ 397 This register holds the upper nine bits 398 [23:15] of the 24-bit Wlan hardware memory 399 address for burst reads from EEPROM accesses. 400 The EEPROM provides the lower 15 bits of this address. 401 The MSB of the address from the EEPROM is ignored. 402 ===============================================*/ 403#define ACX_EE_CFG EE_CFG 404 405/*=============================================== 406 GPIO Output Values -32bit, RW 407 ------------------------------------------ 408 [31:16] Reserved 409 [15: 0] Specify the output values (at the output driver inputs) for 410 GPIO[15:0], respectively. 411 ===============================================*/ 412#define ACX_GPIO_OUT_REG GPIO_OUT 413#define ACX_MAX_GPIO_LINES 15 414 415/*=============================================== 416 Contention window -32bit, RW 417 ------------------------------------------ 418 [31:26] Reserved 419 [25:16] Max (0x3ff) 420 [15:07] Reserved 421 [06:00] Current contention window value - default is 0x1F 422 ===============================================*/ 423#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG 424#define ACX_CONT_WIND_MIN_MASK 0x0000007f 425#define ACX_CONT_WIND_MAX 0x03ff0000 426 427/*=============================================== 428 HI_CFG Interface Configuration Register Values 429 ------------------------------------------ 430 ===============================================*/ 431#define HI_CFG_UART_ENABLE 0x00000004 432#define HI_CFG_RST232_ENABLE 0x00000008 433#define HI_CFG_CLOCK_REQ_SELECT 0x00000010 434#define HI_CFG_HOST_INT_ENABLE 0x00000020 435#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 436#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 437#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 438#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 439#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 440 441/* 442 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile 443 * for platforms using active high interrupt level 444 */ 445#ifdef USE_ACTIVE_HIGH 446#define HI_CFG_DEF_VAL \ 447 (HI_CFG_UART_ENABLE | \ 448 HI_CFG_RST232_ENABLE | \ 449 HI_CFG_CLOCK_REQ_SELECT | \ 450 HI_CFG_HOST_INT_ENABLE) 451#else 452#define HI_CFG_DEF_VAL \ 453 (HI_CFG_UART_ENABLE | \ 454 HI_CFG_RST232_ENABLE | \ 455 HI_CFG_CLOCK_REQ_SELECT | \ 456 HI_CFG_HOST_INT_ENABLE) 457 458#endif 459 460#define REF_FREQ_19_2 0 461#define REF_FREQ_26_0 1 462#define REF_FREQ_38_4 2 463#define REF_FREQ_40_0 3 464#define REF_FREQ_33_6 4 465#define REF_FREQ_NUM 5 466 467#define LUT_PARAM_INTEGER_DIVIDER 0 468#define LUT_PARAM_FRACTIONAL_DIVIDER 1 469#define LUT_PARAM_ATTN_BB 2 470#define LUT_PARAM_ALPHA_BB 3 471#define LUT_PARAM_STOP_TIME_BB 4 472#define LUT_PARAM_BB_PLL_LOOP_FILTER 5 473#define LUT_PARAM_NUM 6 474 475#define ACX_EEPROMLESS_IND_REG (SCR_PAD4) 476#define USE_EEPROM 0 477#define SOFT_RESET_MAX_TIME 1000000 478#define SOFT_RESET_STALL_TIME 1000 479#define NVS_DATA_BUNDARY_ALIGNMENT 4 480 481 482/* Firmware image load chunk size */ 483#define CHUNK_SIZE 512 484 485/* Firmware image header size */ 486#define FW_HDR_SIZE 8 487 488#define ECPU_CONTROL_HALT 0x00000101 489 490 491/****************************************************************************** 492 493 CHANNELS, BAND & REG DOMAINS definitions 494 495******************************************************************************/ 496 497 498enum { 499 RADIO_BAND_2_4GHZ = 0, /* 2.4 Ghz band */ 500 RADIO_BAND_5GHZ = 1, /* 5 Ghz band */ 501 RADIO_BAND_JAPAN_4_9_GHZ = 2, 502 DEFAULT_BAND = RADIO_BAND_2_4GHZ, 503 INVALID_BAND = 0xFE, 504 MAX_RADIO_BANDS = 0xFF 505}; 506 507enum { 508 NO_RATE = 0, 509 RATE_1MBPS = 0x0A, 510 RATE_2MBPS = 0x14, 511 RATE_5_5MBPS = 0x37, 512 RATE_6MBPS = 0x0B, 513 RATE_9MBPS = 0x0F, 514 RATE_11MBPS = 0x6E, 515 RATE_12MBPS = 0x0A, 516 RATE_18MBPS = 0x0E, 517 RATE_22MBPS = 0xDC, 518 RATE_24MBPS = 0x09, 519 RATE_36MBPS = 0x0D, 520 RATE_48MBPS = 0x08, 521 RATE_54MBPS = 0x0C 522}; 523 524enum { 525 RATE_INDEX_1MBPS = 0, 526 RATE_INDEX_2MBPS = 1, 527 RATE_INDEX_5_5MBPS = 2, 528 RATE_INDEX_6MBPS = 3, 529 RATE_INDEX_9MBPS = 4, 530 RATE_INDEX_11MBPS = 5, 531 RATE_INDEX_12MBPS = 6, 532 RATE_INDEX_18MBPS = 7, 533 RATE_INDEX_22MBPS = 8, 534 RATE_INDEX_24MBPS = 9, 535 RATE_INDEX_36MBPS = 10, 536 RATE_INDEX_48MBPS = 11, 537 RATE_INDEX_54MBPS = 12, 538 RATE_INDEX_MAX = RATE_INDEX_54MBPS, 539 MAX_RATE_INDEX, 540 INVALID_RATE_INDEX = MAX_RATE_INDEX, 541 RATE_INDEX_ENUM_MAX_SIZE = 0x7FFFFFFF 542}; 543 544enum { 545 RATE_MASK_1MBPS = 0x1, 546 RATE_MASK_2MBPS = 0x2, 547 RATE_MASK_5_5MBPS = 0x4, 548 RATE_MASK_11MBPS = 0x20, 549}; 550 551#define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */ 552#define OFDM_RATE_BIT BIT(6) 553#define PBCC_RATE_BIT BIT(7) 554 555enum { 556 CCK_LONG = 0, 557 CCK_SHORT = SHORT_PREAMBLE_BIT, 558 PBCC_LONG = PBCC_RATE_BIT, 559 PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT, 560 OFDM = OFDM_RATE_BIT 561}; 562 563/****************************************************************************** 564 565Transmit-Descriptor RATE-SET field definitions... 566 567Define a new "Rate-Set" for TX path that incorporates the 568Rate & Modulation info into a single 16-bit field. 569 570TxdRateSet_t: 571b15 - Indicates Preamble type (1=SHORT, 0=LONG). 572 Notes: 573 Must be LONG (0) for 1Mbps rate. 574 Does not apply (set to 0) for RevG-OFDM rates. 575b14 - Indicates PBCC encoding (1=PBCC, 0=not). 576 Notes: 577 Does not apply (set to 0) for rates 1 and 2 Mbps. 578 Does not apply (set to 0) for RevG-OFDM rates. 579b13 - Unused (set to 0). 580b12-b0 - Supported Rate indicator bits as defined below. 581 582******************************************************************************/ 583 584 585/************************************************************************* 586 587 Interrupt Trigger Register (Host -> WiLink) 588 589**************************************************************************/ 590 591/* Hardware to Embedded CPU Interrupts - first 32-bit register set */ 592 593/* 594 * Host Command Interrupt. Setting this bit masks 595 * the interrupt that the host issues to inform 596 * the FW that it has sent a command 597 * to the Wlan hardware Command Mailbox. 598 */ 599#define INTR_TRIG_CMD BIT(0) 600 601/* 602 * Host Event Acknowlegde Interrupt. The host 603 * sets this bit to acknowledge that it received 604 * the unsolicited information from the event 605 * mailbox. 606 */ 607#define INTR_TRIG_EVENT_ACK BIT(1) 608 609/* 610 * The host sets this bit to inform the Wlan 611 * FW that a TX packet is in the XFER 612 * Buffer #0. 613 */ 614#define INTR_TRIG_TX_PROC0 BIT(2) 615 616/* 617 * The host sets this bit to inform the FW 618 * that it read a packet from RX XFER 619 * Buffer #0. 620 */ 621#define INTR_TRIG_RX_PROC0 BIT(3) 622 623#define INTR_TRIG_DEBUG_ACK BIT(4) 624 625#define INTR_TRIG_STATE_CHANGED BIT(5) 626 627 628/* Hardware to Embedded CPU Interrupts - second 32-bit register set */ 629 630/* 631 * The host sets this bit to inform the FW 632 * that it read a packet from RX XFER 633 * Buffer #1. 634 */ 635#define INTR_TRIG_RX_PROC1 BIT(17) 636 637/* 638 * The host sets this bit to inform the Wlan 639 * hardware that a TX packet is in the XFER 640 * Buffer #1. 641 */ 642#define INTR_TRIG_TX_PROC1 BIT(18) 643 644#endif 645