LXR linux/drivers/net/wireless/wl12xx/wl1271

   1/*
   2 * This file is part of wl1271
   3 *
   4 * Copyright (C) 2008-2009 Nokia Corporation
   5 *
   6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License
  10 * version 2 as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope that it will be useful, but
  13 * WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20 * 02110-1301 USA
  21 *
  22 */
  23
  24#include <linux/gpio.h>
  25
  26#include "wl1271_acx.h"
  27#include "wl1271_reg.h"
  28#include "wl1271_boot.h"
  29#include "wl1271_spi.h"
  30#include "wl1271_event.h"
  31
  32static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
  33        [PART_DOWN] = {
  34                .mem = {
  35                        .start = 0x00000000,
  36                        .size  = 0x000177c0
  37                },
  38                .reg = {
  39                        .start = REGISTERS_BASE,
  40                        .size  = 0x00008800
  41                },
  42        },
  43
  44        [PART_WORK] = {
  45                .mem = {
  46                        .start = 0x00040000,
  47                        .size  = 0x00014fc0
  48                },
  49                .reg = {
  50                        .start = REGISTERS_BASE,
  51                        .size  = 0x0000b000
  52                },
  53        },
  54
  55        [PART_DRPW] = {
  56                .mem = {
  57                        .start = 0x00040000,
  58                        .size  = 0x00014fc0
  59                },
  60                .reg = {
  61                        .start = DRPW_BASE,
  62                        .size  = 0x00006000
  63                }
  64        }
  65};
  66
  67static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
  68{
  69        u32 cpu_ctrl;
  70
  71        /* 10.5.0 run the firmware (I) */
  72        cpu_ctrl = wl1271_reg_read32(wl, ACX_REG_ECPU_CONTROL);
  73
  74        /* 10.5.1 run the firmware (II) */
  75        cpu_ctrl |= flag;
  76        wl1271_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
  77}
  78
  79static void wl1271_boot_fw_version(struct wl1271 *wl)
  80{
  81        struct wl1271_static_data static_data;
  82
  83        wl1271_spi_mem_read(wl, wl->cmd_box_addr,
  84                            &static_data, sizeof(static_data));
  85
  86        strncpy(wl->chip.fw_ver, static_data.fw_version,
  87                sizeof(wl->chip.fw_ver));
  88
  89        /* make sure the string is NULL-terminated */
  90        wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
  91}
  92
  93static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
  94                                             size_t fw_data_len, u32 dest)
  95{
  96        int addr, chunk_num, partition_limit;
  97        u8 *p;
  98
  99        /* whal_FwCtrl_LoadFwImageSm() */
 100
 101        wl1271_debug(DEBUG_BOOT, "starting firmware upload");
 102
 103        wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
 104                     fw_data_len, CHUNK_SIZE);
 105
 106
 107        if ((fw_data_len % 4) != 0) {
 108                wl1271_error("firmware length not multiple of four");
 109                return -EIO;
 110        }
 111
 112        wl1271_set_partition(wl, dest,
 113                             part_table[PART_DOWN].mem.size,
 114                             part_table[PART_DOWN].reg.start,
 115                             part_table[PART_DOWN].reg.size);
 116
 117        /* 10.1 set partition limit and chunk num */
 118        chunk_num = 0;
 119        partition_limit = part_table[PART_DOWN].mem.size;
 120
 121        while (chunk_num < fw_data_len / CHUNK_SIZE) {
 122                /* 10.2 update partition, if needed */
 123                addr = dest + (chunk_num + 2) * CHUNK_SIZE;
 124                if (addr > partition_limit) {
 125                        addr = dest + chunk_num * CHUNK_SIZE;
 126                        partition_limit = chunk_num * CHUNK_SIZE +
 127                                part_table[PART_DOWN].mem.size;
 128
 129                        /* FIXME: Over 80 chars! */
 130                        wl1271_set_partition(wl,
 131                                             addr,
 132                                             part_table[PART_DOWN].mem.size,
 133                                             part_table[PART_DOWN].reg.start,
 134                                             part_table[PART_DOWN].reg.size);
 135                }
 136
 137                /* 10.3 upload the chunk */
 138                addr = dest + chunk_num * CHUNK_SIZE;
 139                p = buf + chunk_num * CHUNK_SIZE;
 140                wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 141                             p, addr);
 142                wl1271_spi_mem_write(wl, addr, p, CHUNK_SIZE);
 143
 144                chunk_num++;
 145        }
 146
 147        /* 10.4 upload the last chunk */
 148        addr = dest + chunk_num * CHUNK_SIZE;
 149        p = buf + chunk_num * CHUNK_SIZE;
 150        wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
 151                     fw_data_len % CHUNK_SIZE, p, addr);
 152        wl1271_spi_mem_write(wl, addr, p, fw_data_len % CHUNK_SIZE);
 153
 154        return 0;
 155}
 156
 157static int wl1271_boot_upload_firmware(struct wl1271 *wl)
 158{
 159        u32 chunks, addr, len;
 160        u8 *fw;
 161
 162        fw = wl->fw;
 163        chunks = be32_to_cpup((u32 *) fw);
 164        fw += sizeof(u32);
 165
 166        wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
 167
 168        while (chunks--) {
 169                addr = be32_to_cpup((u32 *) fw);
 170                fw += sizeof(u32);
 171                len = be32_to_cpup((u32 *) fw);
 172                fw += sizeof(u32);
 173
 174                if (len > 300000) {
 175                        wl1271_info("firmware chunk too long: %u", len);
 176                        return -EINVAL;
 177                }
 178                wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
 179                             chunks, addr, len);
 180                wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
 181                fw += len;
 182        }
 183
 184        return 0;
 185}
 186
 187static int wl1271_boot_upload_nvs(struct wl1271 *wl)
 188{
 189        size_t nvs_len, burst_len;
 190        int i;
 191        u32 dest_addr, val;
 192        u8 *nvs_ptr, *nvs, *nvs_aligned;
 193
 194        nvs = wl->nvs;
 195        if (nvs == NULL)
 196                return -ENODEV;
 197
 198        nvs_ptr = nvs;
 199
 200        nvs_len = wl->nvs_len;
 201
 202        /* Update the device MAC address into the nvs */
 203        nvs[11] = wl->mac_addr[0];
 204        nvs[10] = wl->mac_addr[1];
 205        nvs[6] = wl->mac_addr[2];
 206        nvs[5] = wl->mac_addr[3];
 207        nvs[4] = wl->mac_addr[4];
 208        nvs[3] = wl->mac_addr[5];
 209
 210        /*
 211         * Layout before the actual NVS tables:
 212         * 1 byte : burst length.
 213         * 2 bytes: destination address.
 214         * n bytes: data to burst copy.
 215         *
 216         * This is ended by a 0 length, then the NVS tables.
 217         */
 218
 219        /* FIXME: Do we need to check here whether the LSB is 1? */
 220        while (nvs_ptr[0]) {
 221                burst_len = nvs_ptr[0];
 222                dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 223
 224                /* FIXME: Due to our new wl1271_translate_reg_addr function,
 225                   we need to add the REGISTER_BASE to the destination */
 226                dest_addr += REGISTERS_BASE;
 227
 228                /* We move our pointer to the data */
 229                nvs_ptr += 3;
 230
 231                for (i = 0; i < burst_len; i++) {
 232                        val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 233                               | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 234
 235                        wl1271_debug(DEBUG_BOOT,
 236                                     "nvs burst write 0x%x: 0x%x",
 237                                     dest_addr, val);
 238                        wl1271_reg_write32(wl, dest_addr, val);
 239
 240                        nvs_ptr += 4;
 241                        dest_addr += 4;
 242                }
 243        }
 244
 245        /*
 246         * We've reached the first zero length, the first NVS table
 247         * is 7 bytes further.
 248         */
 249        nvs_ptr += 7;
 250        nvs_len -= nvs_ptr - nvs;
 251        nvs_len = ALIGN(nvs_len, 4);
 252
 253        /* FIXME: The driver sets the partition here, but this is not needed,
 254           since it sets to the same one as currently in use */
 255        /* Now we must set the partition correctly */
 256        wl1271_set_partition(wl,
 257                             part_table[PART_WORK].mem.start,
 258                             part_table[PART_WORK].mem.size,
 259                             part_table[PART_WORK].reg.start,
 260                             part_table[PART_WORK].reg.size);
 261
 262        /* Copy the NVS tables to a new block to ensure alignment */
 263        nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
 264
 265        /* And finally we upload the NVS tables */
 266        /* FIXME: In wl1271, we upload everything at once.
 267           No endianness handling needed here?! The ref driver doesn't do
 268           anything about it at this point */
 269        wl1271_spi_mem_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len);
 270
 271        kfree(nvs_aligned);
 272        return 0;
 273}
 274
 275static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
 276{
 277        enable_irq(wl->irq);
 278        wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
 279                           WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 280        wl1271_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
 281}
 282
 283static int wl1271_boot_soft_reset(struct wl1271 *wl)
 284{
 285        unsigned long timeout;
 286        u32 boot_data;
 287
 288        /* perform soft reset */
 289        wl1271_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
 290
 291        /* SOFT_RESET is self clearing */
 292        timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
 293        while (1) {
 294                boot_data = wl1271_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
 295                wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
 296                if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
 297                        break;
 298
 299                if (time_after(jiffies, timeout)) {
 300                        /* 1.2 check pWhalBus->uSelfClearTime if the
 301                         * timeout was reached */
 302                        wl1271_error("soft reset timeout");
 303                        return -1;
 304                }
 305
 306                udelay(SOFT_RESET_STALL_TIME);
 307        }
 308
 309        /* disable Rx/Tx */
 310        wl1271_reg_write32(wl, ENABLE, 0x0);
 311
 312        /* disable auto calibration on start*/
 313        wl1271_reg_write32(wl, SPARE_A2, 0xffff);
 314
 315        return 0;
 316}
 317
 318static int wl1271_boot_run_firmware(struct wl1271 *wl)
 319{
 320        int loop, ret;
 321        u32 chip_id, interrupt;
 322
 323        wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 324
 325        chip_id = wl1271_reg_read32(wl, CHIP_ID_B);
 326
 327        wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 328
 329        if (chip_id != wl->chip.id) {
 330                wl1271_error("chip id doesn't match after firmware boot");
 331                return -EIO;
 332        }
 333
 334        /* wait for init to complete */
 335        loop = 0;
 336        while (loop++ < INIT_LOOP) {
 337                udelay(INIT_LOOP_DELAY);
 338                interrupt = wl1271_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 339
 340                if (interrupt == 0xffffffff) {
 341                        wl1271_error("error reading hardware complete "
 342                                     "init indication");
 343                        return -EIO;
 344                }
 345                /* check that ACX_INTR_INIT_COMPLETE is enabled */
 346                else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
 347                        wl1271_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
 348                                           WL1271_ACX_INTR_INIT_COMPLETE);
 349                        break;
 350                }
 351        }
 352
 353        if (loop >= INIT_LOOP) {
 354                wl1271_error("timeout waiting for the hardware to "
 355                             "complete initialization");
 356                return -EIO;
 357        }
 358
 359        /* get hardware config command mail box */
 360        wl->cmd_box_addr = wl1271_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
 361
 362        /* get hardware config event mail box */
 363        wl->event_box_addr = wl1271_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
 364
 365        /* set the working partition to its "running" mode offset */
 366        wl1271_set_partition(wl,
 367                             part_table[PART_WORK].mem.start,
 368                             part_table[PART_WORK].mem.size,
 369                             part_table[PART_WORK].reg.start,
 370                             part_table[PART_WORK].reg.size);
 371
 372        wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 373                     wl->cmd_box_addr, wl->event_box_addr);
 374
 375        wl1271_boot_fw_version(wl);
 376
 377        /*
 378         * in case of full asynchronous mode the firmware event must be
 379         * ready to receive event from the command mailbox
 380         */
 381
 382        /* enable gpio interrupts */
 383        wl1271_boot_enable_interrupts(wl);
 384
 385        /* unmask all mbox events  */
 386        wl->event_mask = 0xffffffff;
 387
 388        ret = wl1271_event_unmask(wl);
 389        if (ret < 0) {
 390                wl1271_error("EVENT mask setting failed");
 391                return ret;
 392        }
 393
 394        wl1271_event_mbox_config(wl);
 395
 396        /* firmware startup completed */
 397        return 0;
 398}
 399
 400static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
 401{
 402        u32 polarity, status, i;
 403
 404        wl1271_reg_write32(wl, OCP_POR_CTR, OCP_REG_POLARITY);
 405        wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_READ);
 406
 407        /* Wait until the command is complete (ie. bit 18 is set) */
 408        for (i = 0; i < OCP_CMD_LOOP; i++) {
 409                polarity = wl1271_reg_read32(wl, OCP_DATA_READ);
 410                if (polarity & OCP_READY_MASK)
 411                        break;
 412        }
 413        if (i == OCP_CMD_LOOP) {
 414                wl1271_error("OCP command timeout!");
 415                return -EIO;
 416        }
 417
 418        status = polarity & OCP_STATUS_MASK;
 419        if (status != OCP_STATUS_OK) {
 420                wl1271_error("OCP command failed (%d)", status);
 421                return -EIO;
 422        }
 423
 424        /* We use HIGH polarity, so unset the LOW bit */
 425        polarity &= ~POLARITY_LOW;
 426
 427        wl1271_reg_write32(wl, OCP_POR_CTR, OCP_REG_POLARITY);
 428        wl1271_reg_write32(wl, OCP_DATA_WRITE, polarity);
 429        wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_WRITE);
 430
 431        return 0;
 432}
 433
 434int wl1271_boot(struct wl1271 *wl)
 435{
 436        int ret = 0;
 437        u32 tmp, clk, pause;
 438
 439        if (REF_CLOCK == 0 || REF_CLOCK == 2)
 440                /* ref clk: 19.2/38.4 */
 441                clk = 0x3;
 442        else if (REF_CLOCK == 1 || REF_CLOCK == 3)
 443                /* ref clk: 26/52 */
 444                clk = 0x5;
 445
 446        wl1271_reg_write32(wl, PLL_PARAMETERS, clk);
 447
 448        pause = wl1271_reg_read32(wl, PLL_PARAMETERS);
 449
 450        wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
 451
 452        pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
 453                                           * WU_COUNTER_PAUSE_VAL instead of
 454                                           * 0x3ff (magic number ).  How does
 455                                           * this work?! */
 456        pause |= WU_COUNTER_PAUSE_VAL;
 457        wl1271_reg_write32(wl, WU_COUNTER_PAUSE, pause);
 458
 459        /* Continue the ELP wake up sequence */
 460        wl1271_reg_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 461        udelay(500);
 462
 463        wl1271_set_partition(wl,
 464                             part_table[PART_DRPW].mem.start,
 465                             part_table[PART_DRPW].mem.size,
 466                             part_table[PART_DRPW].reg.start,
 467                             part_table[PART_DRPW].reg.size);
 468
 469        /* Read-modify-write DRPW_SCRATCH_START register (see next state)
 470           to be used by DRPw FW. The RTRIM value will be added by the FW
 471           before taking DRPw out of reset */
 472
 473        wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
 474        clk = wl1271_reg_read32(wl, DRPW_SCRATCH_START);
 475
 476        wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 477
 478        /* 2 */
 479        clk |= (REF_CLOCK << 1) << 4;
 480        wl1271_reg_write32(wl, DRPW_SCRATCH_START, clk);
 481
 482        wl1271_set_partition(wl,
 483                             part_table[PART_WORK].mem.start,
 484                             part_table[PART_WORK].mem.size,
 485                             part_table[PART_WORK].reg.start,
 486                             part_table[PART_WORK].reg.size);
 487
 488        /* Disable interrupts */
 489        wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 490
 491        ret = wl1271_boot_soft_reset(wl);
 492        if (ret < 0)
 493                goto out;
 494
 495        /* 2. start processing NVS file */
 496        ret = wl1271_boot_upload_nvs(wl);
 497        if (ret < 0)
 498                goto out;
 499
 500        /* write firmware's last address (ie. it's length) to
 501         * ACX_EEPROMLESS_IND_REG */
 502        wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
 503
 504        wl1271_reg_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
 505
 506        tmp = wl1271_reg_read32(wl, CHIP_ID_B);
 507
 508        wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 509
 510        /* 6. read the EEPROM parameters */
 511        tmp = wl1271_reg_read32(wl, SCR_PAD2);
 512
 513        ret = wl1271_boot_write_irq_polarity(wl);
 514        if (ret < 0)
 515                goto out;
 516
 517        /* FIXME: Need to check whether this is really what we want */
 518        wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
 519                           WL1271_ACX_ALL_EVENTS_VECTOR);
 520
 521        /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
 522         * to upload_fw) */
 523
 524        ret = wl1271_boot_upload_firmware(wl);
 525        if (ret < 0)
 526                goto out;
 527
 528        /* 10.5 start firmware */
 529        ret = wl1271_boot_run_firmware(wl);
 530        if (ret < 0)
 531                goto out;
 532
 533        /* set the wl1271 default filters */
 534        wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
 535        wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
 536
 537        wl1271_event_mbox_config(wl);
 538
 539out:
 540        return ret;
 541}
 542