1/* 2 * Private structs/constants for PARISC IOSAPIC support 3 * 4 * Copyright (C) 2000 Hewlett Packard (Grant Grundler) 5 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org) 6 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org) 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24/* 25** This file is private to iosapic driver. 26** If stuff needs to be used by another driver, move it to a common file. 27** 28** WARNING: fields most data structures here are ordered to make sure 29** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8) 30*/ 31 32 33/* 34** Interrupt Routing Stuff 35** ----------------------- 36** The interrupt routing table consists of entries derived from 37** MP Specification Draft 1.5. There is one interrupt routing 38** table per cell. N- and L-class consist of a single cell. 39*/ 40struct irt_entry { 41 42 /* Entry Type 139 identifies an I/O SAPIC interrupt entry */ 43 u8 entry_type; 44 45 /* Entry Length 16 indicates entry is 16 bytes long */ 46 u8 entry_length; 47 48 /* 49 ** Interrupt Type of 0 indicates a vectored interrupt, 50 ** all other values are reserved 51 */ 52 u8 interrupt_type; 53 54 /* 55 ** PO and EL 56 ** Polarity of SAPIC I/O input signals: 57 ** 00 = Reserved 58 ** 01 = Active high 59 ** 10 = Reserved 60 ** 11 = Active low 61 ** Trigger mode of SAPIC I/O input signals: 62 ** 00 = Reserved 63 ** 01 = Edge-triggered 64 ** 10 = Reserved 65 ** 11 = Level-triggered 66 */ 67 u8 polarity_trigger; 68 69 /* 70 ** IRQ and DEVNO 71 ** irq identifies PCI interrupt signal where 72 ** 0x0 corresponds to INT_A#, 73 ** 0x1 corresponds to INT_B#, 74 ** 0x2 corresponds to INT_C# 75 ** 0x3 corresponds to INT_D# 76 ** PCI device number where interrupt originates 77 */ 78 u8 src_bus_irq_devno; 79 80 /* Source Bus ID identifies the bus where interrupt signal comes from */ 81 u8 src_bus_id; 82 83 /* 84 ** Segment ID is unique across a protection domain and 85 ** identifies a segment of PCI buses (reserved in 86 ** MP Specification Draft 1.5) 87 */ 88 u8 src_seg_id; 89 90 /* 91 ** Destination I/O SAPIC INTIN# identifies the INTIN n pin 92 ** to which the signal is connected 93 */ 94 u8 dest_iosapic_intin; 95 96 /* 97 ** Destination I/O SAPIC Address identifies the I/O SAPIC 98 ** to which the signal is connected 99 */ 100 u64 dest_iosapic_addr; 101}; 102 103#define IRT_IOSAPIC_TYPE 139 104#define IRT_IOSAPIC_LENGTH 16 105 106#define IRT_VECTORED_INTR 0 107 108#define IRT_PO_MASK 0x3 109#define IRT_ACTIVE_HI 1 110#define IRT_ACTIVE_LO 3 111 112#define IRT_EL_MASK 0x3 113#define IRT_EL_SHIFT 2 114#define IRT_EDGE_TRIG 1 115#define IRT_LEVEL_TRIG 3 116 117#define IRT_IRQ_MASK 0x3 118#define IRT_DEV_MASK 0x1f 119#define IRT_DEV_SHIFT 2 120 121#define IRT_IRQ_DEVNO_MASK ((IRT_DEV_MASK << IRT_DEV_SHIFT) | IRT_IRQ_MASK) 122 123#ifdef SUPPORT_MULTI_CELL 124struct iosapic_irt { 125 struct iosapic_irt *irt_next; /* next routing table */ 126 struct irt_entry *irt_base; /* intr routing table address */ 127 size_t irte_count; /* number of entries in the table */ 128 size_t irte_size; /* size (bytes) of each entry */ 129}; 130#endif 131 132struct vector_info { 133 struct iosapic_info *iosapic; /* I/O SAPIC this vector is on */ 134 struct irt_entry *irte; /* IRT entry */ 135 u32 __iomem *eoi_addr; /* precalculate EOI reg address */ 136 u32 eoi_data; /* IA64: ? PA: swapped txn_data */ 137 int txn_irq; /* virtual IRQ number for processor */ 138 ulong txn_addr; /* IA64: id_eid PA: partial HPA */ 139 u32 txn_data; /* CPU interrupt bit */ 140 u8 status; /* status/flags */ 141 u8 irqline; /* INTINn(IRQ) */ 142}; 143 144 145struct iosapic_info { 146 struct iosapic_info * isi_next; /* list of I/O SAPIC */ 147 void __iomem * addr; /* remapped address */ 148 unsigned long isi_hpa; /* physical base address */ 149 struct vector_info * isi_vector; /* IRdT (IRQ line) array */ 150 int isi_num_vectors; /* size of IRdT array */ 151 int isi_status; /* status/flags */ 152 unsigned int isi_version; /* DEBUG: data fr version reg */ 153}; 154 155 156 157#ifdef __IA64__ 158/* 159** PA risc does NOT have any local sapics. IA64 does. 160** PIB (Processor Interrupt Block) is handled by Astro or Dew (Stretch CEC). 161** 162** PA: Get id_eid from IRT and hardcode PIB to 0xfeeNNNN0 163** Emulate the data on PAT platforms. 164*/ 165struct local_sapic_info { 166 struct local_sapic_info *lsi_next; /* point to next CPU info */ 167 int *lsi_cpu_id; /* point to logical CPU id */ 168 unsigned long *lsi_id_eid; /* point to IA-64 CPU id */ 169 int *lsi_status; /* point to CPU status */ 170 void *lsi_private; /* point to special info */ 171}; 172 173/* 174** "root" data structure which ties everything together. 175** Should always be able to start with sapic_root and locate 176** the desired information. 177*/ 178struct sapic_info { 179 struct sapic_info *si_next; /* info is per cell */ 180 int si_cellid; /* cell id */ 181 unsigned int si_status; /* status */ 182 char *si_pib_base; /* intr blk base address */ 183 local_sapic_info_t *si_local_info; 184 io_sapic_info_t *si_io_info; 185 extint_info_t *si_extint_info;/* External Intr info */ 186}; 187#endif 188 189