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75#if !defined(DEBUG_PARPORT_IP32)
76# define DEBUG_PARPORT_IP32 0
77#endif
78
79
80
81
82
83
84#if DEBUG_PARPORT_IP32 == 1
85# warning DEBUG_PARPORT_IP32 == 1
86#elif DEBUG_PARPORT_IP32 == 2
87# warning DEBUG_PARPORT_IP32 == 2
88#elif DEBUG_PARPORT_IP32 >= 3
89# warning DEBUG_PARPORT_IP32 >= 3
90# if !defined(DEBUG)
91# define DEBUG
92# endif
93#endif
94
95#include <linux/completion.h>
96#include <linux/delay.h>
97#include <linux/dma-mapping.h>
98#include <linux/err.h>
99#include <linux/init.h>
100#include <linux/interrupt.h>
101#include <linux/jiffies.h>
102#include <linux/kernel.h>
103#include <linux/module.h>
104#include <linux/parport.h>
105#include <linux/sched.h>
106#include <linux/spinlock.h>
107#include <linux/stddef.h>
108#include <linux/types.h>
109#include <asm/io.h>
110#include <asm/ip32/ip32_ints.h>
111#include <asm/ip32/mace.h>
112
113
114
115
116#if DEBUG_PARPORT_IP32 >= 1
117# define DEFAULT_VERBOSE_PROBING 1
118#else
119# define DEFAULT_VERBOSE_PROBING 0
120#endif
121
122
123#define PPIP32 "parport_ip32: "
124
125
126
127
128
129
130
131#define PARPORT_IP32_ENABLE_IRQ (1U << 0)
132#define PARPORT_IP32_ENABLE_DMA (1U << 1)
133#define PARPORT_IP32_ENABLE_SPP (1U << 2)
134#define PARPORT_IP32_ENABLE_EPP (1U << 3)
135#define PARPORT_IP32_ENABLE_ECP (1U << 4)
136static unsigned int features = ~0U;
137static int verbose_probing = DEFAULT_VERBOSE_PROBING;
138
139
140static struct parport *this_port = NULL;
141
142
143#define FIFO_NFAULT_TIMEOUT 100
144#define FIFO_POLLING_INTERVAL 50
145
146
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148
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165
166
167struct parport_ip32_regs {
168 void __iomem *data;
169 void __iomem *dsr;
170 void __iomem *dcr;
171 void __iomem *eppAddr;
172 void __iomem *eppData0;
173 void __iomem *eppData1;
174 void __iomem *eppData2;
175 void __iomem *eppData3;
176 void __iomem *ecpAFifo;
177 void __iomem *fifo;
178 void __iomem *cnfgA;
179 void __iomem *cnfgB;
180 void __iomem *ecr;
181};
182
183
184#define DSR_nBUSY (1U << 7)
185#define DSR_nACK (1U << 6)
186#define DSR_PERROR (1U << 5)
187#define DSR_SELECT (1U << 4)
188#define DSR_nFAULT (1U << 3)
189#define DSR_nPRINT (1U << 2)
190
191#define DSR_TIMEOUT (1U << 0)
192
193
194
195#define DCR_DIR (1U << 5)
196#define DCR_IRQ (1U << 4)
197#define DCR_SELECT (1U << 3)
198#define DCR_nINIT (1U << 2)
199#define DCR_AUTOFD (1U << 1)
200#define DCR_STROBE (1U << 0)
201
202
203#define CNFGA_IRQ (1U << 7)
204#define CNFGA_ID_MASK ((1U << 6) | (1U << 5) | (1U << 4))
205#define CNFGA_ID_SHIFT 4
206#define CNFGA_ID_16 (00U << CNFGA_ID_SHIFT)
207#define CNFGA_ID_8 (01U << CNFGA_ID_SHIFT)
208#define CNFGA_ID_32 (02U << CNFGA_ID_SHIFT)
209
210#define CNFGA_nBYTEINTRANS (1U << 2)
211#define CNFGA_PWORDLEFT ((1U << 1) | (1U << 0))
212
213
214#define CNFGB_COMPRESS (1U << 7)
215#define CNFGB_INTRVAL (1U << 6)
216#define CNFGB_IRQ_MASK ((1U << 5) | (1U << 4) | (1U << 3))
217#define CNFGB_IRQ_SHIFT 3
218#define CNFGB_DMA_MASK ((1U << 2) | (1U << 1) | (1U << 0))
219#define CNFGB_DMA_SHIFT 0
220
221
222#define ECR_MODE_MASK ((1U << 7) | (1U << 6) | (1U << 5))
223#define ECR_MODE_SHIFT 5
224#define ECR_MODE_SPP (00U << ECR_MODE_SHIFT)
225#define ECR_MODE_PS2 (01U << ECR_MODE_SHIFT)
226#define ECR_MODE_PPF (02U << ECR_MODE_SHIFT)
227#define ECR_MODE_ECP (03U << ECR_MODE_SHIFT)
228#define ECR_MODE_EPP (04U << ECR_MODE_SHIFT)
229
230#define ECR_MODE_TST (06U << ECR_MODE_SHIFT)
231#define ECR_MODE_CFG (07U << ECR_MODE_SHIFT)
232#define ECR_nERRINTR (1U << 4)
233#define ECR_DMAEN (1U << 3)
234#define ECR_SERVINTR (1U << 2)
235#define ECR_F_FULL (1U << 1)
236#define ECR_F_EMPTY (1U << 0)
237
238
239
240
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242
243
244
245enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE };
246
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260
261struct parport_ip32_private {
262 struct parport_ip32_regs regs;
263 unsigned int dcr_cache;
264 unsigned int dcr_writable;
265 unsigned int pword;
266 unsigned int fifo_depth;
267 unsigned int readIntrThreshold;
268 unsigned int writeIntrThreshold;
269 enum parport_ip32_irq_mode irq_mode;
270 struct completion irq_complete;
271};
272
273
274
275
276
277
278
279
280#if DEBUG_PARPORT_IP32 >= 1
281# define pr_debug1(...) printk(KERN_DEBUG __VA_ARGS__)
282#else
283# define pr_debug1(...) do { } while (0)
284#endif
285
286
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294
295
296
297#define __pr_trace(pr, p, fmt, ...) \
298 pr("%s: %s" fmt "\n", \
299 ({ const struct parport *__p = (p); \
300 __p ? __p->name : "parport_ip32"; }), \
301 __func__ , ##__VA_ARGS__)
302#define pr_trace(p, fmt, ...) __pr_trace(pr_debug, p, fmt , ##__VA_ARGS__)
303#define pr_trace1(p, fmt, ...) __pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__)
304
305
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311
312
313#define __pr_probe(...) \
314 do { if (verbose_probing) printk(__VA_ARGS__); } while (0)
315#define pr_probe(p, fmt, ...) \
316 __pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__)
317
318
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327
328
329#if DEBUG_PARPORT_IP32 >= 2
330static void parport_ip32_dump_state(struct parport *p, char *str,
331 unsigned int show_ecp_config)
332{
333 struct parport_ip32_private * const priv = p->physport->private_data;
334 unsigned int i;
335
336 printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str);
337 {
338 static const char ecr_modes[8][4] = {"SPP", "PS2", "PPF",
339 "ECP", "EPP", "???",
340 "TST", "CFG"};
341 unsigned int ecr = readb(priv->regs.ecr);
342 printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr);
343 printk(" %s",
344 ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]);
345 if (ecr & ECR_nERRINTR)
346 printk(",nErrIntrEn");
347 if (ecr & ECR_DMAEN)
348 printk(",dmaEn");
349 if (ecr & ECR_SERVINTR)
350 printk(",serviceIntr");
351 if (ecr & ECR_F_FULL)
352 printk(",f_full");
353 if (ecr & ECR_F_EMPTY)
354 printk(",f_empty");
355 printk("\n");
356 }
357 if (show_ecp_config) {
358 unsigned int oecr, cnfgA, cnfgB;
359 oecr = readb(priv->regs.ecr);
360 writeb(ECR_MODE_PS2, priv->regs.ecr);
361 writeb(ECR_MODE_CFG, priv->regs.ecr);
362 cnfgA = readb(priv->regs.cnfgA);
363 cnfgB = readb(priv->regs.cnfgB);
364 writeb(ECR_MODE_PS2, priv->regs.ecr);
365 writeb(oecr, priv->regs.ecr);
366 printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA);
367 printk(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses");
368 switch (cnfgA & CNFGA_ID_MASK) {
369 case CNFGA_ID_8:
370 printk(",8 bits");
371 break;
372 case CNFGA_ID_16:
373 printk(",16 bits");
374 break;
375 case CNFGA_ID_32:
376 printk(",32 bits");
377 break;
378 default:
379 printk(",unknown ID");
380 break;
381 }
382 if (!(cnfgA & CNFGA_nBYTEINTRANS))
383 printk(",ByteInTrans");
384 if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8)
385 printk(",%d byte%s left", cnfgA & CNFGA_PWORDLEFT,
386 ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : "");
387 printk("\n");
388 printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB);
389 printk(" irq=%u,dma=%u",
390 (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT,
391 (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT);
392 printk(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL));
393 if (cnfgB & CNFGB_COMPRESS)
394 printk(",compress");
395 printk("\n");
396 }
397 for (i = 0; i < 2; i++) {
398 unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr);
399 printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x",
400 i ? "soft" : "hard", dcr);
401 printk(" %s", (dcr & DCR_DIR) ? "rev" : "fwd");
402 if (dcr & DCR_IRQ)
403 printk(",ackIntEn");
404 if (!(dcr & DCR_SELECT))
405 printk(",nSelectIn");
406 if (dcr & DCR_nINIT)
407 printk(",nInit");
408 if (!(dcr & DCR_AUTOFD))
409 printk(",nAutoFD");
410 if (!(dcr & DCR_STROBE))
411 printk(",nStrobe");
412 printk("\n");
413 }
414#define sep (f++ ? ',' : ' ')
415 {
416 unsigned int f = 0;
417 unsigned int dsr = readb(priv->regs.dsr);
418 printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr);
419 if (!(dsr & DSR_nBUSY))
420 printk("%cBusy", sep);
421 if (dsr & DSR_nACK)
422 printk("%cnAck", sep);
423 if (dsr & DSR_PERROR)
424 printk("%cPError", sep);
425 if (dsr & DSR_SELECT)
426 printk("%cSelect", sep);
427 if (dsr & DSR_nFAULT)
428 printk("%cnFault", sep);
429 if (!(dsr & DSR_nPRINT))
430 printk("%c(Print)", sep);
431 if (dsr & DSR_TIMEOUT)
432 printk("%cTimeout", sep);
433 printk("\n");
434 }
435#undef sep
436}
437#else
438#define parport_ip32_dump_state(...) do { } while (0)
439#endif
440
441
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448
449
450
451#if DEBUG_PARPORT_IP32 >= 1
452#define CHECK_EXTRA_BITS(p, b, m) \
453 do { \
454 unsigned int __b = (b), __m = (m); \
455 if (__b & ~__m) \
456 pr_debug1(PPIP32 "%s: extra bits in %s(%s): " \
457 "0x%02x/0x%02x\n", \
458 (p)->name, __func__, #b, __b, __m); \
459 } while (0)
460#else
461#define CHECK_EXTRA_BITS(...) do { } while (0)
462#endif
463
464
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475
476
477struct parport_ip32_dma_data {
478 enum dma_data_direction dir;
479 dma_addr_t buf;
480 dma_addr_t next;
481 size_t len;
482 size_t left;
483 unsigned int ctx;
484 unsigned int irq_on;
485 spinlock_t lock;
486};
487static struct parport_ip32_dma_data parport_ip32_dma;
488
489
490
491
492
493
494
495
496static void parport_ip32_dma_setup_context(unsigned int limit)
497{
498 unsigned long flags;
499
500 spin_lock_irqsave(&parport_ip32_dma.lock, flags);
501 if (parport_ip32_dma.left > 0) {
502
503
504
505 volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ?
506 &mace->perif.ctrl.parport.context_a :
507 &mace->perif.ctrl.parport.context_b;
508 u64 count;
509 u64 ctxval;
510 if (parport_ip32_dma.left <= limit) {
511 count = parport_ip32_dma.left;
512 ctxval = MACEPAR_CONTEXT_LASTFLAG;
513 } else {
514 count = limit;
515 ctxval = 0;
516 }
517
518 pr_trace(NULL,
519 "(%u): 0x%04x:0x%04x, %u -> %u%s",
520 limit,
521 (unsigned int)parport_ip32_dma.buf,
522 (unsigned int)parport_ip32_dma.next,
523 (unsigned int)count,
524 parport_ip32_dma.ctx, ctxval ? "*" : "");
525
526 ctxval |= parport_ip32_dma.next &
527 MACEPAR_CONTEXT_BASEADDR_MASK;
528 ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) &
529 MACEPAR_CONTEXT_DATALEN_MASK;
530 writeq(ctxval, ctxreg);
531 parport_ip32_dma.next += count;
532 parport_ip32_dma.left -= count;
533 parport_ip32_dma.ctx ^= 1U;
534 }
535
536
537
538 if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) {
539 pr_debug(PPIP32 "IRQ off (ctx)\n");
540 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
541 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
542 parport_ip32_dma.irq_on = 0;
543 }
544 spin_unlock_irqrestore(&parport_ip32_dma.lock, flags);
545}
546
547
548
549
550
551
552static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id)
553{
554 if (parport_ip32_dma.left)
555 pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx);
556 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
557 return IRQ_HANDLED;
558}
559
560#if DEBUG_PARPORT_IP32
561static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id)
562{
563 pr_trace1(NULL, "(%d)", irq);
564 return IRQ_HANDLED;
565}
566#endif
567
568
569
570
571
572
573
574
575
576
577static int parport_ip32_dma_start(enum dma_data_direction dir,
578 void *addr, size_t count)
579{
580 unsigned int limit;
581 u64 ctrl;
582
583 pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count);
584
585
586
587 BUG_ON(dir != DMA_TO_DEVICE);
588
589
590 ctrl = MACEPAR_CTLSTAT_RESET;
591 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
592
593
594 if (!parport_ip32_dma.irq_on) {
595 WARN_ON(1);
596 enable_irq(MACEISA_PAR_CTXA_IRQ);
597 enable_irq(MACEISA_PAR_CTXB_IRQ);
598 parport_ip32_dma.irq_on = 1;
599 }
600
601
602 parport_ip32_dma.dir = dir;
603 parport_ip32_dma.buf = dma_map_single(NULL, addr, count, dir);
604 parport_ip32_dma.len = count;
605 parport_ip32_dma.next = parport_ip32_dma.buf;
606 parport_ip32_dma.left = parport_ip32_dma.len;
607 parport_ip32_dma.ctx = 0;
608
609
610 ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION;
611 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
612
613 limit = MACEPAR_CONTEXT_DATA_BOUND -
614 (parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1));
615 parport_ip32_dma_setup_context(limit);
616 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
617
618
619 ctrl |= MACEPAR_CTLSTAT_ENABLE;
620 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
621
622 return 0;
623}
624
625
626
627
628
629
630
631static void parport_ip32_dma_stop(void)
632{
633 u64 ctx_a;
634 u64 ctx_b;
635 u64 ctrl;
636 u64 diag;
637 size_t res[2];
638
639 pr_trace(NULL, "()");
640
641
642 spin_lock_irq(&parport_ip32_dma.lock);
643 if (parport_ip32_dma.irq_on) {
644 pr_debug(PPIP32 "IRQ off (stop)\n");
645 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
646 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
647 parport_ip32_dma.irq_on = 0;
648 }
649 spin_unlock_irq(&parport_ip32_dma.lock);
650
651
652 synchronize_irq(MACEISA_PAR_CTXA_IRQ);
653 synchronize_irq(MACEISA_PAR_CTXB_IRQ);
654
655
656 ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
657 ctrl &= ~MACEPAR_CTLSTAT_ENABLE;
658 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
659
660
661 ctx_a = readq(&mace->perif.ctrl.parport.context_a);
662 ctx_b = readq(&mace->perif.ctrl.parport.context_b);
663 ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
664 diag = readq(&mace->perif.ctrl.parport.diagnostic);
665 res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ?
666 1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >>
667 MACEPAR_CONTEXT_DATALEN_SHIFT) :
668 0;
669 res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ?
670 1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >>
671 MACEPAR_CONTEXT_DATALEN_SHIFT) :
672 0;
673 if (diag & MACEPAR_DIAG_DMACTIVE)
674 res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] =
675 1 + ((diag & MACEPAR_DIAG_CTRMASK) >>
676 MACEPAR_DIAG_CTRSHIFT);
677 parport_ip32_dma.left += res[0] + res[1];
678
679
680 ctrl = MACEPAR_CTLSTAT_RESET;
681 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
682 pr_debug(PPIP32 "IRQ on (stop)\n");
683 enable_irq(MACEISA_PAR_CTXA_IRQ);
684 enable_irq(MACEISA_PAR_CTXB_IRQ);
685 parport_ip32_dma.irq_on = 1;
686
687 dma_unmap_single(NULL, parport_ip32_dma.buf, parport_ip32_dma.len,
688 parport_ip32_dma.dir);
689}
690
691
692
693
694
695
696static inline size_t parport_ip32_dma_get_residue(void)
697{
698 return parport_ip32_dma.left;
699}
700
701
702
703
704
705
706static int parport_ip32_dma_register(void)
707{
708 int err;
709
710 spin_lock_init(&parport_ip32_dma.lock);
711 parport_ip32_dma.irq_on = 1;
712
713
714 writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat);
715
716
717 err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt,
718 0, "parport_ip32", NULL);
719 if (err)
720 goto fail_a;
721 err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt,
722 0, "parport_ip32", NULL);
723 if (err)
724 goto fail_b;
725#if DEBUG_PARPORT_IP32
726
727 err = request_irq(MACEISA_PAR_MERR_IRQ, parport_ip32_merr_interrupt,
728 0, "parport_ip32", NULL);
729 if (err)
730 goto fail_merr;
731#endif
732 return 0;
733
734#if DEBUG_PARPORT_IP32
735fail_merr:
736 free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
737#endif
738fail_b:
739 free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
740fail_a:
741 return err;
742}
743
744
745
746
747static void parport_ip32_dma_unregister(void)
748{
749#if DEBUG_PARPORT_IP32
750 free_irq(MACEISA_PAR_MERR_IRQ, NULL);
751#endif
752 free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
753 free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
754}
755
756
757
758
759
760
761
762static inline void parport_ip32_wakeup(struct parport *p)
763{
764 struct parport_ip32_private * const priv = p->physport->private_data;
765 complete(&priv->irq_complete);
766}
767
768
769
770
771
772
773
774
775
776static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id)
777{
778 struct parport * const p = dev_id;
779 struct parport_ip32_private * const priv = p->physport->private_data;
780 enum parport_ip32_irq_mode irq_mode = priv->irq_mode;
781
782 switch (irq_mode) {
783 case PARPORT_IP32_IRQ_FWD:
784 return parport_irq_handler(irq, dev_id);
785
786 case PARPORT_IP32_IRQ_HERE:
787 parport_ip32_wakeup(p);
788 break;
789 }
790
791 return IRQ_HANDLED;
792}
793
794
795
796
797
798
799
800static inline unsigned int parport_ip32_read_econtrol(struct parport *p)
801{
802 struct parport_ip32_private * const priv = p->physport->private_data;
803 return readb(priv->regs.ecr);
804}
805
806
807
808
809
810
811static inline void parport_ip32_write_econtrol(struct parport *p,
812 unsigned int c)
813{
814 struct parport_ip32_private * const priv = p->physport->private_data;
815 writeb(c, priv->regs.ecr);
816}
817
818
819
820
821
822
823
824
825
826
827static inline void parport_ip32_frob_econtrol(struct parport *p,
828 unsigned int mask,
829 unsigned int val)
830{
831 unsigned int c;
832 c = (parport_ip32_read_econtrol(p) & ~mask) ^ val;
833 parport_ip32_write_econtrol(p, c);
834}
835
836
837
838
839
840
841
842
843
844static void parport_ip32_set_mode(struct parport *p, unsigned int mode)
845{
846 unsigned int omode;
847
848 mode &= ECR_MODE_MASK;
849 omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK;
850
851 if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2
852 || omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) {
853
854 unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
855 parport_ip32_write_econtrol(p, ecr);
856 }
857 parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR);
858}
859
860
861
862
863
864
865
866static inline unsigned char parport_ip32_read_data(struct parport *p)
867{
868 struct parport_ip32_private * const priv = p->physport->private_data;
869 return readb(priv->regs.data);
870}
871
872
873
874
875
876
877static inline void parport_ip32_write_data(struct parport *p, unsigned char d)
878{
879 struct parport_ip32_private * const priv = p->physport->private_data;
880 writeb(d, priv->regs.data);
881}
882
883
884
885
886
887static inline unsigned char parport_ip32_read_status(struct parport *p)
888{
889 struct parport_ip32_private * const priv = p->physport->private_data;
890 return readb(priv->regs.dsr);
891}
892
893
894
895
896
897static inline unsigned int __parport_ip32_read_control(struct parport *p)
898{
899 struct parport_ip32_private * const priv = p->physport->private_data;
900 return priv->dcr_cache;
901}
902
903
904
905
906
907
908static inline void __parport_ip32_write_control(struct parport *p,
909 unsigned int c)
910{
911 struct parport_ip32_private * const priv = p->physport->private_data;
912 CHECK_EXTRA_BITS(p, c, priv->dcr_writable);
913 c &= priv->dcr_writable;
914 writeb(c, priv->regs.dcr);
915 priv->dcr_cache = c;
916}
917
918
919
920
921
922
923
924
925
926
927
928static inline void __parport_ip32_frob_control(struct parport *p,
929 unsigned int mask,
930 unsigned int val)
931{
932 unsigned int c;
933 c = (__parport_ip32_read_control(p) & ~mask) ^ val;
934 __parport_ip32_write_control(p, c);
935}
936
937
938
939
940
941
942
943
944static inline unsigned char parport_ip32_read_control(struct parport *p)
945{
946 const unsigned int rm =
947 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
948 return __parport_ip32_read_control(p) & rm;
949}
950
951
952
953
954
955
956
957
958
959static inline void parport_ip32_write_control(struct parport *p,
960 unsigned char c)
961{
962 const unsigned int wm =
963 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
964 CHECK_EXTRA_BITS(p, c, wm);
965 __parport_ip32_frob_control(p, wm, c & wm);
966}
967
968
969
970
971
972
973
974
975
976
977static inline unsigned char parport_ip32_frob_control(struct parport *p,
978 unsigned char mask,
979 unsigned char val)
980{
981 const unsigned int wm =
982 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
983 CHECK_EXTRA_BITS(p, mask, wm);
984 CHECK_EXTRA_BITS(p, val, wm);
985 __parport_ip32_frob_control(p, mask & wm, val & wm);
986 return parport_ip32_read_control(p);
987}
988
989
990
991
992
993static inline void parport_ip32_disable_irq(struct parport *p)
994{
995 __parport_ip32_frob_control(p, DCR_IRQ, 0);
996}
997
998
999
1000
1001
1002static inline void parport_ip32_enable_irq(struct parport *p)
1003{
1004 __parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ);
1005}
1006
1007
1008
1009
1010
1011
1012
1013static inline void parport_ip32_data_forward(struct parport *p)
1014{
1015 __parport_ip32_frob_control(p, DCR_DIR, 0);
1016}
1017
1018
1019
1020
1021
1022
1023
1024
1025static inline void parport_ip32_data_reverse(struct parport *p)
1026{
1027 __parport_ip32_frob_control(p, DCR_DIR, DCR_DIR);
1028}
1029
1030
1031
1032
1033
1034
1035static void parport_ip32_init_state(struct pardevice *dev,
1036 struct parport_state *s)
1037{
1038 s->u.ip32.dcr = DCR_SELECT | DCR_nINIT;
1039 s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
1040}
1041
1042
1043
1044
1045
1046
1047static void parport_ip32_save_state(struct parport *p,
1048 struct parport_state *s)
1049{
1050 s->u.ip32.dcr = __parport_ip32_read_control(p);
1051 s->u.ip32.ecr = parport_ip32_read_econtrol(p);
1052}
1053
1054
1055
1056
1057
1058
1059static void parport_ip32_restore_state(struct parport *p,
1060 struct parport_state *s)
1061{
1062 parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK);
1063 parport_ip32_write_econtrol(p, s->u.ip32.ecr);
1064 __parport_ip32_write_control(p, s->u.ip32.dcr);
1065}
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075static unsigned int parport_ip32_clear_epp_timeout(struct parport *p)
1076{
1077 struct parport_ip32_private * const priv = p->physport->private_data;
1078 unsigned int cleared;
1079
1080 if (!(parport_ip32_read_status(p) & DSR_TIMEOUT))
1081 cleared = 1;
1082 else {
1083 unsigned int r;
1084
1085 parport_ip32_read_status(p);
1086 r = parport_ip32_read_status(p);
1087
1088 writeb(r | DSR_TIMEOUT, priv->regs.dsr);
1089
1090 writeb(r & ~DSR_TIMEOUT, priv->regs.dsr);
1091
1092 r = parport_ip32_read_status(p);
1093 cleared = !(r & DSR_TIMEOUT);
1094 }
1095
1096 pr_trace(p, "(): %s", cleared ? "cleared" : "failed");
1097 return cleared;
1098}
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108static size_t parport_ip32_epp_read(void __iomem *eppreg,
1109 struct parport *p, void *buf,
1110 size_t len, int flags)
1111{
1112 struct parport_ip32_private * const priv = p->physport->private_data;
1113 size_t got;
1114 parport_ip32_set_mode(p, ECR_MODE_EPP);
1115 parport_ip32_data_reverse(p);
1116 parport_ip32_write_control(p, DCR_nINIT);
1117 if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
1118 readsb(eppreg, buf, len);
1119 if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1120 parport_ip32_clear_epp_timeout(p);
1121 return -EIO;
1122 }
1123 got = len;
1124 } else {
1125 u8 *bufp = buf;
1126 for (got = 0; got < len; got++) {
1127 *bufp++ = readb(eppreg);
1128 if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1129 parport_ip32_clear_epp_timeout(p);
1130 break;
1131 }
1132 }
1133 }
1134 parport_ip32_data_forward(p);
1135 parport_ip32_set_mode(p, ECR_MODE_PS2);
1136 return got;
1137}
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147static size_t parport_ip32_epp_write(void __iomem *eppreg,
1148 struct parport *p, const void *buf,
1149 size_t len, int flags)
1150{
1151 struct parport_ip32_private * const priv = p->physport->private_data;
1152 size_t written;
1153 parport_ip32_set_mode(p, ECR_MODE_EPP);
1154 parport_ip32_data_forward(p);
1155 parport_ip32_write_control(p, DCR_nINIT);
1156 if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
1157 writesb(eppreg, buf, len);
1158 if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1159 parport_ip32_clear_epp_timeout(p);
1160 return -EIO;
1161 }
1162 written = len;
1163 } else {
1164 const u8 *bufp = buf;
1165 for (written = 0; written < len; written++) {
1166 writeb(*bufp++, eppreg);
1167 if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1168 parport_ip32_clear_epp_timeout(p);
1169 break;
1170 }
1171 }
1172 }
1173 parport_ip32_set_mode(p, ECR_MODE_PS2);
1174 return written;
1175}
1176
1177
1178
1179
1180
1181
1182
1183
1184static size_t parport_ip32_epp_read_data(struct parport *p, void *buf,
1185 size_t len, int flags)
1186{
1187 struct parport_ip32_private * const priv = p->physport->private_data;
1188 return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags);
1189}
1190
1191
1192
1193
1194
1195
1196
1197
1198static size_t parport_ip32_epp_write_data(struct parport *p, const void *buf,
1199 size_t len, int flags)
1200{
1201 struct parport_ip32_private * const priv = p->physport->private_data;
1202 return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags);
1203}
1204
1205
1206
1207
1208
1209
1210
1211
1212static size_t parport_ip32_epp_read_addr(struct parport *p, void *buf,
1213 size_t len, int flags)
1214{
1215 struct parport_ip32_private * const priv = p->physport->private_data;
1216 return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags);
1217}
1218
1219
1220
1221
1222
1223
1224
1225
1226static size_t parport_ip32_epp_write_addr(struct parport *p, const void *buf,
1227 size_t len, int flags)
1228{
1229 struct parport_ip32_private * const priv = p->physport->private_data;
1230 return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags);
1231}
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247static unsigned int parport_ip32_fifo_wait_break(struct parport *p,
1248 unsigned long expire)
1249{
1250 cond_resched();
1251 if (time_after(jiffies, expire)) {
1252 pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name);
1253 return 1;
1254 }
1255 if (signal_pending(current)) {
1256 pr_debug1(PPIP32 "%s: Signal pending\n", p->name);
1257 return 1;
1258 }
1259 if (!(parport_ip32_read_status(p) & DSR_nFAULT)) {
1260 pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name);
1261 return 1;
1262 }
1263 return 0;
1264}
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274static unsigned int parport_ip32_fwp_wait_polling(struct parport *p)
1275{
1276 struct parport_ip32_private * const priv = p->physport->private_data;
1277 struct parport * const physport = p->physport;
1278 unsigned long expire;
1279 unsigned int count;
1280 unsigned int ecr;
1281
1282 expire = jiffies + physport->cad->timeout;
1283 count = 0;
1284 while (1) {
1285 if (parport_ip32_fifo_wait_break(p, expire))
1286 break;
1287
1288
1289
1290
1291
1292 ecr = parport_ip32_read_econtrol(p);
1293 if (ecr & ECR_F_EMPTY) {
1294
1295 count = priv->fifo_depth;
1296 break;
1297 }
1298
1299
1300 udelay(FIFO_POLLING_INTERVAL);
1301 }
1302
1303 return count;
1304}
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p)
1315{
1316 static unsigned int lost_interrupt = 0;
1317 struct parport_ip32_private * const priv = p->physport->private_data;
1318 struct parport * const physport = p->physport;
1319 unsigned long nfault_timeout;
1320 unsigned long expire;
1321 unsigned int count;
1322 unsigned int ecr;
1323
1324 nfault_timeout = min((unsigned long)physport->cad->timeout,
1325 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
1326 expire = jiffies + physport->cad->timeout;
1327 count = 0;
1328 while (1) {
1329 if (parport_ip32_fifo_wait_break(p, expire))
1330 break;
1331
1332
1333 INIT_COMPLETION(priv->irq_complete);
1334
1335
1336 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1337
1338
1339
1340
1341 ecr = parport_ip32_read_econtrol(p);
1342 if (!(ecr & ECR_F_EMPTY)) {
1343
1344
1345 wait_for_completion_interruptible_timeout(
1346 &priv->irq_complete, nfault_timeout);
1347 ecr = parport_ip32_read_econtrol(p);
1348 if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR)
1349 && !lost_interrupt) {
1350 printk(KERN_WARNING PPIP32
1351 "%s: lost interrupt in %s\n",
1352 p->name, __func__);
1353 lost_interrupt = 1;
1354 }
1355 }
1356
1357
1358 parport_ip32_frob_econtrol(p, ECR_SERVINTR, ECR_SERVINTR);
1359
1360
1361 if (ecr & ECR_F_EMPTY) {
1362
1363 count = priv->fifo_depth;
1364 break;
1365 } else if (ecr & ECR_SERVINTR) {
1366
1367
1368 count = priv->writeIntrThreshold;
1369 break;
1370 }
1371
1372
1373
1374
1375 }
1376
1377 return count;
1378}
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391static size_t parport_ip32_fifo_write_block_pio(struct parport *p,
1392 const void *buf, size_t len)
1393{
1394 struct parport_ip32_private * const priv = p->physport->private_data;
1395 const u8 *bufp = buf;
1396 size_t left = len;
1397
1398 priv->irq_mode = PARPORT_IP32_IRQ_HERE;
1399
1400 while (left > 0) {
1401 unsigned int count;
1402
1403 count = (p->irq == PARPORT_IRQ_NONE) ?
1404 parport_ip32_fwp_wait_polling(p) :
1405 parport_ip32_fwp_wait_interrupt(p);
1406 if (count == 0)
1407 break;
1408 if (count > left)
1409 count = left;
1410 if (count == 1) {
1411 writeb(*bufp, priv->regs.fifo);
1412 bufp++, left--;
1413 } else {
1414 writesb(priv->regs.fifo, bufp, count);
1415 bufp += count, left -= count;
1416 }
1417 }
1418
1419 priv->irq_mode = PARPORT_IP32_IRQ_FWD;
1420
1421 return len - left;
1422}
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435static size_t parport_ip32_fifo_write_block_dma(struct parport *p,
1436 const void *buf, size_t len)
1437{
1438 struct parport_ip32_private * const priv = p->physport->private_data;
1439 struct parport * const physport = p->physport;
1440 unsigned long nfault_timeout;
1441 unsigned long expire;
1442 size_t written;
1443 unsigned int ecr;
1444
1445 priv->irq_mode = PARPORT_IP32_IRQ_HERE;
1446
1447 parport_ip32_dma_start(DMA_TO_DEVICE, (void *)buf, len);
1448 INIT_COMPLETION(priv->irq_complete);
1449 parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN);
1450
1451 nfault_timeout = min((unsigned long)physport->cad->timeout,
1452 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
1453 expire = jiffies + physport->cad->timeout;
1454 while (1) {
1455 if (parport_ip32_fifo_wait_break(p, expire))
1456 break;
1457 wait_for_completion_interruptible_timeout(&priv->irq_complete,
1458 nfault_timeout);
1459 ecr = parport_ip32_read_econtrol(p);
1460 if (ecr & ECR_SERVINTR)
1461 break;
1462 }
1463 parport_ip32_dma_stop();
1464 written = len - parport_ip32_dma_get_residue();
1465
1466 priv->irq_mode = PARPORT_IP32_IRQ_FWD;
1467
1468 return written;
1469}
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480static size_t parport_ip32_fifo_write_block(struct parport *p,
1481 const void *buf, size_t len)
1482{
1483 size_t written = 0;
1484 if (len)
1485
1486
1487 written = (p->modes & PARPORT_MODE_DMA) ?
1488 parport_ip32_fifo_write_block_dma(p, buf, len) :
1489 parport_ip32_fifo_write_block_pio(p, buf, len);
1490 return written;
1491}
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501static unsigned int parport_ip32_drain_fifo(struct parport *p,
1502 unsigned long timeout)
1503{
1504 unsigned long expire = jiffies + timeout;
1505 unsigned int polling_interval;
1506 unsigned int counter;
1507
1508
1509 for (counter = 0; counter < 40; counter++) {
1510 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
1511 break;
1512 if (time_after(jiffies, expire))
1513 break;
1514 if (signal_pending(current))
1515 break;
1516 udelay(5);
1517 }
1518
1519
1520 polling_interval = 1;
1521 while (!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY)) {
1522 if (time_after_eq(jiffies, expire))
1523 break;
1524 msleep_interruptible(polling_interval);
1525 if (signal_pending(current))
1526 break;
1527 if (polling_interval < 128)
1528 polling_interval *= 2;
1529 }
1530
1531 return !!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY);
1532}
1533
1534
1535
1536
1537
1538
1539
1540
1541static unsigned int parport_ip32_get_fifo_residue(struct parport *p,
1542 unsigned int mode)
1543{
1544 struct parport_ip32_private * const priv = p->physport->private_data;
1545 unsigned int residue;
1546 unsigned int cnfga;
1547
1548
1549
1550
1551
1552
1553 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
1554 residue = 0;
1555 else {
1556 pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name);
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570 parport_ip32_frob_control(p, DCR_STROBE, 0);
1571
1572
1573 for (residue = priv->fifo_depth; residue > 0; residue--) {
1574 if (parport_ip32_read_econtrol(p) & ECR_F_FULL)
1575 break;
1576 writeb(0x00, priv->regs.fifo);
1577 }
1578 }
1579 if (residue)
1580 pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n",
1581 p->name, residue,
1582 (residue == 1) ? " was" : "s were");
1583
1584
1585 parport_ip32_set_mode(p, ECR_MODE_PS2);
1586
1587
1588 if (mode == ECR_MODE_ECP) {
1589 parport_ip32_data_reverse(p);
1590 parport_ip32_frob_control(p, DCR_nINIT, 0);
1591 if (parport_wait_peripheral(p, DSR_PERROR, 0))
1592 pr_debug1(PPIP32 "%s: PEerror timeout 1 in %s\n",
1593 p->name, __func__);
1594 parport_ip32_frob_control(p, DCR_STROBE, DCR_STROBE);
1595 parport_ip32_frob_control(p, DCR_nINIT, DCR_nINIT);
1596 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR))
1597 pr_debug1(PPIP32 "%s: PEerror timeout 2 in %s\n",
1598 p->name, __func__);
1599 }
1600
1601
1602 parport_ip32_set_mode(p, ECR_MODE_CFG);
1603 cnfga = readb(priv->regs.cnfgA);
1604 if (!(cnfga & CNFGA_nBYTEINTRANS)) {
1605 pr_debug1(PPIP32 "%s: cnfgA contains 0x%02x\n",
1606 p->name, cnfga);
1607 pr_debug1(PPIP32 "%s: Accounting for extra byte\n",
1608 p->name);
1609 residue++;
1610 }
1611
1612
1613
1614
1615
1616 parport_ip32_set_mode(p, ECR_MODE_PS2);
1617 parport_ip32_data_forward(p);
1618
1619 return residue;
1620}
1621
1622
1623
1624
1625
1626
1627
1628
1629static size_t parport_ip32_compat_write_data(struct parport *p,
1630 const void *buf, size_t len,
1631 int flags)
1632{
1633 static unsigned int ready_before = 1;
1634 struct parport_ip32_private * const priv = p->physport->private_data;
1635 struct parport * const physport = p->physport;
1636 size_t written = 0;
1637
1638
1639
1640 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1641 return parport_ieee1284_write_compat(p, buf, len, flags);
1642
1643
1644 parport_ip32_set_mode(p, ECR_MODE_PS2);
1645 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1646 parport_ip32_data_forward(p);
1647 parport_ip32_disable_irq(p);
1648 parport_ip32_set_mode(p, ECR_MODE_PPF);
1649 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
1650
1651
1652 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
1653 DSR_nBUSY | DSR_nFAULT)) {
1654
1655 if (ready_before)
1656 printk(KERN_INFO PPIP32 "%s: not ready in %s\n",
1657 p->name, __func__);
1658 ready_before = 0;
1659 goto stop;
1660 }
1661 ready_before = 1;
1662
1663 written = parport_ip32_fifo_write_block(p, buf, len);
1664
1665
1666 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
1667
1668
1669 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF);
1670
1671
1672 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
1673 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
1674 p->name, __func__);
1675
1676stop:
1677
1678 parport_ip32_set_mode(p, ECR_MODE_PS2);
1679 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1680
1681 return written;
1682}
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695static size_t parport_ip32_ecp_write_data(struct parport *p,
1696 const void *buf, size_t len,
1697 int flags)
1698{
1699 static unsigned int ready_before = 1;
1700 struct parport_ip32_private * const priv = p->physport->private_data;
1701 struct parport * const physport = p->physport;
1702 size_t written = 0;
1703
1704
1705
1706 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1707 return parport_ieee1284_ecp_write_data(p, buf, len, flags);
1708
1709
1710 if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
1711
1712 parport_ip32_frob_control(p, DCR_nINIT | DCR_AUTOFD,
1713 DCR_nINIT | DCR_AUTOFD);
1714
1715
1716 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) {
1717 printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s",
1718 p->name, __func__);
1719 physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
1720 return 0;
1721 }
1722 }
1723
1724
1725 parport_ip32_set_mode(p, ECR_MODE_PS2);
1726 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1727 parport_ip32_data_forward(p);
1728 parport_ip32_disable_irq(p);
1729 parport_ip32_set_mode(p, ECR_MODE_ECP);
1730 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
1731
1732
1733 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
1734 DSR_nBUSY | DSR_nFAULT)) {
1735
1736 if (ready_before)
1737 printk(KERN_INFO PPIP32 "%s: not ready in %s\n",
1738 p->name, __func__);
1739 ready_before = 0;
1740 goto stop;
1741 }
1742 ready_before = 1;
1743
1744 written = parport_ip32_fifo_write_block(p, buf, len);
1745
1746
1747 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
1748
1749
1750 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP);
1751
1752
1753 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
1754 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
1755 p->name, __func__);
1756
1757stop:
1758
1759 parport_ip32_set_mode(p, ECR_MODE_PS2);
1760 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1761
1762 return written;
1763}
1764
1765
1766
1767
1768
1769
1770
1771static __initdata struct parport_operations parport_ip32_ops = {
1772 .write_data = parport_ip32_write_data,
1773 .read_data = parport_ip32_read_data,
1774
1775 .write_control = parport_ip32_write_control,
1776 .read_control = parport_ip32_read_control,
1777 .frob_control = parport_ip32_frob_control,
1778
1779 .read_status = parport_ip32_read_status,
1780
1781 .enable_irq = parport_ip32_enable_irq,
1782 .disable_irq = parport_ip32_disable_irq,
1783
1784 .data_forward = parport_ip32_data_forward,
1785 .data_reverse = parport_ip32_data_reverse,
1786
1787 .init_state = parport_ip32_init_state,
1788 .save_state = parport_ip32_save_state,
1789 .restore_state = parport_ip32_restore_state,
1790
1791 .epp_write_data = parport_ieee1284_epp_write_data,
1792 .epp_read_data = parport_ieee1284_epp_read_data,
1793 .epp_write_addr = parport_ieee1284_epp_write_addr,
1794 .epp_read_addr = parport_ieee1284_epp_read_addr,
1795
1796 .ecp_write_data = parport_ieee1284_ecp_write_data,
1797 .ecp_read_data = parport_ieee1284_ecp_read_data,
1798 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1799
1800 .compat_write_data = parport_ieee1284_write_compat,
1801 .nibble_read_data = parport_ieee1284_read_nibble,
1802 .byte_read_data = parport_ieee1284_read_byte,
1803
1804 .owner = THIS_MODULE,
1805};
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817static __init unsigned int parport_ip32_ecp_supported(struct parport *p)
1818{
1819 struct parport_ip32_private * const priv = p->physport->private_data;
1820 unsigned int ecr;
1821
1822 ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
1823 writeb(ecr, priv->regs.ecr);
1824 if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY))
1825 goto fail;
1826
1827 pr_probe(p, "Found working ECR register\n");
1828 parport_ip32_set_mode(p, ECR_MODE_SPP);
1829 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1830 return 1;
1831
1832fail:
1833 pr_probe(p, "ECR register not found\n");
1834 return 0;
1835}
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845static __init unsigned int parport_ip32_fifo_supported(struct parport *p)
1846{
1847 struct parport_ip32_private * const priv = p->physport->private_data;
1848 unsigned int configa, configb;
1849 unsigned int pword;
1850 unsigned int i;
1851
1852
1853 parport_ip32_set_mode(p, ECR_MODE_CFG);
1854 configa = readb(priv->regs.cnfgA);
1855 configb = readb(priv->regs.cnfgB);
1856
1857
1858 switch (configa & CNFGA_ID_MASK) {
1859 case CNFGA_ID_8:
1860 pword = 1;
1861 break;
1862 case CNFGA_ID_16:
1863 pword = 2;
1864 break;
1865 case CNFGA_ID_32:
1866 pword = 4;
1867 break;
1868 default:
1869 pr_probe(p, "Unknown implementation ID: 0x%0x\n",
1870 (configa & CNFGA_ID_MASK) >> CNFGA_ID_SHIFT);
1871 goto fail;
1872 break;
1873 }
1874 if (pword != 1) {
1875 pr_probe(p, "Unsupported PWord size: %u\n", pword);
1876 goto fail;
1877 }
1878 priv->pword = pword;
1879 pr_probe(p, "PWord is %u bits\n", 8 * priv->pword);
1880
1881
1882 writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB);
1883 if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS)
1884 pr_probe(p, "Hardware compression detected (unsupported)\n");
1885 writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB);
1886
1887
1888 parport_ip32_set_mode(p, ECR_MODE_TST);
1889
1890
1891 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
1892 pr_probe(p, "FIFO not reset\n");
1893 goto fail;
1894 }
1895
1896
1897 priv->fifo_depth = 0;
1898 for (i = 0; i < 1024; i++) {
1899 if (readb(priv->regs.ecr) & ECR_F_FULL) {
1900
1901 priv->fifo_depth = i;
1902 break;
1903 }
1904 writeb((u8)i, priv->regs.fifo);
1905 }
1906 if (i >= 1024) {
1907 pr_probe(p, "Can't fill FIFO\n");
1908 goto fail;
1909 }
1910 if (!priv->fifo_depth) {
1911 pr_probe(p, "Can't get FIFO depth\n");
1912 goto fail;
1913 }
1914 pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth);
1915
1916
1917 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1918
1919
1920
1921 priv->writeIntrThreshold = 0;
1922 for (i = 0; i < priv->fifo_depth; i++) {
1923 if (readb(priv->regs.fifo) != (u8)i) {
1924 pr_probe(p, "Invalid data in FIFO\n");
1925 goto fail;
1926 }
1927 if (!priv->writeIntrThreshold
1928 && readb(priv->regs.ecr) & ECR_SERVINTR)
1929
1930 priv->writeIntrThreshold = i + 1;
1931 if (i + 1 < priv->fifo_depth
1932 && readb(priv->regs.ecr) & ECR_F_EMPTY) {
1933
1934 pr_probe(p, "Data lost in FIFO\n");
1935 goto fail;
1936 }
1937 }
1938 if (!priv->writeIntrThreshold) {
1939 pr_probe(p, "Can't get writeIntrThreshold\n");
1940 goto fail;
1941 }
1942 pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold);
1943
1944
1945 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
1946 pr_probe(p, "Can't empty FIFO\n");
1947 goto fail;
1948 }
1949
1950
1951 parport_ip32_set_mode(p, ECR_MODE_PS2);
1952
1953 parport_ip32_data_reverse(p);
1954
1955 parport_ip32_set_mode(p, ECR_MODE_TST);
1956
1957 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1958
1959
1960
1961 priv->readIntrThreshold = 0;
1962 for (i = 0; i < priv->fifo_depth; i++) {
1963 writeb(0xaa, priv->regs.fifo);
1964 if (readb(priv->regs.ecr) & ECR_SERVINTR) {
1965
1966 priv->readIntrThreshold = i + 1;
1967 break;
1968 }
1969 }
1970 if (!priv->readIntrThreshold) {
1971 pr_probe(p, "Can't get readIntrThreshold\n");
1972 goto fail;
1973 }
1974 pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold);
1975
1976
1977 parport_ip32_set_mode(p, ECR_MODE_PS2);
1978 parport_ip32_data_forward(p);
1979 parport_ip32_set_mode(p, ECR_MODE_SPP);
1980 return 1;
1981
1982fail:
1983 priv->fifo_depth = 0;
1984 parport_ip32_set_mode(p, ECR_MODE_SPP);
1985 return 0;
1986}
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001static void __init
2002parport_ip32_make_isa_registers(struct parport_ip32_regs *regs,
2003 void __iomem *base, void __iomem *base_hi,
2004 unsigned int regshift)
2005{
2006#define r_base(offset) ((u8 __iomem *)base + ((offset) << regshift))
2007#define r_base_hi(offset) ((u8 __iomem *)base_hi + ((offset) << regshift))
2008 *regs = (struct parport_ip32_regs){
2009 .data = r_base(0),
2010 .dsr = r_base(1),
2011 .dcr = r_base(2),
2012 .eppAddr = r_base(3),
2013 .eppData0 = r_base(4),
2014 .eppData1 = r_base(5),
2015 .eppData2 = r_base(6),
2016 .eppData3 = r_base(7),
2017 .ecpAFifo = r_base(0),
2018 .fifo = r_base_hi(0),
2019 .cnfgA = r_base_hi(0),
2020 .cnfgB = r_base_hi(1),
2021 .ecr = r_base_hi(2)
2022 };
2023#undef r_base_hi
2024#undef r_base
2025}
2026
2027
2028
2029
2030
2031
2032
2033static __init struct parport *parport_ip32_probe_port(void)
2034{
2035 struct parport_ip32_regs regs;
2036 struct parport_ip32_private *priv = NULL;
2037 struct parport_operations *ops = NULL;
2038 struct parport *p = NULL;
2039 int err;
2040
2041 parport_ip32_make_isa_registers(®s, &mace->isa.parallel,
2042 &mace->isa.ecp1284, 8 );
2043
2044 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2045 priv = kmalloc(sizeof(struct parport_ip32_private), GFP_KERNEL);
2046 p = parport_register_port(0, PARPORT_IRQ_NONE, PARPORT_DMA_NONE, ops);
2047 if (ops == NULL || priv == NULL || p == NULL) {
2048 err = -ENOMEM;
2049 goto fail;
2050 }
2051 p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel);
2052 p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284);
2053 p->private_data = priv;
2054
2055 *ops = parport_ip32_ops;
2056 *priv = (struct parport_ip32_private){
2057 .regs = regs,
2058 .dcr_writable = DCR_DIR | DCR_SELECT | DCR_nINIT |
2059 DCR_AUTOFD | DCR_STROBE,
2060 .irq_mode = PARPORT_IP32_IRQ_FWD,
2061 };
2062 init_completion(&priv->irq_complete);
2063
2064
2065 if (!parport_ip32_ecp_supported(p)) {
2066 err = -ENODEV;
2067 goto fail;
2068 }
2069 parport_ip32_dump_state(p, "begin init", 0);
2070
2071
2072
2073 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2074 p->modes |= PARPORT_MODE_TRISTATE;
2075
2076 if (!parport_ip32_fifo_supported(p)) {
2077 printk(KERN_WARNING PPIP32
2078 "%s: error: FIFO disabled\n", p->name);
2079
2080 features &= ~PARPORT_IP32_ENABLE_SPP;
2081 features &= ~PARPORT_IP32_ENABLE_ECP;
2082
2083 features &= ~PARPORT_IP32_ENABLE_DMA;
2084 }
2085
2086
2087 if (features & PARPORT_IP32_ENABLE_IRQ) {
2088 int irq = MACEISA_PARALLEL_IRQ;
2089 if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) {
2090 printk(KERN_WARNING PPIP32
2091 "%s: error: IRQ disabled\n", p->name);
2092
2093 features &= ~PARPORT_IP32_ENABLE_DMA;
2094 } else {
2095 pr_probe(p, "Interrupt support enabled\n");
2096 p->irq = irq;
2097 priv->dcr_writable |= DCR_IRQ;
2098 }
2099 }
2100
2101
2102 if (features & PARPORT_IP32_ENABLE_DMA) {
2103 if (parport_ip32_dma_register())
2104 printk(KERN_WARNING PPIP32
2105 "%s: error: DMA disabled\n", p->name);
2106 else {
2107 pr_probe(p, "DMA support enabled\n");
2108 p->dma = 0;
2109 p->modes |= PARPORT_MODE_DMA;
2110 }
2111 }
2112
2113 if (features & PARPORT_IP32_ENABLE_SPP) {
2114
2115 p->ops->compat_write_data = parport_ip32_compat_write_data;
2116 p->modes |= PARPORT_MODE_COMPAT;
2117 pr_probe(p, "Hardware support for SPP mode enabled\n");
2118 }
2119 if (features & PARPORT_IP32_ENABLE_EPP) {
2120
2121 p->ops->epp_read_data = parport_ip32_epp_read_data;
2122 p->ops->epp_write_data = parport_ip32_epp_write_data;
2123 p->ops->epp_read_addr = parport_ip32_epp_read_addr;
2124 p->ops->epp_write_addr = parport_ip32_epp_write_addr;
2125 p->modes |= PARPORT_MODE_EPP;
2126 pr_probe(p, "Hardware support for EPP mode enabled\n");
2127 }
2128 if (features & PARPORT_IP32_ENABLE_ECP) {
2129
2130 p->ops->ecp_write_data = parport_ip32_ecp_write_data;
2131
2132
2133
2134 p->modes |= PARPORT_MODE_ECP;
2135 pr_probe(p, "Hardware support for ECP mode enabled\n");
2136 }
2137
2138
2139 parport_ip32_set_mode(p, ECR_MODE_PS2);
2140 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
2141 parport_ip32_data_forward(p);
2142 parport_ip32_disable_irq(p);
2143 parport_ip32_write_data(p, 0x00);
2144 parport_ip32_dump_state(p, "end init", 0);
2145
2146
2147 printk(KERN_INFO "%s: SGI IP32 at 0x%lx (0x%lx)",
2148 p->name, p->base, p->base_hi);
2149 if (p->irq != PARPORT_IRQ_NONE)
2150 printk(", irq %d", p->irq);
2151 printk(" [");
2152#define printmode(x) if (p->modes & PARPORT_MODE_##x) \
2153 printk("%s%s", f++ ? "," : "", #x)
2154 {
2155 unsigned int f = 0;
2156 printmode(PCSPP);
2157 printmode(TRISTATE);
2158 printmode(COMPAT);
2159 printmode(EPP);
2160 printmode(ECP);
2161 printmode(DMA);
2162 }
2163#undef printmode
2164 printk("]\n");
2165
2166 parport_announce_port(p);
2167 return p;
2168
2169fail:
2170 if (p)
2171 parport_put_port(p);
2172 kfree(priv);
2173 kfree(ops);
2174 return ERR_PTR(err);
2175}
2176
2177
2178
2179
2180
2181
2182
2183
2184static __exit void parport_ip32_unregister_port(struct parport *p)
2185{
2186 struct parport_ip32_private * const priv = p->physport->private_data;
2187 struct parport_operations *ops = p->ops;
2188
2189 parport_remove_port(p);
2190 if (p->modes & PARPORT_MODE_DMA)
2191 parport_ip32_dma_unregister();
2192 if (p->irq != PARPORT_IRQ_NONE)
2193 free_irq(p->irq, p);
2194 parport_put_port(p);
2195 kfree(priv);
2196 kfree(ops);
2197}
2198
2199
2200
2201
2202static int __init parport_ip32_init(void)
2203{
2204 pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n");
2205 pr_debug1(PPIP32 "Compiled on %s, %s\n", __DATE__, __TIME__);
2206 this_port = parport_ip32_probe_port();
2207 return IS_ERR(this_port) ? PTR_ERR(this_port) : 0;
2208}
2209
2210
2211
2212
2213static void __exit parport_ip32_exit(void)
2214{
2215 parport_ip32_unregister_port(this_port);
2216}
2217
2218
2219
2220MODULE_AUTHOR("Arnaud Giersch <arnaud.giersch@free.fr>");
2221MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver");
2222MODULE_LICENSE("GPL");
2223MODULE_VERSION("0.6");
2224
2225module_init(parport_ip32_init);
2226module_exit(parport_ip32_exit);
2227
2228module_param(verbose_probing, bool, S_IRUGO);
2229MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization");
2230
2231module_param(features, uint, S_IRUGO);
2232MODULE_PARM_DESC(features,
2233 "Bit mask of features to enable"
2234 ", bit 0: IRQ support"
2235 ", bit 1: DMA support"
2236 ", bit 2: hardware SPP mode"
2237 ", bit 3: hardware EPP mode"
2238 ", bit 4: hardware ECP mode");
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251