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10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15#include <linux/errno.h>
16#include <linux/pm.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/jiffies.h>
20#include <linux/delay.h>
21#include <linux/pci-aspm.h>
22#include "../pci.h"
23
24#ifdef MODULE_PARAM_PREFIX
25#undef MODULE_PARAM_PREFIX
26#endif
27#define MODULE_PARAM_PREFIX "pcie_aspm."
28
29
30#define ASPM_STATE_L0S_UP (1)
31#define ASPM_STATE_L0S_DW (2)
32#define ASPM_STATE_L1 (4)
33#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
34#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
35
36struct aspm_latency {
37 u32 l0s;
38 u32 l1;
39};
40
41struct pcie_link_state {
42 struct pci_dev *pdev;
43 struct pcie_link_state *root;
44 struct pcie_link_state *parent;
45 struct list_head sibling;
46 struct list_head children;
47 struct list_head link;
48
49
50 u32 aspm_support:3;
51 u32 aspm_enabled:3;
52 u32 aspm_capable:3;
53 u32 aspm_default:3;
54 u32 aspm_disable:3;
55
56
57 u32 clkpm_capable:1;
58 u32 clkpm_enabled:1;
59 u32 clkpm_default:1;
60
61
62 struct aspm_latency latency_up;
63 struct aspm_latency latency_dw;
64
65
66
67
68 struct aspm_latency acceptable[8];
69};
70
71static int aspm_disabled, aspm_force;
72static DEFINE_MUTEX(aspm_lock);
73static LIST_HEAD(link_list);
74
75#define POLICY_DEFAULT 0
76#define POLICY_PERFORMANCE 1
77#define POLICY_POWERSAVE 2
78static int aspm_policy;
79static const char *policy_str[] = {
80 [POLICY_DEFAULT] = "default",
81 [POLICY_PERFORMANCE] = "performance",
82 [POLICY_POWERSAVE] = "powersave"
83};
84
85#define LINK_RETRAIN_TIMEOUT HZ
86
87static int policy_to_aspm_state(struct pcie_link_state *link)
88{
89 switch (aspm_policy) {
90 case POLICY_PERFORMANCE:
91
92 return 0;
93 case POLICY_POWERSAVE:
94
95 return ASPM_STATE_ALL;
96 case POLICY_DEFAULT:
97 return link->aspm_default;
98 }
99 return 0;
100}
101
102static int policy_to_clkpm_state(struct pcie_link_state *link)
103{
104 switch (aspm_policy) {
105 case POLICY_PERFORMANCE:
106
107 return 0;
108 case POLICY_POWERSAVE:
109
110 return 1;
111 case POLICY_DEFAULT:
112 return link->clkpm_default;
113 }
114 return 0;
115}
116
117static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
118{
119 int pos;
120 u16 reg16;
121 struct pci_dev *child;
122 struct pci_bus *linkbus = link->pdev->subordinate;
123
124 list_for_each_entry(child, &linkbus->devices, bus_list) {
125 pos = pci_find_capability(child, PCI_CAP_ID_EXP);
126 if (!pos)
127 return;
128 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
129 if (enable)
130 reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
131 else
132 reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
133 pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16);
134 }
135 link->clkpm_enabled = !!enable;
136}
137
138static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
139{
140
141 if (!link->clkpm_capable && enable)
142 return;
143
144 if (link->clkpm_enabled == enable)
145 return;
146 pcie_set_clkpm_nocheck(link, enable);
147}
148
149static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
150{
151 int pos, capable = 1, enabled = 1;
152 u32 reg32;
153 u16 reg16;
154 struct pci_dev *child;
155 struct pci_bus *linkbus = link->pdev->subordinate;
156
157
158 list_for_each_entry(child, &linkbus->devices, bus_list) {
159 pos = pci_find_capability(child, PCI_CAP_ID_EXP);
160 if (!pos)
161 return;
162 pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32);
163 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
164 capable = 0;
165 enabled = 0;
166 break;
167 }
168 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
169 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
170 enabled = 0;
171 }
172 link->clkpm_enabled = enabled;
173 link->clkpm_default = enabled;
174 link->clkpm_capable = (blacklist) ? 0 : capable;
175}
176
177
178
179
180
181
182static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
183{
184 int ppos, cpos, same_clock = 1;
185 u16 reg16, parent_reg, child_reg[8];
186 unsigned long start_jiffies;
187 struct pci_dev *child, *parent = link->pdev;
188 struct pci_bus *linkbus = parent->subordinate;
189
190
191
192
193 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
194 BUG_ON(!child->is_pcie);
195
196
197 cpos = pci_find_capability(child, PCI_CAP_ID_EXP);
198 pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16);
199 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
200 same_clock = 0;
201
202
203 ppos = pci_find_capability(parent, PCI_CAP_ID_EXP);
204 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
205 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
206 same_clock = 0;
207
208
209 list_for_each_entry(child, &linkbus->devices, bus_list) {
210 cpos = pci_find_capability(child, PCI_CAP_ID_EXP);
211 pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16);
212 child_reg[PCI_FUNC(child->devfn)] = reg16;
213 if (same_clock)
214 reg16 |= PCI_EXP_LNKCTL_CCC;
215 else
216 reg16 &= ~PCI_EXP_LNKCTL_CCC;
217 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
218 }
219
220
221 pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16);
222 parent_reg = reg16;
223 if (same_clock)
224 reg16 |= PCI_EXP_LNKCTL_CCC;
225 else
226 reg16 &= ~PCI_EXP_LNKCTL_CCC;
227 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
228
229
230 reg16 |= PCI_EXP_LNKCTL_RL;
231 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
232
233
234 start_jiffies = jiffies;
235 for (;;) {
236 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
237 if (!(reg16 & PCI_EXP_LNKSTA_LT))
238 break;
239 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
240 break;
241 msleep(1);
242 }
243 if (!(reg16 & PCI_EXP_LNKSTA_LT))
244 return;
245
246
247 dev_printk(KERN_ERR, &parent->dev,
248 "ASPM: Could not configure common clock\n");
249 list_for_each_entry(child, &linkbus->devices, bus_list) {
250 cpos = pci_find_capability(child, PCI_CAP_ID_EXP);
251 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL,
252 child_reg[PCI_FUNC(child->devfn)]);
253 }
254 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
255}
256
257
258static u32 calc_l0s_latency(u32 encoding)
259{
260 if (encoding == 0x7)
261 return (5 * 1000);
262 return (64 << encoding);
263}
264
265
266static u32 calc_l0s_acceptable(u32 encoding)
267{
268 if (encoding == 0x7)
269 return -1U;
270 return (64 << encoding);
271}
272
273
274static u32 calc_l1_latency(u32 encoding)
275{
276 if (encoding == 0x7)
277 return (65 * 1000);
278 return (1000 << encoding);
279}
280
281
282static u32 calc_l1_acceptable(u32 encoding)
283{
284 if (encoding == 0x7)
285 return -1U;
286 return (1000 << encoding);
287}
288
289struct aspm_register_info {
290 u32 support:2;
291 u32 enabled:2;
292 u32 latency_encoding_l0s;
293 u32 latency_encoding_l1;
294};
295
296static void pcie_get_aspm_reg(struct pci_dev *pdev,
297 struct aspm_register_info *info)
298{
299 int pos;
300 u16 reg16;
301 u32 reg32;
302
303 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
304 pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32);
305 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
306 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
307 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
308 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
309 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
310}
311
312static void pcie_aspm_check_latency(struct pci_dev *endpoint)
313{
314 u32 latency, l1_switch_latency = 0;
315 struct aspm_latency *acceptable;
316 struct pcie_link_state *link;
317
318
319 if ((endpoint->current_state != PCI_D0) &&
320 (endpoint->current_state != PCI_UNKNOWN))
321 return;
322
323 link = endpoint->bus->self->link_state;
324 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
325
326 while (link) {
327
328 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
329 (link->latency_up.l0s > acceptable->l0s))
330 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
331
332
333 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
334 (link->latency_dw.l0s > acceptable->l0s))
335 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
336
337
338
339
340
341 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
342 if ((link->aspm_capable & ASPM_STATE_L1) &&
343 (latency + l1_switch_latency > acceptable->l1))
344 link->aspm_capable &= ~ASPM_STATE_L1;
345 l1_switch_latency += 1000;
346
347 link = link->parent;
348 }
349}
350
351static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
352{
353 struct pci_dev *child, *parent = link->pdev;
354 struct pci_bus *linkbus = parent->subordinate;
355 struct aspm_register_info upreg, dwreg;
356
357 if (blacklist) {
358
359 link->aspm_enabled = ASPM_STATE_ALL;
360 link->aspm_disable = ASPM_STATE_ALL;
361 return;
362 }
363
364
365 pcie_aspm_configure_common_clock(link);
366
367
368 pcie_get_aspm_reg(parent, &upreg);
369 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
370 pcie_get_aspm_reg(child, &dwreg);
371
372
373
374
375
376
377
378
379 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
380 link->aspm_support |= ASPM_STATE_L0S;
381 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
382 link->aspm_enabled |= ASPM_STATE_L0S_UP;
383 if (upreg.enabled & PCIE_LINK_STATE_L0S)
384 link->aspm_enabled |= ASPM_STATE_L0S_DW;
385 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
386 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
387
388
389 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
390 link->aspm_support |= ASPM_STATE_L1;
391 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
392 link->aspm_enabled |= ASPM_STATE_L1;
393 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
394 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
395
396
397 link->aspm_default = link->aspm_enabled;
398
399
400 link->aspm_capable = link->aspm_support;
401
402
403
404
405 list_for_each_entry(child, &linkbus->devices, bus_list) {
406 if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
407 link->aspm_disable = ASPM_STATE_ALL;
408 break;
409 }
410 }
411
412
413 list_for_each_entry(child, &linkbus->devices, bus_list) {
414 int pos;
415 u32 reg32, encoding;
416 struct aspm_latency *acceptable =
417 &link->acceptable[PCI_FUNC(child->devfn)];
418
419 if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
420 child->pcie_type != PCI_EXP_TYPE_LEG_END)
421 continue;
422
423 pos = pci_find_capability(child, PCI_CAP_ID_EXP);
424 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
425
426 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
427 acceptable->l0s = calc_l0s_acceptable(encoding);
428
429 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
430 acceptable->l1 = calc_l1_acceptable(encoding);
431
432 pcie_aspm_check_latency(child);
433 }
434}
435
436static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
437{
438 u16 reg16;
439 int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
440
441 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
442 reg16 &= ~0x3;
443 reg16 |= val;
444 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
445}
446
447static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
448{
449 u32 upstream = 0, dwstream = 0;
450 struct pci_dev *child, *parent = link->pdev;
451 struct pci_bus *linkbus = parent->subordinate;
452
453
454 state &= (link->aspm_capable & ~link->aspm_disable);
455 if (link->aspm_enabled == state)
456 return;
457
458 if (state & ASPM_STATE_L0S_UP)
459 dwstream |= PCIE_LINK_STATE_L0S;
460 if (state & ASPM_STATE_L0S_DW)
461 upstream |= PCIE_LINK_STATE_L0S;
462 if (state & ASPM_STATE_L1) {
463 upstream |= PCIE_LINK_STATE_L1;
464 dwstream |= PCIE_LINK_STATE_L1;
465 }
466
467
468
469
470
471
472 if (state & ASPM_STATE_L1)
473 pcie_config_aspm_dev(parent, upstream);
474 list_for_each_entry(child, &linkbus->devices, bus_list)
475 pcie_config_aspm_dev(child, dwstream);
476 if (!(state & ASPM_STATE_L1))
477 pcie_config_aspm_dev(parent, upstream);
478
479 link->aspm_enabled = state;
480}
481
482static void pcie_config_aspm_path(struct pcie_link_state *link)
483{
484 while (link) {
485 pcie_config_aspm_link(link, policy_to_aspm_state(link));
486 link = link->parent;
487 }
488}
489
490static void free_link_state(struct pcie_link_state *link)
491{
492 link->pdev->link_state = NULL;
493 kfree(link);
494}
495
496static int pcie_aspm_sanity_check(struct pci_dev *pdev)
497{
498 struct pci_dev *child;
499 int pos;
500 u32 reg32;
501
502
503
504
505 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
506 pos = pci_find_capability(child, PCI_CAP_ID_EXP);
507 if (!pos)
508 return -EINVAL;
509
510
511
512
513 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
514 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
515 dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
516 " on pre-1.1 PCIe device. You can enable it"
517 " with 'pcie_aspm=force'\n");
518 return -EINVAL;
519 }
520 }
521 return 0;
522}
523
524static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
525{
526 struct pcie_link_state *link;
527
528 link = kzalloc(sizeof(*link), GFP_KERNEL);
529 if (!link)
530 return NULL;
531 INIT_LIST_HEAD(&link->sibling);
532 INIT_LIST_HEAD(&link->children);
533 INIT_LIST_HEAD(&link->link);
534 link->pdev = pdev;
535 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
536 struct pcie_link_state *parent;
537 parent = pdev->bus->parent->self->link_state;
538 if (!parent) {
539 kfree(link);
540 return NULL;
541 }
542 link->parent = parent;
543 list_add(&link->link, &parent->children);
544 }
545
546 if (!link->parent)
547 link->root = link;
548 else
549 link->root = link->parent->root;
550
551 list_add(&link->sibling, &link_list);
552 pdev->link_state = link;
553 return link;
554}
555
556
557
558
559
560
561void pcie_aspm_init_link_state(struct pci_dev *pdev)
562{
563 struct pcie_link_state *link;
564 int blacklist = !!pcie_aspm_sanity_check(pdev);
565
566 if (aspm_disabled || !pdev->is_pcie || pdev->link_state)
567 return;
568 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
569 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
570 return;
571
572
573 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT &&
574 pdev->bus->self)
575 return;
576
577 down_read(&pci_bus_sem);
578 if (list_empty(&pdev->subordinate->devices))
579 goto out;
580
581 mutex_lock(&aspm_lock);
582 link = alloc_pcie_link_state(pdev);
583 if (!link)
584 goto unlock;
585
586
587
588
589
590 pcie_aspm_cap_init(link, blacklist);
591 pcie_config_aspm_path(link);
592
593
594 pcie_clkpm_cap_init(link, blacklist);
595 pcie_set_clkpm(link, policy_to_clkpm_state(link));
596unlock:
597 mutex_unlock(&aspm_lock);
598out:
599 up_read(&pci_bus_sem);
600}
601
602
603static void pcie_update_aspm_capable(struct pcie_link_state *root)
604{
605 struct pcie_link_state *link;
606 BUG_ON(root->parent);
607 list_for_each_entry(link, &link_list, sibling) {
608 if (link->root != root)
609 continue;
610 link->aspm_capable = link->aspm_support;
611 }
612 list_for_each_entry(link, &link_list, sibling) {
613 struct pci_dev *child;
614 struct pci_bus *linkbus = link->pdev->subordinate;
615 if (link->root != root)
616 continue;
617 list_for_each_entry(child, &linkbus->devices, bus_list) {
618 if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) &&
619 (child->pcie_type != PCI_EXP_TYPE_LEG_END))
620 continue;
621 pcie_aspm_check_latency(child);
622 }
623 }
624}
625
626
627void pcie_aspm_exit_link_state(struct pci_dev *pdev)
628{
629 struct pci_dev *parent = pdev->bus->self;
630 struct pcie_link_state *link, *root, *parent_link;
631
632 if (aspm_disabled || !pdev->is_pcie || !parent || !parent->link_state)
633 return;
634 if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
635 (parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
636 return;
637
638 down_read(&pci_bus_sem);
639 mutex_lock(&aspm_lock);
640
641
642
643
644 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
645 goto out;
646
647 link = parent->link_state;
648 root = link->root;
649 parent_link = link->parent;
650
651
652 pcie_config_aspm_link(link, 0);
653 list_del(&link->sibling);
654 list_del(&link->link);
655
656 free_link_state(link);
657
658
659 if (parent_link) {
660 pcie_update_aspm_capable(root);
661 pcie_config_aspm_path(parent_link);
662 }
663out:
664 mutex_unlock(&aspm_lock);
665 up_read(&pci_bus_sem);
666}
667
668
669void pcie_aspm_pm_state_change(struct pci_dev *pdev)
670{
671 struct pcie_link_state *link = pdev->link_state;
672
673 if (aspm_disabled || !pdev->is_pcie || !link)
674 return;
675 if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
676 (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
677 return;
678
679
680
681
682 down_read(&pci_bus_sem);
683 mutex_lock(&aspm_lock);
684 pcie_update_aspm_capable(link->root);
685 pcie_config_aspm_path(link);
686 mutex_unlock(&aspm_lock);
687 up_read(&pci_bus_sem);
688}
689
690
691
692
693
694void pci_disable_link_state(struct pci_dev *pdev, int state)
695{
696 struct pci_dev *parent = pdev->bus->self;
697 struct pcie_link_state *link;
698
699 if (aspm_disabled || !pdev->is_pcie)
700 return;
701 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
702 pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
703 parent = pdev;
704 if (!parent || !parent->link_state)
705 return;
706
707 down_read(&pci_bus_sem);
708 mutex_lock(&aspm_lock);
709 link = parent->link_state;
710 if (state & PCIE_LINK_STATE_L0S)
711 link->aspm_disable |= ASPM_STATE_L0S;
712 if (state & PCIE_LINK_STATE_L1)
713 link->aspm_disable |= ASPM_STATE_L1;
714 pcie_config_aspm_link(link, policy_to_aspm_state(link));
715
716 if (state & PCIE_LINK_STATE_CLKPM) {
717 link->clkpm_capable = 0;
718 pcie_set_clkpm(link, 0);
719 }
720 mutex_unlock(&aspm_lock);
721 up_read(&pci_bus_sem);
722}
723EXPORT_SYMBOL(pci_disable_link_state);
724
725static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
726{
727 int i;
728 struct pcie_link_state *link;
729
730 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
731 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
732 break;
733 if (i >= ARRAY_SIZE(policy_str))
734 return -EINVAL;
735 if (i == aspm_policy)
736 return 0;
737
738 down_read(&pci_bus_sem);
739 mutex_lock(&aspm_lock);
740 aspm_policy = i;
741 list_for_each_entry(link, &link_list, sibling) {
742 pcie_config_aspm_link(link, policy_to_aspm_state(link));
743 pcie_set_clkpm(link, policy_to_clkpm_state(link));
744 }
745 mutex_unlock(&aspm_lock);
746 up_read(&pci_bus_sem);
747 return 0;
748}
749
750static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
751{
752 int i, cnt = 0;
753 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
754 if (i == aspm_policy)
755 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
756 else
757 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
758 return cnt;
759}
760
761module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
762 NULL, 0644);
763
764#ifdef CONFIG_PCIEASPM_DEBUG
765static ssize_t link_state_show(struct device *dev,
766 struct device_attribute *attr,
767 char *buf)
768{
769 struct pci_dev *pci_device = to_pci_dev(dev);
770 struct pcie_link_state *link_state = pci_device->link_state;
771
772 return sprintf(buf, "%d\n", link_state->aspm_enabled);
773}
774
775static ssize_t link_state_store(struct device *dev,
776 struct device_attribute *attr,
777 const char *buf,
778 size_t n)
779{
780 struct pci_dev *pdev = to_pci_dev(dev);
781 struct pcie_link_state *link, *root = pdev->link_state->root;
782 u32 val = buf[0] - '0', state = 0;
783
784 if (n < 1 || val > 3)
785 return -EINVAL;
786
787
788 if (val & PCIE_LINK_STATE_L0S)
789 state |= ASPM_STATE_L0S;
790 if (val & PCIE_LINK_STATE_L1)
791 state |= ASPM_STATE_L1;
792
793 down_read(&pci_bus_sem);
794 mutex_lock(&aspm_lock);
795 list_for_each_entry(link, &link_list, sibling) {
796 if (link->root != root)
797 continue;
798 pcie_config_aspm_link(link, state);
799 }
800 mutex_unlock(&aspm_lock);
801 up_read(&pci_bus_sem);
802 return n;
803}
804
805static ssize_t clk_ctl_show(struct device *dev,
806 struct device_attribute *attr,
807 char *buf)
808{
809 struct pci_dev *pci_device = to_pci_dev(dev);
810 struct pcie_link_state *link_state = pci_device->link_state;
811
812 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
813}
814
815static ssize_t clk_ctl_store(struct device *dev,
816 struct device_attribute *attr,
817 const char *buf,
818 size_t n)
819{
820 struct pci_dev *pdev = to_pci_dev(dev);
821 int state;
822
823 if (n < 1)
824 return -EINVAL;
825 state = buf[0]-'0';
826
827 down_read(&pci_bus_sem);
828 mutex_lock(&aspm_lock);
829 pcie_set_clkpm_nocheck(pdev->link_state, !!state);
830 mutex_unlock(&aspm_lock);
831 up_read(&pci_bus_sem);
832
833 return n;
834}
835
836static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
837static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
838
839static char power_group[] = "power";
840void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
841{
842 struct pcie_link_state *link_state = pdev->link_state;
843
844 if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
845 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
846 return;
847
848 if (link_state->aspm_support)
849 sysfs_add_file_to_group(&pdev->dev.kobj,
850 &dev_attr_link_state.attr, power_group);
851 if (link_state->clkpm_capable)
852 sysfs_add_file_to_group(&pdev->dev.kobj,
853 &dev_attr_clk_ctl.attr, power_group);
854}
855
856void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
857{
858 struct pcie_link_state *link_state = pdev->link_state;
859
860 if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
861 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
862 return;
863
864 if (link_state->aspm_support)
865 sysfs_remove_file_from_group(&pdev->dev.kobj,
866 &dev_attr_link_state.attr, power_group);
867 if (link_state->clkpm_capable)
868 sysfs_remove_file_from_group(&pdev->dev.kobj,
869 &dev_attr_clk_ctl.attr, power_group);
870}
871#endif
872
873static int __init pcie_aspm_disable(char *str)
874{
875 if (!strcmp(str, "off")) {
876 aspm_disabled = 1;
877 printk(KERN_INFO "PCIe ASPM is disabled\n");
878 } else if (!strcmp(str, "force")) {
879 aspm_force = 1;
880 printk(KERN_INFO "PCIe ASPM is forcedly enabled\n");
881 }
882 return 1;
883}
884
885__setup("pcie_aspm=", pcie_aspm_disable);
886
887void pcie_no_aspm(void)
888{
889 if (!aspm_force)
890 aspm_disabled = 1;
891}
892
893
894
895
896
897
898
899int pcie_aspm_enabled(void)
900{
901 return !aspm_disabled;
902}
903EXPORT_SYMBOL(pcie_aspm_enabled);
904
905