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18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/acpi.h>
24#include <linux/kallsyms.h>
25#include <linux/dmi.h>
26#include <linux/pci-aspm.h>
27#include <linux/ioport.h>
28#include "pci.h"
29
30int isa_dma_bridge_buggy;
31EXPORT_SYMBOL(isa_dma_bridge_buggy);
32int pci_pci_problems;
33EXPORT_SYMBOL(pci_pci_problems);
34
35#ifdef CONFIG_PCI_QUIRKS
36
37
38
39
40
41
42
43static void __devinit quirk_resource_alignment(struct pci_dev *dev)
44{
45 int i;
46 struct resource *r;
47 resource_size_t align, size;
48 u16 command;
49
50 if (!pci_is_reassigndev(dev))
51 return;
52
53 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
54 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
55 dev_warn(&dev->dev,
56 "Can't reassign resources to host bridge.\n");
57 return;
58 }
59
60 dev_info(&dev->dev,
61 "Disabling memory decoding and releasing memory resources.\n");
62 pci_read_config_word(dev, PCI_COMMAND, &command);
63 command &= ~PCI_COMMAND_MEMORY;
64 pci_write_config_word(dev, PCI_COMMAND, command);
65
66 align = pci_specified_resource_alignment(dev);
67 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
68 r = &dev->resource[i];
69 if (!(r->flags & IORESOURCE_MEM))
70 continue;
71 size = resource_size(r);
72 if (size < align) {
73 size = align;
74 dev_info(&dev->dev,
75 "Rounding up size of resource #%d to %#llx.\n",
76 i, (unsigned long long)size);
77 }
78 r->end = size - 1;
79 r->start = 0;
80 }
81
82
83
84
85 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
86 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
87 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
88 r = &dev->resource[i];
89 if (!(r->flags & IORESOURCE_MEM))
90 continue;
91 r->end = resource_size(r) - 1;
92 r->start = 0;
93 }
94 pci_disable_bridge_window(dev);
95 }
96}
97DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
98
99
100
101
102
103static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
104{
105 dev->broken_parity_status = 1;
106}
107DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
109
110
111
112static void quirk_passive_release(struct pci_dev *dev)
113{
114 struct pci_dev *d = NULL;
115 unsigned char dlc;
116
117
118
119 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
120 pci_read_config_byte(d, 0x82, &dlc);
121 if (!(dlc & 1<<1)) {
122 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
123 dlc |= 1<<1;
124 pci_write_config_byte(d, 0x82, dlc);
125 }
126 }
127}
128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
129DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
130
131
132
133
134
135
136
137
138static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
139{
140 if (!isa_dma_bridge_buggy) {
141 isa_dma_bridge_buggy=1;
142 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
143 }
144}
145
146
147
148
149DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
156
157
158
159
160static void __devinit quirk_nopcipci(struct pci_dev *dev)
161{
162 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
163 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
164 pci_pci_problems |= PCIPCI_FAIL;
165 }
166}
167DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
169
170static void __devinit quirk_nopciamd(struct pci_dev *dev)
171{
172 u8 rev;
173 pci_read_config_byte(dev, 0x08, &rev);
174 if (rev == 0x13) {
175
176 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
177 pci_pci_problems |= PCIAGP_FAIL;
178 }
179}
180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
181
182
183
184
185static void __devinit quirk_triton(struct pci_dev *dev)
186{
187 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
188 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
189 pci_pci_problems |= PCIPCI_TRITON;
190 }
191}
192DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
193DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
196
197
198
199
200
201
202
203
204
205
206
207static void quirk_vialatency(struct pci_dev *dev)
208{
209 struct pci_dev *p;
210 u8 busarb;
211
212
213
214 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
215 if (p!=NULL) {
216
217
218 if (p->revision < 0x40 || p->revision > 0x42)
219 goto exit;
220 } else {
221 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
222 if (p==NULL)
223 goto exit;
224
225 if (p->revision < 0x10 || p->revision > 0x12)
226 goto exit;
227 }
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242 pci_read_config_byte(dev, 0x76, &busarb);
243
244
245 busarb &= ~(1<<5);
246 busarb |= (1<<4);
247 pci_write_config_byte(dev, 0x76, busarb);
248 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
249exit:
250 pci_dev_put(p);
251}
252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
255
256DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
257DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
258DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
259
260
261
262
263static void __devinit quirk_viaetbf(struct pci_dev *dev)
264{
265 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
266 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
267 pci_pci_problems |= PCIPCI_VIAETBF;
268 }
269}
270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
271
272static void __devinit quirk_vsfx(struct pci_dev *dev)
273{
274 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
275 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
276 pci_pci_problems |= PCIPCI_VSFX;
277 }
278}
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
280
281
282
283
284
285
286
287static void __init quirk_alimagik(struct pci_dev *dev)
288{
289 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
290 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
291 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
292 }
293}
294DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
295DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
296
297
298
299
300
301static void __devinit quirk_natoma(struct pci_dev *dev)
302{
303 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
304 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
305 pci_pci_problems |= PCIPCI_NATOMA;
306 }
307}
308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
313DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
314
315
316
317
318
319static void __devinit quirk_citrine(struct pci_dev *dev)
320{
321 dev->cfg_size = 0xA0;
322}
323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
324
325
326
327
328
329static void __devinit quirk_s3_64M(struct pci_dev *dev)
330{
331 struct resource *r = &dev->resource[0];
332
333 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
334 r->start = 0;
335 r->end = 0x3ffffff;
336 }
337}
338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
340
341static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
342 unsigned size, int nr, const char *name)
343{
344 region &= ~(size-1);
345 if (region) {
346 struct pci_bus_region bus_region;
347 struct resource *res = dev->resource + nr;
348
349 res->name = pci_name(dev);
350 res->start = region;
351 res->end = region + size - 1;
352 res->flags = IORESOURCE_IO;
353
354
355 bus_region.start = res->start;
356 bus_region.end = res->end;
357 pcibios_bus_to_resource(dev, res, &bus_region);
358
359 pci_claim_resource(dev, nr);
360 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
361 }
362}
363
364
365
366
367
368static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
369{
370 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
371
372 request_region(0x3b0, 0x0C, "RadeonIGP");
373 request_region(0x3d3, 0x01, "RadeonIGP");
374}
375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
376
377
378
379
380
381
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383
384
385
386
387
388static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
389{
390 u16 region;
391
392 pci_read_config_word(dev, 0xE0, ®ion);
393 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
394 pci_read_config_word(dev, 0xE2, ®ion);
395 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
396}
397DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
398
399static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
400{
401 u32 devres;
402 u32 mask, size, base;
403
404 pci_read_config_dword(dev, port, &devres);
405 if ((devres & enable) != enable)
406 return;
407 mask = (devres >> 16) & 15;
408 base = devres & 0xffff;
409 size = 16;
410 for (;;) {
411 unsigned bit = size >> 1;
412 if ((bit & mask) == bit)
413 break;
414 size = bit;
415 }
416
417
418
419
420
421 base &= -size;
422 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
423}
424
425static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
426{
427 u32 devres;
428 u32 mask, size, base;
429
430 pci_read_config_dword(dev, port, &devres);
431 if ((devres & enable) != enable)
432 return;
433 base = devres & 0xffff0000;
434 mask = (devres & 0x3f) << 16;
435 size = 128 << 16;
436 for (;;) {
437 unsigned bit = size >> 1;
438 if ((bit & mask) == bit)
439 break;
440 size = bit;
441 }
442
443
444
445
446 base &= -size;
447 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
448}
449
450
451
452
453
454
455
456static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
457{
458 u32 region, res_a;
459
460 pci_read_config_dword(dev, 0x40, ®ion);
461 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
462 pci_read_config_dword(dev, 0x90, ®ion);
463 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
464
465
466 pci_read_config_dword(dev, 0x5c, &res_a);
467
468 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
469 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
470
471
472
473
474 if (res_a & (1 << 29)) {
475 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
476 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
477 }
478
479 if (res_a & (1 << 30)) {
480 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
481 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
482 }
483 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
484 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
485}
486DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
488
489
490
491
492
493
494static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
495{
496 u32 region;
497
498 pci_read_config_dword(dev, 0x40, ®ion);
499 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
500
501 pci_read_config_dword(dev, 0x58, ®ion);
502 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
503}
504DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
514
515static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
516{
517 u32 region;
518
519 pci_read_config_dword(dev, 0x40, ®ion);
520 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
521
522 pci_read_config_dword(dev, 0x48, ®ion);
523 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
524}
525
526static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
527{
528 u32 val;
529 u32 size, base;
530
531 pci_read_config_dword(dev, reg, &val);
532
533
534 if (!(val & 1))
535 return;
536 base = val & 0xfffc;
537 if (dynsize) {
538
539
540
541
542
543
544 size = 16;
545 } else {
546 size = 128;
547 }
548 base &= ~(size-1);
549
550
551 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
552}
553
554static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
555{
556
557 ich6_lpc_acpi_gpio(dev);
558
559
560 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
561 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
562}
563DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
564DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
565
566static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
567{
568 u32 val;
569 u32 mask, base;
570
571 pci_read_config_dword(dev, reg, &val);
572
573
574 if (!(val & 1))
575 return;
576
577
578
579
580
581 base = val & 0xfffc;
582 mask = (val >> 16) & 0xfc;
583 mask |= 3;
584
585
586 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
587}
588
589
590static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
591{
592
593 ich6_lpc_acpi_gpio(dev);
594
595
596 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
597 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
598 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
599 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
600}
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
605DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
606DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
607DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
608DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
613DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
614
615
616
617
618
619static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
620{
621 u32 region;
622
623 if (dev->revision & 0x10) {
624 pci_read_config_dword(dev, 0x48, ®ion);
625 region &= PCI_BASE_ADDRESS_IO_MASK;
626 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
627 }
628}
629DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
630
631
632
633
634
635
636
637static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
638{
639 u16 hm;
640 u32 smb;
641
642 quirk_vt82c586_acpi(dev);
643
644 pci_read_config_word(dev, 0x70, &hm);
645 hm &= PCI_BASE_ADDRESS_IO_MASK;
646 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
647
648 pci_read_config_dword(dev, 0x90, &smb);
649 smb &= PCI_BASE_ADDRESS_IO_MASK;
650 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
651}
652DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
653
654
655
656
657
658
659static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
660{
661 u16 pm, smb;
662
663 pci_read_config_word(dev, 0x88, &pm);
664 pm &= PCI_BASE_ADDRESS_IO_MASK;
665 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
666
667 pci_read_config_word(dev, 0xd0, &smb);
668 smb &= PCI_BASE_ADDRESS_IO_MASK;
669 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
670}
671DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
672
673
674
675
676
677static void __devinit quirk_xio2000a(struct pci_dev *dev)
678{
679 struct pci_dev *pdev;
680 u16 command;
681
682 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
683 "secondary bus fast back-to-back transfers disabled\n");
684 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
685 pci_read_config_word(pdev, PCI_COMMAND, &command);
686 if (command & PCI_COMMAND_FAST_BACK)
687 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
688 }
689}
690DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
691 quirk_xio2000a);
692
693#ifdef CONFIG_X86_IO_APIC
694
695#include <asm/io_apic.h>
696
697
698
699
700
701
702
703
704static void quirk_via_ioapic(struct pci_dev *dev)
705{
706 u8 tmp;
707
708 if (nr_ioapics < 1)
709 tmp = 0;
710 else
711 tmp = 0x1f;
712
713 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
714 tmp == 0 ? "Disa" : "Ena");
715
716
717 pci_write_config_byte (dev, 0x58, tmp);
718}
719DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
720DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
721
722
723
724
725
726
727
728static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
729{
730 u8 misc_control2;
731#define BYPASS_APIC_DEASSERT 8
732
733 pci_read_config_byte(dev, 0x5B, &misc_control2);
734 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
735 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
736 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
737 }
738}
739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
740DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
741
742
743
744
745
746
747
748
749
750
751static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
752{
753 if (dev->revision >= 0x02) {
754 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
755 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
756 }
757}
758DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
759
760static void __init quirk_ioapic_rmw(struct pci_dev *dev)
761{
762 if (dev->devfn == 0 && dev->bus->number == 0)
763 sis_apic_bug = 1;
764}
765DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
766#endif
767
768
769
770
771
772static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
773{
774 if (dev->subordinate && dev->revision <= 0x12) {
775 dev_info(&dev->dev, "AMD8131 rev %x detected; "
776 "disabling PCI-X MMRBC\n", dev->revision);
777 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
778 }
779}
780DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
781
782
783
784
785
786
787
788
789
790static void __devinit quirk_via_acpi(struct pci_dev *d)
791{
792
793
794
795 u8 irq;
796 pci_read_config_byte(d, 0x42, &irq);
797 irq &= 0xf;
798 if (irq && (irq != 2))
799 d->irq = irq;
800}
801DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
802DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
803
804
805
806
807
808
809static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
810
811static void quirk_via_bridge(struct pci_dev *dev)
812{
813
814 switch (dev->device) {
815 case PCI_DEVICE_ID_VIA_82C686:
816
817
818
819 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
820 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
821 break;
822 case PCI_DEVICE_ID_VIA_8237:
823 case PCI_DEVICE_ID_VIA_8237A:
824 via_vlink_dev_lo = 15;
825 break;
826 case PCI_DEVICE_ID_VIA_8235:
827 via_vlink_dev_lo = 16;
828 break;
829 case PCI_DEVICE_ID_VIA_8231:
830 case PCI_DEVICE_ID_VIA_8233_0:
831 case PCI_DEVICE_ID_VIA_8233A:
832 case PCI_DEVICE_ID_VIA_8233C_0:
833 via_vlink_dev_lo = 17;
834 break;
835 }
836}
837DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
838DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
839DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
840DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
842DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
844DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859static void quirk_via_vlink(struct pci_dev *dev)
860{
861 u8 irq, new_irq;
862
863
864 if (via_vlink_dev_lo == -1)
865 return;
866
867 new_irq = dev->irq;
868
869
870 if (!new_irq || new_irq > 15)
871 return;
872
873
874 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
875 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
876 return;
877
878
879
880
881 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
882 if (new_irq != irq) {
883 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
884 irq, new_irq);
885 udelay(15);
886 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
887 }
888}
889DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
890
891
892
893
894
895
896
897static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
898{
899 pci_write_config_byte(dev, 0xfc, 0);
900 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
901}
902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
903
904
905
906
907
908
909
910static void quirk_cardbus_legacy(struct pci_dev *dev)
911{
912 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
913 return;
914 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
915}
916DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
917DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
918
919
920
921
922
923
924
925
926static void quirk_amd_ordering(struct pci_dev *dev)
927{
928 u32 pcic;
929 pci_read_config_dword(dev, 0x4C, &pcic);
930 if ((pcic&6)!=6) {
931 pcic |= 6;
932 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
933 pci_write_config_dword(dev, 0x4C, pcic);
934 pci_read_config_dword(dev, 0x84, &pcic);
935 pcic |= (1<<23);
936 pci_write_config_dword(dev, 0x84, pcic);
937 }
938}
939DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
940DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
941
942
943
944
945
946
947
948
949static void __devinit quirk_dunord ( struct pci_dev * dev )
950{
951 struct resource *r = &dev->resource [1];
952 r->start = 0;
953 r->end = 0xffffff;
954}
955DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
956
957
958
959
960
961
962
963static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
964{
965 dev->transparent = 1;
966}
967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
968DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
969
970
971
972
973
974
975
976static void quirk_mediagx_master(struct pci_dev *dev)
977{
978 u8 reg;
979 pci_read_config_byte(dev, 0x41, ®);
980 if (reg & 2) {
981 reg &= ~2;
982 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
983 pci_write_config_byte(dev, 0x41, reg);
984 }
985}
986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
987DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
988
989
990
991
992
993
994static void quirk_disable_pxb(struct pci_dev *pdev)
995{
996 u16 config;
997
998 if (pdev->revision != 0x04)
999 return;
1000 pci_read_config_word(pdev, 0x40, &config);
1001 if (config & (1<<6)) {
1002 config &= ~(1<<6);
1003 pci_write_config_word(pdev, 0x40, config);
1004 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1005 }
1006}
1007DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1008DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1009
1010static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1011{
1012
1013 u8 tmp;
1014
1015 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1016 if (tmp == 0x01) {
1017 pci_read_config_byte(pdev, 0x40, &tmp);
1018 pci_write_config_byte(pdev, 0x40, tmp|1);
1019 pci_write_config_byte(pdev, 0x9, 1);
1020 pci_write_config_byte(pdev, 0xa, 6);
1021 pci_write_config_byte(pdev, 0x40, tmp);
1022
1023 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1024 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1025 }
1026}
1027DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1028DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1029DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1030DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1031DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1032DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1033
1034
1035
1036
1037static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1038{
1039 u8 prog;
1040 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1041 if (prog & 5) {
1042 prog &= ~5;
1043 pdev->class &= ~5;
1044 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1045
1046 }
1047}
1048DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1049
1050
1051
1052
1053static void __init quirk_ide_samemode(struct pci_dev *pdev)
1054{
1055 u8 prog;
1056
1057 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1058
1059 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1060 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1061 prog &= ~5;
1062 pdev->class &= ~5;
1063 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1064 }
1065}
1066DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1067
1068
1069
1070
1071
1072static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1073{
1074
1075 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1076 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1077}
1078DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1079DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1080
1081DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1082
1083
1084DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1085
1086
1087
1088
1089static void __init quirk_eisa_bridge(struct pci_dev *dev)
1090{
1091 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1092}
1093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121static int asus_hides_smbus;
1122
1123static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1124{
1125 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1126 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1127 switch(dev->subsystem_device) {
1128 case 0x8025:
1129 case 0x8070:
1130 case 0x8088:
1131 case 0x1626:
1132 asus_hides_smbus = 1;
1133 }
1134 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1135 switch(dev->subsystem_device) {
1136 case 0x80b1:
1137 case 0x80b2:
1138 case 0x8093:
1139 asus_hides_smbus = 1;
1140 }
1141 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1142 switch(dev->subsystem_device) {
1143 case 0x8030:
1144 asus_hides_smbus = 1;
1145 }
1146 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1147 switch (dev->subsystem_device) {
1148 case 0x8070:
1149 asus_hides_smbus = 1;
1150 }
1151 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1152 switch (dev->subsystem_device) {
1153 case 0x80c9:
1154 asus_hides_smbus = 1;
1155 }
1156 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1157 switch (dev->subsystem_device) {
1158 case 0x1751:
1159 case 0x1821:
1160 case 0x1897:
1161 asus_hides_smbus = 1;
1162 }
1163 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1164 switch (dev->subsystem_device) {
1165 case 0x184b:
1166 case 0x186a:
1167 asus_hides_smbus = 1;
1168 }
1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1170 switch (dev->subsystem_device) {
1171 case 0x80f2:
1172 asus_hides_smbus = 1;
1173 }
1174 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1175 switch (dev->subsystem_device) {
1176 case 0x1882:
1177 case 0x1977:
1178 asus_hides_smbus = 1;
1179 }
1180 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1181 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1182 switch(dev->subsystem_device) {
1183 case 0x088C:
1184 case 0x0890:
1185 asus_hides_smbus = 1;
1186 }
1187 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1188 switch (dev->subsystem_device) {
1189 case 0x12bc:
1190 case 0x12bd:
1191 case 0x006a:
1192 asus_hides_smbus = 1;
1193 }
1194 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1195 switch (dev->subsystem_device) {
1196 case 0x12bf:
1197 asus_hides_smbus = 1;
1198 }
1199 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1200 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1201 switch(dev->subsystem_device) {
1202 case 0xC00C:
1203 asus_hides_smbus = 1;
1204 }
1205 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1206 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1207 switch(dev->subsystem_device) {
1208 case 0x0058:
1209 asus_hides_smbus = 1;
1210 }
1211 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1212 switch(dev->subsystem_device) {
1213 case 0xB16C:
1214
1215
1216
1217 asus_hides_smbus = 1;
1218 }
1219 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1220 switch(dev->subsystem_device) {
1221 case 0x00b8:
1222 case 0x00b9:
1223 case 0x00ba:
1224
1225
1226
1227
1228
1229 asus_hides_smbus = 1;
1230 }
1231 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1232 switch (dev->subsystem_device) {
1233 case 0x001A:
1234
1235
1236
1237 asus_hides_smbus = 1;
1238 }
1239 }
1240}
1241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1248DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1250DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1251
1252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1253DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1255
1256static void asus_hides_smbus_lpc(struct pci_dev *dev)
1257{
1258 u16 val;
1259
1260 if (likely(!asus_hides_smbus))
1261 return;
1262
1263 pci_read_config_word(dev, 0xF2, &val);
1264 if (val & 0x8) {
1265 pci_write_config_word(dev, 0xF2, val & (~0x8));
1266 pci_read_config_word(dev, 0xF2, &val);
1267 if (val & 0x8)
1268 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1269 else
1270 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1271 }
1272}
1273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1280DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1281DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1282DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1283DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1284DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1285DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1286DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1287
1288
1289static void __iomem *asus_rcba_base;
1290static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1291{
1292 u32 rcba;
1293
1294 if (likely(!asus_hides_smbus))
1295 return;
1296 WARN_ON(asus_rcba_base);
1297
1298 pci_read_config_dword(dev, 0xF0, &rcba);
1299
1300 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1301 if (asus_rcba_base == NULL)
1302 return;
1303}
1304
1305static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1306{
1307 u32 val;
1308
1309 if (likely(!asus_hides_smbus || !asus_rcba_base))
1310 return;
1311
1312 val = readl(asus_rcba_base + 0x3418);
1313 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1314}
1315
1316static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1317{
1318 if (likely(!asus_hides_smbus || !asus_rcba_base))
1319 return;
1320 iounmap(asus_rcba_base);
1321 asus_rcba_base = NULL;
1322 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1323}
1324
1325static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1326{
1327 asus_hides_smbus_lpc_ich6_suspend(dev);
1328 asus_hides_smbus_lpc_ich6_resume_early(dev);
1329 asus_hides_smbus_lpc_ich6_resume(dev);
1330}
1331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1332DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1333DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1334DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1335
1336
1337
1338
1339static void quirk_sis_96x_smbus(struct pci_dev *dev)
1340{
1341 u8 val = 0;
1342 pci_read_config_byte(dev, 0x77, &val);
1343 if (val & 0x10) {
1344 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1345 pci_write_config_byte(dev, 0x77, val & ~0x10);
1346 }
1347}
1348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1349DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1350DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1352DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1353DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1354DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1355DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365#define SIS_DETECT_REGISTER 0x40
1366
1367static void quirk_sis_503(struct pci_dev *dev)
1368{
1369 u8 reg;
1370 u16 devid;
1371
1372 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1373 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1374 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1375 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1376 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1377 return;
1378 }
1379
1380
1381
1382
1383
1384
1385 dev->device = devid;
1386 quirk_sis_96x_smbus(dev);
1387}
1388DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1389DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1390
1391
1392
1393
1394
1395
1396
1397
1398static void asus_hides_ac97_lpc(struct pci_dev *dev)
1399{
1400 u8 val;
1401 int asus_hides_ac97 = 0;
1402
1403 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1404 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1405 asus_hides_ac97 = 1;
1406 }
1407
1408 if (!asus_hides_ac97)
1409 return;
1410
1411 pci_read_config_byte(dev, 0x50, &val);
1412 if (val & 0xc0) {
1413 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1414 pci_read_config_byte(dev, 0x50, &val);
1415 if (val & 0xc0)
1416 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1417 else
1418 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1419 }
1420}
1421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1422DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1423
1424#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1425
1426
1427
1428
1429
1430
1431static void quirk_jmicron_ata(struct pci_dev *pdev)
1432{
1433 u32 conf1, conf5, class;
1434 u8 hdr;
1435
1436
1437 if (PCI_FUNC(pdev->devfn))
1438 return;
1439
1440 pci_read_config_dword(pdev, 0x40, &conf1);
1441 pci_read_config_dword(pdev, 0x80, &conf5);
1442
1443 conf1 &= ~0x00CFF302;
1444 conf5 &= ~(1 << 24);
1445
1446 switch (pdev->device) {
1447 case PCI_DEVICE_ID_JMICRON_JMB360:
1448
1449 conf1 |= 0x0002A100;
1450 break;
1451
1452 case PCI_DEVICE_ID_JMICRON_JMB365:
1453 case PCI_DEVICE_ID_JMICRON_JMB366:
1454
1455 conf5 |= (1 << 24);
1456
1457 case PCI_DEVICE_ID_JMICRON_JMB361:
1458 case PCI_DEVICE_ID_JMICRON_JMB363:
1459
1460
1461 conf1 |= 0x00C2A1B3;
1462 break;
1463
1464 case PCI_DEVICE_ID_JMICRON_JMB368:
1465
1466 conf1 |= 0x00C00000;
1467 break;
1468 }
1469
1470 pci_write_config_dword(pdev, 0x40, conf1);
1471 pci_write_config_dword(pdev, 0x80, conf5);
1472
1473
1474 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1475 pdev->hdr_type = hdr & 0x7f;
1476 pdev->multifunction = !!(hdr & 0x80);
1477
1478 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1479 pdev->class = class >> 8;
1480}
1481DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1482DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1483DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1484DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1485DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1486DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1487DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1488DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1489DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1490DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1491DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1492DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1493
1494#endif
1495
1496#ifdef CONFIG_X86_IO_APIC
1497static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1498{
1499 int i;
1500
1501 if ((pdev->class >> 8) != 0xff00)
1502 return;
1503
1504
1505
1506
1507 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1508 insert_resource(&iomem_resource, &pdev->resource[0]);
1509
1510
1511
1512 for (i=1; i < 6; i++) {
1513 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1514 }
1515
1516}
1517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1518#endif
1519
1520static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1521{
1522 pci_msi_off(pdev);
1523 pdev->no_msi = 1;
1524}
1525DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1526DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1527DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1528
1529
1530
1531
1532
1533
1534static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1535{
1536 pci_msi_off(dev);
1537 dev->no_msi = 1;
1538 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1539}
1540DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1541DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1542DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1543DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1544DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1545
1546
1547
1548
1549
1550static void quirk_intel_pcie_pm(struct pci_dev * dev)
1551{
1552 pci_pm_d3_delay = 120;
1553 dev->no_d1d2 = 1;
1554}
1555
1556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1557DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1559DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1560DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1561DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1577
1578#ifdef CONFIG_X86_IO_APIC
1579
1580
1581
1582
1583
1584
1585static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1586{
1587 if (noioapicquirk || noioapicreroute)
1588 return;
1589
1590 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1591 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1592 dev->vendor, dev->device);
1593}
1594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1602DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1603DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1604DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1605DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1606DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1607DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1608DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1609DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620#define INTEL_6300_IOAPIC_ABAR 0x40
1621#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1622
1623static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1624{
1625 u16 pci_config_word;
1626
1627 if (noioapicquirk)
1628 return;
1629
1630 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1631 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1632 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1633
1634 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1635 dev->vendor, dev->device);
1636}
1637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1638DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1639
1640
1641
1642
1643#define BC_HT1000_FEATURE_REG 0x64
1644#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1645#define BC_HT1000_MAP_IDX 0xC00
1646#define BC_HT1000_MAP_DATA 0xC01
1647
1648static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1649{
1650 u32 pci_config_dword;
1651 u8 irq;
1652
1653 if (noioapicquirk)
1654 return;
1655
1656 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1657 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1658 BC_HT1000_PIC_REGS_ENABLE);
1659
1660 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1661 outb(irq, BC_HT1000_MAP_IDX);
1662 outb(0x00, BC_HT1000_MAP_DATA);
1663 }
1664
1665 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1666
1667 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1668 dev->vendor, dev->device);
1669}
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1671DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681#define AMD_813X_MISC 0x40
1682#define AMD_813X_NOIOAMODE (1<<0)
1683#define AMD_813X_REV_B2 0x13
1684
1685static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1686{
1687 u32 pci_config_dword;
1688
1689 if (noioapicquirk)
1690 return;
1691 if (dev->revision == AMD_813X_REV_B2)
1692 return;
1693
1694 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1695 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1696 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1697
1698 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1699 dev->vendor, dev->device);
1700}
1701DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1702DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1703
1704#define AMD_8111_PCI_IRQ_ROUTING 0x56
1705
1706static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1707{
1708 u16 pci_config_word;
1709
1710 if (noioapicquirk)
1711 return;
1712
1713 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1714 if (!pci_config_word) {
1715 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1716 "already disabled\n", dev->vendor, dev->device);
1717 return;
1718 }
1719 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1720 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1721 dev->vendor, dev->device);
1722}
1723DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1724DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1725#endif
1726
1727
1728
1729
1730
1731
1732static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1733{
1734 struct resource *r = &dev->resource[0];
1735
1736 if (r->start & 0x8) {
1737 r->start = 0;
1738 r->end = 0xf;
1739 }
1740}
1741DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1742 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1743 quirk_tc86c001_ide);
1744
1745static void __devinit quirk_netmos(struct pci_dev *dev)
1746{
1747 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1748 unsigned int num_serial = dev->subsystem_device & 0xf;
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760 switch (dev->device) {
1761 case PCI_DEVICE_ID_NETMOS_9835:
1762
1763 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1764 dev->subsystem_device == 0x0299)
1765 return;
1766 case PCI_DEVICE_ID_NETMOS_9735:
1767 case PCI_DEVICE_ID_NETMOS_9745:
1768 case PCI_DEVICE_ID_NETMOS_9845:
1769 case PCI_DEVICE_ID_NETMOS_9855:
1770 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1771 num_parallel) {
1772 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1773 "%u serial); changing class SERIAL to OTHER "
1774 "(use parport_serial)\n",
1775 dev->device, num_parallel, num_serial);
1776 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1777 (dev->class & 0xff);
1778 }
1779 }
1780}
1781DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1782
1783static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1784{
1785 u16 command, pmcsr;
1786 u8 __iomem *csr;
1787 u8 cmd_hi;
1788 int pm;
1789
1790 switch (dev->device) {
1791
1792 case 0x1029:
1793 case 0x1030 ... 0x1034:
1794 case 0x1038 ... 0x103E:
1795 case 0x1050 ... 0x1057:
1796 case 0x1059:
1797 case 0x1064 ... 0x106B:
1798 case 0x1091 ... 0x1095:
1799 case 0x1209:
1800 case 0x1229:
1801 case 0x2449:
1802 case 0x2459:
1803 case 0x245D:
1804 case 0x27DC:
1805 break;
1806 default:
1807 return;
1808 }
1809
1810
1811
1812
1813
1814
1815
1816
1817 pci_read_config_word(dev, PCI_COMMAND, &command);
1818
1819 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1820 return;
1821
1822
1823
1824
1825
1826 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1827 if (pm) {
1828 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1829 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1830 return;
1831 }
1832
1833
1834 csr = ioremap(pci_resource_start(dev, 0), 8);
1835 if (!csr) {
1836 dev_warn(&dev->dev, "Can't map e100 registers\n");
1837 return;
1838 }
1839
1840 cmd_hi = readb(csr + 3);
1841 if (cmd_hi == 0) {
1842 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1843 "disabling\n");
1844 writeb(1, csr + 3);
1845 }
1846
1847 iounmap(csr);
1848}
1849DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1850
1851
1852
1853
1854
1855static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1856{
1857 dev_info(&dev->dev, "Disabling L0s\n");
1858 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1859}
1860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1861DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1862DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1863DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1864DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1866DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1868DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1869DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1870DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1871DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1873DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1874
1875static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1876{
1877
1878
1879
1880
1881 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1882 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1883 dev->class = PCI_CLASS_STORAGE_SCSI;
1884 }
1885}
1886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1887
1888
1889static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1890{
1891 u16 en1k;
1892 u8 io_base_lo, io_limit_lo;
1893 unsigned long base, limit;
1894 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1895
1896 pci_read_config_word(dev, 0x40, &en1k);
1897
1898 if (en1k & 0x200) {
1899 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1900
1901 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1902 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1903 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1904 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1905
1906 if (base <= limit) {
1907 res->start = base;
1908 res->end = limit + 0x3ff;
1909 }
1910 }
1911}
1912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1913
1914
1915
1916
1917
1918static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1919{
1920 u16 en1k, iobl_adr, iobl_adr_1k;
1921 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1922
1923 pci_read_config_word(dev, 0x40, &en1k);
1924
1925 if (en1k & 0x200) {
1926 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1927
1928 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1929
1930 if (iobl_adr != iobl_adr_1k) {
1931 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1932 iobl_adr,iobl_adr_1k);
1933 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1934 }
1935 }
1936}
1937DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1938
1939
1940
1941
1942
1943static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1944{
1945 uint8_t b;
1946 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1947 if (!(b & 0x20)) {
1948 pci_write_config_byte(dev, 0xf41, b | 0x20);
1949 dev_info(&dev->dev,
1950 "Linking AER extended capability\n");
1951 }
1952 }
1953}
1954DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1955 quirk_nvidia_ck804_pcie_aer_ext_cap);
1956DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1957 quirk_nvidia_ck804_pcie_aer_ext_cap);
1958
1959static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1960{
1961
1962
1963
1964
1965
1966
1967
1968 uint8_t b;
1969 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1970 if (b & 0x40) {
1971
1972 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1973
1974 dev_info(&dev->dev,
1975 "Disabling VIA CX700 PCI parking\n");
1976 }
1977 }
1978
1979 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1980 if (b != 0) {
1981
1982 pci_write_config_byte(dev, 0x72, 0x0);
1983
1984
1985 pci_write_config_byte(dev, 0x75, 0x1);
1986
1987
1988 pci_write_config_byte(dev, 0x77, 0x0);
1989
1990 dev_info(&dev->dev,
1991 "Disabling VIA CX700 PCI caching\n");
1992 }
1993 }
1994}
1995DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2009{
2010
2011
2012
2013
2014 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2015 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2016 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2017 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2018 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2019 (dev->revision & 0xf0) == 0x0)) {
2020 if (dev->vpd)
2021 dev->vpd->len = 0x80;
2022 }
2023}
2024
2025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2026 PCI_DEVICE_ID_NX2_5706,
2027 quirk_brcm_570x_limit_vpd);
2028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2029 PCI_DEVICE_ID_NX2_5706S,
2030 quirk_brcm_570x_limit_vpd);
2031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2032 PCI_DEVICE_ID_NX2_5708,
2033 quirk_brcm_570x_limit_vpd);
2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2035 PCI_DEVICE_ID_NX2_5708S,
2036 quirk_brcm_570x_limit_vpd);
2037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2038 PCI_DEVICE_ID_NX2_5709,
2039 quirk_brcm_570x_limit_vpd);
2040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2041 PCI_DEVICE_ID_NX2_5709S,
2042 quirk_brcm_570x_limit_vpd);
2043
2044
2045
2046
2047
2048
2049
2050static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2051{
2052 u8 reg;
2053
2054 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2055 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2056 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2057 }
2058}
2059
2060DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2061 quirk_unhide_mch_dev6);
2062DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2063 quirk_unhide_mch_dev6);
2064
2065
2066#ifdef CONFIG_PCI_MSI
2067
2068
2069
2070
2071
2072
2073static void __init quirk_disable_all_msi(struct pci_dev *dev)
2074{
2075 pci_no_msi();
2076 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2077}
2078DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2079DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2080DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2081DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2082DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2083DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2084
2085
2086static void __devinit quirk_disable_msi(struct pci_dev *dev)
2087{
2088 if (dev->subordinate) {
2089 dev_warn(&dev->dev, "MSI quirk detected; "
2090 "subordinate MSI disabled\n");
2091 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2092 }
2093}
2094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2095
2096
2097
2098static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2099{
2100 int pos, ttl = 48;
2101
2102 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2103 while (pos && ttl--) {
2104 u8 flags;
2105
2106 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2107 &flags) == 0)
2108 {
2109 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2110 flags & HT_MSI_FLAGS_ENABLE ?
2111 "enabled" : "disabled");
2112 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2113 }
2114
2115 pos = pci_find_next_ht_capability(dev, pos,
2116 HT_CAPTYPE_MSI_MAPPING);
2117 }
2118 return 0;
2119}
2120
2121
2122static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2123{
2124 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2125 dev_warn(&dev->dev, "MSI quirk detected; "
2126 "subordinate MSI disabled\n");
2127 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2128 }
2129}
2130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2131 quirk_msi_ht_cap);
2132
2133
2134
2135
2136static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2137{
2138 struct pci_dev *pdev;
2139
2140 if (!dev->subordinate)
2141 return;
2142
2143
2144
2145
2146 pdev = pci_get_slot(dev->bus, 0);
2147 if (!pdev)
2148 return;
2149 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2150 dev_warn(&dev->dev, "MSI quirk detected; "
2151 "subordinate MSI disabled\n");
2152 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2153 }
2154 pci_dev_put(pdev);
2155}
2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2157 quirk_nvidia_ck804_msi_ht_cap);
2158
2159
2160static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2161{
2162 int pos, ttl = 48;
2163
2164 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2165 while (pos && ttl--) {
2166 u8 flags;
2167
2168 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2169 &flags) == 0) {
2170 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2171
2172 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2173 flags | HT_MSI_FLAGS_ENABLE);
2174 }
2175 pos = pci_find_next_ht_capability(dev, pos,
2176 HT_CAPTYPE_MSI_MAPPING);
2177 }
2178}
2179DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2180 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2181 ht_enable_msi_mapping);
2182
2183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2184 ht_enable_msi_mapping);
2185
2186
2187
2188
2189
2190static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2191{
2192 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2193 dev_info(&dev->dev,
2194 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2195 dev->no_msi = 1;
2196 }
2197}
2198DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2199 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2200 nvenet_msi_disable);
2201
2202static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2203{
2204 int pos, ttl = 48;
2205 int found = 0;
2206
2207
2208 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2209 while (pos && ttl--) {
2210 u8 flags;
2211
2212 if (found < 1)
2213 found = 1;
2214 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2215 &flags) == 0) {
2216 if (flags & HT_MSI_FLAGS_ENABLE) {
2217 if (found < 2) {
2218 found = 2;
2219 break;
2220 }
2221 }
2222 }
2223 pos = pci_find_next_ht_capability(dev, pos,
2224 HT_CAPTYPE_MSI_MAPPING);
2225 }
2226
2227 return found;
2228}
2229
2230static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2231{
2232 struct pci_dev *dev;
2233 int pos;
2234 int i, dev_no;
2235 int found = 0;
2236
2237 dev_no = host_bridge->devfn >> 3;
2238 for (i = dev_no + 1; i < 0x20; i++) {
2239 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2240 if (!dev)
2241 continue;
2242
2243
2244 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2245 if (pos != 0) {
2246 pci_dev_put(dev);
2247 break;
2248 }
2249
2250 if (ht_check_msi_mapping(dev)) {
2251 found = 1;
2252 pci_dev_put(dev);
2253 break;
2254 }
2255 pci_dev_put(dev);
2256 }
2257
2258 return found;
2259}
2260
2261#define PCI_HT_CAP_SLAVE_CTRL0 4
2262#define PCI_HT_CAP_SLAVE_CTRL1 8
2263
2264static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2265{
2266 int pos, ctrl_off;
2267 int end = 0;
2268 u16 flags, ctrl;
2269
2270 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2271
2272 if (!pos)
2273 goto out;
2274
2275 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2276
2277 ctrl_off = ((flags >> 10) & 1) ?
2278 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2279 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2280
2281 if (ctrl & (1 << 6))
2282 end = 1;
2283
2284out:
2285 return end;
2286}
2287
2288static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2289{
2290 struct pci_dev *host_bridge;
2291 int pos;
2292 int i, dev_no;
2293 int found = 0;
2294
2295 dev_no = dev->devfn >> 3;
2296 for (i = dev_no; i >= 0; i--) {
2297 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2298 if (!host_bridge)
2299 continue;
2300
2301 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2302 if (pos != 0) {
2303 found = 1;
2304 break;
2305 }
2306 pci_dev_put(host_bridge);
2307 }
2308
2309 if (!found)
2310 return;
2311
2312
2313 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2314 host_bridge_with_leaf(host_bridge))
2315 goto out;
2316
2317
2318 if (msi_ht_cap_enabled(host_bridge))
2319 goto out;
2320
2321 ht_enable_msi_mapping(dev);
2322
2323out:
2324 pci_dev_put(host_bridge);
2325}
2326
2327static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2328{
2329 int pos, ttl = 48;
2330
2331 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2332 while (pos && ttl--) {
2333 u8 flags;
2334
2335 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2336 &flags) == 0) {
2337 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2338
2339 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2340 flags & ~HT_MSI_FLAGS_ENABLE);
2341 }
2342 pos = pci_find_next_ht_capability(dev, pos,
2343 HT_CAPTYPE_MSI_MAPPING);
2344 }
2345}
2346
2347static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2348{
2349 struct pci_dev *host_bridge;
2350 int pos;
2351 int found;
2352
2353
2354 found = ht_check_msi_mapping(dev);
2355
2356
2357 if (found == 0)
2358 return;
2359
2360
2361
2362
2363
2364 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2365 if (host_bridge == NULL) {
2366 dev_warn(&dev->dev,
2367 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2368 return;
2369 }
2370
2371 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2372 if (pos != 0) {
2373
2374 if (found == 1) {
2375
2376 if (all)
2377 ht_enable_msi_mapping(dev);
2378 else
2379 nv_ht_enable_msi_mapping(dev);
2380 }
2381 return;
2382 }
2383
2384
2385 if (found == 1)
2386 return;
2387
2388
2389 ht_disable_msi_mapping(dev);
2390}
2391
2392static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2393{
2394 return __nv_msi_ht_cap_quirk(dev, 1);
2395}
2396
2397static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2398{
2399 return __nv_msi_ht_cap_quirk(dev, 0);
2400}
2401
2402DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2403DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2404
2405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2406DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2407
2408static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2409{
2410 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2411}
2412static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2413{
2414 struct pci_dev *p;
2415
2416
2417
2418
2419
2420 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2421 NULL);
2422 if (!p)
2423 return;
2424
2425 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2426 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2427 pci_dev_put(p);
2428}
2429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2430 PCI_DEVICE_ID_TIGON3_5780,
2431 quirk_msi_intx_disable_bug);
2432DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2433 PCI_DEVICE_ID_TIGON3_5780S,
2434 quirk_msi_intx_disable_bug);
2435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2436 PCI_DEVICE_ID_TIGON3_5714,
2437 quirk_msi_intx_disable_bug);
2438DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2439 PCI_DEVICE_ID_TIGON3_5714S,
2440 quirk_msi_intx_disable_bug);
2441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2442 PCI_DEVICE_ID_TIGON3_5715,
2443 quirk_msi_intx_disable_bug);
2444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2445 PCI_DEVICE_ID_TIGON3_5715S,
2446 quirk_msi_intx_disable_bug);
2447
2448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2449 quirk_msi_intx_disable_ati_bug);
2450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2451 quirk_msi_intx_disable_ati_bug);
2452DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2453 quirk_msi_intx_disable_ati_bug);
2454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2455 quirk_msi_intx_disable_ati_bug);
2456DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2457 quirk_msi_intx_disable_ati_bug);
2458
2459DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2460 quirk_msi_intx_disable_bug);
2461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2462 quirk_msi_intx_disable_bug);
2463DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2464 quirk_msi_intx_disable_bug);
2465
2466#endif
2467
2468#ifdef CONFIG_PCI_IOV
2469
2470
2471
2472
2473
2474
2475static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2476{
2477 int pos, flags;
2478 u32 bar, start, size;
2479
2480 if (PAGE_SIZE > 0x10000)
2481 return;
2482
2483 flags = pci_resource_flags(dev, 0);
2484 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2485 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2486 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2487 PCI_BASE_ADDRESS_MEM_TYPE_32)
2488 return;
2489
2490 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2491 if (!pos)
2492 return;
2493
2494 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2495 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2496 return;
2497
2498 start = pci_resource_start(dev, 1);
2499 size = pci_resource_len(dev, 1);
2500 if (!start || size != 0x400000 || start & (size - 1))
2501 return;
2502
2503 pci_resource_flags(dev, 1) = 0;
2504 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2505 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2506 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2507
2508 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2509}
2510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
2513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
2515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
2516
2517#endif
2518
2519static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2520 struct pci_fixup *end)
2521{
2522 while (f < end) {
2523 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2524 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2525 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2526 f->hook(dev);
2527 }
2528 f++;
2529 }
2530}
2531
2532extern struct pci_fixup __start_pci_fixups_early[];
2533extern struct pci_fixup __end_pci_fixups_early[];
2534extern struct pci_fixup __start_pci_fixups_header[];
2535extern struct pci_fixup __end_pci_fixups_header[];
2536extern struct pci_fixup __start_pci_fixups_final[];
2537extern struct pci_fixup __end_pci_fixups_final[];
2538extern struct pci_fixup __start_pci_fixups_enable[];
2539extern struct pci_fixup __end_pci_fixups_enable[];
2540extern struct pci_fixup __start_pci_fixups_resume[];
2541extern struct pci_fixup __end_pci_fixups_resume[];
2542extern struct pci_fixup __start_pci_fixups_resume_early[];
2543extern struct pci_fixup __end_pci_fixups_resume_early[];
2544extern struct pci_fixup __start_pci_fixups_suspend[];
2545extern struct pci_fixup __end_pci_fixups_suspend[];
2546
2547
2548void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2549{
2550 struct pci_fixup *start, *end;
2551
2552 switch(pass) {
2553 case pci_fixup_early:
2554 start = __start_pci_fixups_early;
2555 end = __end_pci_fixups_early;
2556 break;
2557
2558 case pci_fixup_header:
2559 start = __start_pci_fixups_header;
2560 end = __end_pci_fixups_header;
2561 break;
2562
2563 case pci_fixup_final:
2564 start = __start_pci_fixups_final;
2565 end = __end_pci_fixups_final;
2566 break;
2567
2568 case pci_fixup_enable:
2569 start = __start_pci_fixups_enable;
2570 end = __end_pci_fixups_enable;
2571 break;
2572
2573 case pci_fixup_resume:
2574 start = __start_pci_fixups_resume;
2575 end = __end_pci_fixups_resume;
2576 break;
2577
2578 case pci_fixup_resume_early:
2579 start = __start_pci_fixups_resume_early;
2580 end = __end_pci_fixups_resume_early;
2581 break;
2582
2583 case pci_fixup_suspend:
2584 start = __start_pci_fixups_suspend;
2585 end = __end_pci_fixups_suspend;
2586 break;
2587
2588 default:
2589
2590 return;
2591 }
2592 pci_do_fixups(dev, start, end);
2593}
2594
2595static int __init pci_apply_final_quirks(void)
2596{
2597 struct pci_dev *dev = NULL;
2598
2599 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2600 pci_fixup_device(pci_fixup_final, dev);
2601 }
2602
2603 return 0;
2604}
2605
2606fs_initcall_sync(pci_apply_final_quirks);
2607#else
2608void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2609#endif
2610EXPORT_SYMBOL(pci_fixup_device);
2611