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24#ifndef __BFI_CBREG_H__
25#define __BFI_CBREG_H__
26
27
28#define HOSTFN0_INT_STATUS 0x00014000
29#define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000
30#define __HOSTFN0_INT_STATUS_LVL_SH 20
31#define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
32#define __HOSTFN0_INT_STATUS_P 0x000fffff
33#define HOSTFN0_INT_MSK 0x00014004
34#define HOST_PAGE_NUM_FN0 0x00014008
35#define __HOST_PAGE_NUM_FN 0x000001ff
36#define HOSTFN1_INT_STATUS 0x00014100
37#define __HOSTFN1_INT_STAT_LVL_MK 0x00f00000
38#define __HOSTFN1_INT_STAT_LVL_SH 20
39#define __HOSTFN1_INT_STAT_LVL(_v) ((_v) << __HOSTFN1_INT_STAT_LVL_SH)
40#define __HOSTFN1_INT_STAT_P 0x000fffff
41#define HOSTFN1_INT_MSK 0x00014104
42#define HOST_PAGE_NUM_FN1 0x00014108
43#define APP_PLL_400_CTL_REG 0x00014204
44#define __P_400_PLL_LOCK 0x80000000
45#define __APP_PLL_400_SRAM_USE_100MHZ 0x00100000
46#define __APP_PLL_400_RESET_TIMER_MK 0x000e0000
47#define __APP_PLL_400_RESET_TIMER_SH 17
48#define __APP_PLL_400_RESET_TIMER(_v) ((_v) << __APP_PLL_400_RESET_TIMER_SH)
49#define __APP_PLL_400_LOGIC_SOFT_RESET 0x00010000
50#define __APP_PLL_400_CNTLMT0_1_MK 0x0000c000
51#define __APP_PLL_400_CNTLMT0_1_SH 14
52#define __APP_PLL_400_CNTLMT0_1(_v) ((_v) << __APP_PLL_400_CNTLMT0_1_SH)
53#define __APP_PLL_400_JITLMT0_1_MK 0x00003000
54#define __APP_PLL_400_JITLMT0_1_SH 12
55#define __APP_PLL_400_JITLMT0_1(_v) ((_v) << __APP_PLL_400_JITLMT0_1_SH)
56#define __APP_PLL_400_HREF 0x00000800
57#define __APP_PLL_400_HDIV 0x00000400
58#define __APP_PLL_400_P0_1_MK 0x00000300
59#define __APP_PLL_400_P0_1_SH 8
60#define __APP_PLL_400_P0_1(_v) ((_v) << __APP_PLL_400_P0_1_SH)
61#define __APP_PLL_400_Z0_2_MK 0x000000e0
62#define __APP_PLL_400_Z0_2_SH 5
63#define __APP_PLL_400_Z0_2(_v) ((_v) << __APP_PLL_400_Z0_2_SH)
64#define __APP_PLL_400_RSEL200500 0x00000010
65#define __APP_PLL_400_ENARST 0x00000008
66#define __APP_PLL_400_BYPASS 0x00000004
67#define __APP_PLL_400_LRESETN 0x00000002
68#define __APP_PLL_400_ENABLE 0x00000001
69#define APP_PLL_212_CTL_REG 0x00014208
70#define __P_212_PLL_LOCK 0x80000000
71#define __APP_PLL_212_RESET_TIMER_MK 0x000e0000
72#define __APP_PLL_212_RESET_TIMER_SH 17
73#define __APP_PLL_212_RESET_TIMER(_v) ((_v) << __APP_PLL_212_RESET_TIMER_SH)
74#define __APP_PLL_212_LOGIC_SOFT_RESET 0x00010000
75#define __APP_PLL_212_CNTLMT0_1_MK 0x0000c000
76#define __APP_PLL_212_CNTLMT0_1_SH 14
77#define __APP_PLL_212_CNTLMT0_1(_v) ((_v) << __APP_PLL_212_CNTLMT0_1_SH)
78#define __APP_PLL_212_JITLMT0_1_MK 0x00003000
79#define __APP_PLL_212_JITLMT0_1_SH 12
80#define __APP_PLL_212_JITLMT0_1(_v) ((_v) << __APP_PLL_212_JITLMT0_1_SH)
81#define __APP_PLL_212_HREF 0x00000800
82#define __APP_PLL_212_HDIV 0x00000400
83#define __APP_PLL_212_P0_1_MK 0x00000300
84#define __APP_PLL_212_P0_1_SH 8
85#define __APP_PLL_212_P0_1(_v) ((_v) << __APP_PLL_212_P0_1_SH)
86#define __APP_PLL_212_Z0_2_MK 0x000000e0
87#define __APP_PLL_212_Z0_2_SH 5
88#define __APP_PLL_212_Z0_2(_v) ((_v) << __APP_PLL_212_Z0_2_SH)
89#define __APP_PLL_212_RSEL200500 0x00000010
90#define __APP_PLL_212_ENARST 0x00000008
91#define __APP_PLL_212_BYPASS 0x00000004
92#define __APP_PLL_212_LRESETN 0x00000002
93#define __APP_PLL_212_ENABLE 0x00000001
94#define HOST_SEM0_REG 0x00014230
95#define __HOST_SEMAPHORE 0x00000001
96#define HOST_SEM1_REG 0x00014234
97#define HOST_SEM2_REG 0x00014238
98#define HOST_SEM3_REG 0x0001423c
99#define HOST_SEM0_INFO_REG 0x00014240
100#define HOST_SEM1_INFO_REG 0x00014244
101#define HOST_SEM2_INFO_REG 0x00014248
102#define HOST_SEM3_INFO_REG 0x0001424c
103#define HOSTFN0_LPU0_CMD_STAT 0x00019000
104#define __HOSTFN0_LPU0_MBOX_INFO_MK 0xfffffffe
105#define __HOSTFN0_LPU0_MBOX_INFO_SH 1
106#define __HOSTFN0_LPU0_MBOX_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX_INFO_SH)
107#define __HOSTFN0_LPU0_MBOX_CMD_STATUS 0x00000001
108#define LPU0_HOSTFN0_CMD_STAT 0x00019008
109#define __LPU0_HOSTFN0_MBOX_INFO_MK 0xfffffffe
110#define __LPU0_HOSTFN0_MBOX_INFO_SH 1
111#define __LPU0_HOSTFN0_MBOX_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX_INFO_SH)
112#define __LPU0_HOSTFN0_MBOX_CMD_STATUS 0x00000001
113#define HOSTFN1_LPU1_CMD_STAT 0x00019014
114#define __HOSTFN1_LPU1_MBOX_INFO_MK 0xfffffffe
115#define __HOSTFN1_LPU1_MBOX_INFO_SH 1
116#define __HOSTFN1_LPU1_MBOX_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX_INFO_SH)
117#define __HOSTFN1_LPU1_MBOX_CMD_STATUS 0x00000001
118#define LPU1_HOSTFN1_CMD_STAT 0x0001901c
119#define __LPU1_HOSTFN1_MBOX_INFO_MK 0xfffffffe
120#define __LPU1_HOSTFN1_MBOX_INFO_SH 1
121#define __LPU1_HOSTFN1_MBOX_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX_INFO_SH)
122#define __LPU1_HOSTFN1_MBOX_CMD_STATUS 0x00000001
123#define CPE_Q0_DEPTH 0x00010014
124#define CPE_Q0_PI 0x0001001c
125#define CPE_Q0_CI 0x00010020
126#define CPE_Q1_DEPTH 0x00010034
127#define CPE_Q1_PI 0x0001003c
128#define CPE_Q1_CI 0x00010040
129#define CPE_Q2_DEPTH 0x00010054
130#define CPE_Q2_PI 0x0001005c
131#define CPE_Q2_CI 0x00010060
132#define CPE_Q3_DEPTH 0x00010074
133#define CPE_Q3_PI 0x0001007c
134#define CPE_Q3_CI 0x00010080
135#define CPE_Q4_DEPTH 0x00010094
136#define CPE_Q4_PI 0x0001009c
137#define CPE_Q4_CI 0x000100a0
138#define CPE_Q5_DEPTH 0x000100b4
139#define CPE_Q5_PI 0x000100bc
140#define CPE_Q5_CI 0x000100c0
141#define CPE_Q6_DEPTH 0x000100d4
142#define CPE_Q6_PI 0x000100dc
143#define CPE_Q6_CI 0x000100e0
144#define CPE_Q7_DEPTH 0x000100f4
145#define CPE_Q7_PI 0x000100fc
146#define CPE_Q7_CI 0x00010100
147#define RME_Q0_DEPTH 0x00011014
148#define RME_Q0_PI 0x0001101c
149#define RME_Q0_CI 0x00011020
150#define RME_Q1_DEPTH 0x00011034
151#define RME_Q1_PI 0x0001103c
152#define RME_Q1_CI 0x00011040
153#define RME_Q2_DEPTH 0x00011054
154#define RME_Q2_PI 0x0001105c
155#define RME_Q2_CI 0x00011060
156#define RME_Q3_DEPTH 0x00011074
157#define RME_Q3_PI 0x0001107c
158#define RME_Q3_CI 0x00011080
159#define RME_Q4_DEPTH 0x00011094
160#define RME_Q4_PI 0x0001109c
161#define RME_Q4_CI 0x000110a0
162#define RME_Q5_DEPTH 0x000110b4
163#define RME_Q5_PI 0x000110bc
164#define RME_Q5_CI 0x000110c0
165#define RME_Q6_DEPTH 0x000110d4
166#define RME_Q6_PI 0x000110dc
167#define RME_Q6_CI 0x000110e0
168#define RME_Q7_DEPTH 0x000110f4
169#define RME_Q7_PI 0x000110fc
170#define RME_Q7_CI 0x00011100
171#define PSS_CTL_REG 0x00018800
172#define __PSS_I2C_CLK_DIV_MK 0x00030000
173#define __PSS_I2C_CLK_DIV_SH 16
174#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
175#define __PSS_LMEM_INIT_DONE 0x00001000
176#define __PSS_LMEM_RESET 0x00000200
177#define __PSS_LMEM_INIT_EN 0x00000100
178#define __PSS_LPU1_RESET 0x00000002
179#define __PSS_LPU0_RESET 0x00000001
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185
186#define __EMPHPOST_AT_4G_MK_FIX 0x0000001c
187#define __EMPHPOST_AT_4G_SH_FIX 0x00000002
188#define __EMPHPRE_AT_4G_FIX 0x00000003
189#define __SFP_TXRATE_EN_FIX 0x00000100
190#define __SFP_RXRATE_EN_FIX 0x00000080
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197#define HOSTFN0_LPU_MBOX0_0 0x00019200
198#define HOSTFN1_LPU_MBOX0_8 0x00019260
199#define LPU_HOSTFN0_MBOX0_0 0x00019280
200#define LPU_HOSTFN1_MBOX0_8 0x000192e0
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206
207#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
208#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
209#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
210#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
211#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
212
213#define CPE_Q_DEPTH(__n) \
214 (CPE_Q0_DEPTH + (__n) * (CPE_Q1_DEPTH - CPE_Q0_DEPTH))
215#define CPE_Q_PI(__n) \
216 (CPE_Q0_PI + (__n) * (CPE_Q1_PI - CPE_Q0_PI))
217#define CPE_Q_CI(__n) \
218 (CPE_Q0_CI + (__n) * (CPE_Q1_CI - CPE_Q0_CI))
219#define RME_Q_DEPTH(__n) \
220 (RME_Q0_DEPTH + (__n) * (RME_Q1_DEPTH - RME_Q0_DEPTH))
221#define RME_Q_PI(__n) \
222 (RME_Q0_PI + (__n) * (RME_Q1_PI - RME_Q0_PI))
223#define RME_Q_CI(__n) \
224 (RME_Q0_CI + (__n) * (RME_Q1_CI - RME_Q0_CI))
225
226#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
227#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
228#define CPE_Q_MASK(__q) ((__q) & 0x3)
229#define RME_Q_MASK(__q) ((__q) & 0x3)
230
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234
235enum {
236 BFA_MSIX_CPE_Q0 = 0,
237 BFA_MSIX_CPE_Q1 = 1,
238 BFA_MSIX_CPE_Q2 = 2,
239 BFA_MSIX_CPE_Q3 = 3,
240 BFA_MSIX_CPE_Q4 = 4,
241 BFA_MSIX_CPE_Q5 = 5,
242 BFA_MSIX_CPE_Q6 = 6,
243 BFA_MSIX_CPE_Q7 = 7,
244 BFA_MSIX_RME_Q0 = 8,
245 BFA_MSIX_RME_Q1 = 9,
246 BFA_MSIX_RME_Q2 = 10,
247 BFA_MSIX_RME_Q3 = 11,
248 BFA_MSIX_RME_Q4 = 12,
249 BFA_MSIX_RME_Q5 = 13,
250 BFA_MSIX_RME_Q6 = 14,
251 BFA_MSIX_RME_Q7 = 15,
252 BFA_MSIX_ERR_EMC = 16,
253 BFA_MSIX_ERR_LPU0 = 17,
254 BFA_MSIX_ERR_LPU1 = 18,
255 BFA_MSIX_ERR_PSS = 19,
256 BFA_MSIX_MBOX_LPU0 = 20,
257 BFA_MSIX_MBOX_LPU1 = 21,
258 BFA_MSIX_CB_MAX = 22,
259};
260
261
262
263
264#define __HFN_INT_CPE_Q0 0x00000001U
265#define __HFN_INT_CPE_Q1 0x00000002U
266#define __HFN_INT_CPE_Q2 0x00000004U
267#define __HFN_INT_CPE_Q3 0x00000008U
268#define __HFN_INT_CPE_Q4 0x00000010U
269#define __HFN_INT_CPE_Q5 0x00000020U
270#define __HFN_INT_CPE_Q6 0x00000040U
271#define __HFN_INT_CPE_Q7 0x00000080U
272#define __HFN_INT_RME_Q0 0x00000100U
273#define __HFN_INT_RME_Q1 0x00000200U
274#define __HFN_INT_RME_Q2 0x00000400U
275#define __HFN_INT_RME_Q3 0x00000800U
276#define __HFN_INT_RME_Q4 0x00001000U
277#define __HFN_INT_RME_Q5 0x00002000U
278#define __HFN_INT_RME_Q6 0x00004000U
279#define __HFN_INT_RME_Q7 0x00008000U
280#define __HFN_INT_ERR_EMC 0x00010000U
281#define __HFN_INT_ERR_LPU0 0x00020000U
282#define __HFN_INT_ERR_LPU1 0x00040000U
283#define __HFN_INT_ERR_PSS 0x00080000U
284#define __HFN_INT_MBOX_LPU0 0x00100000U
285#define __HFN_INT_MBOX_LPU1 0x00200000U
286#define __HFN_INT_MBOX1_LPU0 0x00400000U
287#define __HFN_INT_MBOX1_LPU1 0x00800000U
288#define __HFN_INT_CPE_MASK 0x000000ffU
289#define __HFN_INT_RME_MASK 0x0000ff00U
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294
295#define PSS_SMEM_PAGE_START 0x8000
296#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
297#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
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303
304#endif
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