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25#ifndef _MVS64XX_REG_H_
26#define _MVS64XX_REG_H_
27
28#include <linux/types.h>
29
30#define MAX_LINK_RATE SAS_LINK_RATE_3_0_GBPS
31
32
33enum hw_registers {
34 MVS_GBL_CTL = 0x04,
35 MVS_GBL_INT_STAT = 0x08,
36 MVS_GBL_PI = 0x0C,
37
38 MVS_PHY_CTL = 0x40,
39 MVS_PORTS_IMP = 0x9C,
40
41 MVS_GBL_PORT_TYPE = 0xa0,
42
43 MVS_CTL = 0x100,
44 MVS_PCS = 0x104,
45 MVS_CMD_LIST_LO = 0x108,
46 MVS_CMD_LIST_HI = 0x10C,
47 MVS_RX_FIS_LO = 0x110,
48 MVS_RX_FIS_HI = 0x114,
49
50 MVS_TX_CFG = 0x120,
51 MVS_TX_LO = 0x124,
52 MVS_TX_HI = 0x128,
53
54 MVS_TX_PROD_IDX = 0x12C,
55 MVS_TX_CONS_IDX = 0x130,
56 MVS_RX_CFG = 0x134,
57 MVS_RX_LO = 0x138,
58 MVS_RX_HI = 0x13C,
59 MVS_RX_CONS_IDX = 0x140,
60
61 MVS_INT_COAL = 0x148,
62 MVS_INT_COAL_TMOUT = 0x14C,
63 MVS_INT_STAT = 0x150,
64 MVS_INT_MASK = 0x154,
65 MVS_INT_STAT_SRS_0 = 0x158,
66 MVS_INT_MASK_SRS_0 = 0x15C,
67
68
69 MVS_P0_INT_STAT = 0x160,
70 MVS_P0_INT_MASK = 0x164,
71
72 MVS_P4_INT_STAT = 0x200,
73 MVS_P4_INT_MASK = 0x204,
74
75
76 MVS_P0_SER_CTLSTAT = 0x180,
77
78 MVS_P4_SER_CTLSTAT = 0x220,
79
80 MVS_CMD_ADDR = 0x1B8,
81 MVS_CMD_DATA = 0x1BC,
82
83
84 MVS_P0_CFG_ADDR = 0x1C0,
85 MVS_P0_CFG_DATA = 0x1C4,
86
87 MVS_P4_CFG_ADDR = 0x230,
88 MVS_P4_CFG_DATA = 0x234,
89
90
91 MVS_P0_VSR_ADDR = 0x1E0,
92 MVS_P0_VSR_DATA = 0x1E4,
93
94 MVS_P4_VSR_ADDR = 0x250,
95 MVS_P4_VSR_DATA = 0x254,
96};
97
98enum pci_cfg_registers {
99 PCR_PHY_CTL = 0x40,
100 PCR_PHY_CTL2 = 0x90,
101 PCR_DEV_CTRL = 0xE8,
102 PCR_LINK_STAT = 0xF2,
103};
104
105
106enum sas_sata_vsp_regs {
107 VSR_PHY_STAT = 0x00,
108 VSR_PHY_MODE1 = 0x01,
109 VSR_PHY_MODE2 = 0x02,
110 VSR_PHY_MODE3 = 0x03,
111 VSR_PHY_MODE4 = 0x04,
112 VSR_PHY_MODE5 = 0x05,
113 VSR_PHY_MODE6 = 0x06,
114 VSR_PHY_MODE7 = 0x07,
115 VSR_PHY_MODE8 = 0x08,
116 VSR_PHY_MODE9 = 0x09,
117 VSR_PHY_MODE10 = 0x0A,
118 VSR_PHY_MODE11 = 0x0B,
119 VSR_PHY_VS0 = 0x0C,
120 VSR_PHY_VS1 = 0x0D,
121};
122
123enum chip_register_bits {
124 PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
125 PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
126 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
127 PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
128 (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
129};
130
131#define MAX_SG_ENTRY 64
132
133struct mvs_prd {
134 __le64 addr;
135 __le32 reserved;
136 __le32 len;
137};
138
139#define SPI_CTRL_REG 0xc0
140#define SPI_CTRL_VENDOR_ENABLE (1U<<29)
141#define SPI_CTRL_SPIRDY (1U<<22)
142#define SPI_CTRL_SPISTART (1U<<20)
143
144#define SPI_CMD_REG 0xc4
145#define SPI_DATA_REG 0xc8
146
147#define SPI_CTRL_REG_64XX 0x10
148#define SPI_CMD_REG_64XX 0x14
149#define SPI_DATA_REG_64XX 0x18
150
151#endif
152
